Multi-layer printed circuit board and a BGA semiconductor package using the multi-layer printed circuit board

[0001] [Technical field to which the invention belongs] The present invention relates to a multilayer printed circuit board, and more specifically, in order to mount a semiconductor component in the form of a ball grid array packaging, a large number of pads for connecting bumps are provided on the surface. It relates to a multilayer printed circuit board having a structure and a method for manufacturing the same. In particular, the present invention is thinner than a conventional printed circuit board and can solve the problem of poor adhesion of bumps due to air pockets (Voids) in blind via holes (hereinafter referred to as BVH). It relates to a printed circuit board and a method for manufacturing the printed circuit board. [0002] [Conventional technology] In a conventional multilayer printed circuit board, as shown in FIG. 15, a large number of resin layers 3a and 3b are laminated and formed by a built-up method, and a circuit pattern 5a of a thin metal plate layer is formed on the upper surfaces of the resin layers 3a and 3b. 5b and 5c are formed. Then, a plurality of blind via holes 7 penetrating the resin layers 3a and 3b are formed in order to connect the upper layer circuit pattern 5c and the lower layer circuit pattern 5a. [0003] At this time, each via hole 7 is formed in an inverted conical shape in which the diameter on the inlet side is larger than the diameter on the bottom surface, and in the via hole 7, the inlets of the upper layer via hole 7b and the lower layer via hole 7a are all oriented in the same direction (upward in the figure). Is formed in. Further, since a plating layer 9 is formed on the inner wall of each blind via hole 7 and the plating layer 9 extends to the upper surface of the upper layer circuit pattern 5c and the lower layer circuit pattern 5a, the upper layer circuit pattern 5c and the lower layer circuit pattern 5a are plated. It is electrically connected by layer 9. [0004] An inner lead bump 11 that is electrically connected to a semiconductor chip component is attached to the upper portion of the plating layer 9b on the upper surface of the upper blind via hole 7b, and the upper surface of the plating layer 9 excluding the attachment portion of the inner lead bump 11 is attached. A solder resist layer 12 is formed on the upper surface of the resin layer 3b. That is, in the conventional multilayer printed circuit board, the inner lead bump 11 is attached to the inside of the blind via hole. [0005] Hereinafter, a method of manufacturing a conventional printed circuit board having such a configuration will be described. First, a copper-covered thin plate (Copper Clad Laminate; hereinafter referred to as CCL) coated with an upper metal thin plate 4a and a lower metal thin plate 4b on the upper and lower surfaces of the lower resin layer 3a is prepared, respectively, and the upper metal thin plate 4a and the lower layer resin are prepared. After the layer 3a is engraved to form the lower layer blind via hole 7a, the lower layer plating layer 9a is formed on the upper surface and the side wall surface and the bottom surface of the upper layer metal thin plate 4a, and the upper and lower metal thin plates 4a and 4b are formed. After being electrically connected, the upper metal thin plate 4a and the lower plating layer 9a are patterned to form the lower circuit pattern 5a. [0006] Next, the upper resin layer 3b and the metal film 4c are formed on the upper surface of the lower plating layer 9a and the upper surface of the exposed lower resin layer 3a. Next, the metal film 4c and the upper resin layer 3b are partially eaten to form the upper blind via hole 7b. At this time, the upper surface of the lower plating layer 9a is exposed by the upper blind via hole 7b. [0007] Next, after forming the upper plating layer 9b on the upper surface of the metal film 4c, the inner wall surface of the upper blind via hole 7b, and the upper surface of the lower plating layer 9a exposed on the bottom surface of the upper blind via hole 7b, the upper plating layer 9b and the metal film are formed. Pattern 4c. At this time, the patterned metal film 4c becomes the upper layer circuit pattern 5c. Further, the upper layer circuit pattern 5c and the lower layer plating layer 9a are electrically connected by the upper layer plating layer 9b. [0008] Next, the solder resist layer 12 is formed on the upper surfaces of the upper plating layer 9b and the exposed upper resin layer 3b excluding the inside of the upper blind via hole 7b. At this time, the upper surface of the upper plating layer 9b exposed without being covered by the solder resist layer 12 is a pad portion for attaching bumps for mounting chip components. [0009] Next, the inner lead bump 11 was attached to the upper surface of the upper plating layer 9b in the upper blind via hole 7b, that is, to the pad portion, and the production of the printed circuit board was completed. [0010] [Problems to be Solved by the Invention] However, such a conventional method for manufacturing a printed circuit board has the following inconveniences. First, when the bump 11 is formed on the upper part of the upper blind via hole 7b, the air in the upper blind via hole 7b is not discharged to the outside, so that the air pocket (Void) 14 is formed or the air is bumped 11 It moves in and remains, so the heat generated when mounting chip components on a printed circuit board and the high heat generated during product use causes the air in the air pockets in the blind via holes or bumps to expand. This has the disadvantage of damaging the packaging state of the chip components of the printed circuit board, such as causing cracks in the printed circuit board around the bumps and deteriorating the adhered state of the chip components. [0011] Secondly, in order to solve the above-mentioned problems, bumps are implemented by designing the pad by extending it to the periphery of the blind via hole, as presented in Japanese Patent Publication No. 10-284846. A method of avoiding blind via holes was adopted as the position, but this method had an inconvenience of increasing the size of the printed circuit board. [0012] Third, Flip In the manufacturing process of Chip), in the process of filling the chip and the printed circuit board with an underfiller for correcting the difference in the coefficient of thermal expansion between the chip mounted on the printed circuit board and the printed circuit board. Since the underfiller is not completely filled in the blind via hole 7, there is an inconvenience that the printed circuit board is deformed due to thermal impact. [0013] Fourth, when forming a soft printed circuit board, if the wall thickness of the resin layer is too thin, it is very inconvenient to handle during the manufacturing process and the yield decreases, so the resin layer should be formed thick. Therefore, there is an inconvenience that the wall thickness of the printed circuit board cannot be reduced. The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a soft printed circuit board of an ultra-thin plate. [0014] Another object of the present invention is to provide a printed circuit board in which the circuit pattern formed on the outer layer of the printed circuit board is relatively finely divided. Another object of the present invention is to provide a printed circuit board characterized in that an inner lead bump as an inner lead is formed on the opposite side of the opening of the blind via hole. [0015] Another object of the present invention is to provide a printed circuit board characterized in that the opening of the blind via hole is formed so as to face the central portion of the printed circuit board rather than the outer surface. Further, another object of the present invention is to form the thickness of the upper surface circuit pattern of the printed circuit board on which the chip components are mounted and connected to be thinner than the thickness of the lower surface circuit pattern connected to the main PCB side. An attempt is made to provide a characteristic printed circuit board. [0016] [Means for solving problems] In order to achieve such an object, in the multilayer printed circuit board according to the present invention, in the printed circuit board in which a plurality of insulating resin layers and a plurality of circuit pattern layers are alternately and sequentially laminated to form a plurality of layers. A plurality of insulating resin layers, a plurality of circuit patterns formed on the upper surfaces of the insulating resin layers, a plurality of blind via holes formed so as to penetrate each insulating resin layer and the circuit pattern, and an upper surface of each circuit pattern. The plating layer formed on the inner wall surface and the bottom surface of each via hole, the lower surface of the plating layer formed on the bottom surface of each blind via hole, and the lower surface of each insulating resin layer are formed so as to form the same plane. A plurality of inner lead bump pads attached to the lower surface of the plating layer formed on the bottom surface, and a plurality of inner lead bumps attached to each inner lead bump pad almost directly above the center of each blind via hole. It is configured to include a plurality of outlead bump pad portions formed on each circuit pattern formed on the upper surface of each insulating resin layer. [0017] Then, in order to achieve the object, in the printed circuit board according to the present invention, a plurality of laminated resin layers, a plurality of circuit patterns formed on the upper surface of the resin layers, and a plurality of circuit patterns formed between the circuit patterns. A first substrate composed of a plurality of blind via holes, a plating layer formed on an inner wall surface of the blind via holes and an upper surface of each circuit pattern, a plurality of laminated resin layers, and these resin layers. A plurality of circuit patterns formed on the upper surface of the circuit board, a plurality of blind via holes formed between the circuit patterns, and a plating layer formed on the inner wall surface of the blind via holes and the upper surface of each circuit pattern. It is characterized in that the blind via hole of the first substrate and the blind via hole of the second substrate are arranged so as to face each other. [0018] Moreover, in order to achieve the object, in the method for manufacturing a multilayer printed circuit board according to the present invention, a printing circuit in which a plurality of insulating resin layers and a plurality of circuit pattern layers are alternately and sequentially laminated to form a plurality of layers. In the substrate, a plurality of insulating resin layers, a plurality of upper layer circuit patterns formed on the upper surface of the insulating resin layers, a plurality of lower layer circuit patterns formed on the lower surface of each insulating resin layer, and each insulating resin layer and the upper layer. A plurality of blind via holes formed so as to penetrate the circuit pattern, a plating layer formed on the upper surface of each upper layer circuit pattern, an inner wall surface and a bottom surface of each via hole, and a plurality of inner leads formed in each lower layer circuit pattern. It was formed on the bump pad, a plurality of inner lead bumps attached to each inner lead bump pad almost directly above the center of each blind via hole, and the upper surface of the plating layer formed on the upper surface of each upper layer circuit pattern. It is configured to include a plurality of out-lead bump pads, and each inner lead bump pad is characterized in that it is directly adhered to a plating layer formed on the bottom surface of each blind via hole. [0019] Further, in order to achieve the object, in the BGA semiconductor package according to the present invention, a plurality of insulating resin layers, a plurality of circuit patterns formed on the upper surfaces of the insulating resin layers, and each insulating resin layer and the circuit pattern are provided. A plurality of blind via holes formed so as to penetrate, a plating layer formed on the upper surface of each circuit pattern, an inner wall surface and a bottom surface of each via hole, and a plating layer surface exposed on the lower surface of each insulating resin layer. A plurality of inner lead bump pad portions and a plurality of out lead bump pad portions formed on each circuit pattern formed on the upper surface of each insulating resin layer are provided. The multilayer printed circuit board, a plurality of inner lead bumps attached to the surface of each inner lead bump pad, the semiconductor chip attached to the inner lead bump, and the surface of each out lead bump pad are attached. It is characterized in that it is configured to include a plurality of outlead bumps. [0020] Further, in order to achieve the object, in the method for manufacturing a multilayer printing circuit board according to the present invention, a step of locating a deformed member on one side surface of a core forming resin layer, and a step of positioning the deformed member and the core forming resin layer. On the other hand, a step of sequentially laminating a first metal thin plate layer and a first insulating resin layer on the side surface, and a stage of forming a first blind via hole by engraving the first insulating resin layer so that the first metal thin plate layer is exposed. , The stage of forming the first circuit pattern on the upper surface of the first insulating resin layer, and the stage of forming the first plating layer on the upper surface of the first circuit pattern, the inner wall surface of the first blind via hole, and the upper surface of the first metal thin plate layer. And the stage where the second insulating resin layer and the second metal thin plate layer are sequentially laminated on the upper surfaces of the first insulating resin layer and the first plating layer, and the second insulating resin layer and the second insulating resin layer so that the upper surface of the first plating layer is exposed. The stage of forming the second blind via hole by engraving the second metal thin plate layer, the stage of forming the second plating layer on the upper surface of the second metal thin plate layer, the inner wall surface and the bottom surface of the second blind via hole, and the second. The stage of patterning the metal thin plate layer to form the second circuit pattern, the stage of separating the core forming resin layer and the deformed member from the first metal thin plate layer, and the stage of patterning the first metal thin plate layer for the inner lead bump. It is characterized in that the steps of forming the pad portion and the steps are sequentially performed. [0021] [0021] Then, in order to achieve the object, in the method for manufacturing a multilayer printing circuit board according to the present invention, a deformed member smaller than the core forming resin layer is positioned on one surface of the core forming resin layer, and the upper surface of the deformed member is formed. After laminating the first metal thin plate, the first insulating resin layer, and the second metal thin plate, which are larger than the deformed member, in order, the core forming resin and the first insulating resin layer or the first metal thin plate are bonded to form a panel. The stage of forming a blind via hole so as to penetrate the first insulating resin layer and the second metal thin plate of the panel, and the first metal for electrically connecting the first metal thin plate and the second metal thin plate. The stage of forming a conductive layer on the inner wall surface of the thin plate, the second metal thin plate and the blind via hole, the stage of patterning the second metal thin plate and the conductive layer to form a circuit pattern, and the core forming resin layer and the deformed member. At the stage of removal, the first metal thin plate separated from the deformed member is patterned to form the inner lead bump pad portion. At this time, at least one of the inner lead bump pad portions is the bottom surface portion of the blind via hole. It is characterized in that the steps of forming the inner lead bump pad portion so as to be formed in the above are sequentially performed. [0022] Moreover, in order to achieve the object, in the method for manufacturing a multilayer printing circuit board according to the present invention, deformed members smaller than the core forming resin layer are positioned on both surfaces of the core forming resin layer, and these deformed members are positioned. After laminating the first metal thin plate, the first insulating resin layer, and the second metal thin plate, which are larger than the deformed member, on each upper surface of the above, the core forming resin and the first insulating resin layer or the first metal thin plate are bonded to each other. To electrically connect the first metal thin plate and the second metal thin plate at the stage of forming the panel, the stage of forming the blind via hole so as to penetrate the first insulating resin layer and the second metal thin plate of the panel, and the stage of forming the first metal thin plate and the second metal thin plate. The stage of forming a conductive layer on the inner wall surface of the first metal thin plate, the second metal thin plate and the blind via hole, the stage of patterning the second metal thin plate and the conductive layer to form a circuit pattern, and the core forming resin layer and irregular shape. By removing the members, the structures formed on both surfaces of the core forming resin layer are separated and separated into a first substrate and a second substrate, respectively, and the first metal thin plate of the first substrate is patterned. At this time, at least one of the inner lead bump pad portions is formed at the stage of forming the inner lead bump pad portion so as to be formed on the bottom surface portion of the blind via hole. , Are sequentially performed. [0023] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the first embodiment of the printed circuit board according to the present invention, as shown in FIG. 1, the first resin layer 21a and the second resin layer 21b are vertically laminated and formed on the upper surface of the first resin layer 21a. The first circuit pattern 22a is formed, and the first blind via hole 23a is formed so as to penetrate the first resin layer 21a. At this time, the first blind via hole 23a is formed in an inverted conical shape in which the diameter on the inlet side (upper side) is larger than the diameter on the bottom surface. On the other hand, the first plating layer 24a is formed on the upper surface of the first circuit pattern 22a and the inner wall surface and the bottom surface of the first blind via hole 23a, and the lower surface of the first plating layer 24a formed on the bottom surface of the first blind via hole 23a is formed. It has the same plane as the lower surface of the first resin layer 21a. On the other hand, a second circuit pattern 22b is formed on the upper surface of the second resin layer 21b, and a second blind via hole 23b is formed so as to penetrate the second resin layer 21b. At this time, the second blind via hole 23b is formed on the first circuit pattern 22a so that the first plating layer 24a formed on the upper surface of the first circuit pattern 22a is exposed by the second blind via hole 23b. A second plating layer 24b is formed on the upper surface of the second circuit pattern 22b, the inner wall surface of the second blind via hole 23b, and the upper surface of the first plating layer 24a exposed by the second blind via hole 23b. On the other hand, a third circuit pattern 22c is formed on the lower surface of the first resin layer 21a, and an inner lead bump pad for attaching an inner lead bump for electrically connecting the semiconductor chip component and the printed circuit board 20. Part 22d is formed on the surface of the third circuit pattern 22c. [0024] In this embodiment, a printed circuit board in which two resin layers of a first resin layer 21a and a second resin layer 21b are laminated is shown, but depending on the purpose of use, two or more layers of resin layers are laminated. Can form a printed circuit board. It is also possible to form a solder resist layer on the surface of the printed circuit board 20 in order to protect each circuit pattern of the printed circuit board 20. Specifically, as shown in FIG. 2, the first resin layer 21a The first solder resist layer 25a is formed on the lower surface and a part of the surface of the third circuit pattern 22c, and the exposed part of the third circuit pattern 22c that is not covered by the first solder resist layer 25a is a chip component. It is a pad portion 22d for attaching an inner lead bump for electrically connecting to the printed circuit board 20. Further, a second solder resist layer 25b is formed on the upper surface of the second resin layer 21b and the upper surface of the second plating layer 24b formed inside the second blind via hole 23b. The exposed portion of the second plating layer 24b that is not covered by the second solder resist layer 25b is an outlead for attaching outlead bumps for electrically connecting the main PCB and the printed circuit board 20. The bump pad portion 24c. The inside of the second blind via hole 23b is completely filled with the second solder resist layer 25b. [0025] In FIG. 2, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. FIG. 3 shows a form in which the out-lead bump 26 and the inner lead bump 27 are attached to the printed circuit board shown in FIG. 2. Here, the inner lead bump 27 is connected to the chip component 28. The outlead bump means a bump for connecting to a main PCB board (that is, a main board of an electronic device). [0026] Specifically, the inner lead bump 27 is formed on the upper surface of the inner lead bump pad portion 22d of the third circuit pattern 22c formed on the opposite surface of the opening of the first blind via hole 23a, and the inner lead bump 27 is formed on the upper surface of the inner lead bump 27. (ball grid array) A semiconductor chip 28 is attached. Further, the outlead bump 26 is attached to the upper surface of the outlead bump pad portion 24c on the forming surface of the opening of the second blind via hole 23b. Here, the out-lead bump pad portion 24c is formed larger than the inner lead bump pad portion 22d, and the out-lead bump 26 is formed larger than the inner lead bump 27. The reason is that the size of the chip component connected to the inner lead bump 27, that is, the semiconductor element is the same or reduced due to the densification and integration, but the outside of the semiconductor chip component. Since the number of terminals is increasing, the distance between each terminal is reduced. Therefore, although the inner lead bump pad portion 22d of the printed circuit board 20 is also miniaturized, the size of the main PCB board side does not change relatively. [0027] Further, in the second embodiment of the printed circuit board according to the present invention, as shown in FIG. 4, the two printed circuit boards shown in FIG. 1 are opposed to each other with the central core resin layer 30 interposed therebetween. It is in the form of being adhered to the upper and lower surfaces of the core resin layer 30. Specifically, the printed circuit board attached to the lower part of the core resin layer 30 is referred to as the first substrate 20a, and the printed circuit board attached to the upper part of the core resin layer 30 is referred to as the second substrate 20b. The two substrates 20a and 20b are attached to the core resin layer 30 so that the openings of the second blind via holes 23b face each other so as to face the core resin layer 30. At this time, all the second blind via holes 23b are filled with the core resin layer 30. That is, since the blind via hole 23b is not exposed on the surface side of the printed circuit board, it is possible to solve the problem of defects caused by the formation of the air pocket in the conventional blind via hole. [0028] On the other hand, a plurality of third circuit patterns 22c are formed on the outer surfaces of the first substrate 20a and the second substrate 20b, and a solder is formed on a part of the upper surface of the third circuit pattern 22c and the surface of the first resin layer 21a. A resist layer 40 is formed to insulate between each third circuit pattern 22c. Further, in order to electrically connect the first substrate 20a and the second substrate 20b, through holes 42 penetrating the first and second substrates 20a and 20b and the core resin layer 30 are formed, and the through holes 42 are formed. A plating layer 44 for connecting between substrates is formed on the inner wall surface, and at this time, the plating layer 44 for connecting between substrates is formed on the surfaces of the third circuit pattern 22c and the second substrate 20b formed on the surface of the first substrate 20a. It is extended to the upper surface of the third circuit pattern 22c and electrically connects the first substrate 20a and the second substrate 20b. At this time, the solder resist layer 40 is filled in the central portion of the through hole 42. [0029] In FIG. 4, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. Hereinafter, the manufacturing method of the first embodiment of the printed circuit board according to the present invention will be described with reference to the drawings. First, as shown in FIG. 5 (A), the deformed film F is positioned on the upper and lower surfaces of the core forming prepreg (P). Here, the prepreg P is a plate-shaped film, and the deformed film is smaller than the prepreg P. Then, copper-covered laminated plates (Copper Clad Laminate; CCL) 60a and 60b coated with copper foil on both sides are positioned on the outer surface side of each deformed film F, respectively. Here, the copper-covered laminated plates 60a and 60b are composed of a first resin layer R1 and first and second copper thin plates C1 and C2 coated on both surfaces of the first resin layer R1. [0030] In the figure, reference numeral 60a is a copper-covered laminated plate located on the upper surface of the prepreg P, and reference numeral 60b is a copper-covered laminated plate located on the lower surface of the prepreg P. Next, when the components shown in FIG. 5 (A) were arranged and heated and pressurized, the core-forming prepreg P melted and the copper covering on the upper and lower surfaces was formed as shown in FIG. 5 (B). A single panel in which the laminated plates 60a and 60b are bonded is formed. At this time, the copper-covered laminated plates 60a and 60b do not adhere to each other at the portions to which the deformed films F are attached, and only the portions to which the deformed films F are not attached, that is, the edges, are adhered to each other. After the heat treatment, the prepreg P is hardened, which facilitates panel handling during the subsequent printed circuit board process. [0031] Next, as shown in FIG. 6 (A), the first copper-covered laminated plates 60a and 60b located above and below the prepreg P penetrate the second copper thin plate C2 and the first resin layer R1. Form a blind beer hole 61. At this time, the first blind via hole 61 is formed by using a laser, but if a laser that cannot process copper is used, the second copper thin plate C2 on the surface is removed by an etching process to remove the window. After forming, the first resin layer R1 is removed by laser processing. Further, the reason why the side surface in the first blind via hole 61 is processed diagonally is to smoothly perform the subsequent plating process. The copper-covered laminated plate 60a on the upper side and the copper-covered laminated plate 60b on the lower side of the prepreg P are processed so as to face each other. [0032] Next, as shown in FIG. 6B, the upper surface of the first copper thin plate C1 exposed on the inner side surface 61a of the first blind via hole 61 and the bottom surface 61b of the first blind via hole 61, and the second copper thin plate C2. The first plating layer 62 is formed on the surface of the first copper thin plate C1 and the second copper thin plate C2 is formed in an electrically conductive state. Next, as shown in FIG. 7A, the first plating layer 62 and the second copper thin plate C2 are patterned in the same pattern by a normal etching method or the like to form the first circuit pattern 63. At this time, the first resin layer R1 is exposed at the portion where the first plating layer 62 and the second copper thin plate C2 are removed. [0033] Next, as shown in FIG. 7 (B), on the structure shown in FIG. 7 (A), the second resin layer R2 and the second resin layer R2 and the first on the upper surface of the first circuit pattern 63 and the first resin layer R1 on the lower surface. 3 Laminate each of the thin copper plates C3. At this time, the second resin layer R2 and the third copper thin plate C3 can be laminated separately, and the second resin layer R2 is coated with the third copper thin plate C3 (Resin coated copper). foil; hereinafter RCC) can also be used. [0034] Then, as shown in FIG. 8A, FIG. 7 so that the second resin layer R2 and the third copper thin plate C3 adhere to the panel on which the first resin layer R1 and the first circuit pattern 63 are formed. When the structure shown in (B) is heated and pressurized, the first resin layer R1 and the second resin layer R2 are melted and integrated with each other. Then, as shown in FIG. 8B, a laser is used to form a second blind via hole 64 that penetrates the third copper sheet C3 and the second resin layer R2. At this time, the second blind via hole 64 is also formed so as to have an oblique side wall 64a, and the upper surface of the first plating layer 62 is exposed on the bottom surface 64b of the second blind via hole 64. [0035] Next, as shown in FIG. 9A, the second plating layer 65 is formed on the inner side wall 64a and the bottom surface 64b of the second blind via hole 64 and the entire upper surface of the third copper thin plate C3. Next, as shown in FIG. 9B, the third copper thin plate C3 and the second plating layer 65 are patterned to form the second circuit pattern 66. In the steps up to this point, an example has been described in which the same process is simultaneously performed on both the upper and lower sides of the prepreg P, but after the manufacturing process is performed on only one side, the same manufacturing process is sequentially performed on the other side. A way to proceed is also possible. [0036] Then, as shown in FIG. 10 (A), both ends of the panel shown in FIG. 9 (B) are cut off. That is, it is cut along both ends of the deformed film F. Next, as shown in FIG. 10B, the upper and lower substrates are separated from the deformed film F and the prepreg P at the center to form two printed circuit boards at the same time. For convenience of explanation, the lower substrate of the prepreg P is the first substrate 67a, the upper substrate is the second substrate 67b, and the surfaces on which the second blind via hole 64 is formed are the surfaces of the first and second substrates 67a and 67b. The upper surface is 67c, and the flat surface in contact with the deformed film F is the lower surface 67d. [0037] Next, as shown in FIG. 11, the first copper thin plate C1 on the lower surface 67d of any one of the first substrate 67a and the second substrate 67b is patterned to form the third circuit pattern 68. At this time, since the additional plating layer does not exist, only the thickness of the first copper thin plate C1 is etched, so that the thickness of the copper thin film to be removed by the etching process is thin and a fine circuit pattern is formed. There is a merit that it can be done. [0038] Next, a solder resist layer 69 is formed on a part of the upper surface of the third circuit pattern 68 and a part of the upper surface of the second plating layer 65 on the upper surface of the second circuit pattern 66 by a usual method. At this time, the exposed portion of the third circuit pattern 68 becomes the inner lead bump pad portion 68a, and the exposed portion of the second plating layer 65 becomes the out lead bump pad portion 66a. Therefore, the inner lead bump pad portion 68a is located substantially directly above the first blind via hole 61 in the first and second substrates 67a and 67b. [0039] Next, although not shown, an outlead bump for connecting to the main PCB is attached to the outlead bump pad portion 66a on the upper surface of the second circuit pattern 66, and for the inner lead bump on the upper surface of the third circuit pattern 68. The step of attaching the inner lead bump for connecting to the chip component to the pad portion 68a is executed. Then, the manufacturing method of the second embodiment of the printed circuit board according to the present invention will be described with reference to the drawings. [0040] First, as shown in FIG. 12 (A), the first and second substrates 67a and 67b manufactured via the steps shown in FIGS. 5 (A) to 10 (B) are prepared, and a soft preg is prepared. Arrange so that the openings of the blind via holes 64 of the first and second substrates 67a and 67b face each other with the FP in between. At this time, the shapes of the first and second substrates 67a and 67b do not have to be the same, and the second substrate 67b having a different structure can be formed after the first substrate 67a is manufactured first. [0041] Next, as shown in FIG. 12 (B), the structure of FIG. 12 (A) is heated and pressurized, and the first substrate 67a and the second substrate 67b are adhered to the soft plug FP to form an integrated panel. To manufacture. Here, the soft preg FP becomes the core resin layer FP. Next, as shown in FIG. 13A, a through hole 70 penetrating the first substrate 67a, the second substrate 67b, and the core resin layer FP is formed. [0042] Next, as shown in FIG. 13B, an inter-board connection plating layer 73 is formed on the wall surface of the through hole 70 and the outer surface layers of the first substrate 67a and the second substrate 67b. At this time, the inter-board connection plating layer 73 formed along the inner wall surface of the through hole 70 functions to electrically connect the first substrate 67a and the second substrate 67b. Next, as shown in FIG. 14A, the inter-board connection plating layer 73 and the first copper thin plate C1 are sequentially subjected to photolithography, phenomena, and etching steps to pattern them to form a circuit pattern 74. [0043] Next, as shown in FIG. 14 (B), a solder resist layer 75 is formed on a part of the upper surface of the inter-board connection plating layer 73 and on the upper surface of the first resin layer R1, and at the same time, the inside of the through hole 70 is also a solder resist. The layer 75 is filled, and the production of the printed circuit board according to the present invention is completed. Here, in the inter-board connection plating layer 73, the portion exposed without being covered by the solder resist layer 75 is the outlead bump pad portion and the inner lead bump pad portion of the printed circuit board. That is, after the solder resist layer 75 is formed, the inner lead bump pad portion 76 is formed on the upper surface of the inter-board connection plating layer 73 of the first substrate 67a, and the upper surface of the inter-board connection plating layer 73 of the second substrate 67b is formed. Since the out-lead bump pad portion 77 is formed in, the inner lead bump pad portion 76 and the out-lead bump pad portion 77 are substantially directly above the blind via holes 64 in the first and second substrates 67a and 67b. Located in. [0044] [Effect of the invention] As described above, in the multilayer printed circuit board and the manufacturing method thereof according to the present invention, and in the BGA semiconductor package using the multilayer printed circuit board, since the printed circuit board is manufactured by using the prepreg P as a support plate, the resin layer is used. Even if the wall thickness is as thin as 100 μm or less, it is extremely easy to handle and has the effect of reducing the overall thickness of the printed circuit board. [0045] Further, in the multilayer printed circuit board and the manufacturing method thereof according to the present invention and the BGA semiconductor package using the multilayer printed circuit board, all the openings of the blind via holes are manufactured toward the core resin layer, so that the printed circuit board It is not exposed to the outer surface of the circuit board, and therefore, when mounting the component, there is an effect that the conventional problem that the adhesion state of the bump is deteriorated due to the air pocket formed in the blind via hole can be solved. [0046] Moreover, in the multilayer printed circuit board and the manufacturing method thereof according to the present invention, and in the BGA semiconductor package using the multilayer printed circuit board, when forming the pad for adhering the inner lead bump, only a thin copper thin plate is etched. Therefore, there is an effect that the circuit pattern can be formed finely. [Simple explanation of drawings] FIG. 1 is a vertical cross-sectional view showing a first embodiment of a printed circuit board according to the present invention. 2 is a vertical cross-sectional view showing a state in which a solder resist layer is formed on the printed circuit board of FIG. 1. FIG. 3 is a vertical cross-sectional view showing a state in which solder bumps are attached to the substrate of FIG. 2. FIG. FIG. 4 is a vertical cross-sectional view showing a second embodiment of the printed circuit board according to the present invention. 5 (A) and 5 (B) are process vertical cross-sectional views (No. 1) showing a manufacturing process of the first embodiment of the printed circuit board according to the present invention. 6 (A) and 6 (B) are process vertical cross-sectional views (No. 2) showing the manufacturing process of the first embodiment of the printed circuit board according to the present invention. 7 (A) and 7 (B) are process vertical cross-sectional views (No. 3) showing a manufacturing process of the first embodiment of the printed circuit board according to the present invention. 8 (A) and 8 (B) are process vertical cross-sectional views (No. 4) showing the manufacturing process of the first embodiment of the printed circuit board according to the present invention. 9 (A) and 9 (B) are process vertical cross-sectional views (No. 5) showing the manufacturing process of the first embodiment of the printed circuit board according to the present invention. 10 (A) and 10 (B) are process vertical cross-sectional views (No. 6) showing the manufacturing process of the first embodiment of the printed circuit board according to the present invention. FIG. 11 is a process vertical cross-sectional view (No. 7) showing a manufacturing process of the first embodiment of the printed circuit board according to the present invention. 12 (A) and 12 (B) are process vertical cross-sectional views (No. 1) showing a manufacturing process of the second embodiment of the printed circuit board according to the present invention. 13 (A) and 13 (B) are process vertical cross-sectional views (No. 2) showing the manufacturing process of the second embodiment of the printed circuit board according to the present invention. 14 (A) and 14 (B) are process vertical cross-sectional views (No. 3) showing the manufacturing process of the second embodiment of the printed circuit board according to the present invention. FIG. 15 is a vertical cross-sectional view showing a conventional printed circuit board. [Explanation of symbols] 20 ... printed circuit board 20a ... 1st board 20b ... 2nd board 21a ... 1st resin layer 21b ... 2nd resin layer 22a ... 1st circuit pattern 22b ... 2nd circuit pattern 22c ... 3rd circuit pattern 22d ... Inner lead bump pad 23a ... 1st blind beer hall 23b ... 2nd blind beer hall 24a ... 1st plating layer 24b ... 2nd plating layer 24c ... Pad part for out lead bump 25a ... 1st solder resist layer 25b ... 2nd solder resist layer 26 ... Outlead bump 27 ... Inner lead bump 28 ... BGA semiconductor chip parts 30 ... Core resin layer 40 ... Solder resist layer 42 ... Through hole 44 ... Plating layer for connecting boards 60a, 60b ... Copper-covered laminate 61 ... 1st blind beer hall 62 ... 1st plating layer 63 ... 1st circuit pattern 64 ... 2nd blind beer hall 65 ... 2nd plating layer 66 ... 2nd circuit pattern 67a ... 1st board 67 ... 2nd board 68 ... 3rd circuit pattern 69 ... Solder resist layer 71 ... Through hole 73 ... Plating layer for connecting boards 74 ... circuit pattern 75 ... Solder resist layer