Ram control device and memory device using the same

The present invention relates to a RAM control device that controls access to RAM [Random Access Memory], and a memory device using the RAM control device.

Conventionally, when it is necessary to control access to RAM according to two access clocks that are input asynchronously to each other, in general, dual-port RAM is often adopted as a memory device. The above-mentioned dual-port RAM refers to a RAM having two input / output interfaces (generally, two systems for writing and reading) with respect to a storage unit in a memory device.

In the prior art related to the present invention, the control signals for reading and writing from the two control devices are set as control signals having a clock cycle width synchronized with the internal clock, and the controlled controls are synchronized from both control devices. A dual port RAM circuit that accesses a 1-port type RAM unit in a time-divided manner by delaying one of the control signals by one clock when the signals have the same timing has been disclosed and proposed (Patent Documents). See 1).

Further, as another conventional technique related to the present invention, the clock for the firmware control unit is replaced with the clock for the main signal control unit at the inter-clock arbitration unit at different speeds, and the timing signal from the timing signal generation unit is mainly used. A system control device for in-device clock asynchronous so that access to the information storage unit from the signal control unit and the firmware control unit is time-divided and does not conflict has been disclosed / proposed (see Patent Document 2).<patcit num="1"><text>Japanese Patent Application Laid-Open No. 6-161870</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2000-341255</text></patcit>

<p> Certainly, if dual-port RAM is adopted as a memory device, it is possible to appropriately control access to RAM according to two access clocks that are input asynchronously to each other.</p><p> However, the dual-port RAM has a larger chip area than the single-port RAM having only one input / output interface, which has led to an increase in the scale of the device and an increase in cost.</p><p> On the other hand, when single-port RAM is used as the memory device, since the access clocks of the two systems are asynchronous, there is a risk that the RAM may not be accessed normally depending on the input timing of both access clocks.</p><p> The prior art of Patent Document 1 does not directly access the RAM using an external control signal, but transfers the control signal to the internal clock signals C1 and C2 before accessing the RAM. It was. Therefore, in the prior art of Patent Document 1, an oscillation circuit that generates internal clock signals C1 and C2 is separately required, which causes an increase in circuit scale and power consumption, and depending on the performance of the oscillation circuit, the operating specifications may be changed. There was a risk of affecting it.</p><p> Further, the prior art of Patent Document 2 has a configuration in which one control signal (for example, a low-speed clock) is replaced with the other control signal (for example, a high-speed clock) to access the RAM. Therefore, the prior art of Patent Document 2 is a technique that can be applied only to an application in which the other control signal, which is the transfer destination of one control signal, is always operating.</p><p> In view of the above problems, the present invention can appropriately control access to RAM according to two access clocks that are input asynchronously to each other while suppressing an increase in device scale and cost. It is an object of the present invention to provide a RAM control device and a memory device using the same.</p>

<p> In order to achieve the above object, the RAM control device according to the present invention includes an arbiter circuit and a one-shot circuit, and responds to two systems of first and second access clocks that are input asynchronously to each other. The arbiter circuit is a RAM control device that controls access to the RAM, and the arbiter circuit generates first and second busy signals having mutually exclusive logic according to the first and second access clocks described above. By doing so, the host that sent out the earliest access clock is granted the access right to the RAM, and the one-shot circuit is generated as the RAM clock for determining the access timing to the RAM. The one-shot circuit is a means for generating only one pulse of the RAM clock in response to the clock request signal of the arbiter circuit and sending it to the RAM (first configuration). ).</p><p> In the RAM control device having the first configuration, the RAM clock is a clock having a period within 1/2 of the faster cycle of the first or second access clock (second). Configuration) is recommended.</p><p> Further, in the RAM control device having the first or second configuration, in the arbiter circuit, the first access clock is input to the clock input end, a predetermined logic signal is input to the data input end, and the reset end is the first. 1 The request reset signal is input and the 1st request signal is drawn from the output end with the 1D flip flop; the 1st busy signal is input to one input end and the RAM clock is input to the other inverting input end. The first logic product circuit from which the first request reset signal is drawn from the output end; the first request signal is input to one input end, the second busy signal is input to the other inverting input end, and the first from the output end. With the second logic product circuit from which the access start signal is drawn; the RAM clock is input to the clock input end, the predetermined logic signal is input to the data input end, the first access start signal is input to the set input end, and the output end. With the 2D flip flop from which the 1st busy signal is drawn from; the 2nd access clock is input to the clock input end, the predetermined logic signal is input to the data input end, the 2nd request reset signal is input to the reset end, and the output. With a 3D flip flop from which the 2nd request signal is drawn from the end; the 2nd busy signal is input to one input end, the RAM clock is input to the other inverting input end, and the 2nd request reset signal is output from the output end. The third logic product circuit to be extracted; the second request signal is input to one input end, the first busy signal is input to the other inverting input end, and the second access start signal is extracted from the output end. With the product circuit; the RAM clock is input to the clock input end, a predetermined logic signal is input to the data input end, the second access start signal is input to the set input end, and the second busy signal is extracted from the output end. It has a 4D flip flop; a logical sum circuit in which the first access start signal is input to one input end, the second access start signal is input to the other input end, and the clock request signal is extracted from the output end. It is advisable to make a configuration consisting of (third configuration).</p><p> Further, in the RAM control device having the third configuration, the predetermined logic signals input to the data input ends of the first and third D flip-flops are each inverted output signals (fourth configuration). It is good to do.</p><p> Further, in the RAM control device having the third or fourth configuration, a second busy signal is input to the reset end of the second D flip-flop, or a first busy signal is input to the reset end of the fourth D flip-flop. It is preferable to use a configuration in which a signal is input (fifth configuration).</p><p> Further, in the RAM control device having the first configuration, the arbiter circuit is not intended as a busy signal of any one system based on the presence / absence of input of the first and second access clocks and the logic of the RAM clock. It is determined whether or not a legitimate access clock of another system has been input while a logical transition has occurred, and if it is determined that such a state has occurred, a busy signal that has caused an unintended logical transition is determined. It is preferable to use a configuration (sixth configuration) in which a busy signal of another system is changed to a desired logic according to a legitimate access clock without depending on the above.</p><p> In the RAM control device having the sixth configuration, in the arbiter circuit described above, the first access clock is input to the clock input end, the predetermined logic signal is input to the data input end, and the first request reset is performed at the reset end. With the 1D flip flop where the signal is input and the 1st request signal is drawn from the output end; the 1st busy signal is input to one input end, the RAM clock is input to the other inverting input end, and the RAM clock is input from the output end. The first logic product circuit from which the first request reset signal is drawn; the first request signal is input to one input end, the second busy signal is input to the other inverting input end, and the first pre-signal is output from the output end. With the second logic product circuit to be extracted; the RAM clock is input to the clock input end, a predetermined logic signal is input to the data input end, the first access start signal is input to the set input end, and the first busy from the output end. With the 2D flip flop from which the signal is drawn; the 2nd access clock is input to the clock input end, the predetermined logic signal is input to the data input end, the 2nd request reset signal is input to the reset end, and the second from the output end. With the 3D flip flop from which the request signal is extracted; the 2nd busy signal is input to one input end, the RAM clock is input to the inverting input end of the other, and the 2nd request reset signal is extracted from the output end. With a logic product circuit; with a fourth logic product circuit where a second request signal is input to one input end, a first busy signal is input to the other inverting input end, and a second pre-signal is extracted from the output end; With the 4D flip flop, the RAM clock is input to the clock input end, the predetermined logic signal is input to the data input end, the second access start signal is input to the set input end, and the second busy signal is drawn from the output end. With a logic sum circuit in which the first access start signal is input to one input end, the second access start signal is input to the other input end, and the clock request signal is extracted from the output end;The first request signal is input to the first input end, the second request signal is input to the second inverting input end, the RAM clock is input to the third input end, and the first through signal is output from the output end. The 5th logic product circuit to be extracted; the 1st pre-signal is input to one input end, the 1st through signal is input to the other input end, and the 1st access start signal is extracted from the output end. With the circuit; the first request signal is input to the first inverting input end, the second request signal is input to the second input end, the RAM clock is input to the third input end, and the second from the output end. With the 6th logic product circuit from which the through signal is extracted; the 2nd pre-signal is input to one input end, the 2nd through signal is input to the other input end, and the 2nd access start signal is extracted from the output end. It is advisable to make a configuration (seventh configuration) having two logical sum circuits and;.</p><p> Further, in the RAM control device having the seventh configuration, the predetermined logic signals input to the data input ends of the first and third D flip-flops are each inverted output signals (eighth configuration). It is good to do.</p><p> Further, in the RAM control device having the seventh or eighth configuration, a second busy signal is input to the reset end of the second D flip-flop, or a first busy signal is input to the reset end of the fourth D flip-flop. It is preferable to use a configuration in which a signal is input (9th configuration).</p><p> Further, the RAM control device having the first configuration is arranged in front of the arbiter circuit, and one cycle of continuous pulse trains of the faster first access clock among the first and second access clocks. It consists of a clock division circuit that divides the clock into two systems in a form that is alternately distributed to each system, and the arbiter circuit has a total of three systems including the first access clock and the second access clock divided into two systems. It is advisable to configure the configuration (10th configuration) to generate three busy signals according to the access clock of.</p><p> In the RAM control device having the tenth configuration, the RAM clock is a clock having a period in which the arbitration chain between the first access clocks divided into two systems can be completed within one cycle of the second access clock. It is preferable to use the configuration (11th configuration).</p><p> Further, in the RAM control device having the tenth or eleventh configuration, one of the first access clocks divided into two systems is input to the clock input end of the arbiter circuit, and a predetermined logic signal is sent to the data input end. The first request reset signal is input to the reset end and the first request signal is drawn from the output end with the 1D flip flop; the first busy signal is input to one input end and the other inverting input end. With the first logic product circuit where the RAM clock is input and the first request reset signal is drawn from the output end; the first request signal is input to the first input end and the second busy signal is drawn to the second inverting input end. Is input, the third busy signal is input to the third inverting input end, and the first access start signal is extracted from the output end with the second logical product circuit; the RAM clock is input to the clock input end and data is input. A 2D flip flop where a predetermined logic signal is input to the end, a 1st access start signal is input to the set input end, and a 1st busy signal is drawn from the output end; The other of the access clocks is input, the predetermined logic signal is input to the data input end, the second request reset signal is input to the reset end, and the second request signal is drawn from the output end. With a third logic product circuit where a second busy signal is input at one end, the RAM clock is input at the other inverting input end, and a second request reset signal is drawn from the output end; a second request is made at the first input end. A fourth logical product in which a signal is input, a first busy signal is input to the second inverted input end, a third busy signal is input to the third inverted input end, and a second access start signal is extracted from the output end. Circuit: The RAM clock is input to the clock input end, a predetermined logic signal is input to the data input end, the second access start signal is input to the set input end, and the second busy signal is extracted from the output end. With flip flop;With the 5D flip flop, the 2nd access clock is input to the clock input end, the predetermined logic signal is input to the data input end, the 3rd request reset signal is input to the reset end, and the 3rd request signal is extracted from the output end. A third busy signal is input to one input end, the RAM clock is input to the other inverting input end, and a third request reset signal is extracted from the output end. The third request signal is input to, the first busy signal is input to the second inverting input terminal, the second busy signal is input to the third inverting input terminal, and the third access start signal is extracted from the output terminal. With the 6th logic product circuit; the RAM clock is input to the clock input end, the predetermined logic signal is input to the data input end, the 3rd access start signal is input to the set input end, and the 3rd busy signal is input from the output end. With the 6D flip flop being pulled out; the first access start signal is input to the first input end, the second access start signal is input to the second input end, and the third access start signal is input to the third input end. It is preferable to have a configuration (12th configuration) having a first logical sum circuit that is input and the clock request signal is extracted from the output terminal.The first access start signal is input to the first input end, the second access start signal is input to the second input end, the third access start signal is input to the third input end, and the clock is input from the output end. It is preferable to have a configuration (12th configuration) having a first logical sum circuit from which the request signal is extracted and;The first access start signal is input to the first input end, the second access start signal is input to the second input end, the third access start signal is input to the third input end, and the clock is input from the output end. It is preferable to have a configuration (12th configuration) having a first logical sum circuit from which the request signal is extracted and;</p><p> Further, in the RAM control device having the twelfth configuration, the predetermined logic signals input to the data input terminals of the first, third, and fifth D flip-flops are their own inverted output signals (thirteenth configuration). Configuration) is recommended.</p><p> Further, in the RAM control device having the twelfth or thirteenth configuration, a third busy signal is input to the reset end of the second and fourth D flip-flops, or a third busy signal is input to the reset end of the sixth D flip-flop. It is preferable to use a configuration (14th configuration) in which the logical sum signal of the first busy signal and the second busy signal is input.</p><p> Further, in the RAM control device having any of the tenth to fourteenth configurations, the arbiter circuit may have a configuration (fifteenth configuration) including the clock division circuit.</p><p> Further, the memory device according to the present invention has a configuration including a RAM control device having the above-mentioned first to fifteenth configurations and a RAM that operates in response to the RAM clock (sixteenth configuration). It is said that.</p>

<p> In the case of the RAM control device according to the present invention and the memory device using the same, the RAM can be input according to the access clocks of the two systems asynchronously input to each other while suppressing the expansion of the device scale and the cost increase. Access can be controlled appropriately.</p>

<figref num="1">Is a block diagram showing a first configuration example of the memory device according to the present invention.</figref><figref num="2">Is a block diagram showing an example of internal configurations of the arbiter circuit 1 and the output latch circuit 4.</figref><figref num="3">Is a state diagram (a) and a logical value table (b) for explaining the operation state transition of the arbiter circuit 1.</figref><figref num="4">Is a timing chart for explaining the RAM control operation.</figref><figref num="5">Is a block diagram showing another internal configuration example of the arbiter circuit 1.</figref><figref num="6">Is a diagram for explaining the period limitation of RAM access according to the maximum operating frequency of the access clock.</figref><figref num="7">Is a block diagram showing a second configuration example of the memory device according to the present invention.</figref><figref num="8">Is a block diagram showing an example of internal configurations of the clock division circuit 7 and the arbiter circuit 8.</figref><figref num="9">Is a state diagram (a) and a logical value table (b) for explaining the operation state transition of the arbiter circuit 8.</figref><figref num="10">Is a diagram for explaining the period limitation of RAM access according to the maximum operating frequency of the access clock in the second configuration example.</figref>

Code description

1 Arbiter circuit 2 One-shot circuit 3 RAM (single port RAM) 4 Output latch circuit 5 Read / write circuit 6a, 6b (1st, 2nd) hosts 7 clock split circuit 8 Arbiter circuit 11a, 11b (1st, 3D) flip-flops 12a, 12b (1st, 2nd) inverter 13a, 13b (1st, 3rd) AND circuit 14a, 14b (2nd, 4th) AND circuit 15a, 15b (2nd, 4th) D flip-flops 16 OR circuit 17a, 17b (5th, 6th) AND circuit 18a, 18b (1st, 2nd) OR circuit 41 D flip flop 42 Inverter 43a, 43b selector 44a, 44b D flip flops 71 D flip flop 72 Inverter 73a, 73b AND circuit 81a, 81b, 81c (1st, 3rd, 5th) D flip-flops 82a, 82b, 82c (1st, 2nd, 3rd) inverters 83a, 83b, 83c (1st, 3rd, 5th) AND circuit 84a, 84b, 84c (2nd, 4th, 6th) AND circuit 85a, 85b, 85c (2nd, 4th, 6th) D flip-flops 86 1st OR circuit 87 Second OR circuit

FIG. 1 is a block diagram showing a first configuration example of the memory device according to the present invention.

As shown in FIG. 1, the memory device of the present embodiment includes an arbiter circuit 1, a one-shot circuit 2, RAM 3, an output latch circuit 4, and a read / write circuit 5, and includes a host 6a. , 6b (eg MPU [Micro Processing Unit] and display driver) depending on the two first and second access clocks (CLK1, CLK2) (eg MPU access and display access) that are input asynchronously to each other. It is configured to control access to RAM3.

The arbiter circuit 1 generates first and second busy signals (BUSY1 and BUSY2) having mutually exclusive logic according to the above-mentioned CLK1 and CLK2, and thereby is the first via the read / write circuit 5. The access right to RAM3 is granted to any one of the hosts 6a and 6b that sent the access clock to, and the clock request signal (CLKRQ) is sent to the one-shot circuit 2 to access the RAM3. It is a means (arbitration means / priority determination means) for requesting the generation of a RAM clock (RAMCLK) for determining.

The one-shot circuit 2 is a means for generating only one pulse of RAMCLK in response to the CLKRQ from the arbiter circuit 1 and sending this to RAM3. In addition to RAM3 described above, RAMCLK is also sent to the arbiter circuit 1 and the output latch circuit 4.

As RAM3, a single port RAM that has only one input / output interface is adopted. As a result, it is possible to suppress an increase in the scale of the device and an increase in cost as compared with the case where the dual port RAM is used.

The output latch circuit 4 is a means for latching the RAM output signals (RAMO) corresponding to CLK1 and CLK2, respectively, and sending them to the read / write circuit 5 as first and second RAM output latch signals (RAMOLAT1 and RAMOLAT2).

The read / write circuit 5 recognizes whether the host 6a or 6b is granted access occupancy to RAM3 according to BUSY1 and BUSY2 from the arbiter circuit 1, and receives a chip select signal from RAM3. (RAMCS), write enable signal (RAMWE), read enable signal (RAMRD), address signal (RAMADRS), and data signal (RAMDATA).

The RAMCS, RAMWE, and RAMRD described above may be signals generated by the arbiter circuit 1 based on BUSY1 and BUSY2.

Next, the internal configurations of the arbiter circuit 1 and the output latch circuit 4 will be described in detail with reference to FIG. FIG. 2 is a block diagram showing an example of internal configurations of the arbiter circuit 1 and the output latch circuit 4.

As shown in FIG. 2, the arbiter circuit 1 of the present embodiment includes D flip-flops 11a to 11b, inverters 12a to 12b, AND circuits 13a to 13b, AND circuits 14a to 14b, and D flip-flops 15a. It has ~ 15b and a logical sum circuit 16.

In the 1st D flip flop 11a, CLK1 is input to the clock input end, a predetermined logic signal (own inverted output signal via the first inverter 12a) is input to the data input end, and the first request reset signal (1st request reset signal) is input to the reset end. REQ1RST) is input, and the first request signal (REQ1) is extracted from the output end.

In the first AND circuit 13a, BUSY1 is input to one input end, RAMCLK is input to the other inverting input end, and REQ1RST is drawn from the output end.

In the second AND circuit 14a, REQ1 is input to one input end, BUSY2 is input to the other inverting input end, and the first access start signal (STAT1) is extracted from the output end.

In the second D flip flop 15a, RAMCLK is input to the clock input end, a predetermined logic signal (reference voltage signal corresponding to the low level, for example, ground voltage) is input to the data input end, and STAT1 is input to the set input end. BUSY 1 is pulled out from the output end.

In the 3D flip flop 11b, CLK2 is input to the clock input end, a predetermined logic signal (own inverted output signal via the second inverter 12b) is input to the data input end, and the second request reset signal (2nd request reset signal) is input to the reset end. REQ2RST) is input, and the second request signal (REQ2) is pulled out from the output end.

In the third AND circuit 13b, BUSY2 is input to one input end, RAMCLK is input to the other inverting input end, and REQ2RST is drawn from the output end.

In the fourth AND circuit 14b, REQ2 is input to one input end, BUSY1 is input to the other inverting input end, and the second access start signal (STAT2) is extracted from the output end.

In the 4D flip flop 15b, RAMCLK is input to the clock input end, a predetermined logic signal (reference voltage signal corresponding to the low level, for example, ground voltage) is input to the data input end, and STAT2 is input to the set input end. BUSY2 is pulled out from the output end. Moreover, BUSY1 is input to the reset end of the 4th D flip-flop 15b.

In the OR circuit 16, STAT1 is input to one input end, STAT2 is input to the other input end, and CLKRQ is extracted from the output end.

The first to fourth D flip-flops 11a, 15a, 11b, and 15b described above are all triggered by the rising edge of the clock signal (CLK1, CLK2, RAMCLK) input by each of them.

On the other hand, the output latch circuit 4 of the present embodiment includes a D flip-flop 41, an inverter 42, selectors 43a to 43b, and D flip-flops 44a to 44b.

In the D flip-flop 41, RAMCLK is input to the clock input end, BUSY1 is input to the data input end, and a latch select signal (LAT SELECT) is extracted from the output end.

The selector 43a selectively outputs RAMO to the latter stage if LATSELECT is high level (1), and selects and outputs RAMO LAT1 to the latter stage if LATSELECT is low level (0).

The selector 43b selectively outputs RAMOLAT2 to the latter stage if LATSELECT is high level (1), and selects and outputs RAMO to the latter stage if LATSELECT is low level (0).

In the D flip-flop 44a, the inverted RAMCLK is input to the clock input end via the inverter 42, the output signal of the selector 43a is input to the data input end, and RAMOLAT1 is pulled out from the output end.

In the D flip-flop 44b, the inverted RAMCLK is input to the clock input end via the inverter 42, the output signal of the selector 43b is input to the data input end, and RAMOLAT2 is pulled out from the output end.

The above-mentioned D flip-flops 41 and 44a to 44b are all triggered by the falling edge of the clock signal (RAMCLK, inverted RAMCLK) input by each of them.

Next, the operating state transition of the arbiter circuit 1 having the above configuration will be described in detail with reference to FIG. FIG. 3 is a state diagram (a) and a logical value table (b) for explaining the operation state transition of the arbiter circuit 1.

The arbiter circuit 1 having the above configuration is configured to operate as a so-called asynchronous finite state machine (AFSM [Asynchronous Finite State Machine]). It becomes like (b).

That is, in the arbiter circuit 1, based on the logic of the first and second busy signals (BUSY1 and BUSY2) described above, the standby state (STBY state), the access state by CLK1 (BUSY1 state), and the access state by CLK2 (BUSY2). Three operating states are defined.

The first busy signal (BUSY1) corresponds to the first digit of the state counter, and the second busy signal (BUSY2) corresponds to the second digit of the state counter. Therefore, as shown in FIG. 3B, the state counters of the above-mentioned operating states are in the STBY state {00}, the BUSY1 state {01}, and the BUSY2 state {10}. The state of {11} does not exist as described later.

As shown in Fig. 3 (a), the operating state of the arbiter circuit 1 is located in the STBY state immediately after the reset, and shifts to the BUSY1 state when STAT1 rises. After that, it returns to the STBY state again at the rise of RAMCLK. Similarly, the STBY state shifts to the BUSY2 state when STAT2 rises, and returns to the STBY state when RAMCLK rises.

As described above, the arbiter circuit 1 of the present embodiment has a configuration in which the state counter changes by only one bit (one digit) before and after the operation state transition, that is, a pseudo Gray code counter. Therefore, in the arbiter circuit 1 of the present embodiment, when the operating state is changed, the other state is not used, so that there is no possibility that the state is misidentified at the moment of the operating state transition.

Next, the operation of the RAM control device having the above configuration (here, read operation) will be described in detail with reference to FIG. FIG. 4 is a timing chart for explaining the RAM control operation. This figure shows the operation waveform when CLK2 is input (rising) immediately after CLK1 is input (rising).

As shown in FIG. 4, when CLK1 rises to a high level at time t1, REQ1 changes from a low level to a high level. At this time, if the operating state of the arbiter circuit 1 is the STBY state (BUSY1 and BUSY2 are both at the low level), STAT1 transitions from the low level to the high level as shown in this figure. When STAT1 rises to a high level, BUSY1 is set to a high level, and the operating state of the arbiter circuit 1 shifts from the previous STBY state to the BUSY1 state. The read / write circuit 5 recognizes this operation state transition and starts accessing RAM3 (chip select, address setting, etc.) according to CLK1.

Further, when CLKRQ rises to a high level in response to STAT1, the one-shot circuit 2 is activated and RAMCLK is generated. The period d1 from the rise of STAT1 (that is, the rise of CLKRQ) until the one-shot pulse of RAMCLK is actually lowered to the low level, and RAMCLK once lowered to the low level are returned to the high level again. The period d2 until the pulse is determined by a delay circuit (not shown) provided inside the one-shot circuit 2.

If the above periods d1 and d2 are set too long, access may be lost, and conversely, if they are set too short, access may be poor. Therefore, the periods d1 and d2 need to be appropriately set according to the maximum operating frequencies of CLK1 and CLK2, as will be described later.

On the other hand, immediately after the input of CLK1, at time t2, when CLK2 rises to a high level, REQ2 changes from a low level to a high level. However, since BUSY1 is already at a high level at this point, REQ2 is cut off by the fourth AND circuit 14b, and STAT2 is maintained at a low level. Therefore, BUSY2 does not overlap with BUSY1 and transition to a high level, and access according to CLK2 corresponds to CLK1 until the operating state of the arbiter circuit 1 returns from the BUSY1 state to the STBY state. It will wait until the access is completed.

After that, when RAMCLK is lowered to a low level by the one-shot circuit 2 at time t3, the read operation corresponding to CLK1, that is, the output operation of RAMO is started in RAM3 .

At this time, in the arbiter circuit 1, REQ1RST rises to a high level and REQ1 is reset from a high level to a low level according to the falling edge of RAMCLK. Accordingly, STAT1 (and thus CLKRQ) is also returned to the low level. However, BUSY1 will continue to be maintained at a high level.

Further, in the output latch circuit 4, LAT SELECT is changed to a high level (same logic as BUSY 1) according to the falling edge of RAMCLK. As a result, in the selector 43a, RAMO is selectively output to the D flip-flop 44a, and in the selector 43b, RAMOLAT2 is selectively output to the D flip-flop 44b.

After that, when RAMCLK is raised to a high level again at time t4, BUSY1 is reset to a low level in the arbiter circuit 1, and its operating state is returned from the previous BUSY state to the STBY state. The read / write circuit 5 recognizes this operation state transition and ends the access to RAM 3 according to CLK1. In the arbiter circuit 1, REQ1RST is also reset to the low level according to the logical transition of BUSY1.

Further, in the output latch circuit 4, the RAMO read at the time t4 is latched as RAMOLAT1 according to the rising edge of RAMCLK (that is, the falling edge of the inverted RAMCLK). Therefore, in the read / write circuit 5, it is possible to read RAMOLAT1 (read data corresponding to CLK1) from the output latch circuit 4 at an arbitrary timing thereafter.

As described above, when the access corresponding to the earliest CLK1 is completed at time t4 and BUSY1 is reset to the low level, the cutoff of REQ2 by the fourth AND circuit 14b is released at time t5. , STAT2 transitions from low level to high level. As a result, after time t5, access according to CLK2 is performed based on the same operation as before.

In Fig. 4, the period from time t4 to t5 is exaggerated, but it is clearly shown that the transition from the BUSY1 state to the BUSY2 state is not directly performed, but is once performed via the STBY state. It is a depiction to do, and it is actually a very short period.

Further, in FIG. 4, the case where CLK1 is input first and then CLK2 is input has been illustrated as an example, but even if the case after that is reversed, the same operation as described above is performed according to CLK2. Access according to CLK1 will be waited until the access is completed.

That is, the arbiter circuit 1 of the present embodiment has a configuration in which the access clock input first is prioritized, and one access clock is not always prioritized, and subsequent access is performed during the preceding access. Even if requested, the preceding access is not stopped, and the succeeding access is waited until the preceding access is completed. Therefore, restrictions due to access timing are not required.

As described above, the RAM control device of the present embodiment includes an arbiter circuit 1 and a one-shot circuit 2, and RAM 3 is provided according to two systems of CLK1 and CLK2 that are input asynchronously to each other. The arbiter circuit 1 is a RAM control device that controls access to, and sends out the earliest access clock by generating BUSY1 and BUSY2 having mutually exclusive logic according to the above-mentioned CLK1 and CLK2. The one-shot circuit 2 is an arbiter, which is a means for giving access to RAM3 to the host and requesting the one-shot circuit 2 to generate a RAMCLK for determining the access timing to RAM3. It is configured as a means to generate only one pulse of RAMCLK according to the CLKRQ of the circuit 1 and send it to RAM3.

With such a configuration, it is possible to appropriately control access to RAM3 according to the two CLK1 and CLK2 systems that are input asynchronously to each other, while suppressing the expansion of the device scale and cost increase. Become.

Further, in the RAM control device of the present embodiment, only one RAM CLK is generated by the one-shot circuit 2 for two CLK1 and CLK2 systems. Therefore, it is not necessary to consider the timing shift between a plurality of clocks as compared with the configuration in which RAMCLK is generated for each of CLK1 and CLK2, and their arbitration and selective output are performed.

Further, the RAM control device of the present embodiment has a configuration in which it recognizes an access request according to the rise of CLK1 and CLK2, but does not require any fall of the access request. That is, the RAM control device of this embodiment operates only on the rising edges of CLK1 and CLK2. The rising edges of CLK1 and CLK2 are generated only when there is some kind of access request from hosts 6a and 6b to RAM3. Therefore, for example, it is possible to sufficiently cope with the case where the other operating frequency is extremely long with respect to one operating frequency, or conversely, the case where the other operating frequency is extremely short.

Further, as shown in FIG. 2, the arbiter circuit 1 of the present embodiment has a configuration in which BUSY1 is input to the reset end of the 4D flip-flop 15b. With such a configuration, by any chance, CLK1 and CLK2 rise at the same time, the mask operation in the 2nd and 4th AND circuits 14a and 14b is not in time, and both STAT1 and STAT2 become high level, and BUSY1 and BUSY2 Even if both are set to the high level, the 4D flip-flop 15b is immediately reset by BUSY1, so BUSY2 is returned to the low level without delay. As a result, both BUSY1 and BUSY2 are not maintained at a high level, and the operating state of the arbiter circuit 1 is preferentially shifted to the BUSY1 state. Therefore, even if the inputs of CLK1 and CLK2 completely overlap, it is possible to guarantee the normal operation without taking measures against whiskers in the analog part.

As for the priority of CLK1 and CLK2 at the time of simultaneous input, either of them may be prioritized. That is, as described above, CLK1 may be prioritized, or conversely, BUSY2 may be input to the reset end of the second D flip-flop 15a to prioritize CLK2.

Further, as shown in FIG. 2, the arbiter circuit 1 of the present embodiment has its own inverted output signal (that is, inverted REQ1, inverted REQ1, inverted) with respect to the data input terminals of the first and third D flip-flops 11a and 11b. It is configured to input REQ2) respectively. With such a configuration, even if RAMCLK does not rise due to the influence of noise etc. after STAT1 (STAT2) is set to a high level, REQ1 (on the next rising edge of CLK1 (CLK2)) Since the low level (inverted REQ1 (inverted REQ2)) is written in REQ2), the operating state of the arbiter circuit 1 returns from the BUSY1 (BUSY2) state to the STBY state. Therefore, it is possible to prevent the RAM control device from falling into a state in which the RAM control device cannot escape from the BUSY1 (BUSY2) state (so-called deadlock state or hang-up state).

If the above deadlock countermeasures are not required, a predetermined logic signal (voltage signal corresponding to a high level, for example, power supply voltage) is input to the data input terminals of the first and third D flip-flops 11a and 11b. Just leave it.

However, in the arbiter circuit 1 having the above configuration, if the logic of either BUSY1 or BUSY2 changes due to noise or the like and the state transitions to a state (illegal state) that cannot be taken by the normal flow, there is access from another system. However, there is a risk of falling into a state in which the request is not reflected (so-called deadlock state or hang-up state).

Specifically, if the logic of BUSY1 generated by the 2D flip-flop 15a is unintentionally changed to a high level due to noise or the like, CLK1 is not input, so REQ1 remains at a low level. , RAMCLK is not generated in the one-shot circuit 2. Under such conditions, if CLK2 is subsequently input, REQ2 is unintentionally gated at the high level BUSY1, so the high level transition of REQ2 is not propagated and STAT2 is started. It becomes a form that can not be done. As a result, access based on CLK2 becomes impossible until the next access based on CLK1 is completed and the unintended BUSY1 state is returned to the STBY state. Further, if the logic of BUSY2 generated by the 4D flip-flop 15b is unintentionally changed to a high level due to noise or the like, on the contrary to the above, access based on CLK1 becomes impossible.

In view of the above, for legitimate access in the illegal state, the internal configuration of the arbiter circuit 1 is partially changed so that the request signal corresponding to the request signal passes through the exclusive gate due to the unintended busy signal of the other system. Is desirable.

FIG. 5 is a block diagram showing another internal configuration example of the arbiter circuit 1.

The arbiter circuit 1 of this configuration example has almost the same configuration as described above. Therefore, detailed explanations of the same components will be omitted by assigning the same reference numerals as those in FIG. 2, and the characteristic parts (deadlock countermeasures) of this configuration will be focused on below. ..

As shown in FIG. 5, the arbiter circuit 1 of this configuration example includes logical product circuits 17a to 17b and OR circuits 18a to 18b in addition to the components shown in FIG.

In the arbiter circuit 1 of this configuration example, the output signal of the second AND circuit 14a is not directly used as STAT1 but is used as the first pre-signal (PRE1). Similarly, the output signal of the AND circuit 14b is not used directly as STAT2, but as the second pre-signal (PRE2).

In the fifth AND circuit 17a, REQ1 is input to the first input end, REQ2 is input to the second inverting input end, RAMCLK is input to the third input end, and the first through signal (1st through signal) from the output end. TH1) has been pulled out.

In the first OR circuit 18a, PRE1 is input to one input end, TH1 is input to the other input end, and STAT1 is extracted from the output end.

In the sixth AND circuit 17b, REQ1 is input to the first inverting input end, REQ2 is input to the second input end, RAMCLK is input to the third input end, and the second through signal (from the output end). TH2) has been pulled out.

In the second OR circuit 18b, PRE2 is input to one input end, TH2 is input to the other input end, and STAT2 is extracted from the output end.

In the arbiter circuit 1 having the above configuration, for example, when the logic of BUSY1 generated by the second D flip-flop 15a is unintentionally changed to a high level due to noise or the like, and CLK2 is input under that state, REQ2 Is gated at BUSY1, which is unintentionally high level, as mentioned earlier, so the high level transition of REQ2 is not propagated to PRE2 and STAT2 is not launched. Therefore, when CLK2 is input after an unintended logical transition of BUSY1, REQ1 is maintained at a low level and REQ2 is maintained at a high level, but PRE2 is maintained at a low level and RAMCLK is initially maintained at a high level. Become a shape.

On the other hand, when REQ1, REQ2, and RAMCLK of the above logic are input to the sixth AND circuit 17b, the logic of TH2 is changed from the low level to the high level. Therefore, in the second OR circuit 18b, STAT2 is raised to a high level and RAMCLK is generated according to CLK2 without depending on the logic of PRE2. If even one of REQ1, REQ2, and RAMCLK does not have the above logic, the logic of TH2 becomes low level, so PRE2 is output as STAT2.

That is, when a valid CLK2 is input in a state where an unintended logical transition occurs in BUSY1, in the arbiter circuit 1 of this configuration example, REQ2 passes through the exclusive gate by BUSY1 (to be exact, to be exact). Although it does not normally go through the flow, as a result, REQ2 seems to have passed through the exclusive gate by BUSY1).

In this way, the arbiter circuit 1 of this configuration example is valid under the condition that an unintended logical transition occurs in BUSY1 based on both logics of REQ1 to REQ2 (that is, with or without input of CLK1 to CLK2) and RAMCLK logic. If it is determined whether or not CLK2 has been input and it is determined that such a state has occurred, BUSY2 is desired according to the valid CLK2 without depending on BUSY1 that has caused an unintended logical transition. It is designed to be transformed into logic. Therefore, in the case of the arbiter circuit 1 of this configuration example, it is possible to perform access based on CLK2 without waiting for the input of CLK1 and then return to the STBY state without delay.

Contrary to the above, if CLK1 is input while BUSY2 is unintentionally changed to a high level, REQ1 becomes a high level, REQ2 becomes a low level, and RAMCLK becomes a high level. 5 In the AND circuit 17a, the logic of TH1 is at a high level. Therefore, in the first OR circuit 18a, STAT1 is raised to a high level and RAMCLK is generated according to CLK1 without depending on the logic of PRE1. Therefore, in the case of the arbiter circuit 1 of this configuration example, it is possible to perform access based on CLK1 without waiting for the input of CLK2, and then return to the STBY state without delay.

Next, the RAM access period limit (RAMCLK cycle limit) according to the maximum operating frequency of the access clock will be described in detail with reference to FIG. FIG. 6 is a diagram for explaining the period limitation of RAM access according to the maximum operating frequency of the access clock.

The most frequently accessed case for RAM3 is when continuous access according to CLK1 is continued and access according to CLK2 is requested (and vice versa), as shown in Fig. 6. Is. Note that FIG. 6 depicts the worst case in which CLK2 was launched immediately before CLK1.

Here, as described above, in the arbiter circuit 1, the access according to CLK1 can wait for the end of the access according to CLK2, and conversely, the access according to CLK2 is the access according to CLK1. You can wait for the end. However, regarding continuous access according to CLK1, if the access according to CLK2 does not end within one cycle of CLK1, the access according to the later CLK1 waits for the end of the access according to the first CLK1. It cannot be done and access is lost.

Therefore, in order to maintain the normal operation of the RAM control device, it is necessary to complete two RAM accesses (accesses corresponding to CLK1 and CLK2) in one cycle of CLK1. That is, in the one-shot circuit 2, the period d1 from when the CLKRQ is started until the one-shot pulse of RAMCLK is lowered to the low level, and the RAMCLK once lowered to the low level are returned to the high level again. It is necessary to appropriately set the period d2 (see Fig. 4) to the maximum operating frequency (that is, the shortest period) of the faster access clock (CLK1 in the case of Fig. 6). More specifically, the total period of the periods d1 and d2 (that is, the RAM access period W) is equal to or greater than the minimum period Z that does not cause an access failure of RAM3, and the shortest period X of CLK1. The above periods d1 and d2 may be set so as to be 1/2 or less.

However, it is expected that the maximum operating frequency of the access clock will continue to increase in the future, and it will become more difficult to manage and set the above periods d1 and d2 so as to satisfy the above conditions. Be done.

In view of the above, it is desirable to partially change the circuit specifications of the memory device in order to relax the above conditions as much as possible.

FIG. 7 is a block diagram showing a second configuration example of the memory device according to the present invention.

As shown in FIG. 7 (a), in the first configuration example described above, both access clocks (CLK1 and CLK2) of the two systems are directly input to the arbiter circuit 1 to perform mutual arbitration, and one of them is used. After converting to a clock request signal (CLKRQ), the one-shot circuit 2 was configured to generate a RAM clock (RAMCLK).

On the other hand, in the second configuration example, for example, the MPU access clock (MCLK) and the display access clock (DCLK) are assumed as the first to second access clocks, and MCLK operates more than DCLK. As shown in Fig. 7 (b), under the assumption that the frequency is high, one system of MCLK is distributed to two systems by alternately distributing a continuous pulse sequence of MCLK for each cycle using the clock division circuit 7. After dividing into the 1st and 2nd divided access clocks (MCLK1, MCLK2), a total of 3 access clocks (MCLK1, MCLK2, DCLK) including DCLK are input to the arbiter circuit 8 to perform mutual arbitration. , After converting to one clock request signal (CLKRQ), the one-shot circuit 2 is configured to generate the RAM clock (RAMCLK).

Next, the internal configurations of the clock division circuit 7 and the arbiter circuit 8 will be described in detail with reference to FIG. FIG. 8 is a block diagram showing an example of internal configurations of the clock division circuit 7 and the arbiter circuit 8.

As shown in FIG. 8, the clock division circuit 7 of this configuration example includes a D flip-flop 71, an inverter 72, and a logical product circuit 73a to 73b.

In the D flip-flop 71, MCLK is input to the clock input end, a predetermined logic signal (own inverted output signal via the inverter 72) is input to the data input end, and a mask signal (MASK) is extracted from the output end. There is.

In the AND circuit 73a, MASK is input to one input end, MCLK is input to the other input end, and MCLK1 is extracted from the output end.

In the AND circuit 73b, MASK is input to one inverting input end, MCLK is input to the other input end, and MCLK2 is extracted from the output end.

In the clock division circuit 7 having the above configuration, the logical product operation of MASK and MCLK and the logical product operation of the inverted MASK and MCLK are performed to perform MCLK as shown in FIG. 10 to be described in detail later. MCLK1 to MCLK2 are generated in a form in which the continuous pulse trains of are alternately distributed every cycle.

On the other hand, the arbiter circuit 8 of this configuration example includes D flip-flops 81a to 81c, inverters 82a to 82c, AND circuits 83a to 83c, AND circuits 84a to 84c, and D flip-flops 85a to 85c. It has sum circuits 86 to 87.

In the 1st D flip flop 81a, MCLK1 is input to the clock input end, a predetermined logic signal (own inverted output signal via the 1st inverter 82a) is input to the data input end, and the 1st MPU request reset signal (1st MPU request reset signal) is input to the reset end. MREQ1RST) is input, and the first MPU request signal (MREQ1) is extracted from the output end.

In the first AND circuit 83a, the first MPU busy signal (MBUSY1) is input to one input end, RAMCLK is input to the other inverting input end, and MREQ1RST is extracted from the output end.

In the second logical product circuit 84a, MREQ1 is input to the first input end, the second MPU busy signal (MBUSY2) is input to the second inverting input end, and the display busy signal (DBUSY) is input to the third inverting input end. Is input, and the 1st MPU access start signal (MSTAT1) is extracted from the output end.

In the second D flip flop 85a, RAMCLK is input to the clock input end, a predetermined logic signal (reference voltage signal corresponding to the low level, for example, ground voltage) is input to the data input end, and MSTAT1 is input to the set input end. MBUSY1 is pulled out from the output end.

In the 3D flip flop 81b, MCLK2 is input to the clock input end, a predetermined logic signal (own inverted output signal via the 2nd inverter 82b) is input to the data input end, and the 2nd MPU request reset signal (2nd MPU request reset signal) is input to the reset end. MREQ2RST) is input, and the second MPU request signal (MREQ2) is extracted from the output end.

In the third logical product circuit 83b, MBUSY2 is input to one input end, RAMCLK is input to the other inverting input end, and MREQ2RST is drawn from the output end.

In the fourth AND circuit 84b, MREQ2 is input to the first input end, MBUSY1 is input to the second inverting input end, DBUSY is input to the third inverting input end, and the second MPU access starts from the output end. The signal (MSTAT2) is being pulled out.

In the 4D flip flop 85b, RAMCLK is input to the clock input end, a predetermined logic signal (reference voltage signal corresponding to the low level, for example, ground voltage) is input to the data input end, and MSTAT2 is input to the set input end. MBUSY2 is pulled out from the output end.

In the 5th D flip flop 81c, DCLK is input to the clock input end, a predetermined logic signal (own inverted output signal via the 3rd inverter 82c) is input to the data input end, and a display request reset signal (DREQRST) is input to the reset end. ) Is input, and the display request signal (DREQ) is extracted from the output end.

In the fifth logical product circuit 83c, DBUSY is input to one input end, RAMCLK is input to the other inverting input end, and DREQRST is drawn from the output end.

In the sixth AND circuit 84c, DREQ is input to the first input end, MBUSY1 is input to the second inverting input end, MBUSY2 is input to the third inverting input end, and the display access start signal is input from the output end. (DSTAT) has been pulled out.

In the 6th D flip flop 85c, RAMCLK is input to the clock input end, a predetermined logic signal (reference voltage signal corresponding to the low level, for example, ground voltage) is input to the data input end, and DSTAT is input to the set input end. DBUSY is pulled out from the output end. A reset signal (RST) is input to the reset end of the 6th D flip-flop 85c.

In the first OR circuit 86, MSTAT1 is input to the first input end, MSTAT2 is input to the second input end, DSTAT is input to the third input end, and CLKRQ is extracted from the output end. ..

In the second OR circuit 87, MBUSY1 is input to one input end, MBUSY2 is input to the other input end, and RST is drawn from the output end.

The above-mentioned 1st to 6th D flip-flops 81a, 85a, 81b, 85b, 81c, and 85c are all triggered by the rising edge of the clock signal (MCLK1, MCLK2, DCLK, RAMCLK) input by each user. Is.

As can be seen from the above, the arbiter circuit 8 of this configuration example has a configuration in which the 2-system input type arbiter circuit 1 shown in FIG. 2 is changed to a 3-system input type, and the basic operation of the circuit is as described above. Therefore, a detailed explanation on this is omitted.

As for the priority of MCLK and DCLK at the time of simultaneous input, either of them may be prioritized. That is, as shown in FIG. 8, by inputting the OR signals of MBUSY1 and MBUSY2 to the reset end of the 6th D flip-flop 85c, the configuration may give priority to MCLK, or conversely, the second and second flip-flops. DBUSY may be input to the reset ends of the 4D flip-flops 85a and 85b to give priority to DCLK.

Next, the operating state transition of the arbiter circuit 8 having the above configuration will be described in detail with reference to FIG. FIG. 9 is a state diagram (a) and a logical value table (b) for explaining the operation state transition of the arbiter circuit 8.

The arbiter circuit 8 having the above configuration is configured to operate as a so-called asynchronous finite state machine as in the first configuration example described above, and its phase diagram and logical value table are shown in FIG. 9 (a). , (B).

That is, in the arbiter circuit 8, based on the logic of the three busy signals (MBUSY1, MBUSY2, DBUSY) described above, the standby state (STBY state), the access state by MCLK1 (MBUSY1 state), and the access state by MCLK2 (MBUSY2 state). , And the access state by DCLK (DBUSY state), four operating states are defined.

The 1st to 2nd MPU busy signals (MBUSY1 to MBUSY2) correspond to the 1st to 2nd digits of the state counter, and the display busy signal (DBUSY) corresponds to the 3rd digit of the state counter. Therefore, as shown in FIG. 9B, the state counters of the above-mentioned operating states are in the STBY state {000}, the MBUSY1 state {001}, the MBUSY2 state {010}, and the DBUSY state {100}. The state of {111} does not exist as described later.

As shown in FIG. 9A, the operating state of the arbiter circuit 8 is located in the STBY state immediately after the reset, and shifts to the MBUSY1 state when MSTAT1 rises. After that, it returns to the STBY state again at the rise of RAMCLK. Similarly, the STBY state shifts to the MBUSY2 state when MSTAT2 rises, and returns to the STBY state again when RAMCLK rises. In addition, the STBY state shifts to the DBUSY state when DSTAT rises, and returns to the STBY state when RAMCLK rises.

As described above, the arbiter circuit 8 of this configuration example has a configuration in which the state counter changes by only one bit (one digit) before and after the operation state transition, that is, pseudo gray, as in the first configuration example described above. It is said to be a code counter. Therefore, in the case of the arbiter circuit 8 of the present configuration example, when the operating state is transitioned, the other state is not used, so that there is no possibility that the state is misidentified at the moment of the operating state transition.

Finally, the RAM access period limitation (RAMCLK cycle limitation) according to the maximum operating frequency of the access clock in the second configuration example will be described in detail with reference to FIG. FIG. 10 is a diagram for explaining the period limitation of RAM access according to the maximum operating frequency of the access clock in the second configuration example.

The most frequently accessed case for RAM3 is, as shown in FIG. 10, when the access according to DCLK is requested while the continuous access according to MCLK continues. Note that FIG. 10 depicts the worst case in which DCLK was launched immediately before MCLK2.

As described above, in the arbiter circuit 8 of this configuration example, MCLK is dividedly input as two systems of MCLK1 and MCLK2, and access management is individually performed according to each. Therefore, in the arbiter circuit 8 of this configuration example, DCLK is started immediately before MCLK2, and as a result of waiting for access according to MCLK2, access according to the MCLK2 is performed by the next input of MCLK1. Even if it does not end, arbitration can be performed between MCLK1 and MCLK2, and access according to the next MCLK1 can be made to stand by without any problem. It is possible to make access.

When continuous access according to MCLK is continued, as shown in FIG. 10, an arbitration chain occurs between MCLK1 and MCLK2 after that, but in this case as well, the other access is terminated. You can wait and then perform your own access. Such an operation is continuously performed until the arbitration chain between MCLK1 and MCLK2 is broken.

As described above, the arbiter circuit 8 of this configuration example can wait for the execution of the access according to the late pulse until the end of the access according to the early pulse with respect to the continuous access according to the MCLK, so that the access omission occurs. It has a difficult structure.

However, even in the arbiter circuit 8 of this configuration example, if an arbitration chain occurs between MCLK1 and MCLK2 and the next DCLK is input before this is completed, the operation will be performed. There is a risk of bankruptcy and loss of access.

Therefore, in order to maintain the normal operation of the RAM control device, it is desirable to set the RAM access period W (= d1 + d2) so as to satisfy the following conditional expression (1).

<maths num="1"><img file="JP5000514B2_D0001.tif" /></maths> In the above equation (1), X is the shortest period of MCLK, Y is the shortest period of DCLK, and Z is the minimum period that does not cause access failure of RAM3.

For example, when X = 100 [ns], Y = 1000 [ns], and Z = 40 [ns], in the first configuration, the condition of 40 [ns] W 50 [ns] is satisfied. The RAM access period W (= d1 + d2) had to be set, but if the second configuration is adopted, the RAM access period will satisfy the condition of 40 [ns] W 90.9 [ns]. As long as W is set, it is possible to avoid the breakdown of the arbitration operation.

That is, by adopting the second configuration, it is possible to secure a margin of about twice for the RAM access period W, and the restriction can be greatly relaxed, so further speeding up is expected in the future. It is possible to fully support the access clock.

In the above embodiment, a configuration in which a single-port RAM is adopted as the RAM 3 has been described as an example, but the configuration of the present invention is not limited to this, and the input / output interface of the dual-port RAM is used. Of these, it can be widely applied as two systems of access control means for either one.

In addition to the above embodiments, the configuration of the present invention can be modified in various ways without departing from the gist of the invention.

For example, in the above embodiment, in the one-shot circuit 2, RAMCLK is lowered to a low level when the period d1 elapses from the rise of CLKRQ, and RAMCLK is returned to a high level when the period d2 elapses. Although the configuration has been described as an example, the configuration of the present invention is not limited to this, and CLKRQ (the logical inversion signal according to the embodiment) is simply delayed by the period d1. It is also possible to generate only one pulse of RAMCLK. This is because the CLKRQ has a form of transitioning to a high level according to the rise of the access start signal and then returning to a low level according to the fall of RAMCLK, that is, a pulse waveform, so that the logic inversion signal is This is because if is delayed by the period d1, the result is that RAMCLK is generated by only one pulse. In this case, RAMCLK falls to the low level when the period d1 elapses from the rise of CLKRQ, and returns to the high level when the period d1 elapses. With such a configuration, the one-shot circuit 2 can be realized extremely easily. As described above, the period d1 may be appropriately set according to the operating frequency of the access clock.

Further, in the embodiment described with reference to FIGS. 7 and 8, the configuration in which the clock division circuit 7 and the arbiter circuit 8 are provided independently has been described as an example, but the configuration of the present invention is the same. The clock division circuit may be included in the arbiter circuit.

The present invention is a technique useful for reducing the scale and cost of a RAM control device.