Semiconductor memory device and memory system including the same

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an outer data inner control pad structure and a memory system comprising the same.

A semiconductor memory device having a conventional outer data inner control pad (ODIC) structure has a structure in which data pads are arranged on both sides and instruction pads are arranged inside, and is arranged on one side. Data input / output via the existing data pad is input / output only to the memory cell array block arranged on one side, and data input / output via the data pad arranged on the other side is arranged on the other side. It is input / output only to the memory cell array block that is set.

FIG. 1 is a block diagram showing an example configuration of a semiconductor memory device having a conventional ODIC pad structure, and is a diagram showing a configuration of a semiconductor memory device including four memory cell array blocks BLK1 to BLK4.

In FIG. 1, the data pad DQ1 of the first group, the address / instruction signal application pad CMD / ADD, and the data pad DQ2 of the second group are the areas where the memory cell array blocks BLK1 and BLK3 are arranged and the memory cell array block BLK2. It is arranged in a row with the area where BLK4 is arranged. As shown in FIG. 1, in a semiconductor memory device having an ODIC pad structure, the data pad DQ1 of the first group and the data pad DQ2 of the second group are arranged on both sides, and the address / command signal application pad CMD / ADD is in the center. Have been placed.

In FIG. 1, data DO1 and DO2 input / output from / to the memory cell array blocks BLK1 and BLK2 are input / output via the data pad DQ1 of the first group, and input / output from / to the memory cell array blocks BLK3 and BLK4. The data DO3 and DO4 to be input are input / output via the data pad DQ2 of the second group.

A recent semiconductor memory device does not transmit only data at the time of data transmission, but an error detection code is added to the data and transmitted. Therefore, an error detection code generator is added to the semiconductor memory device. Then, the error detection code generator must generate an error detection code for all the bit data output from the memory cell array blocks BLK1 to BLK4. For example, if data is selectively output from memory cell array blocks BLK1, BLK3 or memory cell array blocks BLK2, BLK4, an error detection code must be generated for data DO1, DO4 or data DO2, DO3.

However, for example, if an error detection code generator is placed in area A between the areas where the memory cell array blocks BLK1 to BLK4 are placed and data is output from data DO1, DO4 or data DO2, DO3, then data DO1, DO4 or Data DO2 and DO3 must be input to the error detection code generator. Therefore, the signal line for transmitting data DO1 and DO2 must be arranged on the error detection code generator side, and the signal line for transmitting data DO3 and DO4 must be arranged on the error detection code generator side. Must be. This not only increases the layout area of the semiconductor memory device, but also lengthens the signal line and causes a signal transmission delay.

Then, such a problem is caused by the error detection code generator being arranged in the area B between the areas where the memory cell array blocks BLK1 and BLK2 are arranged, or the area C between the areas where the memory cell array blocks BLK3 and BLK4 are arranged. It is also generated when it is placed in.

<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2000-058772</text></patcit><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2002-223203</text></patcit><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2001-249854</text></patcit>

<p> An object of the present invention is to provide a semiconductor memory device capable of generating an error detection code without increasing the layout area and without lowering the error detection capability.</p><p> Another object of the present invention is to provide a memory system for achieving the above object.</p>

<p> The first embodiment of the semiconductor memory device of the present invention for achieving the above object is the first memory cell array block for generating the first data, the second memory cell array block for generating the second data, and the first data. On the other hand, the first error detection that generates the first error detection code and generates the first final error detection signal by combining some bits in the first error detection code and some bits in the second error detection code. The code generator, the second error detection code generated for the second data, the remaining bits excluding the partial bit in the second error detection code, and the said in the first error detection code. It is characterized by including a second error detection code generator that generates a second final error detection signal by combining the remaining bits excluding some bits.</p><p> Each of the first and second error detection code generators is configured by using the cyclic redundancy check code method, and includes an exclusive OR circuit configured by using the same error detection code generation polypoly, or the first one. Each of the second error detection code generation circuit and the second error detection code generation circuit is configured by using the cyclic redundancy check code method, and is characterized by including an exclusive OR circuit configured by using different error detection code generation polynomies.</p><p> The semiconductor memory device serially converts the first data and the first final error detection signal into a first parallel series converter and outputs the second data and the second final error detection signal in series. It is characterized by further including a second parallel series converter for output.</p><p> The pad of the semiconductor memory device has an ODIC pad structure, and the first error detection code generator is arranged adjacent to a first data pad that outputs the first data and the first final error detection signal. The second error detection code generator is characterized by being arranged adjacent to the second data pad that outputs the second data and the second final error detection signal.</p><p> The semiconductor memory device of the first form generates a third error detection code for the third data applied from the outside, and a part of the bits in the third error detection code and one of the fourth error detection codes. The third error detection code generator that generates the third final error detection signal by combining the bites, and the fourth error detection code that generates the fourth error detection code for the fourth data applied from the outside to detect the fourth error. A fourth error detection code generation that generates a fourth final error detection signal by combining the remaining bits excluding the partial bits in the code and the remaining bits excluding the partial bits in the third error detection code. The device compares the third final error detection signal applied from the outside with the third final error detection signal, and compares the fourth final error detection signal applied from the outside with the fourth final error detection signal to make an error. It is further provided with an error detector that generates a detection signal. Each of the third and fourth error detection code generators is configured by using the cyclic redundancy check code method, and includes an exclusive OR circuit configured by using the same error detection code generation polypoly, or the third and third error detection code generators. Each of the fourth error detection code generator and the fourth error detection code generator is configured by using the cyclic redundancy check code method, and is characterized by including an exclusive OR circuit configured by using different error detection code generation polynomies. The semiconductor memory device includes a first series-parallel converter that converts and outputs a third data and a third final error detection signal applied from the outside in parallel, and a fourth data and a fourth final error detection signal applied from the outside. It is characterized by including a second series-parallel converter that converts and outputs in parallel.</p><p> Further, the semiconductor memory device of the first form generates a third error detection code for the first data, and generates a part bit in the third error detection code and a part bit in the fourth error detection code. A third error detection code generator that generates the third final error detection signal in combination, and the partial bit in the fourth error detection code that generates the fourth error detection code for the second data. Further includes a fourth error detection code generator that generates the fourth final error detection signal by combining the remaining bits excluding the above and the remaining bits excluding the partial bit in the third error detection code. It is characterized by that. Each of the first to fourth error detection code generators is configured using the cyclic redundancy check code method, and each of the first and third error detection code generators is configured using different error detection code generation polynomies. The first exclusive OR circuit is provided, and each of the second and fourth error detection code generation circuits is provided with a second exclusive OR circuit configured by using different error detection code generation polynomies. It is a feature. Then, the semiconductor memory device further includes a control unit for enabling the first and second error detection code generators and the third and fourth error detection code generators while periodically alternating with each other. It is a feature.</p><p> The semiconductor memory device of the second form for achieving the above object is the first that generates 2n-bit first data in the first-bit structure mode and generates n-bits of the first data in the second-bit structure mode. A memory cell array block, a second memory cell array block that generates 2n bits of second data in the first bit structure mode, and n bits of the second data in the second bit structure mode, and the first bit. The first error detection code is generated for the upper n bits of the first data of 2 n bits in the structure mode and the upper n bits of the first data in the second bit structure mode, and in the first error detection code. The first error detection code generator that generates a part of the first final error detection signal by combining some bits of the third error detection code and some bits in the third error detection code, and 2n bits in the first bit structure mode. A second error detection code is generated for the lower n bits of the first data, and a part of the bits in the second error detection code and a part of the bits in the fourth error detection code are combined to detect the first final error. In the second error detection code generator that generates the remaining bits excluding the partial bits of the signal, and in the upper n bits of the second data of 2 n bits in the first bit structure mode and in the second bit structure mode. The third error detection code is generated in the upper n bits of the second data, and the remaining bits excluding the partial bit in the third error detection code and the partial bit in the first error detection code. The third error detection code generator that generates a part of the second final error detection signal by combining the remaining bits excluding the above, and the lower n bits of the second data of 2n bits in the first bit structure mode. On the other hand, a fourth error detection code is generated, and the remaining bits excluding the partial bits in the fourth error detection code are combined with the remaining bits excluding the partial bits in the second error detection code. It is characterized by including a fourth error detection code generator that generates the remaining bits of the second final error detection signal excluding the partial bits.</p><p> The semiconductor memory device of the second form has the fifth error with respect to the upper n bits of the first data of 2 n bits in the first bit structure mode and the n bits of the first data in the second bit structure mode. Generate a 5th error detection code that generates a detection code and generates a part of the 3rd final error detection signal by combining some bits in the 5th error detection code and some bits in the 7th error detection code. A sixth error detection code is generated for the device and the lower n bits of the first data of 2 n bits in the first bit structure mode, and some bits in the sixth error detection code and the eighth error detection code are generated. A sixth error detection code generator that combines some of the bits to generate the remaining bits of the first final error detection signal excluding the partial bits, and the 2n-bit first in the first bit structure mode. The 7th error detection code is generated in the upper n bits of the 2 data and the upper n bits of the 2nd data in the 2nd bit structure mode, and the remaining bits excluding the partial bits in the 7th error detection code. A seventh error detection code generator that combines a bit and the remaining bits of the fifth error detection code excluding the partial bit to generate a partial bit of the second final error detection signal, and the first bit. The eighth error detection code is generated for the lower n bits of the second data of 2n bits in the structure mode, and the remaining bits excluding the partial bits in the eighth error detection code and the sixth error detection are detected. It is further provided with an eighth error detection code generator that combines the remaining bits of the code excluding the partial bits to generate the remaining bits of the fourth final error detection signal excluding the partial bits. It is a feature.</p><p> Each of the first to eighth error detection code generators is configured by using the cyclic redundancy check code method, and each of the first to fourth error detection code generators uses the same first error detection code generation polymorphism. Each of the fifth to eighth error detection code generators is configured by using a second error detection code generation polymorphism different from the first error detection code generation polymorphism. It is characterized by having a second exclusive OR circuit. The semiconductor memory device is further provided with a control unit for enabling the first and fourth error detection code generators and the fifth and eighth error detection code generators while alternating periodically.</p><p> The pad of the semiconductor memory device of the second form has an ODIC pad structure, and the first, second, fifth, and sixth error detection code generators output the first data and the first final error detection signal. The third, fourth, seventh, and eighth error detection code generators are arranged adjacent to the data pad, and the third, fourth, seventh, and eighth error detection code generators are arranged adjacent to the second data pad that outputs the second data and the second final error detection signal. It is characterized by that.</p><p> The first form of the memory system of the present invention for achieving the other object is the first memory cell array block for generating the first data, the second memory cell array block for generating the second data, and the first data. Generates the first error detection code, and generates the first final error detection signal by combining some bits in the first error detection code and some bits in the second error detection code. The second error detection code is generated for the device and the second data, and the remaining bits excluding the partial bit in the second error detection code and the partial in the first error detection code. A second error detection code generator that combines the remaining bits excluding the bits to generate a second final error detection signal is provided to generate the first and second data and the first and second final error detection signals. A third error detection code is generated for the semiconductor memory device and the first data output from the semiconductor memory device, and some bits in the third error detection code and some bits in the fourth error detection code. The third error detection code generator that generates the third final error detection signal by combining the above, the fourth error detection code is generated for the second data output from the semiconductor memory device, and the fourth error detection code is generated. A fourth error detection code generator that generates a fourth final error detection signal by combining the remaining bits excluding the partial bits in the data and the remaining bits excluding the partial bits in the third error detection code. , And the first final error detection signal output from the semiconductor memory device and the third final error detection signal are compared, and the second final error detection signal and the fourth final error detection signal output from the semiconductor memory device are compared. It is characterized by including a memory control unit having an error detector that generates an error detection signal in comparison with the above.</p><p> Each of the first to fourth error detection code generators is configured by using the cyclic redundancy check code method, and each of the first and third error detection code generators uses the same first error detection code generation polymorphism. A second exclusive OR circuit configured by using the same second error detection code generation polynomial for each of the second and fourth error detection code generators. It is characterized by having.</p><p> A second embodiment of the memory system of the present invention for achieving the other object generates 2n bits of the first data in the first bit structure mode and n bits of the first data in the second bit structure mode. First memory cell array block to be generated, second memory cell array block that generates 2n bits of second data in the first bit structure mode and n bits of the second data in the second bit structure mode, said first The first error detection code is generated for the upper n bits of the first data of 2 n bits in the 1-bit structure mode and the upper n bits of the first data in the second bit structure mode, and the first error detection is performed. 1st error detection code generator that combines some bits in the code and some bits in the 3rd error detection code to generate some bits of the 1st final error detection signal, 2n bits in the 1st bit structure mode A second error detection code is generated for the lower n bits of the first data, and a part of the bits in the second error detection code and a part of the bits in the fourth error detection code are combined to form the first final error. A second error detection code generator that generates the remaining bits of the detection signal except for some of the bits, an upper n-bit of 2n bits of the second data in the first-bit structure mode, and a second-bit structure mode. The third error detection code is generated for the upper n bits of the second data, and the remaining bits excluding the partial bits in the third error detection code and the one in the first error detection code. A third error detection code generator that combines the remaining bits excluding the partial bits to generate some bits of the second final error detection signal, and a lower n of 2n bits of the second data in the first bit structure mode. A fourth error detection code is generated for the bits, and the remaining bits excluding the partial bits in the fourth error detection code and the remaining bits excluding the partial bits in the second error detection code. The second final error detection signal is provided with a fourth error detection code generator that generates the remaining bits excluding some bits of the second final error detection signal.The semiconductor memory device that generates the first and second data and the first and second final error detection signals, and the upper n bits of the 2n bits of the first data output from the semiconductor memory device in the first bit structure mode and the upper n bits. A fifth error detection code is generated for the n bits of the first data output from the semiconductor memory device in the second bit structure mode, and some bits in the fifth error detection code and the seventh error are detected. A fifth error detection code generator that combines some bits in the code to generate some bits of the third final error detection signal, for the lower n bits of the first data of 2 n bits in the first bit structure mode. A sixth error detection code was generated, and a part of the bits in the sixth error detection code and a part of the bits in the eighth error detection code were combined to remove the part of the third final error detection signal. The sixth error detection code generator that generates the remaining bits, the upper n bits of the second data of 2 n bits output from the semiconductor memory device in the first bit structure mode, and the second in the second bit structure mode. The 7th error detection code is generated for n bits of data, and the remaining bits excluding the partial bits in the 7th error detection code and the partial bits in the 5th error detection code are excluded. The 7th error detection code generator that combines the remaining bits to generate a part of the 4th final error detection signal, the 2nth bit for the lower n bits of the 2nd data in the 1st bit structure mode. The 8th error detection code is generated, and the remaining bits excluding the partial bits in the 8th error detection code are combined with the remaining bits excluding the partial bits in the 6th error detection code. 4 An error is compared between the eighth error detection code generator that generates the remaining bits of the final error detection signal excluding the partial bits and the first to fourth final error detection signals output from the semiconductor memory device. It is characterized by including a memory control unit having an error detection signal generator that generates a detection signal.The semiconductor memory device that generates the error detection signal, the upper n bits of the 2 n-bit first data output from the semiconductor memory device in the first bit structure mode, and the output from the semiconductor memory device in the second bit structure mode. A fifth error detection code is generated for the n bits of the first data to be generated, and a part of the bits in the fifth error detection code and a part of the bits in the seventh error detection code are combined to form the third final error. The fifth error detection code generator that generates a part of the bits of the detection signal, the sixth error detection code is generated for the lower n bits of the first data of 2 n bits in the first bit structure mode, and the sixth error detection code is generated. A sixth error detection code generator that combines some bits in the error detection code and some bits in the eighth error detection code to generate the remaining bits of the third final error detection signal excluding the partial bits. The 7th error detection code for the upper n bits of the 2n bits of the second data output from the semiconductor memory device in the first bit structure mode and the n bits of the second data in the second bit structure mode. The fourth final error detection signal is generated by combining the remaining bits excluding the partial bits in the seventh error detection code and the remaining bits excluding the partial bits in the fifth error detection code. The seventh error detection code generator that generates a part of the bits of the above, the eighth error detection code is generated for the lower n bits of the second data of 2n bits in the first bit structure mode, and the eighth error detection is performed. The remaining bits excluding the partial bits in the code and the remaining bits excluding the partial bits in the sixth error detection code were combined to remove the partial bits of the fourth final error detection signal. A memory having an eighth error detection code generator that generates the remaining bits and an error detection signal generator that generates an error detection signal by comparing the first to fourth final error detection signals output from the semiconductor memory device. It is characterized by including a control unit.The semiconductor memory device that generates the error detection signal, the upper n bits of the 2 n-bit first data output from the semiconductor memory device in the first bit structure mode, and the output from the semiconductor memory device in the second bit structure mode. A fifth error detection code is generated for the n bits of the first data to be generated, and a part of the bits in the fifth error detection code and a part of the bits in the seventh error detection code are combined to form the third final error. The fifth error detection code generator that generates a part of the bits of the detection signal, the sixth error detection code is generated for the lower n bits of the first data of 2 n bits in the first bit structure mode, and the sixth error detection code is generated. A sixth error detection code generator that combines some bits in the error detection code and some bits in the eighth error detection code to generate the remaining bits of the third final error detection signal excluding the partial bits. The 7th error detection code for the upper n bits of the 2n bits of the second data output from the semiconductor memory device in the first bit structure mode and the n bits of the second data in the second bit structure mode. Is generated, and the remaining bits excluding the partial bits in the 7th error detection code and the remaining bits excluding the partial bits in the 5th error detection code are combined to form a 4th final error detection signal. The 7th error detection code generator that generates a part of the bits of the 8th error detection code generates the 8th error detection code for the lower n bits of the 2n bits of the 2n data in the 1st bit structure mode. The remaining bits excluding the partial bits in the code and the remaining bits excluding the partial bits in the sixth error detection code were combined to remove the partial bits of the fourth final error detection signal. A memory having an eighth error detection code generator that generates the remaining bits and an error detection signal generator that generates an error detection signal by comparing the first to fourth final error detection signals output from the semiconductor memory device. It is characterized by including a control unit.A fifth error detection code is generated for the upper n bits of the 2n bits of the first data output from the Mori device and the n bits of the first data output from the semiconductor memory device in the second bit structure mode. , The fifth error detection code generator that generates a part bit of the third final error detection signal by combining some bits in the fifth error detection code and some bits in the seventh error detection code. A sixth error detection code is generated for the lower n bits of the first data of 2 n bits in the bit structure mode, and some bits in the sixth error detection code and some bits in the eighth error detection code are generated. A sixth error detection code generator that is combined to generate the remaining bits of the third final error detection signal excluding the partial bits, and a 2n-bit second output from the semiconductor memory device in the first bit structure mode. The 7th error detection code is generated for the upper n bits of the 2 data and the n bits of the 2nd data in the 2nd bit structure mode, and the remainder excluding the partial bits in the 7th error detection code. 7th error detection code generator that generates a partial bit of the 4th final error detection signal by combining the bit of the above and the remaining bits excluding the partial bit in the 5th error detection code, the 1st bit structure. The eighth error detection code is generated for the lower n bits of the second data of 2n bits in the mode, and the remaining bits excluding the partial bits in the eighth error detection code and the sixth error detection code. From the eighth error detection code generator and the semiconductor memory device that combine the remaining bits excluding the partial bits in the data to generate the remaining bits excluding the partial bits of the fourth final error detection signal. It is characterized by including a memory control unit having an error detection signal generator that generates an error detection signal by comparing the output first to fourth final error detection signals.A fifth error detection code is generated for the upper n bits of the 2 n-bit first data output from the Mori device and the n bits of the first data output from the semiconductor memory device in the second bit structure mode. , The fifth error detection code generator that generates a part bit of the third final error detection signal by combining some bits in the fifth error detection code and some bits in the seventh error detection code. A sixth error detection code is generated for the lower n bits of the first data of 2 n bits in the bit structure mode, and some bits in the sixth error detection code and some bits in the eighth error detection code are generated. A sixth error detection code generator that is combined to generate the remaining bits of the third final error detection signal excluding the partial bits, and a 2n-bit second output from the semiconductor memory device in the first bit structure mode. The 7th error detection code is generated for the upper n bits of the 2 data and the n bits of the 2nd data in the 2nd bit structure mode, and the remainder excluding the partial bits in the 7th error detection code. 7th error detection code generator that generates a partial bit of the 4th final error detection signal by combining the bit of the above and the remaining bits excluding the partial bit in the 5th error detection code, the 1st bit structure. The eighth error detection code is generated for the lower n bits of the second data of 2n bits in the mode, and the remaining bits excluding the partial bits in the eighth error detection code and the sixth error detection code. From the eighth error detection code generator and the semiconductor memory device that combine the remaining bits excluding the partial bits in the data to generate the remaining bits excluding the partial bits of the fourth final error detection signal. It is characterized by including a memory control unit having an error detection signal generator that generates an error detection signal by comparing the output first to fourth final error detection signals.The fifth error detection code that generates a error detection code and generates a part bit of the third final error detection signal by combining some bits in the fifth error detection code and some bits in the seventh error detection code. The generator generates a 6th error detection code for the lower n bits of the 1st data of 2n bits in the 1st bit structure mode, and some bits in the 6th error detection code and the 8th error detection code. A sixth error detection code generator that combines some of the bits to generate the remaining bits of the third final error detection signal excluding the partial bits, and outputs from the semiconductor memory device in the first bit structure mode. The seventh error detection code is generated for the upper n bits of the second data of 2 n bits and the n bits of the second data in the second bit structure mode, and the one in the seventh error detection code is generated. A seventh error detection code generator that generates a partial bit of the fourth final error detection signal by combining the remaining bits excluding the partial bits and the remaining bits excluding the partial bits in the fifth error detection code. , The 8th error detection code is generated for the lower n bits of the 2n data of the 2n bits in the 1st bit structure mode, and the remaining bits excluding the partial bits in the 8th error detection code are used. The eighth error detection code generator, which combines the remaining bits of the sixth error detection code excluding the partial bits to generate the remaining bits of the fourth final error detection signal excluding the partial bits. It is characterized by including a memory control unit having an error detection signal generator that generates an error detection signal by comparing the first to fourth final error detection signals output from the semiconductor memory device.The fifth error detection code that generates a error detection code and generates a part bit of the third final error detection signal by combining some bits in the fifth error detection code and some bits in the seventh error detection code. The generator generates a 6th error detection code for the lower n bits of the 1st data of 2n bits in the 1st bit structure mode, and some bits in the 6th error detection code and the 8th error detection code. A sixth error detection code generator that combines some of the bits to generate the remaining bits of the third final error detection signal excluding the partial bits, and outputs from the semiconductor memory device in the first bit structure mode. The 7th error detection code is generated for the upper n bits of the 2n bits of the 2nd data and the n bits of the 2nd data in the 2nd bit structure mode, and the 1st in the 7th error detection code is generated. A seventh error detection code generator that generates a partial bit of the fourth final error detection signal by combining the remaining bits excluding the partial bits and the remaining bits excluding the partial bits in the fifth error detection code. , The 8th error detection code is generated for the lower n bits of the 2n data of the 2n bits in the 1st bit structure mode, and the remaining bits excluding the partial bits in the 8th error detection code are used. The eighth error detection code generator, which combines the remaining bits of the sixth error detection code excluding the partial bits to generate the remaining bits of the fourth final error detection signal excluding the partial bits. It is characterized by including a memory control unit having an error detection signal generator that generates an error detection signal by comparing the first to fourth final error detection signals output from the semiconductor memory device.A sixth error detection code generator that combines a bit and some bits in the eighth error detection code to generate the remaining bits excluding the partial bits of the third final error detection signal, the first bit structure mode. The seventh error detection code is generated for the upper n bits of the 2n bits of the second data output from the semiconductor memory device and the n bits of the second data in the second bit structure mode, and the seventh error detection code is generated. The remaining bits excluding the partial bits in the error detection code and the remaining bits excluding the partial bits in the fifth error detection code are combined to generate a partial bit of the fourth final error detection signal. The seventh error detection code generator generates an eighth error detection code for the lower n bits of the second data of 2 n bits in the first bit structure mode, and the partial bits in the eighth error detection code. The remaining bits excluding the part are combined with the remaining bits excluding the part bit in the sixth error detection code to generate the remaining bit excluding the part bit of the fourth final error detection signal. 8 Provided with an error detection code generator and a memory control unit having an error detection signal generator that generates an error detection signal by comparing the first to fourth final error detection signals output from the semiconductor memory device. It is characterized by.A sixth error detection code generator that combines a bit and some bits in the eighth error detection code to generate the remaining bits excluding the partial bits of the third final error detection signal, the first bit structure mode. The seventh error detection code is generated for the upper n bits of the 2n bits of the second data output from the semiconductor memory device and the n bits of the second data in the second bit structure mode, and the seventh error detection code is generated. The remaining bits excluding the partial bits in the error detection code and the remaining bits excluding the partial bits in the fifth error detection code are combined to generate a partial bit of the fourth final error detection signal. The seventh error detection code generator generates an eighth error detection code for the lower n bits of the second data of 2 n bits in the first bit structure mode, and the partial bits in the eighth error detection code. The remaining bits excluding the part are combined with the remaining bits excluding the part bit in the sixth error detection code to generate the remaining bit excluding the part bit of the fourth final error detection signal. 8 Provided with an error detection code generator and a memory control unit having an error detection signal generator that generates an error detection signal by comparing the first to fourth final error detection signals output from the semiconductor memory device. It is characterized by.The fourth error detection code is generated by combining the remaining bits excluding the partial bits in the eighth error detection code and the remaining bits excluding the partial bits in the sixth error detection code. Error detection by comparing the 8th error detection code generator that generates the remaining bits of the final error detection signal excluding the partial bits and the 1st to 4th final error detection signals output from the semiconductor memory device. It is characterized by including a memory control unit having an error detection signal generator that generates a signal.The fourth error detection code is generated by combining the remaining bits excluding the partial bits in the eighth error detection code and the remaining bits excluding the partial bits in the sixth error detection code. Error detection by comparing the 8th error detection code generator that generates the remaining bits of the final error detection signal excluding the partial bits and the 1st to 4th final error detection signals output from the semiconductor memory device. It is characterized by including a memory control unit having an error detection signal generator that generates a signal.</p><p> Each of the first to eighth error detection code generators is configured by using the cyclic redundancy check code method, and each of the first and fifth error detection code generators uses the same first error detection code generation polymorphism. The second exclusive OR circuit is provided, and each of the second and sixth error detection code generators is configured by using the same second error detection code generation polypoly. Each of the third and seventh error detection code generators includes a third exclusive OR circuit configured by using the same third error detection code generation polypoly, and the fourth and eighth error detection codes are detected. Each of the code generators is characterized by having a fourth exclusive OR circuit constructed by using the same fourth error detection code generation polypoly.</p>

<p> The semiconductor memory device according to the present invention can reduce the layout area even in the case of the ODIC pad structure, and can generate an error detection code without lowering the error detection capability.</p><p> Further, the memory system according to the present invention can generate an error detection code by using a separate error detection code generator without deteriorating the error detection capability.</p>

Hereinafter, the semiconductor memory device according to the present invention and the memory system having the same will be described with reference to the attached drawings.

FIG. 2 is a block diagram showing the configuration of the first embodiment of the semiconductor memory device having the ODIC pad structure of the present invention, and is a block diagram showing the first to fourth memory cell array blocks BLK1 to BLK4, the first and second error detection code generators. ECCG1, ECCG2, 1st and 2nd parallel series data converters 1P2S, 2P2S and clock signal generator CLKG, 1st parallel series converter 1P2S consists of k parallel series converters 1P2S1 ~ 1P2Sk The 2 parallel series converter 2P2S is composed of k parallel series converters 2P2S1 ~ 2P2Sk.

The pads of FIG. 2 have an ODIC pad structure similar to the pads of FIG. 1, and in FIG. 2, DQ11 to DQ1k are the data pads of the first group, and DQ21 to DQ2k are the data pads of the second group. Each is shown. Data DO1 to DO4 indicate n-bit data output from the first to fourth memory cell array blocks BLK1 to BLK4, respectively.

The semiconductor memory device of FIG. 2 has a total of 2 n-bit data output from the first and fourth memory cell array blocks BLK1 and BLK4, or a total of 2 n-bit data output from the second and third memory cell array blocks BLK2 and BLK3. It is shown assuming that the data DO2 and DO3 of are output selectively.

The functions of the blocks shown in FIG. 2 will be described below.

The first error detection code generator ECCG1 inputs the n-bit data DO1 or DO2 output from the first or second memory cell array block BLK1 or BLK2 to generate a 2m-bit first error detection code, and generates a 2m-bit first error detection code. The upper m-bit of the first error detection code and the second error detection code of the upper m-bit transmitted from the second error detection code generator ECCG2 are combined to generate the final error detection code of the upper m-bit. The second error detection code generator ECCG2 inputs the n-bit data DO3 or DO4 output from the third or fourth memory cell array block BLK3 or BLK4 to generate a 2m-bit second error detection code, and generates a 2m-bit second error detection code. The lower m-bit of the second error detection code of the above and the first error detection code of the lower m-bit transmitted from the first error detection code generator ECCG1 are combined to generate the final error detection code of the lower m-bit. The clock signal generator CLKG has n / k + m / k clock signals P1 to P (n / k + m / k) having different phases in response to an externally applied clock signal (not shown). ), Or n / k + m / k clock signals P1 to P (n / k + m / k) having internally different phases. Each of the parallel series converters 1P2S1 to 1P2Sk responds to each of n / k + m / k clock signals P1 to P (n / k + m / k) with data for each n / k bit and m / k. The upper final error detection code for each bit is converted in series and output via the corresponding pads DQ11 to DQ1k. Each of the parallel series converters 2P2S1 to 2P2Sk responds to each of n / k + m / k clock signals P1 to P (n / k + m / k) with data for each n / k bit and m / k. The upper final error detection code for each bit is converted in series and output via the corresponding pads DQ21 to DQ2k.

The semiconductor memory device having the ODIC pad structure shown in FIG. 2 has a control 1 error detection code generator ECCG1 and a first for generating an error detection code for the data output from the first or second memory cell array block BLK1 or BLK2. 3 or 4th memory cell array block A control for generating an error detection code for the data output from BLK3 or BLK4. 2 An error detection code generator ECCG2 is provided separately. This eliminates the need for long signal lines for transmitting data DO1 and DO2 and signal lines for transmitting data DO3 and DO4.

The semiconductor memory device having the ODIC pad structure shown in FIG. 2 transmits the first error detection code of the upper m-bit from the first error detection code generator ECCG1 to the second error detection code generator ECCG2 to generate the second error detection code. The lower m-bit second error detection code is transmitted from the device ECCG2 to the first error detection code generator ECCG1. Therefore, 2 m of signal lines must be arranged long. However, this is very small compared to the number of signal lines for transmitting data. Therefore, the layout area of the semiconductor memory device having the ODIC pad structure according to the present invention is reduced.

FIG. 3 shows the configuration of the first error detection code generator of FIG. 2, which is composed of an error detection code generation circuit 10 and an exclusive OR circuit 12.

The functions of the blocks shown in FIG. 3 will be described below.

When the n-bit data D is input, the error detection code generation circuit 10 generates 2 m-bit first error detection codes 1ec1 and 1ec2 for the n-bit data. The exclusive OR gate 12 takes the exclusive OR of the first error detection code 1ec1 of the 2 m bits, the first error detection code 1ec1 of the upper m bits of 1ec2, and the second error detection code 2ec1 of the upper m bits. Generates the final error detection code fec1 for the upper mbit.

Although not shown, the second error detection code generator is configured in the same manner as in FIG.

FIG. 4 shows the configuration of the embodiment in the error detection code generation circuit of FIG. 3, and is composed of the first to eighth exclusive OR circuits.

The circuit in Fig. 4 is configured by the Cyclic Redundancy Check (CRC) code method, and the error detection code generation polynomial is X.⁸+ X⁵+ X³+ X²It is a figure which shows the structure of + X + 1.

In addition, the error detection code generator in Fig. 4 outputs 40-bit data d32 ... d10 ... 0 with "00000000" data added to the least significant bit data side of the 32-bit parallel output data d32 to d1. It shows the configuration in which the rest generated by dividing by the data "100101111" corresponding to the polypoly is generated by the error detection codes r1 to r8.

In FIG. 4, the first exclusive OR circuit takes the exclusive OR of the data d1, d2, d5, d7 to d11, d17, d20 to d25, d27, d29, and d32 to generate the error detection code r1. The second exclusive OR circuit takes the exclusive OR of the data d2, d4 ~ d6, d11, d16, d17, d19, d25 ~ d29, d31, d32 to generate the error detection code r2, and the third exclusive The OR circuit takes the exclusive OR of the data d2 ~ d4, d7 ~ d9, d11, d16 ~ d18, d20 ~ d23, d26, d28 ~ d32 to generate the error detection code r3, and the fourth exclusive OR. The circuit takes the exclusive OR of the data d3, d5, d6, d9, d11, d14 ~ d16, d19, d23, d24, d28, d30 ~ d32 to generate the error detection code r4. Then, the fifth exclusive OR circuit takes the exclusive OR of the data d2, d4, d5, d8, d10, d13 to d15, d18, d22, d23, d27, d29 to d31 and generates the error detection code r5. Then, the 6th exclusive OR circuit takes the exclusive OR of the data d2 ~ d5, d8, d10 ~ d14, d20, d23 ~ d28, d30, d32 to generate the error detection code r6, and the 7th exclusive OR. The exclusive OR circuit takes the exclusive OR of the data d1 ~ d4, d7, d9 ~ d13, d19, d22 ~ d27, d29, d31 to generate the error detection code r7, and the 8th exclusive OR circuit is the data d1. The error detection code r8 is generated by taking the exclusive OR of ~ d3, d6, d8 ~ d12, d18, d21 ~ d26, d28, and d30.

The error detection code generation circuit of FIG. 4 generates 2m-bit first error detection codes c1 to c8: 1ec so that the first error detection code generator generates the final error detection code fec of the upper m-bit. To do.

Assuming that the conventional semiconductor memory device shown in FIG. 1 is configured to have one error detection code generator and generate an 8-bit final error detection code for all 64-bit data, FIG. 2 shows. The semiconductor memory device of the present invention includes two error detection code generators, and an error detection code generation circuit in which each of the two error detection code generators generates an 8-bit error detection code for 32-bit data. Be prepared.

Therefore, each of the error detection code generators of the semiconductor memory device according to the present invention has the same order of error detection code generation polynomial as that used in the error detection code generator of the conventional semiconductor memory device for a small number of bits of data. Since the error detection code is generated using, the error detection capability will not be reduced.

FIG. 5 is a diagram showing the configuration of each embodiment of the parallel series converter shown in FIG. 2, and shows AND gates AND1 to AND (n / k) and AND (n / k + 1) to AND (n / k + m). It consists of / k) and OR gate OR1.

In FIG. 5, do11 to do (n / k) is the n / k bit data, 1ec11 to 1ec1 (m / k) is the m / k bit error detection code, and P1 to P (n / k + m /). k) Clock signals with different phases, DOUT indicates output data, respectively.

AND gates AND1 ~ AND (n / k + m / k) each respond to (n / k + m / k) clock signals P1 ~ P (n / k + m / k) with n / k. + m / k bit data and error detection code are output in sequence. The OR gate OR1 is ORed with the data output from each of the AND gates AND1 to AND (n / k + m / k) to generate the output data DOUT. Therefore, the n / k + m / k bit data and the error detection code are converted in series and output.

The parallel series converter in Fig. 5 is shown to output n / k bit data first and then m / k bit error detection code. However, the data is output after the error detection code is transmitted first. It may be transmitted, or an error detection code may be transmitted in the middle of the data.

FIG. 6 is a diagram showing the configuration of the second embodiment of the semiconductor memory device having the ODIC pad structure of the present invention, in which the first to fourth memory cell array blocks BLK1 to BLK4 and the first to fourth error detection code generators ECCG1 are shown. It consists of ~ ECCG4, 1st and 2nd parallel series converters 1P2S, 2P2S, and clock signal generator CLKG. The first parallel series converter 1P2S and the second parallel series converter 2P2S have the same configuration as in FIG.

The pads of FIG. 6 have an ODIC structure similar to the pads of FIG. 2, and in FIG. 6, DQ11 to DQ1k are the data pads of the first group, and DQ21 to DQ2k are the data pads of the second group. Shown. Data DO1 to DO4 indicate 2n-bit data output from the 1st to 4th memory cell array blocks BLK1 to BLK4, respectively.

The semiconductor memory device of FIG. 6 is a total of 4 n-bit data output from the first and fourth memory cell array blocks BLK1 and BLK4, or all 4 n-bit data output from the second and third memory cell array blocks BLK2 and BLK3. It is shown on the assumption that data DO2 and DO3 are output selectively.

The functions of each block shown in FIG. 6 will be described below.

The 1st error detection code generator ECCG1 outputs a 2m-bit 1st error detection code to the 2n-bit data DO1 or the lower n-bit data of DO2 output from the 1st or 2nd memory cell array block BLK1 or BLK2. The upper m-bit of the 1st error detection code of 2m bits and the upper m-bit of the 3rd error detection code of 2m bits output from the 3rd error detection code generator ECCG3 are combined to generate the upper m-bit of the final error detection code. Generate lower m bits within 2 m bits. The second error detection code generator ECCG2 outputs a 2m-bit second error detection code to the 2n-bit data DO1 or the upper n-bit data of DO2 output from the first or second memory cell array block BLK1 or BLK2. The final error of the upper 2m bits is generated by combining the upper m bits of the 2m bit 2nd error detection code and the upper m bits of the 2m bits 4th error detection code output from the 4th error detection code generator ECCG4. Generate the upper m bits in the upper 2 m bits of the detection code. The third error detection code generator ECCG3 outputs a 2m-bit third error detection code to the 2n-bit data DO3 or the lower n-bit data of DO4 output from the third or fourth memory cell array block BLK3 or BLK4. The lower m bits of the 3rd error detection code of 2m bits and the lower m bits of the 1st error detection code of 2m bits output from the 1st error detection code generator ECCG1 are combined to generate the lower 2m of the final error detection code. Generate lower m bits in bits. The 4th error detection code generator ECCG4 outputs a 2m-bit 4th error detection code to the 2n-bit data DO3 or the upper n-bit data of DO4 output from the 3rd or 4th memory cell array block BLK3 or BLK4. The upper m bits of the 4th error detection code of 2m bits and the upper m bits of the 2nd error detection code of 2m bits output from the 2nd error detection code generator ECCG2. To generate the upper m bits in the lower 2 m bits of the final error detection code in combination with. The clock signal generator CLKG generates 2n / k + 2m / k clock signals having different phases in response to an externally applied clock signal (not shown), or internally has different phases. 2n / k + 2m / k clock signals with. Each of the k parallel series converters 1P2S1 to 1P2Sk has different phases. In response to each of the 2n / k + 2m / k clock signals, the data DO1 or DO2 and every 2m / k bits per 2n / k bits. The upper final error detection code of is converted in series and output via the corresponding pads DQ11 to DQ1k. Data DO3 or DO4 every 2n / k bits and lower final error detection code every 2m / k bits in response to each of the k parallel series converters 2P2S1 to 2P2Sk or clock signals with different phases. It is converted in series and output via the corresponding pads DQ21 to DQ2k.

The semiconductor memory device having the ODIC pad structure of FIG. 6 is a first and second error detection code generator for generating an error detection code for the data output from the first or second memory cell array block BLK1 or BLK2. ECCG1, ECCG2 and 3rd or 4th memory cell array block The 3rd and 4th error detection code generators ECCG3 and ECCG4 for generating error detection code for the data output from BLK3 or BLK4 are separately provided. To. This eliminates the need for long signal lines to carry data DO1 or DO2 and data DO3 or DO4, but simply to carry the m-bit error detection code output from each error detection code generator. Only all 4m signal lines need be long. This is very small compared to the number of signal lines for transmitting data, and therefore the semiconductor memory device having the ODIC pad structure of the present invention has a reduced layout area.

The error detection code generator of FIG. 6 has the same configuration as the error detection code generator of FIG. 3, and the error detection code generation circuit is configured in the same manner as the error detection code generation circuit of FIG. And although not shown, the series-parallel converter is also configured by the same method as the series-parallel converter of FIG.

If all 64-bit data DO1 or DO2 is output from the 1st or 2nd memory cell array blocks BLK1 and BLK2, the 1st to 4th error detection code generators ECCG1 to ECCG4 are 32 bits by the error detection code generation circuit shown in Fig. 4. An error detection code for each 8 bits is generated for each data, and a final error detection code for each 4 bits is generated by the exclusive logical sum gate shown in FIG.

The semiconductor memory device of FIG. 6 can also generate an error detection code without deteriorating the error detection capability as in the semiconductor memory device of FIG.

FIG. 7 is a diagram showing a configuration of a third embodiment in the semiconductor memory device of the present invention, in which the first to fourth memory cell array blocks BLK1 to BLK4, the first to eighth selectors SEL1 to SEL8, and the first to fourth are used. It consists of error detection code generators ECCG1 to ECCG4, first and second parallel series converters 1P2S, 2P2S, clock signal generator CLKG, and control signal generator CONP. Each of the first to fourth memory cell array blocks BLK1 to BLK4 is composed of the first and second submemory cell array blocks BLLK11, BLLK12 to BLLK41, and BLLK42, and the first parallel series converter 1P2S is k parallel series converters. It is composed of 1P2S1 ~ 1P2Sk, and the second parallel series converter 2P2S is composed of k parallel series converters 2P2S1 ~ 2P2Sk.

The pads of FIG. 7 have an ODIC structure similar to the pads of FIG. 1, and in FIG. 7, DQ11 to DQ1k are the data pads of the first group, and DQ21 to DQ2k are the data pads of the second group. Shown. 2 n-bit data DO11, DO12, DO21, DO22, DO31, DO32, DO41, DO42 indicate n-bit first and second data output from the first to fourth memory cell array blocks BLK1 to BLK4, respectively.

The semiconductor memory device of FIG. 7 can operate in the 1st bit structure mode or the 2nd bit structure mode, and is output from the 1st and 4th memory cell array blocks BLK1 and BLK4 in the 1st bit structure mode. All 4n-bit data DO11, DO12, DO41, DO42 or all 4n-bit data DO21, DO22, DO31, DO32 output from the 2nd and 3rd memory cell array blocks BLK2, BLK3 can be selectively output. It is possible. Then, in the second bit structure mode, all the data output from the first and second sub-memory cell array blocks BLK11 or BLK12, BLK41 or BLK42 of the first and fourth memory cell array blocks BLK1 and BLK4, respectively. 2n-bit data or all 2n-bit data output from the 1st and 2nd sub-memory cell array blocks BLK21 or BLK22, BLK41 or BLK42 of the 1st and 2nd sub-memory cell array blocks of BLK2 and BLK3, respectively. Can be selectively output.

The functions of the blocks shown in FIG. 7 will be described below.

If the command signal COM applied via the address and command signal application pad CMD / ADD is a mode setting command, the control signal generation unit CONP decodes the mode setting code applied at this time and has a first bit structure. If a mode signal that specifies the mode or 2nd bit structure mode is set, the command signal COM is a write or read command, and the mode signal specifies the 1st bit structure mode, all the 1st and 2nd control signals con1 and con2 are set. Activate and deactivate the second control signal con2 if the mode signal specifies the second bit structure mode and activate the first control signal con1 in response to a 1-bit column (or row) address. Inactivate. The 1-bit column (or row) address is an address used to divide the first and second sub-memory cell array blocks of the memory cell array blocks BLK1 to BLK4, respectively. The first, fourth, fifth, and eighth selectors SEL1, SEL4, SEL5, and SEL8 each select and output the first data DO11, DO31, DO21, and DO41 when the first control signal con1 is activated. , When deactivated, the second data DO12, DO32, DO22, DO42 are selected and output. The second, third, sixth, and seventh selectors SEL2, SEL3, SEL6, and SEL7 each select and output the second data DO12, DO32, DO22, and DO42 when the second control signal con2 is activated. , When the second control signal con2 is deactivated, the data output is blocked. The first to fourth error detection code generators ECCG1 to ECCG4 each perform the same functions as the first to fourth error detection code generators shown in FIG. The 1st and 2nd parallel series converters 1P2S and 2P2S each perform the same function as the 1st and 2nd parallel series converters in FIG. The clock signal generator CLKG performs the same function as the clock signal generator shown in FIG. However, in the 1st bit structure mode, data is output via the data pads DQ11 to DQ1k and DQ21 to DQ2k of the 1st and 2nd groups of k pieces each, and the 2nd bit.

The layout area of the semiconductor memory device having the ODIC pad structure shown in FIG. 7 is reduced as in the semiconductor memory device shown in FIG.

Further, the error detection code generator of FIG. 7 can have the same configuration as the error detection code generator of FIG. 3, and the error detection code generation circuit should be configured in the same manner as the error detection code generation circuit of FIG. Can be done. And although not shown, the series-parallel converter can also be configured by the same method as the series-parallel converter of FIG.

The semiconductor memory device of FIG. 7 can also generate an error detection code without deteriorating the error detection capability.

The first and fourth error detection code generators and the second and third error detection code generators of FIGS. 6 and 7 may be configured by using the same error detection code generation polynomials, and different error detection codes. It may be constructed using a generation polynomial. If different error detection code generation polynomials are used, the configurations of the first and fourth error detection code generators and the configurations of the second and third error detection code generators will be different.

FIG. 8 is a block diagram showing the configuration of the fourth embodiment of the semiconductor memory device having the ODIC pad structure of the present invention, and two of each of the first to fourth error detection code generators ECCG1 to ECCG4 of FIG. 7 are shown. Similar to the configuration shown in FIG. 7, except that the first to fourth error detection code generators ECCG11, ECCG12 to ECCG41, and ECCG42 are replaced, and the control signal generator CONP is replaced with the control signal generator CONP'. It is configured.

Of the blocks of FIG. 8, the functions of the same blocks as those of FIG. 7 are omitted, and the functions of the alternative blocks will be described here.

The two first to fourth error detection code generators ECCG11, ECCG12 to ECCG41, and ECCG42 are each configured using different error detection code generation polynomials. For example, the error detection code generators ECCG11, ECCG21, ECCG31, and ECCG41 are configured using the same error detection code generation polypoly, and the error detection code generators ECCG12, ECCG22, ECCG32, and ECCG42 are error detection code generators ECCG11, ECCG21, It is constructed using an error detection code generation polypoly different from ECCG31 and ECCG41. As yet another example, two error detection code generators ECCG11 and ECCG41 are configured using the same error detection code generation polypoly, and error detection code generators ECCG21 and ECCG31 are error detection code generators ECCG11 and ECCG41. The error detection code generators ECCG12 and ECCG42 are configured using error detection code generation polynomies different from those of the error detection code generators ECCG11, ECCG41, ECCG21, and ECCG31. The generators ECCG22 and ECCG32 are configured using an error detection code generation polymorphism different from the error detection code generators ECCG11, ECCG41, ECCG21, ECCG31, ECCG12, and ECCG42. The control signal generator CONP'has the function of the control signal generator CONP in FIG. 7, and further counts a predetermined time in response to one clock signal generated from the clock signal generator CLKG to cycle the third control signal con3. Is activated. The error detection code generators ECCG11, ECCG21, ECCG31, and ECCG41 are enabled when the third control signal con3 is activated to perform the same operation as the error detection code generator shown in FIG. 7, and the error detection code generator ECCG12. , ECCG22, ECCG32, ECCG42 are enabled when the third control signal con3 is deactivated and error detection in Figure 7.

The semiconductor memory device of FIG. 8 can generate a final error detection code by an error detection code generator having different configurations periodically.

The semiconductor memory device of FIG. 8 also has a large number of signal lines arranged longer than the semiconductor memory devices of FIGS. 2, 6 and 7, but a smaller number of signal lines are arranged than the conventional semiconductor memory device. It will be. Therefore, the layout area can be reduced as compared with the conventional semiconductor memory device.

Further, the semiconductor memory device of FIG. 8 can increase the error detection capability by operating with an error detection code generator composed of periodically different error detection code generation polynomials.

Although the above-described embodiment has described the present invention using a semiconductor memory device having an ODIC pad structure, it can be applied even if the semiconductor memory device does not have an ODIC pad structure.

Then, if the semiconductor memory device of the embodiment of FIG. 8 is a dynamic semiconductor memory device (DRAM), it can be configured to generate a third control signal con3 in response to a refresh instruction or a cycle. For example, using a method in which the third control signal con3 is activated in response to the first refresh instruction or cycle and the third control signal con3 is deactivated in response to the second refresh instruction or cycle. Can be configured. That is, it is sufficient that the third control signal con3 can be toggled in response to the refresh instruction or the cycle.

FIG. 9 is a diagram showing a configuration of an embodiment in the memory system of the present invention, which is composed of a semiconductor memory device 100 and a memory control unit 200. The memory control unit 200 is composed of the first and second series-parallel converters 1S2P, 2S2P, the clock signal generator CLKG, the first to fourth error detection code generators ECCG1 to ECCG2, the error detector ED, and the data input unit 20. , The error detector ED is composed of XOR gates XOR1 to XOR4 and OR gate OR. The first series-parallel converter 1S2P is composed of k series-parallel converters 1S2P1 to 1S2Pk, and the second series-parallel converter 2S2P is composed of k series-parallel converters 2S2P1 to 2S2Pk.

The semiconductor memory device 100 of the memory system of FIG. 9 shows a configuration assuming a configuration having the same configuration as that of FIG.

The error detection code generators ECCG1 to ECCG4 of the memory control unit 200 in FIG. 9 have the same configuration by the cyclic redundancy check code method as each of the first to fourth error detection code generators ECCG1 to ECCG4 in FIG. It is constructed using the error detection code generation polynomial of. Therefore, the error detection code generators ECCG1 to ECCG4 of FIG. 9 can be configured to have the same configuration as the error detection code generators ECCG1 to ECCG4 of FIG.

In FIG. 9, each of the data dout11 to dout1k shows the data output from each of the data pads DQ11 to DQ1k, and each of the data dout21 to dout2k shows the data output from each of the data pads DQ21 to DQ2k.

The functions of the blocks shown in FIG. 9 will be described below.

The semiconductor memory device 100 performs the same function as the semiconductor memory device of FIG. The clock signal generator CLKG performs the same function as the clock signal generator CLKG in FIG. 6 and outputs n / k + m / k clock signals P1 to P (n / k + m / k) having different phases. Generate. Each series-parallel converter 1S2P1 to 1S2Pk is applied in series in response to each of n / k + m / k clock signals P1 to P (n / k + m / k). The data and the upper final error detection code for each m / k bit are input and converted in parallel to generate the 2n bit upper data and the 2m bit upper final error detection code. Each of the series-parallel converters 2S2P1 to 2S2Pk is a lower level of each n / k bit applied in series in response to each of n / k + m / k clock signals P1 to P (n / k + m / k). The data and the lower final error detection code for each m / k bit are input and converted in parallel to generate the 2n bit lower data and the 2m bit lower final error detection code. The first to fourth error detection code generators ECCG1 to ECCG4 each perform the same operation as the error detection code generators ECCG1 to ECCG4 in FIG. 6 to generate the final error detection code for each m-bit. Each of the XOR gates XOR1 to XOR4 corresponds to the final error detection code for each m-bit output from each of the first to fourth error detection code generators ECCG1 to ECCG4 and the output from the first and second series-parallel converters. The error detection signals e1 to e4 are generated by taking the exclusive OR with the final error detection code for each m-bit. That is, if the m-bit final error detection code output from the error detection code generator and the corresponding m-bit final error detection code output from the series-parallel converter are the same for each of the XOR gates XOR1 to XOR4, " The data of "0" is output, and if it is different, the data of "1" is generated. The OR gate OR ORs the error detection signals e1 to e4 to generate an error detection signal ER of "1" if at least one is "1". Data entry unit 20 has "0" gills

Further, although not shown, the error detection signal ER can be configured to be transmitted to the semiconductor memory device 100. Further, the semiconductor memory device 100 can be configured to block the transmission of output data when the error detection signal ER of "1" is transmitted.

FIG. 10 is a diagram showing the configuration of the embodiment in each of the series-parallel converters of FIG. 9, and shows D flip-flops DF11 to DF1 (n / k + n / k-1) and DF21 to DF2 (n / k + m /). It consists of k).

In FIG. 10, dout1 is the n / k-bit series input data and m / k-bit series input error detection code, DI11 to DI1 (n / k) is the n / k-bit parallel output data, and 1ec11 to 1ec1 ( m / k) indicates a parallel output error detection code of m / k bits, and P1 to P (n / k + m / k) clock signals having different phases.

D flip-flops DF11 to DF1 (n / k + m / k-1) each have n / k-bit data and n / k-bit data input in series in response to each n / k + m / k-1 clock signal. Saves and outputs the 1st to m / k-1st error detection codes. D flip-flops DF21 to DF2 (n / k + m / k) Each responds to n / k + m / k clock signals and D flip-flops DF11 to DF1 (n / k + m / k-1) The data output from each and the m / k th input error detection code are saved, and the n / k bit parallel output data and the m / k bit parallel output error detection code are output at the same time. Therefore, the n / k + m / k bit data and the error detection code are converted in parallel and output.

Further, it has been shown that the semiconductor memory device of the memory system in the above-described embodiment includes only an error detection code generator and a parallel series converter to generate and transmit an error detection code for output data. A series-parallel converter, an error detection code generator, and an error detector configured in the control unit may be further provided to generate an error detection signal for the input data. Similarly, the memory control unit may further include an error detection code generator and a parallel series converter configured in the semiconductor memory device so as to generate and transmit an error detection code for the output data. ..

The memory control unit of the memory system in the above-described embodiment is configured to have a configuration corresponding to the case where the semiconductor memory device has the configuration shown in FIG. 6, and if the semiconductor memory device has the configuration shown in FIGS. 2 and 7. Alternatively, when the configuration shown in FIG. 8 is provided, the configuration may be configured to correspond to the configuration of each semiconductor memory device.

The semiconductor memory device in the above-described embodiment can also be applied to a semiconductor memory device that does not have an ODIC pad structure.

The semiconductor memory device according to the above-described embodiment is provided with a parallel-series converter to output data, but the semiconductor memory device may output parallel data as it is without having a parallel-series converter. Similarly, the memory control unit includes the series-parallel converter to input data, but the memory control unit may not have the series-parallel converter and input the parallel data as it is.

The data transmission / reception method in the above-described embodiment can be applied not only between the semiconductor memory device and the memory control unit but also to all data transmission / reception systems.

Although the above description has been made with reference to the preferred embodiments of the present invention, those skilled in the art will use the present invention as long as they do not deviate from the ideas and domains of the present invention described in the appended claims. It can be modified and changed in various ways.

<figref num="1">It is a block diagram which shows the structure of an example of the semiconductor memory apparatus which has a conventional ODIC pad structure.</figref><figref num="2">It is a block diagram which shows the structure of 1st Embodiment of the semiconductor memory apparatus which has the ODIC pad structure of this invention.</figref><figref num="3">It is a figure which shows the structure of the 1st error detection code generator of FIG.</figref><figref num="4">It is a figure which shows the structure of the embodiment in the error detection code generation circuit of FIG.</figref><figref num="5">It is a figure which shows the structure of each embodiment of the parallel series converter shown in FIG.</figref><figref num="6">It is a figure which shows the structure of the 2nd Embodiment of the semiconductor memory apparatus which has the ODIC pad structure of this invention.</figref><figref num="7">It is a figure which shows the structure of the 3rd Embodiment of the semiconductor memory apparatus which has the ODIC pad structure of this invention.</figref><figref num="8">It is a figure which shows the structure of the 4th Embodiment of the semiconductor memory apparatus which has the ODIC pad structure of this invention.</figref><figref num="9">It is a figure which shows the structure of embodiment in the memory system of this invention.</figref><figref num="10">It is a figure which shows the structure of the embodiment in each series-parallel converter of FIG.</figref>

Code description

1P2S 1st and 2nd parallel series converters 2P2S 1st and 2nd parallel series converters BLK1 1st memory cell array block BLK2 2nd memory cell array block BLK3 3rd memory cell array block BLK4 4th memory cell array block CLKG clock signal generator CONP control signal generator con1 1st control signal con2 2nd control signal DQ1k 1st group data pad DQ2k 2nd group data pad DO11 data DO12 data DO21 data DO22 data DO31 data DO32 data DO41 data DO42 data ECCG1 1st error detection code generator ECCG2 2nd error detection code generator ECCG3 3rd error detection code generator ECCG4 4th error detection code generator SEL1 1st selector SEL2 2nd selector SEL3 3rd selector SEL4 4th selector SEL5 5th selector SEL6 6th selector SEL7 7th selector SEL8 8th selector