Compliant substrate in particular for deposit by hetero-epitaxy
22 claims: 15 independent, 7 dependent
- 1キャリヤ(1,14,21,31)と該キャリヤの表面上に形成した少なくとも一つの薄層(4,13,23,34)とを備え、一体の形で応力供給構造を受けることが意図されているコンプライアント基板(5,20,30)であって、そのキャリヤとその薄層とが、前記構造によってもたらされた応力の全てあるいはその一部を吸収するように意図された結合手段(3;11,15,16;24,25)によって互いに結合されるコンプライアント基板において、 前記結合手段が、微小キャビティの層及び/又は前記構造によってもたらされた応力の全てあるいはその一部を吸収するように制御された結合エネルギーを有する結合界面、の中から選択された少なくとも一つの結合ゾーンを備えていることを特徴とするコンプライアント基板。
- 2一体の形で応力供給構造を受けることが意図されているコンプライアント基板(5)の製造方法であって、 キャリヤ(1)を提供するステップと、 一あるいは二以上の気体種のボンバードによる注入を通して微小キャビティの層(3)を形成するステップと、 を含み、 前記注入が、前記キャリヤの表面を介して行われ、前記キャリヤの表面と前記微小キャビティの層との間の領域が薄層(4)を規定し、 前記キャリヤと前記薄層とが、前記構造によってもたらされた応力の全てあるいはその一部を吸収するように意図された前記微小キャビティの層(3)によって互いに結合される ことを特徴とす るコ ンプライアント基板の製造方法。
- 3気体種が希ガス、水素、及びフッ素の中から選択されることを特徴とする請求項2に記載のコンプライアント基板の製造方法。
- 4一あるいは二以上の注入された気体種の拡散を行うことを特徴とする請求項2に記載のコンプライアント基板の製造方法。
- 5注入の後に熱処理を行うことを特徴とする請求項2に記載のコンプライアント基板の製造方法。
- 6前記キャリヤの表面 と微小キャビティ層との間の領域を薄くして前記の薄層を形成することを特徴とする 請求項2 に記載のコンプライアント基板の製造方法。
- 7ボンバードによる注入が、 前記キャリヤの表面 に支持される犠牲層(2)を介して行われ、その犠牲層はその後で除去され るこ とを特徴とする 請求項2 に記載のコンプライアント基板の製造方法。
- 8前記注入が 前記キャリヤの表面 を介して行われ、 前記キャリヤの表面 が第1の薄層を支持し、 前記キャリヤの表面 と微小キャビティ層との間の領域が第2の薄層を規定することを特徴とする請求項2から 請求項5 のいずれか一項に記載のコンプライアント基板の製造方法。
- 9微小キャビティ層が、前記第1の薄層と 前記キャリヤ との間の界面の近傍に形成されることを特徴とする 請求項8 に記載のコンプライアント基板の製造方法。
- 10ボンバードによる注入が、第1の薄層で支持される犠牲層を介して行われ、その犠牲層はその後で除去されることを特徴とする 請求項8または請求項9 のいずれかに記載のコンプライアント基板の製造方法。
- 11一体の形で応力供給構造を受けることが意図されているコンプライアント基板の製造方法であって、 キャリヤ(10)を提供するステップであって、前記キャリヤ(10)の一つの表面が、結合手段(11)によって覆われる、ステップと、 一あるいは二以上の気体種のボンバードによる注入を通して微小キャビティの層(12)を形成するステップであって、前記注入が、前記キャリヤの表面を介して行われ、前記キャリヤの表面と前記微小キャビティの層との間の領域が薄層(13)を規定する、ステップと、 第二キャリヤ層(14)を提供するステップであって、前記第二キャリヤ(14)の一つの表面が、第二結合手段(15)によって覆われる、ステップと、 前記構造によってもたらされた応力の全てあるいはその一部を吸収するように制御された結合エネルギーを有する結合界面(16)によって、前記結合手段(11)と前記第二結合手段(15)とを結合するステップと、 を含み、 制御された結合エネルギーを有する前記結合界面が表面準備及び/又は熱処理及び/又は界面における欠陥の形成に起因して形成されることを特徴とす るコ ンプライアント基板の製造方法。
- 12表面準備に起因して形成された界面が、その表面の少なくとも一つがラフネス及び/又は親水性の制御を行った界面であることを特徴とする 請求項11 に記載のコンプライアント基板の製造方法。
- 13前記結合ゾーンが、薄層(23;34)とキャリヤ(21;31)との間に少なくとも一つの中間層(22;32,33)も備えたことを特徴とする請求項1に記載のコンプライアント基板。
- 14中間層(22;32,33)が金属層または金属合金層であることを特徴とする 請求項13 に記載のコンプライアント基板。
- 15少なくとも一つの中間層が、応力を緩和することができる非均質性を有するように形成されたことを特徴とする 請求項13 に記載のコンプライアント基板。
- 16結合手段が、微小キャビティとその微小キャビティの上または下のいずれかに配置した結合界面とを備えたことを特徴とする請求項1または 請求項13から請求項15 のいずれか一項に記載のコンプライアント基板。
- 17前記薄層(4,13,23,34)が第1の結晶材料から成り、前記構造を形成する第2の結晶材料に対してヘテロエピタキシャル成長の種として用いられる前の層であることを特徴とする請求項1または 請求項13から請求項16 のいずれか一項に記載のコンプライアント基板。
- 18前記薄層が前記第1の結晶材料に対して異種の原子を含む応力付与の前の層であり、前記異種原子の存在が前記基板のコンプライアンスを促進することを特徴とする 請求項17 に記載のコンプライアント基板。
- 19前記異種原子がボンバードによる注入された原子及び/又は拡散した原子であることを特徴とする 請求項18 に記載のコンプライアント基板。
- 20前記異種原子が薄層のドーピング剤であることを特徴とする 請求項18または請求項19 のいずれかに記載のコンプライアント基板。
- 21前記第1の結晶材料が半導体であることを特徴とする 請求項17から請求項20 のいずれかに記載のコンプライアント基板(5,20,30)。
- 22請求項17から請求項21 のいずれか一項に記載のコンプライアント基板(5,20,30)を用いたGaN、SiGe、AlN、InN及びSiCの中から選択された結晶材料をヘテロエピタキシャル成長させる方法。
Independent claims22
1 paragraph, as filed
[0001] [Technical field to which the invention belongs] The present invention is capable of accepting stress induced by a compliant substrate, i.e., a layer deposited on the surface of the substrate by heteroepitaxy to receive minimal possible stress. It is about the substrate. [0002] [Problems to be solved by conventional techniques and inventions] In the use of electronics and optoelectronics, many semiconductor materials, especially compound semiconductors such as group III-V, are required. However, at present, only methods for producing solid substrates for certain semiconductors, such as, for example, silicon, gallium arsenide, silicon carbide and indium phosphide, are known. For other semiconductors, the method of choice is heteroepitaxial growth on a substrate that fits the grid of the semiconductor layer on which the crystalline network grows. [0003] However, the limitation of having to meet the lattice parameters at the interface formed between the layers and the substrate is that it is rare to find a substrate with a grid network that matches the desired layer, so the number of layers to grow. And its diversity is severely restricted. For example, no solid substrate is perfectly compatible with heteroepitaxial growth of GaN, AlN and InN. [0004] The use of poorly compatible substrates leads to the growth of very poor quality layers. In particular, as soon as the layer thickness exceeds the critical value (decreases as the poor fit of the grid network increases), the stress in the heteroepitaxial layer is released through the formation of structural defects (particularly dislocations). [0005] To overcome these problems, epitaxy experts on thick substrates have used growth methods involving the formation of buffer layer stacks. The purpose of this buffer layer stacking is to absorb the stress induced by the difference in lattice parameters between the substrate and the epitaxially grown layer due to the difference in the coefficient of thermal expansion between the two materials, mainly on the epitaxy surface. Is to do. In the case of this layer, the temperature at which the epitaxial layer grows is also a parameter to be considered. This stack of buffer layers is terminated with a superficial layer used to terminate the desired layer, the epitaxial growth layer. However, even when using all this know-how, the materials obtained always contain crystal defects and are often of poor quality for the manufacture of electronics and optoelectronic devices. [0006] Various studies have been conducted on compliant substrates to improve this problem. As an example, by YHLO, Appl.Phys.Lett. The paper "New Approach to Grow Pseudomorphic Structures over the Critical Thickness" published in 59 (18) (October 28, 1991) can be mentioned. In this field, a compliant substrate is essentially a crystal substrate whose crystal lattice (lattice parameters) do not need to be adapted to the layer, and when the heteroepitaxial layer grows, the stress associated with layer growth. It is desired that the relaxation of the above occurs not in the heteroepitaxial layer but in the compliant substrate itself or at the interface. In this case, a very high quality heteroepitaxial layer can be obtained, and in principle the compliant substrate allows the growth of any kind of layer on the crystal lattice. [0007] Manufacture of compliant substrates is divided into three groups. [0008] The first group is self-supporting, very fine (several nm) substrates, which are difficult and virtually impossible to manufacture when large surface areas are required. In this regard, for reference, Appl. Phys. Lett. By FEEJECKAM et al. The paper "Lattice Engineered Compliant Substrate for defect-free Hetero-epitaxial Growth" published in 70 (13) (March 31, 1997) can be mentioned. [0009] The second group is related to the SOI (Silicon-On-Insulator) structure on the substrate. In this case, the resulting surface film is very thin and the underlying insulating layer tends to deform due to the effects of temperature during the growth of the thin film. [0010] The third group involves so-called "twist bonding" type structures. In this case, the thin film that continues to undergo stress relaxation, called compliance, is molecularly attached to two crystal substrates of the same type with no crystal network oriented by thinning one of the substrates to a very thin layer. It is formed by bonding the two crystal substrates through adhesion). In this regard, for reference, Appl. Phys. Lett. By FEEJECKAM et al. The paper "Dislocation-free InSb Grown on GaAs Compliant Universal Substrates" published in 71 (6) (August 11, 1997) can be mentioned. This undirected bond causes the formation of dislocations found in the thinned layer near the interface, thereby adapting the stress when the heteroepitaxial layer grows on the interface. [0011] The use of compliant substrates in these prior arts is limited. For self-supporting membranes, the limit is a few mm<sup>2</sup>On the surface, and a few tens of centimeters more<sup>2</sup>It is attributed to the difficulty or practical impossibility of forming a film of several nanometers on the surface of the surface. With such a film thickness, no material is well established for handling. For SOI structures, the limitation is attributed to the incomplete compliance of the board. This is related to the ability of the insulator to deform (or shift) to absorb stress. To achieve this result, the composition must be heat treated at high temperature and / or adapted (eg, silicon dioxide type insulators doped with boron or phosphorus). These heat treatments are not always consistent with the layer to be epitaxial. With the third group of substrates, it is difficult to obtain defect-free bonds on large surfaces and to make the layers very thin. In addition, this technique reduces the incompatibility of crystal orientation between two substrates if it is desired to adequately control the number and type of dislocations that convey compliant properties to this type of structure. Requires very good control over. [0012] It is also well known that a tight bond between the two materials is obtained by molecular attachment. In some cases, it occurs in connection with the terminations present on the surface at the time of bonding. For example, the term hydrophilic or hydrophobic bonds are used. [0013] Surface hydrophilicity generally saturates the surface with OH hydroxyl groups (for silicon, for example, surface density 4.6 / nm).<sup>2</sup>) Obtained by chemical cleaning for the purpose. So water molecules can naturally adsorb to these sites. The contact between the two prepared surfaces has a large binding energy even at room temperature (0.1 J / m in the case of silicon oxide / silicon oxide bond).<sup>2</sup>) Will be attached. Subsequent heat treatment is enhanced by the development of bonds present at the interface. Therefore, SiO<sub>2</sub>-SiO<sub>2</sub>For bonds, heat treatment at low temperatures (usually below 300 ° C) results in hydrogen bonds between the hydroxyl groups facing the two surfaces through the initiation of the initial Si-O-Si bond. Therefore, the binding energy is 2 J / m at 900 ° C.<sup>2</sup>It increases regularly with temperature until it reaches the binding energy of. [0014] In contrast, hydrophobic bonds (ie, bonds that do not contain water molecules or hydroxyl groups) generally peel off the surface to remove bare oxides. In the case of silicon, for example, the cleaning used for peeling saturates the surface mainly at the Si-H termination. Bonding resistance is guaranteed by van der Waals-type attractive forces, and the binding energy measured at room temperature for silicon-silicon bonds is (approximately 10 mJ / m).<sup>2</sup>), It is closely related to theoretical calculation. With increasing temperature, Si-Si bonds are formed by the reconstruction of the two contact surfaces. [0015] This bonding mechanism occurs for many materials if the roughness and flatness are low enough. It is well lit that these two methods used are capable of controlling the binding forces between different contact materials in relation to heat treatment and surface treatment with surface roughness. An example of the development of this binding energy is described in the following literature: J. Micrmech. Microeng. Mechanism for Silicon Direct Bonding by Y. BACKLUND et al., 2 (1992), pp. 158-160 (see especially Figure 1). This binding energy is determined by a method that utilizes the growth of cracks in the interfacial bond by the effect of blade insertion, parallel to this interface at the bond interface. [0016] In 1989, some researchers attached a molecule that formed a bond between a GaAs / InGaAs / GaAs multilayer film (previously made on a substrate that fits this structure well) and a silicon oxide carrier. Some have discussed the possibility of using. Low binding force can be obtained by specific surface preparation. In this regard, for reference, J.Appl.Phys. By JFKLEM et al. The paper "Charging of Thin AlGaAs / InGaAs / GaAs Quantum-well Structure Bonded Directly to SiO2 / Si and Glass Substrates" published in 66 (1) (1st week of July 1989) can be mentioned. [0017] Injecting a rare gas or hydrogen into a semiconductor material or a solid material, whether crystalline or not, with a bombard can form microcavities or microplates at a depth close to the average penetration depth of the injected species. .. The morphology of these defects (size, shape, etc.) may change during heat treatment, and in particular these cavities may grow these sizes. Depending on the type of material, especially its mechanical properties, these cavities induce surface deformations called "blisters", depending on the conditions of the heat treatment. The most important parameters that need to be controlled to obtain such deformation are the dose of the gas introduced during the injection, the injection depth of the gas species, and the heating schedule applied during the injection. As an example, 3x10 with energy of 40 keV<sup>16</sup>H<sup>+</sup>/cm<sup>2</sup>When hydrogen is injected into a silicon wafer at this dose, a continuous embedded layer of microcavities with an average depth of 330 nm and a thickness of approximately 150 nm is formed. It means a layer containing microcavities uniformly dispersed over a certain thickness by a continuous layer. These microcavities have an elongated shape (hence the name "microplate"). These sizes are, for example, on the order of 6 nm in length and 2 atomic planes in thickness. After heat treatment at 700 ° C for 30 minutes, the microcavities expand and their size increases, for example, from 6 nm to 50 nm in length and to several atomic planes in thickness of 4-6 nm. On the other hand, it should be noted that the injection surface is not disturbed. The cavity size and the pressure in these cavities are not large enough to induce surface deformation. This forms a continuous layer of embedded defects with zones containing microcracks (or microcavities or microplates) but no surface degradation. [0018] The presence of microcavities is also seen, for example, in the case of injections made by helium bombard at an average injection depth of Rp on a silicon substrate. In this case, the resulting cavity is even present at an annealing temperature on the order of 1000 ° C. These defects cause strong and deep weaknesses in the material. [0019] [Means for solving problems] In order to remedy the shortcomings of the prior art, the present invention proposes a compliant substrate that supplies a thin film of material to be used to initiate heteroepitaxial growth of other materials. The embedded region is such that the thin layer and / or the bonding means accepts all or part of the stresses generated during the epitaxial growth of the epitaxial material and thus prevents these stresses from occurring in the epitaxial material. The thin layer is bonded to the remainder of the substrate by a bonding means called). [0020] The compliant properties of such structures relative to the material to be deposited next are related to the differences in lattice parameters, coefficient of thermal expansion, and presence of embedded regions. By definition, the purpose of this compliant substrate is to adapt the stress of the film of the deposited material by stress relief, although it can also be an embedded region, a thin layer. [0021] [0021] One variant of the method is to modify the crystal parameters of the thin film forming the germination film for epitaxy, resulting in heterogeneous surface thin films to change the stress state prior to epitaxial growth of the resulting layer. Includes the inclusion of atoms. [0022] It has also been found that such compliant substrates may, in principle, be used to absorb stress due to causes other than material growth due to epitaxy. In fact, this compliant substrate may be used to receive any stress supply structure. [0023] Therefore, an object of the present invention is a compliant substrate comprising a carrier and at least one thin layer formed on the surface of the carrier and intended to receive a stress supply structure in an integral manner. In a compliant substrate in which the carrier and its thin layer are bonded to each other by the bonding means and all or part of the stress provided by the structure is absorbed by the thin layer and / or the bonding means, the bonding means are bonded. It comprises at least one coupling zone selected from zones, i.e., a layer of microcavities and / or a binding interface whose binding energy is controlled to allow absorption of said stress. To provide a compliant substrate. [0024] The binding zone may be a defect layer, for example a microcavity layer. The defective layer may be formed through injection with one or more gas species bombards. These gas species may be selected from rare gases, hydrogen, and fluorine. Doping agents may be associated with one or more gas species. It is also possible to diffuse one or more injected gas species. Heat treatment may be performed to allow defects to grow after injection. Bombard injection is performed specifically through the substrate surface, and the region between the substrate surface and the microcavity layer defines the thin layer. Optionally, the region between the substrate surface and the microcavity layer is thinned to form the thin layer. Bombard injection may be performed via a sacrificial layer supported on the substrate surface, which sacrificial layer is subsequently removed. [0025] The injection is done through the substrate surface, which surface supports the first thin layer and the region between the substrate surface and the microcavity layer defines the second thin layer. The microcavity layer is formed near the interface between the first thin layer and the substrate. Bombard injection may be done through a sacrificial layer supported by a first thin layer, which sacrificial layer is subsequently removed. [0026] Bonding energy may be controlled by surface preparation and / or heat treatment and / or defect formation at the interface. These defects may be formed, for example, through injection by bombard and / or by binding the defects. The formation of this defect generally weakens the bond interface. The surface preparation may be a control of roughness and / or hydrophilicity. Wafer roughness may be obtained, for example, by chemical attack by HF. Hydrophilicity may be obtained by RCA type chemical cleaning. The binding zone also includes at least one intermediate layer between the thin layer and the carrier. The intermediate layer may be formed to have non-homogeneity capable of relieving stress. Examples include grain boundary bonds, growth lines, inclusions and the like. This layer may etch all or part of its surface. The intermediate layer may be a metal layer or a metal alloy layer. [0027] The bonding means may include a microcavity and a bonding interface located either above or below the microcavity. [0028] In one particular application, the thin layer consists of a first crystalline material and is intended to be used as a seed for heteroepitaxial growth with respect to the second crystalline material forming the structure. This thin layer may be a layer prior to stress application through the introduction of heteroatoms into the first crystalline material to facilitate compliance with the substrate. Heterogeneous material may be introduced via bombard injection and / or diffusion insertion. This injection may be done through the sacrificial layer. This hetero atom may be a thin layer doping agent. The first crystal material is particularly a semiconductor and may be, for example, Si or GaAs. Such compliant substrates may be used advantageously for heteroepitaxial growth of crystalline materials selected from GaN, SiGe, AlN, InN and SiC. [0029] BEST MODE FOR CARRYING OUT THE INVENTION The present invention is better understood and other advantages and special aspects become apparent by reading the following non-limiting description with reference to the accompanying drawings. [0030] By preferred example, the rest of the specification relates to the manufacture of compliant substrates for the deposition of materials by heteroepitaxy. [0031] It is possible to obtain a thin film from a substrate injected with a particle type (eg, ions), and this injection forms a layer of defects at a depth near the average penetration depth of that particle type. The defect layer defines a thin film between the substrate and the defect layer. This particle type is selected so that the layer of defects formed can accept the stress applied to the thin thin film. The role of the defect layer is also to support a thin film thickness (perpendicular, perpendicular to the surface) while leaving no stress in the horizontal plane (parallel to the surface). In some cases, for example, after the injection step, to increase the defect size, fuse the defects into larger sized clusters, and change the dispersion of the defects to make the layers more compatible with stress acceptance. Therefore, it may be necessary to heat-treat the substrate. [0032] It is preferable to select the particle type from a rare gas, hydrogen, or a combination thereof, which are known to enable the generation of microcavity type defects. In this case, above that, the injection of the particle species is lower than the critical dose, which is more likely to induce "bulging" type surface deformation, but sufficient dose must be selected to generate those microcavities. It doesn't become. As an example, in the case of silicon, 3x10<sup>16</sup>/cm<sup>2</sup>You may choose to inject hydrogen ions at the dose of. However, this critical dose must be identified as being related to injection conditions and the type of doping. [0033] The film thickness must be determined by the choice of injection energy. Low injection energy must be selected to form a very thin membrane (necessary to ensure good compliance). For example, in the case of silicon and hydrogen ions, the energy is preferably selected between 1 keV and 10 keV. In this range, it is possible to form a film with a film thickness between 5 nm and 60 nm. It is also possible to obtain a predetermined film thickness by thinning the film obtained by injection using energy larger than the energy for directly supplying the predetermined film thickness. [0034] In some cases, it may be advantageous to inject through a surface layer, such as a silicon oxide layer. In this case, it is no longer necessary to use very low energy. Removal of the sacrificial layer may be sufficient to obtain a very thin surface layer. [0035] Figures 1 (a) to 1 (c) show this last example. FIG. 1A shows a side view of a substrate 1 made of single crystal silicon, for example, coated with a silicon oxide layer 2 acting as a sacrificial layer. FIG. 1 (b) shows the stage of ion implantation using hydrogen ions into the substrate 1 via the oxide layer 2. The injection was performed under the above conditions. A microcavity or microplate layer 3 is obtained and the layer of the thin film 4 adjacent to the oxide layer 2 is determined. Due to the presence of this oxide layer, the film thickness of the thin layer 4 may be reduced and adjusted very accurately. Next, the oxide layer 2 is removed by chemical impact, and the compliant substrate 5 is obtained as shown in FIG. 1 (c). That is, an assembly formed of microcarriers and a thin layer 4 (used as a seed for the material to be epitaxed) forms a compliant layer. Optionally, heat treatment is performed to increase the size of the microcavities in layer 3. [0036] For some applications, ion implantation may also be performed via the two single crystal layers. The first single crystal layer formed on the substrate has a thickness between the surface of the substrate and the layer of microcavities induced by injection. The second single crystal layer may be deposited on or transferred to the substrate. As an example, the selected substrate was transferred onto a silicon substrate using a method as described in French Patent No. 2 681 472, which relates to thinning by the sacrificial layer method (eg,). The structure may consist of a thin layer of GaAs (thickness of 3 nm). The sacrificial layer of silicon oxide is then deposited on the structure so that hydrogen can be injected to a predetermined depth. Hydrogen injection into silicon causes the sacrificial oxide layer and so as to form microcavities within the silicon very close to the depth of the GaAs / Si interface, eg, a few nm, or even a few tens of nm. This is done across the GaAs layer. One modification of the embodiment includes forming microcavities near the interface between GaAs and silicon. [0037] As mentioned above, the binding force depends on many parameters (type of species on the surface, heating schedule performed, initial surface roughness). However, these forces may be controlled so that the binding energy can be controlled. These bonding forces are stresses caused by the presence of a thin epitaxial layer of material and induced by differences in lattice parameters and coefficients of thermal expansion, taking into account the stresses induced by bonding through molecular adhesion. It may be explained in relation to stress. As an example, a very thin film thickness (5 nm) is used to form a thin film of a semiconductor material as described in Japanese Patent No. 2 681 472 for the hydrophilic bond of a single crystal silicon wafer. It is possible to obtain a very thin layer of silicon (10 nm or less) on the oxide layer (below). Compared to the method disclosed in French Patent No. 2 681 472, the originality in this case is the final control of the binding force, ie, annealing at low temperature (usually 6 × 10).<sup>16</sup>H<sup>+</sup>/cm<sup>2</sup>(30 minutes at 450 ° C) with a hydrogen injection dose on the order of) and after fracture by mechanical polishing. An example of the obtained binding force is shown graphically in FIG. For example, SiO with a surface roughness of 6.25 Arms (AFM measurement of a 1 × 1 μm analytical surface) for two contact surfaces.<sub>2</sub>-SiO<sub>2</sub>250mJ / m for binding<sup>2</sup>Bond energy on the order of is obtained after processing at 800 ° C. [0038] FIGS. 2 (a) to 2 (c) show examples of embodiments. FIG. 2A shows a side view of the substrate 10 made of single crystal silicon, one surface of which is coated with the silicon oxide layer 11. Hydrogen ions are injected through the oxide layer 11 to induce a fracture layer. A microcavity layer 12 is obtained and a very thin region 13 of silicon is defined between it and the oxide layer 11. FIG. 2B also shows a side view of another silicon substrate 14 coated with a very thin layer 1 of silicon oxide. The substrates 10 and 14 are integrally formed by the molecular adhesion of the oxide layers 11 and 15. Next, through appropriate heat treatment, the microcavities of layer 12 were formed by obtaining cracks and coalescing the substrate 10 so as to separate it into two parts. The free surface of region 13 is polished to form a thin layer for heteroepitaxy (see Figure 2 (c)). Oxide layers 11 and 15 are bonded by the bonding interface 16. [0039] The thin film structure that acts as a seed / bonding zone for the bonding interface / substrate is described in French Patent No. 2 681. It may be obtained by a method other than the method disclosed in the Publication No. 472. As a suggestion, a method based on bonding by molecular adhesion and thinning by scraping and polishing may be mentioned. It is also possible to use a thin layer transferred by lift-off epitaxy. In particular, the literature describes many examples for obtaining thin films of III-V materials such as GaAs. It is also possible to use a carrier handle to transfer the thin layer used as a seed from the base substrate to the substrate to be compliant. [0040] It is also possible to utilize many of the bond defects (ie, non-bond zones) present at this interface to control the bond strength. [0041] One of the previously proposed solutions is to obtain a binding force between the thin layer used as a seed and the carrier, which is low enough for the thin layer to absorb stress but never separates. [0042] An example of a modification of this method involves taking advantage of these cohesive forces and the presence of intermediate layers; because these intermediate layers can enhance the compliant nature of the structure. More precisely, in this case, it is necessary to consider not only the bonding force between the seed film and the surface, but also the adhesive force between different layers and different thin layers to explain the stress. .. [0043] FIG. 3 is a side view of such a compliant substrate. The compliant substrate 20 includes a carrier 21, an intermediate layer 22 coated with a thin layer 23 intended to act as a seed for heteroepitaxy. The intermediate layer 22 is bonded to the carrier 21 via the bonding interface 24. [0044] As an example, for the intermediate layer 22, a metal is used whose mechanical properties (deformation) absorb most of the stress. For example, French Patent No. 2 681 The method described in Publication No. 472 may be used to obtain a thin layer 23 of the semiconductor used for germination (germination), but the thin layer 23 is integrally formed with the intermediate layer 22. Therefore, a metal compound containing Au (95%) -Sn (5%) or a compound containing Al (5%) -Cu (95%) is used. These metal compounds have viscous properties over a wide temperature range that accommodates the temperatures at which epitaxy normally occurs (900-1000 ° C). Examples may include the use of Pd, Pt, Silicide, metal alloys, metal-board alloys. [0045] The intermediate layer may also cover a portion of the substrate that forms a so-called appropriately carrier. This is shown in FIG. 4, where the compliant substrate 30 includes a carrier portion 31 coated with a first intermediate layer 32, a second intermediate layer 33, and a thin layer 34 used as a seed. The bonding interface 35 is then saturated between the two intermediate layers 32 and 33. These intermediate layers may be of the same type or different types. [0046] The formation of the intermediate layer on the thin layer and optionally on the carrier substrate is carried out prior to the transfer of the intermediate layer / thin layer used as a seed on the carrier substrate. The intermediate layer is an amorphous, polycrystalline, or crystalline type solid. One or more sub-layers may be formed and / or one or more interfaces may be formed in the same or different materials. [0047] The formation of an intermediate layer on a compatible thin layer and optionally on a carrier substrate is carried out by one of the following methods: -Using conventional thin-layer vacuum deposition methods (deposition, cathode spray, CVD, MBE ...), -By electrochemical deposition (electrolysis, electroless plating ...) -Thin layer dislocation method (bonded and thinned by molecular adhesion, bonded and thinned using the method described in French Patent No. 2 681 472, and the intermediate layer (already attached to the thin layer) By binding through a handle that acts as a carrier and removing the handle) -By some thickness conversion from the surface. This conversion may be performed, for example, by oxidation or nitriding. If oxidation is used, it may be obtained thermally, anodic, or by other methods (oxygen plasma, oxygen infusion ...). Oxidation may be carried out via a combination of multiple oxidation methods. -Use a method that allows the formation of a deformable porous layer. [0048] The thickness of the surface film may be extremely important in the manufacture of compliant substrates. In some cases, it is necessary to be able to form a surface layer with a very thin film thickness. Several methods may be used to thin the thin film. Non-limiting methods are listed below: ion polishing, chemical etching, sacrificial layer formation (surface oxidation, nitriding, ...) and removal of this sacrificial layer by various methods. [0049] In one application where the thin layer acting as a seed is silicon, this film can be obtained by the SINOX method or, for example, French Patent No. 2 681. It may be an upper film having a silicon-on-insulator structure formed by a molecular adhesion method called a so-called wafer bond as described in Japanese Publication No. 472. In this case, the film thickness of the silicon before thinning is, for example, on the order of 0.2 μm. A silicon oxide film having a thickness of about 0.4 μm is formed by heat-treating the surface silicon film at 1000 ° C. for 70 minutes in a steam atmosphere. Therefore, the surface silicon film becomes thin to a thin film thickness on the order of 1 nm to several tens of nm. Chemical removal of the surface silica film is performed with 10% hydrofluoric acid. It is advantageous that this thinning step of this silicon film is carried out for very thin films of silicon by heat treatment of the surface at high temperature in a hydrogen atmosphere. For example, treatment for 10 minutes at a temperature in the region of 1150 ° C causes crystal rearrangement of the free silicon surface. At the same time, the thinning of the silicon film of several nm becomes clear. [0050] In the approach to compliance, one of the principles is to allow the relaxation of epitaxy-related stresses through the compliance membrane. Prior to epitaxy, it is advantageous to introduce stresses in the surface layer that act as seeds at room temperature through changes in physical parameters, changes in chemical properties that depend on the type and nature of the deposition method performed. These methods are carried out with the aim of facilitating the subsequent relaxation of sedimentary stress. By pre-stressing the material, it is possible to promote the occurrence of dislocations on the surface films of compliance or at the interfaces of these films. [0051] Epitaxy is generally performed at temperatures of several hundred degrees Celsius. Therefore, the grid compatibility criteria need not be considered at room temperature. For example, it is important to assess the role of heat-derived stresses associated with the difference in thermal expansion between various membranes and mechanical carriers (substrates). [0052] You may use the fact that it is possible to change the crystal parameters of the surface film using bombard injection of atoms in the crystal matrix of the surface film, optionally with the addition of thermal diffusion of atoms. An example of a modification of bombard injection may use a method based solely on the thermal diffusion of atoms, such as the diffusion of a doping agent in silicon. As an example of ion implantation, the injection of boron into crystalline silicon will be described. This leads to a reduction in the crystal lattice of 0.0014 Å / atom for the insertion. When the surface film adheres strongly to the mechanical carrier, the silicon film is placed in a stretched state. Similarly, the effect of germanium injection leads to an increase in the crystal lattice of 0.0022 Å / atom. When the surface film adheres strongly to the mechanical carrier, the silicon film is placed in a compressed state. [0053] In the case of this silicon membrane, which has been compliant by thinning through sacrificial oxidation as described above, it is advantageous to inject before removing the oxide film. As an example, the number 10<sup>15</sup>/cm<sup>2</sup>From several tens<sup>16</sup>/cm<sup>2</sup>By injection of boron through an oxide film with a thickness of around 0.4 μm at an energy in the region of 110 keV, a very thin silicon film because the depth of this film matches the depth of ion implantation. Can be boron-rich. [Simple explanation of drawings] FIG. 1 is a first example of an embodiment of the compliant substrate of the present invention, showing a side view when the crystal zone is a microcavity. FIG. 2 is a second example of the embodiment of the compliant substrate of the present invention, showing a side view when the crystal zone has a bonding interface. FIG. 3 shows a side view of the compliant substrate of the present invention when the crystal zone includes a bonding interface and an intermediate layer. FIG. 4 shows a side view of the compliant substrate of the present invention when the crystal zone has a bonding interface between two intermediate layers. FIG. 5 SiO related to temperature and surface roughness<sub>2</sub>-SiO<sub>2</sub>The graph which shows the change of the binding energy with respect to the bond is shown. [Explanation of symbols] 1,14,21,31 carrier 2 sacrificial layer 3; 11,15,16; 24,25 Joining means 4,13,23,34 Thin layer 5,20,30 Compliant board
9 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9
Every citation, both ways
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US9666432B2 | Cited by | United States of America | Applicant |
| GB2531453A | Cited by | United Kingdom | Search report |
| WO2015002782A1 | Cited by | World Intellectual Property Organization (WIPO) | International search |
| US9768016B2 | Cited by | United States of America | Applicant |
| JPH03142822A | Cites | Japan | Examiner |
| JPH05211128A | Cites | Japan | Examiner |
| JPH07142570A | Cites | Japan | Examiner |
| JP03142822A | Cites | Japan | – |
| JP07142570A | Cites | Japan | – |
| JP05211128A | Cites | Japan | – |
| L. Di Cioccio,Silicon carbide on insulator formation by the Smart-Cut(R) process,Materials Science and Engineering B,1997年 4月,46巻,1-3号,pp. 349-356 | Non-patent | – | – |
| F. E. Ejeckam,Lattice engineered compliant substrate for defect-free heteroepitaxial growth,Applied Physics Letters,1997年 3月31日,70巻,13号,pp. 1685-1687 | Non-patent | – | – |
8 members in 5 offices
Priority claims3
| Document | Office | Kind | Date |
|---|---|---|---|
| 9801061 | France | – | |
| 9801061 | France | A | |
| 9900187 | France | W |
Members8
| Document | Office | Kind | |
|---|---|---|---|
| WO9939377A1 | World Intellectual Property Organization (WIPO) | A1 | |
| FR2774511A1 | France | A1 | |
| EP1051739A1 | European Patent Office (EPO) | A1 | |
| JP2002502121A | Japan | A | |
| FR2774511B1 | France | B1 | |
| US2009311477A1 | United States of America | A1 | |
| JP4994530B2This record | Japan | B2 | |
| EP1051739B1 | European Patent Office (EPO) | B1 |
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Numbers
- Publication
- 4994530
- Application
- 2000529746
Titles2
- Japanese
- 特にヘテロエピタキシャル堆積用のコンプライアント基板
- English
- Compliant substrate especially for heteroepitaxial deposition
Classification
- CPC, 5
- H10P90/1916
- Y10T428/24355
- Y10T428/31678
- H10P90/1914
- H10W10/181
- IPC, 5
- H01L21 20
- H01L21 265
- H01L27 12
- H01L21 02
- H01L21 762
