Wireless communications system with secondary synchronization code based on values in primary synchronization code

[0001] Background of the Invention This embodiment relates to a wireless communication system, and more particularly to communication of primary and secondary synchronization codes in such a system. [0002] Wireless communications are becoming very common in businesses, individuals, and other applications, and as a result, this communications technology continues to evolve in a variety of areas. One such evolution includes the use of spread spectrum communications, such as code division multiple access (CDMA) and wideband code division multiple access (WCDMA) cellular communications. In such communication, the user station (eg, a handheld cellular telephone) communicates with the base station. This base station usually corresponds to a "cell". In order to carry out communication from the user station to the base station, the user station must synchronize with the base station. In this case, in the process of executing this synchronization process, the user station needs to detect both the primary synchronization code (PSC) and the secondary synchronization code (SSC) transmitted from the base station. The PSC is transmitted with the same coded information for multiple base stations, whereas each base station transmits a unique SSC. Normally, the synchronization process is performed when the user station is turned on and, in the case of a mobile station, the user station moves from one cell to another. In the latter case, this movement and the accompanying signal switching is referred to in the art as soft handoff. When the PSC is detected, the user station is notified of the communication cycle timing. When the SSC is detected, the user station is notified of the data (that is, frame) position in the base station communication. Further, when the user station detects a unique base station SSC, the user station can identify a so-called long code group unique to the base station and sent from the base station. The user station can then use the long code to demodulate the data received from the base station. [0003] Although several methods have been proposed and implemented in the past regarding the synchronization methods described above, the inventor of the present invention has shown that these methods can be improved. For example, as will be described later, when the user station attempts to determine the SSC of the base station, the user station usually executes a correlation evaluation technique to decode the transmission from the base station. An example of this technique is the Walsh-Hadamard transform. In practice, this technique allows the user station to compare the various SSCs with the actual SSCs contained in the base station's transmission. If you look at the correlation between the two and it is very high, you can be confident that the user station has detected the SSC of the base station. There is a high possibility that the user station can correctly detect the SSC even with the conventional method, but in the embodiment of the present invention, the probability can be improved as compared with the conventional technique. In particular, in the context of the embodiments of the present invention, the conventional method confirms that the user station may detect the wrong SSC. In other words, even if there is a high cross-correlation between the detected SSC and another SSC that does not actually correspond to the SSC of the correct base station, if the cross-correlation is high during the analysis of the user station, the user station will be the base station. The point is to conclude that SSC was detected. In this case, if the user station concludes that the correct SSC was detected even if the wrong SSC was actually detected, the user station attempts to communicate with the base station using the incorrect SSC, and the user station tries to communicate with the base station. As a result, communication will not be performed correctly. Therefore, when comparing the transmission contents of a base station containing a unique base station SSC with various SSCs at the user station, the degree of correlation detected by the user station is relatively high when the correct SSC is targeted. On the other hand, when targeting other SSCs, it is necessary to make the correlation degree detected by the user station relatively small. The preferred embodiments described below meet this requirement. [0004] [A brief summary of the present invention] In a preferred embodiment, a wireless communication system is provided. The system includes a transmitter circuit, which comprises an encoder circuit that transmits a plurality of frames. Each of the plurality of frames contains a primary synchronization code and a secondary synchronization code. The encoder circuit includes a circuit that outputs a primary synchronization code in response to the first sequence. Further, the encoder circuit includes a circuit that outputs a secondary synchronization code in response to the second sequence and the third sequence. The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal to all other sequences of the plurality of sequences. The third sequence contains a subset of the bits from the first sequence. Other circuits, systems, and methods are also disclosed and described as claims. [0005] [Detailed Description of the Invention] FIG. 1 shows a diagram of a cellular communication system 10 with an example of current code division multiple access (CDMA) or wideband CDMA (WCDMA) in which preferred embodiments work. System 10 shows two base stations, BST1 and BST2. Each base station BST1 and BST2 includes antennas AT1 and AT2, respectively, and each base station transmits and receives a CDMA signal via the antenna. The general area covered by each base station defines the corresponding cell. Therefore, the base station BST1 normally communicates with the cellular device in the cell 1, whereas the base station BST2 normally communicates with the cellular device in the cell 2. Of course, there is also an overlap between the communication ranges of cells 1 and 2 by design so that continuous communication can be supported when the communication station moves from one cell to another. In fact, in this regard, System 10 also includes the user station UST. This user station is shown in association with vehicle V to indicate that the user station UST is a mobile. Further, in this example, the user station UST includes an antenna ATU to enable transmission and reception of cellular communication. [0006] In some respects, the system 10 can operate according to well-known and common techniques for spread spectrum communications such as various cellular or CDMA communications. Such general techniques are well known in the present art. For example, the call is initiated from the user station UST and the call is processed by one or both of the base stations BST1 and BST2. Other techniques are also recognized by those skilled in the art. [0007] One aspect of System 10's operation involves a technique called soft handoff. This technique has been further improved by preferred embodiments and is also reflected in the prior art in some respects. Briefly, soft handoffs usually occur when the user station UST is near the common boundary between cells 1 and 2. For example, it is assumed that the user station UST has moved from the first position near the base station BST1 to the second position near the base station BST2. In this case, the soft handoff is a process in which the user station UST tries to maintain communication with the user station when it moves from the base station BST1 to the base station BST2. This process involves operations at base stations BS1 and BS2 and user station UST, some of which are achieved by prior art. However, these operations are further improved by performing the preferred embodiments. For the sake of simplicity, the prior art and improvements to the prior art will be described separately below. [0008] In the prior art, in order to realize soft handoff, base stations BST1 and BST2 detect a change in the relative physical position of the user UST by processing signal communication from the user station UST. In addition, the user station UST identifies that the signal from the base station BST2 has become sufficiently strong, and notifies the base station BST1 that currently supports communication with the user station UST to that effect. In this way, base station BST2 is a candidate for soft handoff. The system controller can determine the start of the soft handoff process based on the resources available at base station BST2 and other system states. Initially, at this time, both base stations BST1 and BST2 transmit a signal to the user station UST with the same information. The user station UST also correctly identifies and demodulates these signals so that the user of the user station UST can understand only a single information data stream. However, if the user station UST continues to move, the controller will allow proper control. The control is that one base station (eg BST1) eventually ceases to communicate with the user station UST (ie disconnects) and the other base station (eg BST2) continues to communicate with the user station UST. It is something to do. This process is preferably performed in a way that the user station UST does not need to be aware of. Therefore, in this way, one base station "hands off" communication to the other base station. [0009] The scope of the present invention is intended for synchronization at any time during the startup of the user station UST or during the operations described above for soft handoff. In both cases, the scope of the invention relates to the transmission of primary synchronization codes (PSC) and secondary synchronization codes (SSC) by base stations BST1 and BST2 and the identification of these codes by user station UST. .. As already explained in the Invention Background section of this document, each base station BST1 and BST2 (and others) has its own SSC. Therefore, when the user station UST moves from the cell 1 corresponding to the base station BST1 to the cell 2 corresponding to the base station BST2, the user station UST attempts to receive communication from the base station BST2. At this time, the user station UST needs to identify the SSC of the base station BST2. In addition, the user station UST appears to have previously identified the SSC of base station BST1. It is because the user station UST was turned on while vehicle V was in cell 1 or the user station UST had previously moved from another cell to cell 1 (that is, a soft handoff occurred earlier). This is because this identification operation was necessary before, assuming any of (was). In any case, as a requirement for complete signal communication, the user station UST must first identify the SSC of the base station (eg, base station BST2). This is because the user station UST cannot correctly decode the data transmission from the base station unless the event occurs. Assuming the above, the preferred embodiment aims to improve SSC communication from the base station to the user station. This is achieved by the base station transmitting the SSC and the user station identifying the SSC. [0010] Further, as a preliminary knowledge, FIG. 2 shows a CDMA communication frame FR in which a preferred embodiment code can be incorporated. The general timing associated with frame FR and its subdivision described below are well known in the art. The frame FR has a length of 10 milliseconds and is subdivided into equal-length slots. Previously, the number of these isometric slots was proposed to be 16 in relation to the 3G standard, but recently this standard consists of 15 isometric slots for each frame for the purpose of harmonization. It has been modified so that. Therefore, in order to maintain the consistency of the explanation, the following explanation describes an example in which 15 slots are included in one frame. However, one of ordinary skill in the art can easily appreciate that the preferred embodiment can be modified to accommodate 16 (or other) slots in one frame. Further, even if some examples described later describe a 15-slot frame, another embodiment may deal with a 16-slot frame. In each case, before unification, each of the 16 slots is 625 microseconds in length, and after unification, each of the 15 slots is 667 microseconds in length. To help you refer to these contents, in Figure 2, 15 slots are SL₁From SL₁₅Shown in, slot SL as an example for the detailed description below₁And SL₁₅Is enlarged and shown. [0011] Each slot (slot SL₁And SL₁₅(Including) corresponds to communication of 10 CDMA symbols. Further, in CDMA communication, modulation is performed using a spreading code composed of a series of binary pulses, and one CDMA signal transmitted by this code is called a "chip". The current 1CDMA transfer rate is 3.84M chips / sec, so a 10ms frame FR includes 38,400 chips (ie 3.84M chips / sec * 10ms = 38,400). As a result, each of the 15 slots accommodates a total of 2,560 chips (ie 38,400 chips / 15 slots = 2,560), and each of the 10 CDMA symbols contained in one slot is modulated by 256 chips (ie 2,560). Chip / slot ÷ 1 slot / 10 symbol = 256). [0012] Now, returning to the aspect of synchronization between base stations and user stations, and considering that each base station BST1 and BST2 transmits a unique SSC, it is necessary to pay attention to the following points. That is, the user station UST detects the SSC in fact in the second stage of signal acquisition. That is, prior to this stage, in the prior art, the first stage of signal acquisition by PSC (also transmitted by each base station) is performed. In the first stage of signal acquisition, the PSC is the same for all base stations. Slot SL in Figure 2 to Understand PSC₁And SL₁₅As an example, each of these slots is drawn so that the PSC is transmitted as one symbol / slot. That is, the PSC is modulated as 256 chips. In addition, the frame FR contains 15 slots, so the PSC is sent 15 times per frame. Further, each transmission position of the PSC has the same relative symbol position as all the other slots, and in the example of FIG. 2, each PSC exists at the location of the symbol 1 of each slot. Assuming that the PSC exists, the user station UST tries to detect its existence by using a match filter or the like at the first acquisition stage. When the PSC is detected, the user station UST can detect the cycle timing of the frame FR. This same timing detection process can be performed in subsequent frames by detecting the PSC. [0013] Figure 2 also shows that frame FR contains SSC. The transmission of each SSC and its detection by the user station UST is referred to in this technique as the second stage of acquisition in the synchronization process and has been improved using preferred embodiments. In a preferred embodiment, a portion of the SSC is transmitted at the same symbolic position as each PSC. This is the slot SL in Figure 2.₁And SL₁₅It is illustrated as an example at the location of symbol 1 (not shown, but also at the location of symbol 1 in the remaining slots of the frame FR). Therefore, the 15 parts that make up the SSC are the SL of the frame FR.₁From SL₁₅Included in, these 15 parts are collected to form the complete SSC of the base station transmitting the frame FR. Furthermore, the entire collection of 15 individual parts of the SSC of the frame is sometimes called a comma-free code of the base station in this technology, and each of these 15 individual parts is called a comma-free code word. Finally, as explained above, the SSC is unique to each base station, while the PSC is the same for multiple base stations. [0014] For more detailed background information on PSCs and SSCs, FIG. 3 shows a synchronization code generator block 20. This effectively corresponds to the circuit introduced in U.S. Pat. No. 09 / 316,193 (March 21, 1999) "Simplified 1st and 2nd Synchronous Codes with Improved Correlation Characteristics for WCDMA". It is incorporated by reference in this application. We recommend that you consider the patent application you are using in detail. However, note in the application is that when transmitting the SSC and PSC, these signals are orthogonal to each other, thereby improving the functionality of the user station and allowing these simultaneous transmission codes to be detected. is there. A detailed description of the incorporated patent application will also be described along with a detailed description of the preferred examples described below. [0015] A closer look at Figure 3 reveals that block 20 has a first output 20 for outputting PSCs.₁And a second output to output SSC 20₂There is. Each of these signals will be described in detail below separately. [0016] Output 20₁The PSC output from is created by the first pattern block 22. The pattern block 22 represents a bit sequence output method. These bits can be created by various circuits and can be stored as coefficients. The value of the first pattern block 22 represents a general-purpose hierarchical Golay sequence, which is well known in the art and is described in detail in Incorporated Patent Application No. 09 / 316,193. Further, the sequence from the first pattern block 22 is a 256-bit sequence, and therefore these 256 bits are periodically output as a PSC. Finally, in the referenced patent application, this Golay sequence is linked to an exclusive OR circuit, which receives an additional 256 sequences of zeros. However, the result of this exclusive OR operation is simply to output the input Golay sequence, so for simplicity, this additional structure is not shown in Figure 3. [0017] Output 20₂The SSC output by is the output of the exclusive OR circuit 24. First input 24 of the exclusive OR circuit 24₁Receives a value from the second pattern block 26 and receives the second input 24 of the exclusive OR circuit 24.₂Receives a value from the first pattern block 22 (that is, a Golay sequence). The second pattern block 26 creates a pattern consisting of 256 bits, which also represent the Golay sequence. In this way, the exclusive OR circuit 24 receives two Golay sequences, and each signal is orthogonal to each other. Further, in this regard, FIGS. 4a and 4b are input 24 from the second pattern block 26 described above.₁Shows the orthogonal sequence sent to. The pattern in Figure 4a contains two types of 8-bit Golay sequences, A and B, which can be created by various circuits or stored as coefficients. These are as follows.<img file="JP4970643B2_D0001.tif" />17 sequences X shown in Figure 4a₁From X₁₇Each of is created by a combination of A and B and its complement (indicated as -A and -B, respectively). Therefore, each of the 17 rows in Figure 4a contains a different 128-bit sequence that is orthogonal to the other sequences. In addition, to create each 256-bit sequence, the first 128-bit sequence from Figure 4a is concatenated with its complement as shown in Figure 4b, for a total of 17 sequences S (0) to S (16). Sequence is created. Sequences S (0) to S (16) are the inputs 24 of the exclusive OR circuit 24.₁Is connected with. This circuit manipulates these sequences and the corresponding Golay sequence bits received from the first pattern block 22 and outputs the result as an SSC 20₂Output from. [0018] The generation of PSCs and SSCs was described, and the previous methods using the synchronous code generator block 20 are shown in FIGS. 3 to 4b. Each of these aspects aims to achieve the goal of increasing the likelihood of correctly identifying PSCs and SSCs in the user station UST. Although the methods of FIGS. 3 to 4b satisfy the goal, it has been found that the examples of the present invention can further improve this point. Therefore, the following description mainly describes another method included in the scope of the present invention when generating PSCs and SSCs for use in a system such as system 10 and incorporating them into a frame such as frame FR. In that method, the correct detection of PSC and SSC and the operations performed as a result of the detection are improved over the previous method. [0019] FIG. 5 illustrates a synchronization code generator block 30 according to a preferred embodiment. The first output 30 for outputting PSC to block 30₁And a second output 30 to output the SSC₂There is. These synchronization codes and the circuits for creating them will be described in detail below. [0020] Output 30₁The PSC output by is created by the first pattern block 32. The pattern block 32 represents a method of creating a hierarchical bit sequence having autocorrelation characteristics suitable for processing. For ease of reference, such bits are commonly represented in FIG. 5 by the values A and B (and their complements). These bits can be created by various circuits or stored as coefficients in a memory or the like. In a preferred embodiment, the value of the first pattern block 32 represents a sequence commonly referred to in the present art as a general purpose hierarchical Golay sequence. This particular sequence is repeated in the text as follows:<img file="JP4970643B2_D0002.tif" />There are many ways to look at these bits. First, A and B each represent an 8-bit value. Second, since block 22 has a total of 32 8-bit values, a 256-bit PSC is created, which is repeated when 256 bits are transmitted. Third, the PSC from block 22 is represented by a combination of two different 8-bit values, A and B and their complements -A and -B. The values of A and B are as follows.<img file="JP4970643B2_D0003.tif" />Finally, note that the values shown in A and B are shown as real numbers, but the values are converted to binary bits. This is done by converting the real value -1 to the binary value 1 and the real value 1 to the binary value 0. [0021] [0021] Output 30₂The SSC created by is the output of the exclusive OR circuit 34. Here, the first input 34 of the exclusive OR circuit 34₁Receives a value from the second pattern block 36 and receives the second input 34 of the exclusive OR circuit 34.₂Receives a value from the third pattern block 38. The values from the pattern blocks 36 and 38 can be created by various circuits or stored as coefficients in a memory or the like. Further, each bit sequence created by the second pattern block 36 and the third pattern block 38 will be described separately below. [0022] The second pattern block 36 is a 256-bit code selected from various sets of 256-bit codes. Here, it is desirable that each 256-bit code in the set is orthogonal to all other 256-bit codes in the set. In a preferred embodiment, the code set is taken from a code called Hadamard code in the present technology, which is a type of Walsh code. The Hadamard code in the second pattern block 36 is a combination of basic Walsh code sequences, starting at length 2 and extending in length to develop into a variety of alternative codes. In this case, the orthogonality between each set of codes is maintained. For example, Table 1 below shows two basic Walsh codes, each with 2 bits (that is, length 2).<img file="JP4970643B2_D0004.tif" />The code identifiers in Table 1 have the subscript "2" to indicate that the code length is 2 bits. The rest of the identifier is unique for each code. The two codes in Table 1 are orthogonal to each other. This can be seen by multiplying the bits at the first position of each code to form the first product and finding the sum with the product of the bits at the second position of each code. Orthogonality is confirmed as long as the sum is zero. Therefore, for Table 1, this sum is zero (that is, [(1 * 1) + (1 * -1)] = 0) and code C1.₂Is the code C2₂Orthogonal to. [0023] Based on the bit values in Table 1, each code can be extended to 4 codes with 4 bits (ie, length 4) as shown in Table 2 below.<img file="JP4970643B2_D0005.tif" />The shades used to enclose the quadrants in Table 2 help to understand the evolution of the sequences in Table 1. Specifically, the basic code in Table 1 is repeated in Table 2 according to the values and the bit order in Table 1. More specifically, in the code in Table 1, three of all bit values are 1, and the fourth bit value is -1. Based on these values to derive Table 2, the entire pattern of the four bits in Table 1 is copied and written to the quartered portion of Table 2. This 4-split part corresponds to the bit position in Table 1. Therefore, in Table 1, the upper row has two values of 1, and in Table 2, the reference value of Table 1 is copied to these two quadrants in the upper two quadrants. Similarly, in Table 1, the left side of the lower row has a value of 1, so in Table 2, the reference value from Table 1 is copied to the lower left quadrant. Conversely, in Table 1, the value is -1 at the position to the right of the lower row, so in Table 2, the complement of the reference value in Table 1 is copied to the 4 divisions in the lower right. To. Finally, in Table 2, one of ordinary skill in the art can easily confirm that each 4-bit code in Table 2 is orthogonal to the other codes in the table. This can also be confirmed by finding the sum of all products at the same position in the code. The result of the sum is zero. [0024] Given Tables 1 and 2, 256 code sets can be expanded by repeating the same pattern for increasing code length, just as the 2 bits in Table 1 were extended to the 4 bits in Table 2. .. In this case, each of these codes would be 256 in length (that is, select 256 bits from a set of 1s and -1s). The resulting 256-bit code is the Hadamard code used by the second pattern block 36. Specifically, once these 256 Haadmard codes have been established, the code used in the second pattern block 36 can be determined by selecting a subset of these codes. To explain the example in Figure 5, select every 8th chord from this set, select a total of 17 chords, and select these 17 chords as C1.₂₅₆From C17₂₅₆Called. Further, when the code is selected every eight in the embodiment of FIG. 5, the first pattern that the code can select is all 256 values equal to -1, which corresponds to the index value N = 0. Also, C1₂₅₆Is actually selected to correspond to index N = 2. Then select every 8th code, that is, the additional selections correspond to N = 10, N = 18, etc., and the 17th code C17.₂₅₆Corresponds to N = 130. Finally, after deriving the 17 codes above, for every base station with code generator block 30, create a unique group of 16 codes (or 15 codes after unification) before unification. Select a unique group from these 17 codes that you have assigned, and arrange them in a specific order. In addition, within this group, one or more 16 chords can be a chord that repeats any of a total of 17 chords. For example, these 16 code groups are shown in Table 3 below.<img file="JP4970643B2_D0006.tif" />Thus, for the example in Table 3, the second pattern block 36 outputs a sequence of 16 chords, each of which consists of 256 bits. [0025] Next, the third pattern block 38 will be described. This block is generally Z₁Outputs the bit sequence specified as, which consists of the value A used in block 32. In block 38, the value A is repeated so as to match the number of bits output by the second pattern block 36. Therefore, since the second pattern block 36 outputs in 256-bit units as described above, the third pattern block 38 also outputs 256 bits. The latter bit is the value A repeated 32 times in sequence (that is, 32 times * 8 bits of value A = 256 bits). That is, word Z₁Is expressed as follows.<img file="JP4970643B2_D0007.tif" />[0026] The operation of the synchronization code generator block 30 will be described below. First, PSC generation is relatively easy. The reason is that the Golay value output from the first pattern block 32 becomes PSC, and is preferably output in the order shown in FIG. 5 according to the values of A and B described above. Next, the generation of SSC is performed by the operation of the exclusive OR circuit 34. Specifically, the Hadamard code from the second pattern block 36 is actually the sequence Z from the third block 38.₁Is masked by. Sequence Z from the third pattern block 38₁Given that is based on the value A, it can be said that this mask value consists of a multi-bit (eg, 8-bit) subset of the Golay sequence used for the PSC. The result of this exclusive OR operation is SSC. That is, the SSC is the Hadamard code from the second pattern block 36 and the sequence Z from the third block 38.₁Created in response to. The resulting SSC has an output of 30₂Is output from. Further, from the above description, it can be seen that the exclusive OR operation outputs a total of 16 quantities each consisting of 256 bits. Also, in Fig. 2, it was stated that the SSC is divided and transmitted (comma free word). In this case, each divided part occupies the same symbol position in any of the 16 slots (for example, 16 slots before unification or 15 slots after unification). Considering this relationship, it can be seen that each of these parts corresponds to the value after the exclusive OR of any of the 16 codes from the second pattern block 36 to the repetition value of A. Furthermore, it can be seen that by using the mask value A in this way, the aperiodic autocorrelation degree of the SSC created by the synchronization code generator block 30 with the PSC becomes low. Therefore, the user station UST can correctly distinguish between PSC and SSC, and the operation of the entire system is improved. Finally, this preferred embodiment includes the exclusive OR operation for generating the SSC described above, but in the alternative embodiment, the actual operation may not be performed. This is because the bits obtained as a result of the operation can be stored in a memory or a lookup table, and these bits can be output as an SSC. Therefore, in this alternative embodiment as well, the resulting bits are responsive to these sequences, given that they were derived from the sequences of blocks 36 and 38. However, the method of deriving it is different. For example, instead of dynamically performing an exclusive OR operation to generate these bits, they are hard-coded after determining these bits. [0027] It was shown that the operability of the synchronous code generator block 30 was improved as compared with the previous method, but within the scope of the present invention, it was confirmed that the synchronous code generator block 30 was further improved by the alternative embodiment. ing. Before explaining this alternative embodiment, its improvements can be understood by further analyzing the behavior of the synchronous code generator block 30 when executing the alternative embodiment. In this regard, it can be seen that there is room for improving the aperiodic cross-correlation between the various SSCs created by the synchronous code generator block 30 in relation to the scope of the present invention. This point will be described below. [0028] The table shown in Figure 6 shows the maximum aperiodic sidelobe (MAS), which is the above C1 created using the synchronization code generator block 30.₂₅₆From C17₂₅₆This is the result obtained by measuring the degree of correlation between each of the 17 codes shown in. For simplicity, in Figure 6, only 17 codes are shown in the top row of the table and the numbers 1 to 17 in the left column. The MAS in Figure 6 is determined between each code and its own code and between each code and other codes with respect to 0Hz frequency errors over all 256 chip time shifts of each code. For example, code 1 has a MAS of 8 for code 2 and code 1 has a MAS of 128 for code 17. Given the values in FIG. 6, those skilled in the art will appreciate that cross-correlation between codes, especially between specific codes, may be unfavorable. In particular, it can be seen that the maximum peak of the SSC correlation for itself is 256 without reference to FIG. However, Figure 6 shows that the cross-correlation between one SSC and another is close to this same 256 peak value. For example, the MAS for codes 2 to 3 is 248, and in another example, the MAS for codes 4 to 6 is 240. Therefore, these and other relatively high cross-correlation levels make it difficult for the user station UST to correctly detect the actual SSC transmitted by the base station. [0029] Figure 7 above is C1₂₅₆From C17₂₅₆It shows the improvement function of SSC creation by the synchronous code generator block 30 by expressing the correlation between 32 comma-free codes created from 17 individual codes shown as. In particular, Figure 7 shows these comma-free codes for 32 comma-free codes (each code is code C1).₂₅₆From C17₂₅₆It represents the correlation between each of the 16 codes taken from the set of) and all the other of these comma-free codes. In addition, Figure 7 shows non-coherent with 8 chip offsets over a frame. averaging) shows the correlation performed. Even if such an averaging operation is executed, the following two points can be found. First, the aperiodic autocorrelation of comma-free codes is relatively high (eg, up to about 180) even after averaging one frame. In practice, this may not be a problem, such as with multipath. However, it is desirable to reduce the aperiodic autocorrelation of the comma-free code, as implemented by the alternative examples below. Second, the comma-free code aperiodic cross-correlation is also relatively high (eg, up to 130), even after performing a one-frame averaging process. The maximum normalized correlation is 256, and in the worst case, the aperiodic cross-correlation is only 6.0 dB below the main peak. This is because if there is a second base station (eg BST2) and its sync channel is received 8 chips away from base station BST1, depending on the relative power, the second base station will communicate with base station BST1. This means that it may adversely affect the second acquisition stage of the user station UST in an attempt to acquire. Finally, while shifting multiples of 8 chips can be the worst case of this property, it should also be noted that shifts other than multiples of 8 chips also result in unwanted cross-correlation characteristics. Therefore, this point can be improved by providing an alternative example in which the aperiodic cross-correlation of the SSC and the comma-free code is reduced, as realized in the examples described below. [0030] FIG. 8 shows a synchronization code generator block 40 as a preferred alternative embodiment. Block 40 has a first output 40 for outputting PSC.₁And a second output 40 to output the SSC₂There is. In general, block 40 executes the same aspects as the synchronization code generator block 30 shown in FIG. 5, so the same reference numbers are diverted from FIG. 5 to FIG. 8 as they are for such aspects. To briefly explain these common aspects, the synchronous code generator block 40 outputs PSC as a Golay sequence from the first pattern block 32, and the synchronous code generator block 40 outputs SSC as an output from the XOR circuit 34. There is. One input to this circuit 34₁Is concatenated and receives the Hadamard sequence from the second pattern block 36, another input 34₂Are connected and masking pattern Z₂To receive. However, the masking pattern Z of block 40₂Is the masking pattern Z used in block 30 in Figure 5.₁Is different. This difference will be described in detail below. [0031] Masking pattern Z₂More specifically, this masking pattern is obtained from the third pattern block 42. In this case as well, the value shown in this block may be created by various circuits or stored as a coefficient in a memory or the like. In addition, Z₂The values of all bits of are based on either the value A or its complement. The latter is shown in Figure 8<img file="JP4970643B2_D0008.tif" />It can also be referred to as -A, either expressed as or for consistency with the other expressions above. In either case, Z₂The sequence of is also 256 bits and is expressed as follows.<img file="JP4970643B2_D0009.tif" />Thus, pattern Z₂Is the above pattern Z₁Similarly, it is based on a subset of the values used in the PSC Golay sequence. Pattern Z₂In the case of, this subset is made up of both values A and -A, whereas pattern Z₁In the case of, it is created only with the value A. In any case, Z from the third pattern block 42₂All bits of are applied to the corresponding 256 Hadamard bits from the second pattern block 36 via the exclusive OR circuit 34. By performing this operation, the bits from the second pattern block 36 are masked in 8-bit units by the value A or its complement. The result of this exclusive OR operation is SSC, output 40₂Is output from. Further, in the preferred embodiment of block 40, the SSC is generated by incorporating the exclusive OR operation, but in the alternative embodiment, the bits obtained as a result of the operation are stored in a memory, a lookup table, or the like, and those bits are stored in the SSC. It is possible to avoid executing the actual operation just by outputting as. Thus, in this alternative embodiment, the resulting bits also respond to the sequences of blocks 36 and 42 in that they are derived from these sequences. However, this derivation operation is performed by a method different from the method of dynamically executing and generating the exclusive OR operation. [0032] Next, the operation of the synchronization code generator block 40 will be described. However, since the attributes equivalent to block 30 have already been explained, detailed explanations of various aspects are omitted. The PSC generation of block 40 is the same as that of block 30, and the Golay value is output directly from the first pattern block 32 according to the values of A and B described above and the sequence shown in both FIGS. 5 and 8. The SSC is generated by the operation of the exclusive OR circuit 34. For block 40, the Hadamard code is the same as the code for block 30, but the patterns that mask these codes are different. That is, Z from the third pattern block 42₂Mask by. But masking pattern Z₂Is masking pattern Z₁Different from, but pattern Z₂Is also a subset of the multiple bits of the Golay sequence of block 32 used for PSC (eg, 8 bits for A and its complement). Again, by using the masking value in this way, the aperiodic autocorrelation for the PSC of the SSC created by the synchronization code generator block 40 is low, and in fact, this low correlation is equivalent to that of block 30. It turned out to be. Therefore, the masking sequence is Z₁From Z₂Even if you change to, the performance of the first acquisition stage is the same in block 40. Further, as explained below, masking pattern Z₁Masking pattern Z instead of₂The use of also improves the aperiodic cross-correlation between the SSC and the comma-free code for block 40. [0033] FIG. 9 is a table showing the MAS for the synchronization code generator block 40, showing a comparison with the MAS table corresponding to the block 30 shown in FIG. Therefore, Figure 9 is also C1 above.₂₅₆From C17₂₅₆It represents the correlation between the 17 individual codes shown as. This correlation is determined for each code and its own code and between each code and other codes for 0Hz frequency errors over all chip time shifts of each code 256. As in Figure 6, the main peak of the correlation for the SSC itself is 256. However, a comparison of FIGS. 9 and 6 shows that the maximum MAS of block 40 is significantly reduced compared to that of synchronous code generator block 30. Specifically, in FIG. 9, the maximum MAS is 128 (eg, between codes 9 and 17), whereas in FIG. 6, the maximum MAS is almost doubled, that is, in FIG. 6, the maximum MAS is 248 (eg, between codes 9 and 17). , Between codes 3 and 2). Therefore, the cross-correlation value between the individual codes output by block 40 is improved from the cross-correlation value of block 30. [0034] FIG. 10 shows the improved behavior of the synchronous code generator block 40 by showing block 40 a drawing corresponding to the drawing shown in FIG. 7 for block 30. Therefore, Figure 10 also plots the correlation between each set of 32 comma-free codes, with each code having a total of 17 individual codes C1.₂₅₆From C17₂₅₆It consists of 16 of them. Again, the illustrated correlation has a non-coherent average (8 chip offset) performed over a frame. Comparing Figure 10 and Figure 7 reveals some points regarding the improved performance of block 40. First, both the aperiodic self and the cross-correlation of the comma-free code have their maximum values reduced to about 66, which is about 11.8 dB lower than the maximum correlation of 256. Next, although it was mentioned above that 8-chip time-shifting is the worst case for FIG. 7, the cross-correlation is improved for all time-shifting, as measured in FIG. 10 in the alternative embodiment of block 40. Has been done. Even in the worst case, the 8-chip shift, the cross-correlation is 11.8 dB lower than the maximum correlation of 256. Therefore, the SSC's aperiodic cross-correlation attributes and comma-free code have been significantly improved for block 40. Finally, from the advantages mentioned above, it is easy to expect that the performance of the second acquisition stage will be significantly improved due to these advantages. [0035] The above description of the present invention includes yet another embodiment based on each system consideration. For example, in the past it has been proposed for the 3G standard to select comma-free chords as a group of 16 chords from a total set of 17 chords. Recently, for the purpose of unification, each comma-free code has been modified to consist of 15 chords selected from a total set of 16 (rather than 17) chords. Applying this modification to the description of the invention, one method is the C1 described above.₂₅₆From C17₂₅₆C17, the last chord selected in the chord selection₂₅₆Is a method of simply discarding. C17₂₅₆Corresponds to index N = 18. Therefore, C17₂₅₆Can be removed as possible code, which leaves only 16 codes, from which you can create each of the 15 comma-free codes. However, for the embodiments of the present invention, such a method means that a 32 length Walsh-Hadamard transform must be used for these 16 codes. Therefore, yet another embodiment will be described below as an alternative method that satisfies the unified change. [0036] FIG. 11 shows a synchronization code generator block 50 as another preferred alternative embodiment for the purpose of unifying changes and solving the problems of the present invention described above. Block 50 has a first output 50 for outputting PSC₁And a second output 50 to output the SSC₂There is. Since block 50 is equivalent to the synchronization code generator block 40 shown in FIG. 8 in various respects, only the differences will be mainly described here, and the common points will be described very briefly. The common points can be understood by those skilled in the art from the above explanation. In terms of common aspects, block 50 outputs PSCs from the first pattern block 32 using the same Golay sequence, and block 50 outputs SSCs as output from the XOR circuit 52. Different reference numbers are used for this XOR circuit. This is the input 52, as described in detail below.₁And 52₂This is because the value input to the circuit via is different from the previous embodiment. However, in general, the XOR circuit 52 is from block 54 to input 52.₁The Hadamard sequence is received via (the extraction method is different from the above method), and the XOR circuit 52 is input from block 56 to 52.₂Masking sequence Z via₃To receive. In response to these inputs, the XOR circuit 52 has an output of 50.₂Output SSC to. Of course, in this case as well, it is not necessary to perform an actual exclusive XOR operation simply by storing the bits obtained as a result of this operation in a memory or a lookup table and outputting those bits as SSC. [0037] Consider more specifically the Hadamard sequence from block 54. First, comparing with the example of FIG. 5, in the example of FIG. 5, the chords are selected every 8th from the 256-bit code set to a total of 17 chords. On the other hand, in block 54, every 16th code is selected from the 256-bit code set, and the index value also starts from N = 0. Therefore, after index N = 0, each 16th code is selected. That is, subsequent selections correspond to N = 16, N = 32, etc., and the 16th code of block 54 corresponds to N = 240. In addition, after selecting 16 codes, for all base stations equipped with code generator block 50, block 54 is unique to 15 codes selected from these 16 codes and arranged in a particular order. A comma-free code consisting of various groups is assigned and used. [0038] Masking pattern Z₃More specifically, this pattern is given by the third pattern block 56. In this case as well, the values shown therein may be created by various circuits or stored as coefficients. In this case Z₃The bit value of is based on the value A and its complement and the value B and its complement. More specifically, the following value is given to the value C shown in block 56.<img file="JP4970643B2_D0010.tif" />Here, the values of A and B are the same as previously described for the synchronization code generator block 30 in FIG. Then Z₃The sequence of is also 256 bits and can be expressed by the value C as follows.<img file="JP4970643B2_D0011.tif" />Therefore, pattern Z₃Is the above pattern Z₁And Z₂Like, it is based on a subset of the values used in the PSC Golay sequence. But pattern Z₃In the case of, this subset consists of the values A, -A, B, and -B. Here, each of these values is part of the overall pattern used in the Golay sequence to output the PSC. In any case, Z from the third pattern block 56₃Bits correspond to the corresponding 256 Hadamard bits from the second pattern block 36 via the exclusive OR circuit 52. Again, this operation masks the bits from the third pattern block 56. This mask is due to C and its complement. The result of this exclusive OR operation is output 50₂It is the SSC indicated by. [0039] FIG. 12 shows in detail the operation of the synchronous code generator block 50 by showing the block 50 a drawing equivalent to that shown in FIG. 10 for the block 40. Figure 12 plots the correlation between each set of 32 comma-free codes, each consisting of 15 of a total of 16 individual codewords (that is, the 17 shown in Figure 10). Rather than retrieving 16 codes from the total set of codewords in. FIG. 12 shows the correlation in which the unconnected average (16 chip offset) was executed over one frame. Comparing FIG. 12 and FIG. 10, it can be seen that FIG. 12 approaches the same level for both aperiodic autocorrelation and cross-correlation of the comma-free code. Furthermore, with respect to FIG. 12, the worst aperiodic cross-correlation in the comma-free code at the 16-chip offset after executing the 1-frame averaging process also corresponds to the worst cross-correlation of the SSC shown in FIG. However, last but not least, the additional advantage shown in Figure 12 can be achieved using only 16 codewords to meet the unified requirements described above, and for the second acquisition stage, the length is 16 Can be detected using the Walsh-Hadamard transform of. [0040] FIG. 13 shows a block diagram of the base station BST1 (or BST2), and any of the various embodiments of the synchronization code generator block can be implemented in this base station. The configuration of the base station BST1 according to the preferred embodiment will be described below with reference to FIG. Those skilled in the art will appreciate that this particular architecture is presented as an example only, and that other base station architectures can also be used in accordance with the scope of the invention. [0041] As shown in FIG. 13, the base station BST1 includes an amplifier 62. This sends out the amplified transmission signal via the base station antenna AT1 (or a plurality of antennas), and amplifies the signal received from the antenna AT1. RF interface function 64 includes suitable transmit and receive formats and filter circuitry. In addition, RF interface function 64 includes an analog-to-digital converter to digitize the amplified received signal. It also includes a digital-to-analog converter to convert the transmitted signal to the analog domain. Therefore, the RF interface function 64 communicates digitally with the baseband interface 65. This interface performs proper signal formatting processing between the RF interface function 64 and the baseband device 60. [0042] The baseband device 60 communicates with the final network. This network is an E1 or T1 class, or packet network, as shown in FIG. 13, and communicates via the physical layer interface 75 and the network interface adapter 76. The physical layer interface 75 and the network interface adapter 76 are conventional subsystems and are selected according to the network type suitable for base station BST1 and the corresponding interface. [0043] The baseband device 60 executes a digital signal processing function when processing wireless communication in the base station BST1. This feature includes, among other things, the ability to create and incorporate PSCs and SSCs from any block of the sync code generator blocks mentioned above. To perform these functions, the baseband device 60 can be thought of as a subsystem that includes one or more high performance digital signal processor (DSP) devices. These devices include TMS320c5x and TMS320c6x class DSPs marketed by Texas Instruments Incorporated, as well as appropriate memory and external features suitable for processing the digital processing requirements of base station BST1. In FIG. 13, the implementation of the baseband device 60 is described according to various functions, not according to the configuration. Those skilled in the art will appreciate that the baseband device 60 can be easily realized by using a conventional integrated circuit or the like that can be understood from the above functional description, and according to the desired capacity for the base station BST1. [0044] On the transmitting side, the baseband device 60 includes an encoding / modulation function 74. It is connected between the physical layer interface 75 and the baseband interface 65, as shown in FIG. The encoding / modulation function 74 receives digital data from the physical layer interface 75 and executes a digital processing function suitable for a specific protocol. For example, the encoding / modulation function 74 can first encode the received digital data into symbols. The spread code is then used to spread these symbols into a chip sequence according to the selected chip rate. This spreading process also includes a process of spreading the symbol to a plurality of subchannels. Cell-specific scramble codes are typically applied to these diffuse symbols. As a result, the receiving radio device can distinguish between the transmission generated by this base station BST1 and the transmission of the adjacent cell. In addition, the encoding / modulation function 74 can incorporate any of the functions of blocks 30, 40, or 50 described above, thereby creating PSCs and SSCs at the appropriate symbolic positions within the frame. insert. Next, the diffusion symbol is modulated. Typically, multiple subchannels are divided into in-phase (I) and orthogonal (Q) groups, so that the final modulated signal contains both components. Next, after performing appropriate filtering and pre-equalization processing for channel distortion, the spectral diffusion signal is applied to the baseband interface 65 and transmitted by the antenna AT1 via the RF interface function 64 and the amplifier 62. [0045] On the receiving side, the baseband device 60 digitizes the received signal within the RF interface function 64 and then receives the input digital signal from the baseband interface 65. When these signals are applied to the chip rate demodulation / despread function 68, this function extracts the transmission symbol from the digitized received data. Assuming that the base station BST1 receives signals from a plurality of radio devices in a cell via a plurality of channels, the channel estimation function 66 estimates random channel fluctuations. The channel estimation function 66 and the chip rate demodulation / reverse diffusion function 68 each output to the symbol user detection combination function. Here, the demodulated data is associated with each channel. The symbol decoding function 72 then decodes the received signal into a bitstream for each channel and conversation, making it convenient for communication via the physical layer interface 75 and the network interface function 76. [0046] From the above description, it can be seen that the above embodiment provides a transmitter for communicating the PSC and SSC for the wireless system and for the first and second acquisition stages. Moreover, although this embodiment has been described in detail, it is possible to replace, modify, or change the above description without departing from the scope of the present invention. In fact, we have introduced several different examples that help extend the scope of the invention. Further, other modifications can be made to the description of the present invention. For example, the base station transmitter of FIG. 13 is just one of many transmitter examples, including the sync code generator block described in this document. The Hadamard sequence is shown as the preferred sequence as a mask for creating the SSC, but as another example, another sequence taken from the set of orthogonal codes can be used. The Golay sequence is shown as the preferred sequence for creating the PSC, but as another example, other hierarchical sequences with excellent autocorrelation characteristics can be used. In addition, the masking sequences presented here represent special changes to the Golay sequences (using a subset of the Golay sequences to mask the Hadamard sequences), but if they do not deviate from the scope of the invention, the other subsets You may select it or change the individual bit value slightly. As yet another example, the masking operation preferably performed by the exclusive OR operation may be performed by another data manipulation between the bit masking set and the set of orthogonal codes (eg, Hadamard sequence). Therefore, from the above description, those skilled in the art need to fully recognize the scope of the present invention as defined in the following claims. [0047] Cross-reference of related applications This application benefits from 35 USC § 119 (e) (1), US Provisional Application No. 60 / 140,006 (TI-29347PS) (submitted June 18, 1999, incorporated herein by reference). Insist. [Simple explanation of drawings] FIG. 1 is a diagram of a cellular communication system according to an example of current code division multiple access (CDMA) in which a preferred embodiment operates. FIG. 2 is a diagram showing a CDMA communication frame FR in which a preferred embodiment can be incorporated. FIG. 3 shows a synchronous code generator block that is substantially equivalent to the circuit of a patent application that has already been submitted. FIG. 4 is a diagram showing a sequence, where a is a 128-bit sequence created by combining bits selected from a set consisting of values A and B and their complements -A and -B, and b is 256. It is a figure which shows the combination of sequence pairs taken out from a to make a bit sequence. FIG. 5 is a diagram showing a synchronization code generator block according to a preferred embodiment. FIG. 6 shows the maximum aperiodic sidelobe (MAS) of the results obtained by measuring the correlation between each of the 17 256-bit codes when created using the synchronous code generator block of FIG. It is a table. FIG. 7 is a diagram showing the correlation between 32 comma-free codes created from the 17 individual codes of FIG. FIG. 8 shows a synchronization code generator block as a preferred alternative embodiment. FIG. 9 is a diagram showing the MAS of the result obtained by measuring the correlation between each of the 17 256-bit codes when created using the synchronization code generator block of FIG. FIG. 10 is a diagram showing the correlation between 32 comma-free codes created from the 17 individual codes of FIG. FIG. 11 is a diagram showing a synchronization code generator block for the purpose of unified change in a preferred alternative embodiment. FIG. 12 is a diagram showing the correlation between 32 comma-free codes created from a group of 16 256-bit codes. FIG. 13 is a block diagram of a base station BST1 on which any embodiment of a synchronous code generator block can be implemented. [Explanation of symbols] 10 Cellular communication system 20 Sync Code Generator Block 20₁ First output 20₂ Second output 22 First pattern block 24 Exclusive OR circuit twenty four₁ First input twenty four₂ Second input 26 Second pattern block 30 Sync Code Generator Block 30₁ First output 30₂ Second output 32 First pattern block 34 Exclusive OR circuit 34₁ First input 34₂ Second input 36 Second pattern block 38 Third pattern block 40 Sync Code Generator Block 40₁ First output 40₂ Second output 42 Third pattern block 50 Sync Code Generator Block 50₁ First output 50₂ Second output 52 Exclusive OR circuit 52 52₁ input 52₂ input 54 Second pattern block 56 Third pattern block 60 Baseband device 62 Amplifier 64 RF interface 65 baseband interface 66 channel estimation 68 Chip rate demodulation / despread 70 symbol user detection combination 72 symbol decoding 74 Encoding / Modulation 75 physical interface 76 Network interface