Conditional access information arrangement

The present invention is a system for processing packets of program component data from packet video signals, particularly packet payloads for subscribers to conditionally access for entitlement information. It is related to a circuit that detects.

This detection circuit is known, for example, from US Pat. No. 5,168,356 and US Pat. No. 5,289,276, and it is advantageous to transmit a compressed video signal in packets with each packet providing an error protection / correction measure. That's what it is. The systems disclosed in the aforementioned patents transmit and process a single television program, albeit with multiple program components, from each transmission channel. These systems utilize an inverse transport processor to extract the video signal components of their respective programs for further processing to condition the video components for playback.

That is, for example, the reception of transmitted television signals is limited to specific subscribers by encrypting the signals, Pittsfield, Wiltshire, UK (Wilts, Cricklade, 17 Pittfield). Known from Swift Television Publications, SATELLITE BOOK, and "A COMPLETE GUIDE TO SATELLITE TV THEORY AND PRACTICE". This limitation is different entitlement data (entitlement) By transmitting data) periodically, it can be changed according to the intention of the broadcasting station. This entitlement data is processed by the smart card inside each receiver and used by cryptographic or decryption devices only within those receivers that are entitled to play the relevant program material. To generate an encryption or decryption key. In the type of packet video system described above, the entitlement data is contained within a particular packet containing data that is easily accessible to the smart card circuit.

<p> Wide-area broadcasting systems such as direct broadcasting satellite systems for North America have a large number of subscribers (reception contractors). This number is so large that it is not possible to suddenly change the entitlement data for a particular recipient. For example, a broadcaster may have to stop television broadcasting in the area where the sports stadium is located if the sports match tickets are not sold out. This information may not be available until just before the match. Of course, broadcasters want to wait until just before making a decision to stop television broadcasting in the local area.</p><p> Therefore, it is an object of the present invention to provide a system in which entitlement data is layered so as to immediately deny the right to receive program material.</p>

<p> The present invention is a system / method for sending and receiving layered entitlement data. An example of a receiver includes a packet transport processor that selects a packet with a payload that includes a conditional access payload header and a payload of the remaining entitlement data. Each payload header contains a group of bytes that are encoded to allow or disallow processing of entitlement data for each receiver. A conditional access filter pre-programmed with a subscriber's specific conditional access code word to match with the subscriber's specific (unique) conditional access code word. Check the grouping of each byte in the conditional access header. The processor is allowed to process the entitlement data only if a match occurs.</p>

<figref num="1">It is a schematic representation of a time division multiplexing packet television signal.</figref><figref num="2">It is a schematic representation of each signal packet.</figref><figref num="3">It is a block diagram which shows the receiver for the selection and processing of the packet of the multiplexed component signal (multiplexed component signals) which carries out this invention.</figref><figref num="4">It is a block diagram of a conditional access filter / start code detector.</figref><figref num="5">It is a flowchart which shows the operation of a conditional access filter.</figref><figref num="6">It is a block diagram of another conditional access filter.</figref><figref num="7">It is a block diagram of a typical memory management circuit that can be implemented for element 17 shown in FIG.</figref><figref num="8">A schematic representation of the memory address configuration for service channel data.</figref><figref num="9">It is a flowchart which shows the operation of memory address control.</figref>

FIG. 1 shows a packet signal stream consisting of a series of boxes representing signal packets containing components of several different televisions or interactive television programs. It is assumed that these program components are made up of compressed data, and the amount of video in each image is variable. The packet has a constant length. Packets of characters with the same subscript represent components of a single program. For example, Vi, Ai, Di represent video, audio and data packets, and packets called V1, A1, D1 represent video, audio and data components for Program 1, V3, A31. , A32, D3 represent the video, audio 1, audio 2, and data components of Program 3. Data packet (data) packets) Di can include, for example, control data for initiating a given operation in the receiver. Alternatively, they can include, for example, executable code that forms an application that is placed within the receiver or executed by a microprocessor associated with the receiver.

The top line of the packet string shows each component of a particular program grouped together. However, packets from the same program do not need to be grouped, as indicated by the full string of packets. There is also no particular order for the sequence of occurrence of each component.

Each packet is arranged to include a prefix and payload as shown in FIG. The prefix in this example contains two 8-bit bytes, including five fields where four (P, BB, CF, CS) are 1-bit fields and one (SCID) is a 12-bit field. The SCID field is the signal component identifier. The field CF contains a flag to indicate whether the packet payload is encrypted, and the field CS is used to decrypt any of the two selectable decryption keys. Contains a flag to indicate whether it should be. The prefixes of every packet are packet aligned, so the location of each field is easily identifiable.

Within each payload is a header that contains the continuity count CC (modulo 16), which is specific to the program component, and the TOGGLE flag bit. The continuous count is simply the serial number of sequential packets of the same program component. The TOGGLE flag bit is a 1-bit signal that changes the logical value level or toggles based on the occurrence of an image layer start code in the MPEG compressed video component.

Figure 3 shows a portion of a digital television signal receiver in block format that includes an element of an inverse transport processor. The signal is detected by the antenna 10, extracts a specific band of the received signal, and is supplied to the tuner detector 11 that supplies a binary baseband compressed signal. The frequency band is selected by the user through the microprocessor 19 by conventional methods. Broadcast digital signals are usually erroneously coded, for example, by a Reed-Solomon forward error correction (FEC) code. Thus, the baseband signal is supplied to the FEC decoder 12. The FEC decoder 12 synchronizes the received video and provides an error-corrected stream of signal packets having the format shown in FIG. The FEC12 delivers packets at regular intervals or, for example, at the request of memory controller 17. In both cases, packet framing or synchronization signals are provided by the FEC circuit. This indicates the number of times each packet information is transferred from FEC12.

The detection frequency band can include a plurality of time division multiplexing programs in the form of packets. To be useful, only packets from a single program should be sent to other circuit elements. In this example, it is assumed that the user does not know which packet to select. This information is included in the program guide. A program guide is itself a program consisting of data related to program signals and components by SCID and can include, for example, information related to subscriber entitlements. This program guide is a list of SCID programs for each program's audio, video, data, and other components. The program guide (packet D4 in Figure 1) is assigned to a fixed SCID. When power is supplied to the receiver, the microprocessor 19 is programmed to load the SCID associated with the program guide into one of the banks of a similar programmable SCID register 13. The SCID field of the prefix part of each detection packet of the signal from FEC12 is continuously loaded into the other SCID register 14. The programmable register and the receive SCID register are coupled to the respective input ports of the comparator 15, and the receive SCID is compared with the program guide SCID. If the SCID for the packet matches the program guide SCID, the comparator 15 conditions the memory controller 17 to route the packet to a given location in memory 18 for use by the microprocessor. wear. If the received SCID does not match the program guide SCID, the corresponding packet is simply dumped.

Although shown as a computer keyboard, the microprocessor listens for programming commands from the user via a conventional remote controller, or interface 20, which may be a receiver front panel switch. The user can request to see the program supplied to Channel 4 (analog television system terminology). The microprocessor 19 scans the program guide loaded into memory 18 for each SCID of the program component on channel 4 and in the programmable registers of register bank 13 associated with the corresponding component signal processing path. It is programmed to load these SCIDs into their respective other registers.

Receive packets of an audio, video, or data program for the desired program are ultimately routed to their respective audio processor 23, video processor 22, or auxiliary data processor 21, (24) signal processor, respectively. Must be selected. Although the data is received at a relatively constant rate, the signal processor nominally requires burst input data (eg, in their respective decompressed formats). A typical system shown in FIG. 3 first routes each packet to a predetermined memory location in common memory 18. After that, each processor 21 to 24 requests a component packet from memory 18. By routing the components through the common memory, the desired signal data rate buffering or throttling countermeasures can be implemented.

Audio packets, video packets and data packets are loaded into their respective predetermined memory locations, enabling a convenient signal processor for buffer access to component data. Each SCID comparator is associated with these memory areas so that the payload of each component packet is loaded into the appropriate memory area. This association may be actually wired in the memory controller 17, or the association may be programmable. In the former case, specific registers in programmable registers 13 are always assigned to audio, video and data SCIDs, respectively. In the latter case, audio, video and data SCIDs can be loaded into any of the programmable registers 13. Then, when each SCID is loaded into a programmable register, the appropriate association is programmed in memory controller 17.

In the steady state, after the program SCID is stored in the programmable SCID register 13, the SCID of the received signal packet is compared to all of the SCIDs in the programmable SCID register. If the match is made with either stored audio, video, or data SCID, the corresponding packet payload is stored in the audio, video or data memory area or memory block, respectively.

Each signal packet is coupled from the FEC 12 to the memory controller 17 via the signal decryptor 16. Only the signal payload is encrypted and the packet header is passed by the unaltered cryptanalyzer. Whether or not a packet should be decrypted is determined by the CF flag of the packet prefix, and how the packet should be decrypted (one of two alternative decryption keys) is determined by the CS flag. Will be done. If there is no SCID match for each packet, the decryptor simply disables the passage of any data.

The decryptor is programmed by the decryption keys provided by the smart card device 31. The smart card generates the appropriate decryption key in response to the entitlement information contained in a particular packet in the program guide. The system in this example incorporates two levels of encryption or program access: the entitlement control message ECM and the entitlement management message EMM. Program entitlement control and management information is regularly transmitted in identifiable packets with a particular SCID contained in the packet stream containing the program guide. The ECM information contained in these packets is used by the smart card and is used by the decryptor. keys) is generated. The EMM information contained in these packets is used in the subscriber's unique smart card to determine the program material in which the subscriber is entitled. The EMM entitlement information in these packets can be geographically specific, group specific, or subscriber specific. For example, the system includes a modem (not shown) to inform a program provider, for example, a satellite broadcaster, of billing information from a smart card. The smart card can be programmed with, for example, the area code of the receiver location and the telephone exchange. The EMM contains data that, when processed by a smart card, is entitled to receive a particular program in a particular area code or denies the reception of this program.

Program providers require the ability to entitle subscribers with very short lead times, for example, as far as pay-per-view programs are concerned. Identification of a particular subscriber may be disabled until just before the broadcast of a particular program. With such short lead times, it may not be possible to program the EMM based on the subscriber. Other coding layers are immediately added to the entitlement information by including a conditional access code, allowing / disallowing the reception of EMM and ECM data in each packet, thereby for some programs. Allows near-instant permission / prohibition.

The packet payload containing the EMM and ECM entitlement data contains a 128-bit payload header arranged in four specially encoded 32-bit groups. Each group is coded with a conditional access code, and each conditional access code can be coded differently. Each subscriber is assigned a specific conditional access code. Matched filter filter), i.e., the E-code decoder 30, is configured to detect subscriber-specific bit patterns in 128-bit headers. If a match is detected, the decoder communicates with the memory controller 17 and the smart card 31 so that the rest of the entitlement payload is used by the smart card (via memory 18). If no match is detected, the payload is not accepted by the particular receiver. If the collation filter 30 is programmable, the conditional access code can be changed cyclically. These codes can be supplied periodically by smart cards. For more specific details on smart card behavior related to viewer entitlement, see the SATELLITE BOOK, A COMPLETE GUIDE TO SATELLITE TV THEORY AND PRACTICE. Is stated in Section 25.

The collation filter, or E-code decoder, is configured to perform a second function of detecting a particular MPEG video header. These headers are 32-bit start codes (that's why the headers in the entitlement payload are encoded in 32-bit groups). If the video data is lost, the MPEG video decoder can only restart the video data decompression at a particular data entry point. These entry points match the MPEG start code. The decoder blocks the flow of video data to memory after the loss of video packets and resumes writing the video payload to memory only after the next MPEG start code is detected by the decoder 30. -It is configured to communicate with the controller 17.

FIG. 4 shows a typical device (decoder 30 in FIG. 3) for detecting a packet containing conditional access information or an MPEG start code. Whether the decoder 30 is conditioned to detect the entitlement payload or MPEG start code depends on the capabilities of the currently received SCID. In Figure 4, the data supplied by the decryptor 16 is assumed to be 8-bit bytes and packet aligned. That is, the first byte of the entitlement payload or the first byte of the MPEG start code is accurately aligned to a specific byte position, such as the beginning of the packet payload. The reason is to detect specific headers or start code words, as their position in the bit / byte stream is known precisely. The data from the decryptor 16 is fed to an 8-bit register 250 having an 8-bit parallel output port coupled to each first input connection of the comparator 254. The comparator 254 can consist of, for example, a bank of eight two-input exclusive Noah (XNOR) circuits with each output connection coupled to an and-gate and latch. This latch may be a data latch configured to latch the and-gate results at each byte interval.

The 32-bit MPEG start code is stored as 4 bytes in the 8-bit register bank 265. The conditional access code is stored as 8-bit bytes in 16 8-bit register banks 257. The loading of register banks 251 and 265 is controlled by microprocessor 19 and / or smart cards. The start code register 265 is coupled to the 4: 1 multiplexer 266 and the conditional access code register is coupled to the 16: 1 multiplexer 257. The output ports of multiplexers 257 and 266 are coupled to a 2: 1 multiplexer 249. Each output connection of the multiplexer 249 is coupled to each corresponding second input terminal of the comparator 254. (Note that the I / O connections for multiplexers 249,257 and 266 are 8-bit buses). If the respective value shown in each output junction of register 250 is the same as the corresponding output value indicated in each output junction of the multiplexer 249, then the true signal is for the corresponding data byte. Generated by the comparator 254 of.

To detect the start code, the multiplexer 266 is scanned by counter 258 and sequentially transfers four different registers 265 to the comparer in synchronization with the generation of the first four payload data bytes from decryptor 16. Join. On the other hand, to detect the conditional access code, the multiplexer 257 is scanned by the counter 258 and sequentially couples a different one of the registers 265 to the comparator 254.

The output of the comparator is supplied to the accumulator / test circuit 255. Circuit 255 determines if any of a given number of byte matching conditions have occurred and, if so, generates a write enable signal for the entitlement data for the rest of the particular payload being inspected. To do. In this system, the entitlement payload header contains 128 bits arranged in four 32-bit conditional codes. Conditional access filters 30 for different subscribers are configured to look for different combinations of 128-bit bytes. For example, a subscriber device can be configured to match the first 4 bytes of a conditional access code. Other subscriber devices can be configured to match the second 4 bytes of the conditional access code, and so on. In any of these typical situations, circuit 255 determines if a match has occurred for the appropriate four consecutive bytes.

The use of 16 registers in the bank for subscriber-specific conditional access codes simplifies the circuit structure somewhat. Each subscriber has a 4-byte conditional access code, which can be loaded four times into 16 register sets. Therefore, at the transmitter, the broadcaster does not have to be involved in the relative location for four groups of four bytes of the conditional access code being transmitted. The alternative device can incorporate only four registers in a single group to hold subscriber-specific conditional access codes, and these registers are modulo 4 with a 128-bit entitlement payload header. It can be scanned repeatedly.

This unfavorably limits the system bandwidth of other services and only takes too much time, so sending each of the 232 possible entitlement codes for every feature is not possible. Not practical. This limitation, where grouping is defined by 3 bytes in each 4-byte conditional access code, can be somewhat resolved by arranging the conditional access code with some logical value grouping. Thus, all subscribers in a group can be addressed by conditioning the receivers in each group to ignore one byte in the 4-byte conditional code. In this example, each 4-byte access code represents 256 subscribers. Filter conditioning is done, for example, by sending all 0s at the first 4 bytes and configuring a conditional access filter to detect this condition. If this condition is met, the conditional access filter is electrically reconfigured to detect a 3-byte match for each 4-byte group.

A third modification is provided to allow conditional access for all subscribers. This is done by encoding the entitlement payload with all 0s (or all 1s). Therefore, the conditional access filter is configured to also include an all-zero detector (elements 261-263).

The bits of each receive byte of the data are coupled to their respective terminals of 8-bit or gate 263. If any of these bits has a logical value of 1, the or gate 263 outputs a logical value of 1. The output of the or-gate 263 is coupled to one of the inputs of the two-input or-gate 262, which has an output and a second input, respectively, coupled to the data and Q output terminals of the D-latch 261. The D-latch is clocked by the timing circuit 259 in synchronization with the reception of the input data bytes. If any bit of the data byte generated after the latch is reset has a Boolean value of 1, the latch 261 will show a Boolean value of 1 at its Q output until the next reset pulse. The Q output of latch 261 is coupled to an inverter that exhibits 0 output level whenever the latch exhibits 1 output level. Thus, if the 128-bit (16-byte) header is then passed through register 250, the inverter output is high and 128-bit is 0. The latch is reset before each new payload is received. After passing through the entitlement payload header, circuit 255 generates a data write enable signal in response to detection of a high output level from the inverter.

FIG. 5 is a flowchart showing the operation of the conditional access filter 30. This process is initiated by the detection of the associated SCID. Once the appropriate SCID is found, the payload is fed to filter 30 {300}. A comparison {302} is made between the first 4 bytes of the header and the subscriber-specific conditional access code. If a match occurs, the entitlement data write enable is raised {310}. If no match occurs, the first 4 bytes are checked against all 0s {306}. If no all 0s are found, the second 4 bytes of the header are compared to the subscriber-specific conditional access code {308}. If they match {312}, a write enable is generated {310}. If they do not match, the third 4-byte set is compared to the subscriber-specific conditional access code {314}. If this matches {316}, a write enable is raised {310}. If they do not match, the fourth 4-byte set is compared to the subscriber-specific conditional access code {317}. If they match {318}, a write enable is raised {310}. If they do not match, the last 12 bytes of the header are checked for all 0s {320}. If all 0s are detected in the last 12 bytes, a write enable is generated {310}, otherwise processing waits for the next packet {300}. In the alternative device, in step {320}, the system can be programmed to look for all 0s in all 16 bytes of the header. It should be understood that some other fixed pattern may utilize all non-zeros, such as all 1s or, for example, patterns in which 0s and 1s alternate.

In step {306}, if the first 4 bytes are all 0s, then 3 of the 2nd 4 bytes of the header are compared to the subscriber-specific conditional access code {354}. In the device of Figure 4, this is achieved by configuring element 255 to look for three matches for a single 4-byte group. If three of the four bytes match {326}, a write enable occurs {322}, if they do not match, three of the third set of four header bytes are subscriber-specific conditions. {330} compared to the attached access code. If three of the four bytes match {332}, a write enable signal is generated {322}, if they do not match, three of the last four bytes are compared to the subscriber-specific conditional access code. Will be {336}. If they match, a write enable signal is generated {322}, otherwise an all-zero condition is checked {320}.

It should be noted that if only two of each group of 4 bytes are matched, the other detection levels can be incorporated as in steps {324 ~ 340}. This can be conditioned, for example, by arranging the first 8 bytes all to 0 or the first 4 bytes all to 1. In this case, each group enabled by the conditional access code will be much larger.

With respect to storing the entitlement payload in memory, the system writes the payload header to memory when it receives and inspects the conditional access code. If a conditional access code is detected, the write enable detected only allows memory control to continue writing the payload. Conversely, if the conditional access code is not found in the first 16 bytes of the payload, the rest of the payload is not written to memory and the memory address for the conditional access payload is 16 in the payload conditional access header. Reset to overwrite bytes.

Figure 6 shows other conditional access filters that compare as many as 32 bits (4 bytes) at a time. This makes it possible to detect the start code without knowing the byte position of the start code in advance. The start code is stored in an 8-bit register (the 8-bit register is used because the 8-bit μPC bus is used). The output port of the register is coupled to the first input set of the multiplexer 298. The subscriber-specific conditional access code is stored in a second register bank 299 with each output port coupled to a second set of inputs for the multiplexer 298. The multiplexer 298 has an output set connected to each first 8-bit input port of the comparators 270 to 273.

Whether register 265 or 299 is coupled to the comparator is controlled by the accumulator / test circuit 297 in response to μPC.

The input bytes from the decryptor 16 are coupled to the parallel / series registers 247-277. Each register 274-277 has a parallel output port coupled to the second 8-bit input port of the comparators 270-273. The system is timed so that four consecutive bytes of the input signal are currently loaded into registers 247-277. The output terminal of the comparator is coupled to the accumulator / test circuit 297 via the respective or gates 278 to 281. The second input terminal of the or circuit is coupled to each control output connection of the accumulator / test circuit 297.

Like the device of FIG. 4, the device of FIG. 6 includes an all-zero detector that detects all zeros in all the first 4 and 16 bytes.

To detect a 4-byte conditional access code, only one consecutive 4-byte group is loaded into registers 247-277 and tested against the subscriber-specific access code contained in register 299. .. If all four comparators detect a match, then Gate 283 raises a logical value of 1, indicating a match. If one of the comparators cannot find a match, then and gate raises a logical value of 0. To detect the 4-choice 3 input byte conditional access code set, the accumulator / test circuit 297 supplies one of the control lines coupled to the or-gate with a logical value of 1. This forces the output of this or gate to a logical value of 1, and of course is a valid match from the associated comparator. Therefore, conditional access code detection is performed in a single contiguous 4-byte group, as in the case of 4-byte detection.

All control lines of the or gate are held at a logical value of 0 to detect the start code. The input bytes are sequentially fed to registers 247-277 of the cascade connection, and testing for a match with the start code stored in register 265 is performed on each contiguous, comprehensive 4-input byte set.

FIG. 7 shows a typical device for the memory controller 17 shown in FIG. Each program component is stored in a different adjacent block of memory 18.

In addition, other data, such as data generated by the microprocessor 19 or a smart card (not shown), can be stored in memory 18.

The address is supplied by the multiplexer 105, and the input data is supplied to the memory 18 by the multiplexer 99. The output data from the memory management circuit is supplied to the signal processor by another multiplexer 104. The output data supplied to the multiplexer 104 can be obtained directly from the microprocessor 19, memory 18, or from the multiplexer 99. The program data is of standard image resolution and image quality and is assumed to occur at a particular data rate. On the other hand, the high-definition television signal HDTV that can be supplied by this receiver is generated at a very high data speed. In fact, all data supplied by the FEC is stored through the multiplexer 99 and the memory I / O circuit 102, except for faster HDTV signals that can be routed directly from the multiplexer 99 to the multiplexer 104. Routed through 18. Data is supplied to the multiplexer 99 from the decryptor 16, the smart card circuit, the microprocessor 19, and the media error code source 100. The term "media error code" as used herein interrupts processing until the detection of a given code word, such as a start code, and then resumes processing, for example with a start code. Means a special code word that is inserted into a data stream to condition a processor (decompressor).

The memory address is supplied from the program addressing circuits 79 to 97, from the microprocessor 19, from the smart card device 31, and from the auxiliary packet address counter 78 to the multiplexer 105. The selection of a particular address at any particular time period is directly controlled by the memory access DMA circuit 98. The SCID control signal from the comparator 15 and the "data needed" signal from each signal processor are fed to the DMA98 and in response the memory access contention is arbitrated. The DMA98 works with the service pointer controller 93 to provide the appropriate read or write address for each program signal component.

Each address for a memory block of various signal components is generated by a group of four program components, namely service pointer registers 83, 87, 88 and 92. A start pointer for each block of memory in which each signal component is stored is contained in register 87 for each signal component. The start pointer may be a fixed value or may be calculated in the microprocessor 19 by conventional memory management methods.

One pointer to the last address of each block is stored in one service register bank 88 for each potential program. Like the start address, the end, or last address, may be a fixed value or it may be calculated with the value provided by microprocessor 19. The use of calculated values for start and end pointers is preferred as it provides a more versatile system with less memory.

The memory write pointer, or head pointer, is generated by the adder 80 and the service head register 83. There is a service head register for each potential program component. The write pointer value, i.e., the head pointer value, is stored in register 83 and is fed to the address multiplexer 105 during the memory write cycle. A head pointer that is incremented by one unit is also coupled to adder 80, and the incremented pointer is stored in the appropriate register 83 during the next write cycle. Register 83 for the appropriate program component currently being serviced is selected by the service pointer controller 93.

In this example, the start and end pointers are assumed to be 16-bit pointers. Register 83 is a 16-bit write pointer, or head pointer. The 16-bit pointer is chosen to facilitate the use of the 16-bit or 8-bit bus to load the start and end pointers into registers 87 and 88. Memory 18, on the other hand, has an 18-bit address. The 18-bit write address is formed by concatenating the most significant 2 bits of the start pointer to a 16-bit head pointer that has a start pointer bit at the most significant bit position of the combined 18-bit write address. To. The start pointer is supplied to the service pointer controller 93 by each register 87. The service pointer controller is higher (more) than the start pointer stored in register 87. significant) Parses the start pointer bits and associates these bits with the 16-bit head pointer bus. This is indicated by the bus 96, which is shown to be coupled to the head pointer bus leaving the multiplexer 85, and by the thick arrow in FIG.

In Figure 8, the top, middle, and bottom rows of the box represent the start pointer, address, and head or tail pointer bits, respectively. The higher numbered boxes represent the more significant bit positions. The arrows indicate from which bit position of the start pointer or head / tail pointer the bits of each address are obtained. In this derivation, the thick arrow represents steady operation.

Similarly, the memory read or tail pointer is generated by adder 79 and service tail register 92. There is a service tail register for each potential program component. The read or tail pointer value is stored in register 92 and supplied to the address multiplexer 105 during the memory read cycle. The tail pointer that is incremented by one unit is also coupled to adder 79, and the incremented pointer is stored in the appropriate register 92 during the next read cycle. Register 92 is selected by the service pointer controller 93 for the appropriate program component currently being serviced.

Register 92 provides a 16-bit tail pointer. The 18-bit read address is formed by concatenating the most significant 2 bits of the start pointer to a 16-bit tail pointer that has a start pointer bit at the most significant bit position of the combined 18-bit write address. To. The service pointer controller parses higher start pointer bits from the start pointer stored in register 87 and associates these bits with the 16-bit head pointer bus. This is indicated by bus 94, which is coupled to the tail pointer bus leaving the multiplexer 90.

The data is stored in memory 18 at the calculated address. After storing 1 byte of data, the head pointer is incremented by 1 and compared to the end pointer for this program component, and if they are equal, a more significant bit of the head pointer is of the start pointer. It is replaced with the lower 14 bits, and 0 is placed at the lower 2 bits of the head pointer part of the address. This is shown in Figure 8 with respect to the hatched arrow between the start pointer and the address. This behavior is indicated by arrow 97 pointing the head pointer bus from the service pointer controller 93 to the multiplexer 85. Suppose you override the head pointer bit by supplying the lower 14 start pointer bits. During this one write cycle, by replacing the head pointer bit with the lower start pointer bit of the address, the memory scrolls through the memory block specified by the upper two start pointer bits, and thus within the block. Eliminates the need to reprogram the write address at the beginning of each packet for its own memory location.

If the head pointer is always equal to the tail pointer (used to indicate where to read data from memory 18), a signal indicating that a head tail crash has occurred is sent to the microprocessor interrupt. Sent. Further writing from this program channel to memory 18 is disabled until the microprocessor makes the channel reusable. This case is very rare and should not occur during normal operation.

Data is retrieved from memory 18 at the request of each signal processor according to the addresses calculated by adder 79 and register 92. After reading 1 byte of stored data, the tail pointer is incremented by 1 unit and compared to the end pointer for this logical channel in the service pointer controller 93. If the tail and end pointers are equal, the higher bits of the tail pointer are replaced with the lower 14-bit start pointer, and 0 is placed in the lower 2 bits of the tail pointer portion of the address. This is indicated by an arrow 95 exiting controller 93 and pointing to the tail pointer bus from the multiplexer 90. Now, if the tail pointer is equal to the head pointer, then each memory block is defined as empty. And no more bytes are sent to the associated signal processor until more data is received from the FEC for this program channel. The actual replacement of the head or tail pointer portion of each write or read address with the lower 14 bits of the start pointer is achieved by using appropriate multiplexing or three-state interconnection.

Memory read / write control is performed by the service pointer controller and direct memory access DMA, elements 93 and 94. The DMA is programmed to schedule read and write cycles. Scheduling depends on whether FEC12 is supplying data to be written to memory. The FEC data write operation takes precedence so that no input signal, component, or data is lost. In the typical device shown in Figure 7, there are four types of devices that can access memory. These are application devices such as smart cards, FECs (more precisely, decryptors 16), microprocessors 19 and audio and video processors. Memory conflict (memory) contention) is processed as follows. In response to data requests from the various processing elements described above, DMA allocates a block of memory for each program component. Access to memory can be achieved in the 95nS time slot during which 1 byte of data is read from or written to memory 18. There are two main access allocation modes, each defined as "FEC is supplying data" or "FEC is not supplying data". Assuming a maximum FEC data rate of 5 Mbytes / sec for each of these modes, i.e. 1 byte for each 200 nS, time slots are allocated and prioritized as follows: These are when FEC supplies the data 1) EEC data writing; 2) Application device read / microprocessor read / write; 3) Write FEC data; 4) Microprocessor read / write; and When FEC does not supply data 1) Smart card read / write; 2) Application device read / read / microprocessor read / write; 3) Smart card read / write; 4) Microprocessor read / write. Is.

Since FEC data writing cannot be deferred, the FEC (ie, more precisely the decryptor) must guarantee memory access for each 200nS period when providing data. Alternating time slots are shared by application devices and microprocessors. The microprocessor realizes the use of application time slots when there is no data available to the requesting device.

The controller 93 communicates with the SCID detector to determine whether to access the respective start pointer register, head pointer register, and end pointer register during the memory write operation. The controller 93 communicates with the DMA to determine which of its start, end, and tail registers to access during the memory read operation. The DMA98 controls the selection of corresponding addresses and data by multiplexers 99, 104 and 105.

FIG. 9 shows a typical flowchart of the DMA98's memory access process. DMA responds to the detection or non-detection of received packets by detecting SCID {200}. If an SCID is detected that indicates the existence of data from the decryptor 16 written to memory, the 1-byte program data from the decryptor is written to buffer memory 18 {201}. The block of memory to be written is determined by processor 93, which responds to the current SCID. It then determines whether any of the program component processors, including smart cards and μPCs, require read / write (R / W) access to the data or memory 18 {202}. If no data request is made in DMA, processing returns to step {200}. If a data R / W request has been made, DMA determines the priority of the request {203}. This is accomplished by or instead of traditional interrupt routines by sequential single-byte services in any order of these program processors requesting data. For example, assume that any access priority is video, audio I, audio II, smart card, and μPC. It is also assumed that only video, audio II and μPC require memory access. During the operation of the current step {203}, a 1-byte video is read from memory. During the next step operation {203}, 1 byte Audio II is read from memory, and during the next subsequent step {203}, 1 byte μPC data is written to or read from memory 18. Etc. Addresses for smart card and μPC access are provided by the smart card and μPC respectively, while addresses for video, audio and program guides are provided by the address pointer device (80-93). It should be noted that.

Once preferred access is established {203}, the required program processor is serviced by a byte of data written to or read from memory 18 {204}. Next, the 1-byte data from the decryptor 16 is written to memory {205}. A check {206} is performed to determine if the μPC is requesting access. If μPC is requesting access, it will be serviced by 1 byte of data {207}. If the μPC is not requesting access, the process jumps to step {202} to determine if any of the program processors request access. In this way, incoming data is always guaranteed access to other memory access periods, and intervening memory access periods are extended among program processors.

If no data is currently available from decryptor 16, i.e. SCID is not currently detected, processing {208 ~ 216} follows. First, the smart card is inspected to determine if it is requesting memory access {208}. If so, 1 byte of memory access is given {209}, otherwise a check is done to determine if any of the program processors are requesting memory access. {210}. If a data R / W request is made, the DMA determines the priority of the request {211}. A suitable processor is serviced by 1 byte of memory read or write access {212}. If the data R / W request is not made by the program processor, the process jumps to step {213} where the test is performed to determine if the smart card is requesting memory access. .. If so, the smart card is serviced by 1-byte memory access {216}, otherwise the process jumps to step {200}.

In this preferred example, in "FEC not supplying data" mode, the smart card is given a 2: 1 access precedence over all other program processors. This priority is programmed into the programmable state machine in the DMA device and modified by the μPC. As mentioned above, the system is intended to provide interactive services, and the μPC19 performs at least in part interactive operations in response to interactive data. In this role, μPC19 uses memory 18 for both application storage and working memory. In these examples, the system operator can change the memory access priority to give the μPC 19 higher frequency memory access. Memory access priority reprogramming can be included as a subset of interactive application instructions.

If a packet is lost, insert a media error code into the video component signal stream and condition the video signal stretcher to suspend decompression until a particular signal entry point occurs in the data stream. It is advantageous to attach it. It is impractical to predict where and in which video packet the next entry point can occur. In order to find the next entry point as fast as possible, it is necessary to include the media error code at the beginning of the first video packet after detecting that the packet has been lost. The circuit of Figure 7 puts a media error code at the beginning of each video packet and then removes the media error code of each packet if there is no loss of the previous packet. The media error code is the first M provided for the current video packet payload by writing to memory 18 during the M write cycle prior to the video payload received from the decryptor. Inserted into memory address location. At the same time, the multiplexer 99 is conditioned by DMA98 to give the media error code from source 100 to the I / O of memory 18. M is simply the integer memory location needed to store the media error code. Assuming the memory stores 8 bits and the media error code is 32 bits, M is equal to 4.

The address for loading the media error code into memory is provided by the respective video component service register 83 via the multiplexer 82 and multiplexer 85. The first M addresses provided by the pointer register 83 for loading the media error code into the memory location loaded with the video component data are simply generated by the normal video head pointer. It is understood that there are the next M sequential addresses. Since these same addresses are coupled to the delay element 84 of the M stage, the first M addresses are obtained as the output of the delay element 84 immediately after the last byte of the media error code is stored in the memory 18. Be done.

The timing for loading the media error code into memory coincides with the decision of the lost packet. Packet error or loss detection is performed by error detector 101, which responds to the CC and HD data of the current packet.

If packet loss is detected, the video component of the current packet is stored in memory 18 starting at the next address location, the (M + 1) th address location. This is achieved by conditioning the multiplexer 85 to keep sending undelayed head pointers from the appropriate register 83. On the other hand, if no packet loss is detected, the first M bytes of the video component in the current packet are stored in the memory location where the media error code was previously stored.

Packet error or loss detection is performed by error detector 101, which responds to the CC and HD data of the current packet. The detector 101 checks the continuous count CC of the current packet to determine if the continuity count CC of the current packet differs from the CC of the previous packet by one unit. In addition, the TOGGLE bit of the current packet is checked to determine if it indicates the proper state for each video frame. If the CC value is inaccurate, the state of the TOGGLE bit is checked. The first or second error remediation mode is performed, respectively, depending on whether one or both of the CC and TOGGLE bits are in error. In a second mode initiated by both the wrong CC and TOGGLE bits, the system is conditioned to be reset to a packet containing a picture layer header. In the first mode, where only CC is wrong, the system has a slice layer. Conditioned to be reset to a packet containing header). (The slice layer is a subset of the compressed data in the frame.) In both the first and second modes, the media error code written to memory is decompressed to perform a remedial action. It is held in each payload to notify the decompressor.

It can be particularly useful to partition the system so that SCID detectors, cryptanalyzers, addressing circuits, conditional access filters, and smart card interfaces are all contained on a single integrated circuit. Do you get it. This limits the number of external paths that result in critical timing constraints.

10 Tuner detector 12 FEC 13 Programmable SCID register 15 SCID match detection 16 Decryptor 30 E-code decoder 31 smart card