Integrated Circuit chip and manufacturing method thereof and multi chip package

The present invention relates to a semiconductor device, and more specifically, a semiconductor package using an integrated circuit chip in which a bond pad is formed in an upper part of a cell area, a multi chip package. ) And its manufacturing method.

Technological development is becoming smaller and smaller in the electronic industry. In the semiconductor field as well, there is a demand for reducing the size of integrated circuit chips, and many efforts are being made to solve the problems of reducing the bond pad size and reducing the bond pad pitch in order to cope with the miniaturization. ..

A typical integrated circuit chip that has undergone a wafer assembly process acts as an input / output terminal for electrical signals on the active surface of a semiconductor substrate provided with an on-chip circuit. A bond pad is formed, and the active surface excluding the bond pad has a structure in which a protective film such as a nitride film is covered. The integrated circuit chip is classified into a center pad type and an edge pad type according to the formation position of the bond pad.

FIG. 1 is a plan view showing a general center pad type integrated circuit chip, FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. 1, and FIG. 3 is a general edge pad type integrated circuit chip. It is a plan view which shows the integrated circuit chip, and FIG.

As shown in FIGS. 1 and 2, the center pad type integrated circuit chip 110 has a peripheral region A for forming a bond pad 112 in the center of the semiconductor substrate 111._periIs secured and the cell region where the integrated circuit is formed (A, which is the inner region of the alternate long and short dash line)._cell1, A_cell2) Is the structure formed on the outside. Then, as shown in FIGS. 3 and 4, the edge pad type integrated circuit chip 120 has a peripheral region A for forming a bond pad 122 at the end of the semiconductor substrate 121._peri1, A_peri2Is secured, and the cell area (A, which is the inner area of the alternate long and short dash line)_cell) Is the structure formed inside it. Reference numbers 113 and 123 are protective films.

However, the integrated circuit chip having the above-described structure has a limit in reducing the chip size regardless of the bond pad arrangement form. Basically, the cell area (A_cellOr A_cell1, A_cell2) And the peripheral area for bond pad formation (A)_periOr A_peri1, A_peri2) And must be provided. At present, the reduction of the chip size is only realized by increasing the degree of integration and decreasing the bond pad size in a state where the above-mentioned cell region and the peripheral region including the region for forming the bond pad are secured. That is, the reduction in bond pad size is realized by reducing the size of the cell region or the peripheral region for the formation of the bond pad itself.

Further, the integrated circuit chip having the above-mentioned structure has a limit in reducing the bond pad size and the pad pitch. With the development of semiconductor technology, the bond pad size and bond pad pitch have decreased, and it has become possible to realize smaller and multi-pin integrated circuit chips. This is because it is necessary to secure a basic size that allows the electrical Die Sorting test and the electrical interconnection to be carried out in. Currently, technical limitations have emerged in the ability to manufacture and test accuracy of probes used for electrical property inspection, not responding to the declining trend of bond pad sizes, and electrical interconnections such as wire bonding and beams have emerged. The technical limitations of beam lead bonding have emerged.

Further, in the case of a multi-chip package having a plurality of integrated circuit chips having the above-mentioned structure, there is a limit to the reduction of the package size, and there are various restrictions on the package implementation due to the position constraint of the bond pad. In particular, in the case of a center pad type integrated circuit chip, it is difficult to stack the same type of chips, and the length of the bonding wire becomes long.

<p> Therefore, an object of the present invention is to provide an integrated circuit chip capable of overcoming the limitation of chip size reduction as described above. Another object of the present invention is to provide an integrated circuit chip capable of overcoming the limits of bond pad size and bond pad pitch reduction. Further, another object of the present invention is to provide a multi-chip package that can overcome the limitation of embodying the multi-chip package by the bond pad arrangement structure.</p>

<p><u style="single"> Said</u>In order to achieve the object, the semiconductor multi-chip package according to the present invention is A package substrate having a surface on which a large number of bonding chips are formed and two or more semiconductor chips mounted on the surface of the package substrate are provided. At least one of the semiconductor chips Adjacent to each other<u style="single">Peripheral circuit area and cell area</u>A semiconductor substrate having an integrated circuit formed on top of it, The bond pad wiring pattern formed on the semiconductor substrate and<u style="single"> A first interlayer insulating film covering the bond pad wiring pattern and </u><u style="single"> A second interlayer insulating film covering the first interlayer insulating film and</u><u style="single"> On the second interlayer insulating film</u>A pad rearrangement pattern that includes a bond pad that is in direct contact with the bond pad wiring pattern and is located above at least a portion of the cell region. With an insulating layer formed on the pad rearrangement pattern, The bond pad wiring pattern is formed on at least a portion of the peripheral circuit area. The bond pad is included in the pad rearrangement pattern exposed through the insulating layer. Each bonding tip is characterized by being electrically coupled to the corresponding bond pad. The chip size can be reduced by forming the rearranged bond pad in the upper part of the cell region and not providing a region prepared for forming the bond pad in the peripheral region.</p><p> Here, in the integrated circuit chip according to the present invention, it is desirable that an interlayer insulating film covering the protective film is formed and a rearranged bond pad is formed on the interlayer insulating film, and the rearranged bond pad is formed on the interlayer insulating film. It is desirable that it is formed in the same layer as the pad rewiring pattern. The interlayer insulating film preferably flattens the semiconductor substrate and consists of a multi-layer insulating film, such as a high Density Plasma (HDP) oxide film, a benzocyclobutene (BCB) film, and a polybenzoxazole. At least one of a (polybenzoxazole; PBO) film and a polyimide film is preferable. In particular, High Density Plasma SiO₂Membrane; HDP-SiO₂Membrane) is preferred. The final insulating film covering the pad rewiring pattern is preferably at least one of a high-density plasma oxide film and a polyimide film. On the other hand, as the interlayer insulating film, the first interlayer insulating film and the second interlayer insulating film are formed over the entire surface, or the rearranged bond pad region of the pad rewiring pattern is in contact with the first interlayer insulating film. Can be partially formed.</p><p> Further, other integrated circuit chips according to the present invention include a semiconductor substrate having a cell region and a peripheral region, a bond pad formed in the peripheral region, a protective film formed on the semiconductor substrate to expose the bond pad, and the like. An interlayer insulating film formed on the protective film to flatten the semiconductor substrate, a pad rewiring pattern formed on the interlayer insulating film and connected to the bond pad, and a final insulating film covering the pad rewiring pattern. It is characterized by including a rearranged bond pad formed by exposing the pad rewiring pattern from above the cell region. Preferably, the bond pad has a center pad type arrangement structure and the rearranged bond pad has an edge pad type arrangement structure.</p><p> Further, in the multi-chip package according to the present invention, as described above, a plurality of integrated circuit chips of the present invention including the rearranged bond pads formed on the cell region are arranged and mounted vertically or horizontally on the substrate. It is characterized in that the integrated circuit chip and the substrate are wire-bonded. Here, when the integrated circuit chips are the same type of chips, it is preferable to stack them vertically on the substrate with an insert between the chips interposed therebetween, and when the sizes of the integrated circuit chips are different, first, the integrated circuit having the largest size is used. It is preferable to mount the chips on a substrate and stack them on the integrated circuit chips in ascending order of size.</p><p> Further, in the other multi-chip package according to the present invention, the plurality of first and second chips according to the present invention including the rearranged bond pad formed on the cell region as described above include a plurality of leads. It is mounted on a lead frame and is characterized in that the rearranged bond pads of the first and second chips are wire bonded to the leads.</p><p> In the case of a lead frame of a general form having a die pad, it is preferable that the first and second chips are mounted on the upper surface and the lower surface of the die pad, respectively. A plurality of integrated circuit chips vertically stacked on the first chip and the second chip can be further provided.</p>

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. In the drawings, the thickness of the film and the like are emphasized for a clearer explanation. In the drawings, the same reference numerals indicate the same components.

(First Example) 5 to 8 are cross-sectional views showing a process of manufacturing the first embodiment of the integrated circuit chip according to the present invention, and FIG. 9 is a plan view of the first embodiment of the integrated circuit chip according to the present invention. Yes, FIG. 10 is a partial cross-sectional view showing another connecting structure of the "A" portion of FIG. 8, and FIG. 11 is a cross-sectional view showing a state in which wire bonding is performed on the integrated circuit chip of FIG. ..

The integrated circuit chip 10 shown in FIGS. 8 and 9 has a cell region A in which an integrated circuit is formed by a center pad type chip design._cell1, A_cell2Peripheral area A between_periThe semiconductor substrate 11 includes a bond pad wiring pattern 12 connected to an integrated circuit on the semiconductor substrate 11. The bond pad wiring pattern 12 is formed in a line form having a predetermined pattern on the layer on which the conventional bond pad is formed, and one end thereof is a peripheral region A._periLocated in. Peripheral area A_periSince the bond pad region is not secured and only a part of the bond pad wiring pattern 12 which is a line form exists, the width of is narrower than that of the conventional one. As a result, the semiconductor substrate 11 has an overall width reduced by the width required for the bond pad region.

Here, peripheral area A_periThe bond pad wiring pattern portion located in is used when forming a separate peripheral circuit as needed. When it is not necessary, the bond pad wiring pattern 12 is not located in the peripheral area and the cell area A_cell1, A_cell2Can only be located in. Further, the connection between the bond pad wiring pattern 12 and the integrated circuit of the semiconductor substrate is in the cell area A._cell1, A_cell2And surrounding area A_periIt is possible in any of the above. As the material of the bond pad wiring pattern 12, a metal having excellent electrical conductivity, for example, an aluminum material can be used.

A protective film 16 that covers the bond pad wiring pattern 12 and an interlayer insulating film 13 that covers the protective film 16 are formed on the semiconductor substrate 11. The interlayer insulating film 13 is insulated and so as to support the physical stress applied in the process of electrical interconnection such as wire bonding or beam lead bonding to the rearranged bond pad 17 described later. It is made of a material with excellent strength. As the interlayer insulating film, a high density plasma (HDP) oxide film, a benzocyclobutene (BCB) film, a polybenzoxazole (PBO) film, and a polyimide film are preferable. Among them, the interlayer insulating film 13 is a high-density plasma oxide film using silane, oxygen, and argon gas having excellent strength against physical stress, for example, a high-density plasma silicon oxide film (HDP-SiO).₂Membrane) is preferred.

A pad rewiring pattern 15 is formed in a predetermined pattern on the interlayer insulating film 13. The pad rewiring pattern 15 is a wiring pattern in which the position of the rearranged bond pad 17 is rearranged in the upper part of the cell region. One end of the pad rewiring pattern 15 is connected to the bond pad wiring pattern 12 exposed from the interlayer insulating film 13, and the other end is sized so as to have a constant size in the upper part of the cell region at the end of the semiconductor substrate 11. Has an expanded area. The connection with the bond pad wiring pattern 12 forms a hole of a predetermined size in the interlayer insulating film 13 as shown in "A" of FIG. 8, and a part of the pad rewiring pattern 15 is formed in the hole. The bond pad wiring pattern 12 is exposed in the form of a bond pad having the minimum size, and the bond pad wiring pattern 12 is exposed so as to enter the connection in the form of a via hole, or as shown in FIG. It can be connected so as to cover the part. Pad rewiring pattern 15, not shown in detail, is 300-500 Å thick titanium (Ti), about 15000 Å thick aluminum (Al) on it, and 300-500 Å thick nitriding on it. It is preferably composed of three layers such as titanium (TiN). In some cases, copper, aluminum, zinc, iron, platinum, cobalt, lead, nickel, or alloys thereof can be used.

A final insulating film 18 is formed on the interlayer insulating film 13 to cover the pad rewiring pattern 15 and expose a certain portion of the pad rewiring pattern 15. The pad rewiring pattern portion exposed from the final insulating film 18 is defined as the rearranged bond pad 17, and the pad rewiring pattern 15 and the rearranged bond pad 17 are located on the same layer. On the other hand, the rearranged bond pad 17 has a cell region A at the end of the semiconductor substrate 11._cell1, A_cell2It is located at the top of. As shown in FIG. 11, an electrical interconnect means, for example, a bonding wire 99, can be bonded to the rewiring bond pad 17. The formation position of the rearranged bond pad 17 can be varied as needed in consideration of electrical interconnection.

Here, it is shown that the rearranged bond pads 17 are arranged in a row at both ends facing each other, but there are various arrangements such as an arrangement at all four ends and a zigzag form. Can have a form. On the other hand, the final insulating film 18 is HDP-SiO.₂The polyimide film can be composed of a high-density plasma oxide film such as a film or HDP-SiN film, and the polyimide film is HDP-SiO so that the internal circuit can be protected from α particles.₂It can be further formed on the membrane.

Such an integrated circuit chip is located in the upper part of the cell region without the rearranged bond pad being formed in the peripheral region of the semiconductor substrate. Therefore, with the same width of the cell area, the peripheral area A_periSince the width of the integrated circuit chip can be reduced by the width of the region for forming the conventional bond pad, the overall width of the integrated circuit chip is reduced as compared with the conventional one. The width of the cell area is the same as before. Of course, the thickness is increased by the pad rewiring pattern in the upper part of the cell region and the final insulating film, but the increase in thickness is not large with respect to the decrease in width, and the overall chip size is reduced. The interlayer insulating film can support the physical stress applied when electrical interconnection, for example wire bonding, is performed on the rearranged bond pad formed in the upper part of the cell region, so that the lower part of the rearranged bond pad is integrated. Does not damage the circuit.

Further, the above-mentioned integrated circuit chip has a structure in which an integrated circuit chip designed as a center pad type circuit is changed to an edge pad type integrated circuit chip form. By changing from a center pad type to an edge pad type integrated circuit chip, the distance between the bond pads can be increased, and the contact of the probe can be made easier in the electrical property inspection. Then, by such a structural change, the center pad type integrated circuit chip, which is generally known to have superior electrical characteristics as compared with the edge pad type, is converted into an edge pad type structure, and LOC (Lead On Chip) is used. ) It can be embodied in a package in a normal form that is not a form. Further, the rearranged bond pad can be formed at an arbitrary position on the upper layer of the interlayer insulating film so that the bond pad has a fine pitch by reducing the chip size, and the degree of integration is improved and the number of pins is increased. It is easy to deal with.

Such an integrated circuit chip is manufactured in the state of a semiconductor wafer by the following process. First, in a general wafer state, cell region A, as shown in FIG._cell1, A_cell2The bond pad wiring pattern 12 is formed on the silicon-like semiconductor substrate 11 for which the formation of the integrated circuit has been completed, and the protective film 16 is covered. A bond pad wiring pattern 12 having a predetermined pattern is integrated on a semiconductor substrate 11 on which an integrated circuit is formed through a predetermined wafer assembly process by a plating method using a photosensitive film pattern as a mask or a vapor deposition method such as sputtering. It can be formed by selectively connecting with. Here, the bond pad wiring pattern 12 is the cell area A._cell1, A_cell2Upper and peripheral area A_periAlthough it is shown in the figure, it is located in cell area A._cell1, A_cell2Can be located only in.

Next, as shown in FIG. 6, the step of forming the interlayer insulating film 13 on the protective film 16 proceeds. As described above, the interlayer insulating film 13 has excellent strength and is in charge of the interlayer insulating function so as to prevent the physical stress applied by the electrical interconnection from being transmitted to the integrated circuit below. HDP-SiO₂Form a film. This makes it possible to protect the lower integrated circuit even when a certain degree of physical stress is applied. The interlayer insulating film 13 also exerts a flattening action on the upper portion of the semiconductor substrate 11. The opening 14 that exposes the bond pad wiring pattern 12 is the cell region A._cell1, A_cell2Formed on top or peripheral area A_periIt is formed in the part located in.

Although FIG. 6 illustrates that the step of forming the interlayer insulating film 13 is performed in one step, it can also proceed in two steps. After forming the interlayer insulating film 13 in the secondary order, the flattening step can be further advanced. By further advancing the flattening step, the flatness of the interlayer insulating film 13 is improved, and the flatness of the pad rewiring pattern 15 formed on the interlayer insulating film 13 is also improved. As a result, when electrical interconnection such as wire bonding is carried out on the rearranged bond pad (17 in FIG. 8), poor bonding with the bonding wire or beam lead is prevented, and the bonding force is improved. The flattening step can be performed by known chemical mechanical polishing.

When the interlayer insulating film 13 is formed, as shown in FIG. 7, the pad rewiring pattern 15 connected to the exposed portion of the bond pad wiring pattern 12 by the opening 14 of the interlayer insulating film 13 is formed into the interlayer insulating film. 13 Go through the steps of forming in a predetermined pattern on top. The pad rewiring pattern 15 can be obtained in a desired pattern by vapor deposition such as plating and sputtering as in the bond pad wiring pattern 12.

When the pad rewiring pattern 15 is formed, the final insulating film 18 is formed as the next step. As shown in FIG. 8, a part of the pad rewiring pattern 15 on the end of the cell region is exposed on the entire surface of the interlayer insulating film 13 including the pad rewiring pattern 15, and the rearranged bond pad 17 is formed. The final insulating film 18 to be formed is formed. The final insulating film 18 is HDP-SiO like the interlayer insulating film 13 so as to protect the pad rewiring pattern 15 and the integrated circuit under the pad rewiring pattern 15.₂The material is used to protect the integrated circuit from the external environment. The final insulating film 18 is first subjected to HDP-SiO for strength reinforcement and protection from the external environment.₂It can be embodied in two layers by forming a film and then forming a polyimide film on it for protection from sputum particles.

(Second Example) FIG. 12 is a cross-sectional view showing a manufacturing process of the second embodiment of the integrated circuit chip according to the present invention. In the integrated circuit chip 30 shown in FIG. 12, a first interlayer insulating film 13 is formed on the protective film 16, a second interlayer insulating film 20a is formed on the protective film 16, and a pad rewiring pattern 15 is formed on the first interlayer insulating film 20a. It is a formed structure. A second interlayer insulating film 20a that functions as a dielectric layer is formed between the first interlayer insulating film 13 and the pad rewiring pattern 15, so that the electrical characteristics of the integrated circuit chip 30, such as capacitance, are lowered. I am trying to do it. The thickness of the second interlayer insulating film 20a is set to an appropriate level, for example, about 2 to 50 μm, in consideration of capacitance characteristics and strength reinforcement. A substance such as benzocyclobutene, polybenzoxazole, or polyimide can be mainly used for the second interlayer insulating film 20a.

Such an integrated circuit chip 30 is manufactured by the following process. However, up to the stage where the first interlayer insulating film is formed on the semiconductor substrate 11, the same as the manufacturing method of the first embodiment described above, and the illustration and description thereof will be omitted. Cell region A of semiconductor substrate 11_cell1, A_cell2A bond pad wiring pattern 12 connected to the integrated circuit of the semiconductor substrate 52 is formed, and a protective film 16 is formed on the protective film 16 so that a part of the bond pad wiring pattern 12 is opened. The second interlayer insulating film 20a is formed in the state where the interlayer insulating film 13 is formed. The second interlayer insulating film 20a can be formed by a conventional spin coating method and a photographic process. At this time, the second interlayer insulating film 20a is formed on the first interlayer insulating film 13, and the portion exposed from the first interlayer insulating film 13 is removed to expose the bond pad wiring pattern 12. Then, the pad rewiring pattern 15 connected to the bond pad wiring pattern 12 is formed on the second interlayer insulating film 20a, the final insulating film 18 is formed, and the rearranged bond pad 17 is formed on the cell region. Here, polyimide can be used for the second interlayer insulating film 20a and the final insulating film 18.

(Third Example) 13 to 15 are cross-sectional views showing a manufacturing process of the third embodiment of the integrated circuit chip according to the present invention. In the integrated circuit chip 50 shown in FIG. 13, a second interlayer insulating film 20b is formed on the first interlayer insulating film 13 as in the integrated circuit chip 30 of the second embodiment described above. Unlike the integrated circuit chip 30 of the second embodiment, the rearranged bond pad 17 has a structure formed on the first interlayer insulating film 13. The lower part of the rearranged bond pad 17 of the second interlayer insulating film 20b is removed so that the cushioning phenomenon due to the physical stress applied when electrically interconnecting due to the characteristics of the integrated circuit chip 50 does not occur. It is a form.

In such an integrated circuit chip 50, the step of forming the second interlayer insulating film 20a in the manufacturing method of the second embodiment rearranges the second interlayer insulating film 20b as shown in FIG. With the first interlayer insulating film 13 at the position where the bond pad 17 should be formed removed so as to be opened, as a subsequent step, the pad rewiring pattern 15 is formed as shown in FIG. As shown in FIG. 15, the final insulating film 18 can be formed so that a certain portion of the pad rewiring pattern 15 is exposed. The exposed part becomes the rearranged bond pad 17.

(Fourth Example) FIG. 16 is a cross-sectional view showing a fourth embodiment of the integrated circuit chip according to the present invention. Unlike the above-described embodiment, in the integrated circuit chip 80 shown in FIG. 16, the bond pad 12 arranged in the center pad type has a peripheral region A._periLocated in. The protective film 16 exposes the bond pad 12 and is formed on the semiconductor substrate 81. Usually, an integrated circuit chip in a state where the wafer assembly process is completed has such a state. An interlayer insulating film 13 is formed on the protective film 16 so as to flatten the upper portion of the semiconductor substrate 81. The pad rewiring pattern 15 formed on the interlayer insulating film 13 is connected to the bond pad 12, and the final insulating film 18 covers the pad rewiring pattern 15. Cell region A from final insulating film 18_cell1, A_cell2The rearranged bond pad 17 is formed as a portion of the pad rewiring pattern 15 exposed above. The rearranged bond pad 17 has an edge pad type arrangement structure formed at the end of the integrated circuit chip 80.

Such an integrated circuit chip does not have the structural advantage of reducing the chip size, unlike the above-described embodiment, but due to the structural change of converting the center pad type integrated circuit chip to the edge pad type, the bond pad can be used. The placement restrictions can be overcome, and the limits of bond pad size and bond pad pitch reduction can be overcome.

(Fifth Example) FIG. 17 is a cross-sectional view showing a fifth embodiment of the integrated circuit chip according to the present invention. In the integrated circuit chip 90 shown in FIG. 17, the bond pad 12 arranged in the center pad type is in the peripheral region A as in the fourth embodiment._periA protective film 16 is formed on the semiconductor substrate 81 so as to expose the bond pad 12. However, unlike the fourth embodiment, the first interlayer insulating film 13 and the second interlayer insulating film 20 are formed on the protective film 16 while flattening the upper portion of the semiconductor substrate 81. A pad rewiring pattern 15 is formed on the second interlayer insulating film 20, and is connected to the bond pad 12 through the first interlayer insulating film 13 and the second interlayer insulating film 20. A final insulating film 18 covering the pad rewiring pattern 15 is formed on the second interlayer insulating film 13, and the cell region A is formed from the final insulating film 18._cell1, A_cell2The structure in which the rearranged bond pad 17 is formed as a portion of the pad rewiring pattern 15 exposed above is the same as in the fourth embodiment.

In such an integrated circuit chip, a process of electrically connecting to the rearranged bond pad by a two-layer interlayer insulating film structure consisting of a first interlayer insulating film and a second interlayer insulating film under the rearranged bond pad. Be able to disperse and support the physical stress applied in. Further, the rearranged bond pad is formed through a plurality of flattening processes by the interlayer insulating film, and the bonding stability in electrical connection with the outside such as wire bonding can be improved. On the other hand, various forms of multi-chip packages can be realized by applying the examples of the integrated circuit chip according to the present invention.

(First Example of Multi-Chip Package) FIG. 18 is a cross-sectional view showing a first embodiment of the multi-chip package according to the present invention. The multi-chip package 200 shown in FIG. 18 is an integrated circuit chip according to the present invention in which rearranged bond pads 217a and 217b are formed on the cell region described above. The structure is such that 210b is vertically laminated on the substrate 251. The electrical connection between the first and second chips 210a and 210b and the substrate 251 is made by wire bonding using a bonding wire 257. Here, both the first chip 210a and the second chip 210b have a center pad type integrated circuit design structure, and the rearranged bond pads 217a and 217b formed on the cell region are formed at the chip ends. It has an edge pad type arrangement structure. The first chip 210a is mounted on the substrate 251 with an adhesive 261 and the second chip 210b is mounted on the first chip 210a with an interchip insert 263 interposed therebetween. The inter-chip insert 263 secures a space for the bonding wire 257 that connects the first chip 210a and the substrate 251. Here, as the substrate 251, a printed circuit board, a tape wiring board, or the like can be applied.

The upper part of the substrate 251 is sealed from the external environment by a sealing portion 259 formed of an epoxy molding resin, in which the first chip 210a, the second chip 210b, the bonding wire 257, and their electrical connecting portions are sealed. Be protected. A solder ball 271 is formed as an external connection terminal on the lower portion of the substrate 251. Reference numeral 253 is a substrate bonding pad formed on the substrate 251.

The multi-chip package of this embodiment includes a plurality of integrated circuit chips in which rearranged bond pads are formed on a cell region to form a single package, thereby increasing the memory capacity and increasing the number of input / output pins. Can cope with the increase. Further, an integrated circuit chip according to the present invention in which the rearranged bond pad has an edge pad type arrangement structure is applied to overcome the stacking constraint due to the bond pad arrangement structure of the center pad type integrated circuit chip in which the bond pad is formed in the center. be able to.

(Second Example of Multi-Chip Package) FIG. 19 is a cross-sectional view showing a second embodiment of the multi-chip package according to the present invention. In the multi-chip package 300 shown in FIG. 19, the first chip 310a and the second chip 310b in which the rearranged bond pads 317a and 317b, which are integrated circuit chips according to the present invention as described above, are formed on the cell region. Is horizontally arranged on the substrate 351 and has a structure in which the chips 310a and 310b and the substrate 351 are wire-bonded by a bonding wire 357 and electrically connected. Reference numeral 353 is a substrate wiring pattern, 359 is a sealing portion, 361 is an adhesive, and 371 is a solder ball.

In the multi-chip package of this embodiment, a plurality of integrated circuit chips having rearranged bond pads formed on the cell region are horizontally arranged to form a single package, thereby increasing the memory capacity and inputting. It is possible to cope with an increase in the number of output pins.

(Third Example of Multi-Chip Package) FIG. 20 is a cross-sectional view showing a third embodiment of the multi-chip package according to the present invention. In the multi-chip package 400 shown in FIG. 20, unlike the multi-chip package of the first embodiment composed of chips of the same type, the rearranged bond pads 417a, 417b, and 417c are formed on the cell region. This is a structure in which integrated circuit chips 410a, 410b, and 410c according to the present invention, which are different types of chips having different sizes, are vertically laminated. The integrated circuit chips 410a, 410b, and 410c are vertically stacked on the substrate 451 in the order of the integrated circuit chip 410a having a large chip size and the integrated circuit chip 410c having a small chip size. The integrated circuit chips 410a, 410b, 410c and the substrate 451 are electrically connected by the bonding wire 457. Here, unlike the first embodiment, no separate interchip insert is required.

The multi-chip package of this embodiment can be embodied not only by the same type of chips but also by different types of chips. The integrated circuit chip having the center pad type bond pad is converted into the integrated circuit chip having the edge pad type rearranged bond pad, and a plurality of integrated circuit chips can be vertically stacked, and the length of the bonding wire is shortened.

(Fourth Example of Multi-Chip Package) FIG. 21 is a cross-sectional view showing a fourth embodiment of the multi-chip package according to the present invention. The multi-chip package 500 shown in FIG. 21 is a so-called Dual Die package (DDP) in which two integrated circuit chips 510a and 510b are embedded in a lead frame as a chip mounting means. It is a package form with a LOC (Lead On Chip) structure. The first chip 510a is a center pad type in which the bond pad 517a is formed in the center of the chip, and the second chip 510b is a rearranged bond pad 517b formed by rearranging the bond pads at the end of the chip. It is an edge pad type.

A separate die pad for mounting an integrated circuit chip is not provided, and the first chip 510a is attached to the back surface of the LOC type lead frame lead 551 in which the opposing leads extend from the leads of a general lead frame with adhesive tape 563. It is attached. The bond pad 517a of the first chip 510a is located between the opposing leads 551 and is wire bonded to the upper surface of the corresponding lead 551 by a bonding wire 557a. A second chip 510b is attached to the back surface of the first chip 510a with an adhesive 561. The rearranged bond pad 557b of the second chip 510b is attached to the underside of the lead 551. The first chip 510a, the second chip 510b, the bonding wire 551, and their bonding portions are sealed by a sealing portion 559.

It is shown that the multi-chip package according to the present invention, such as the multi-chip package in the form of a dual die package, can embody the package by using the center pad type chip and the edge pad type rearrangement chip. In addition, the LOC package structure allows for the inclusion of large integrated circuit chips.

(Fifth Example of Multi-Chip Package) FIG. 22 is a cross-sectional view showing a fifth embodiment of the multi-chip package according to the present invention. The multi-chip package 600 shown in FIG. 22 is a dual Die package (DDP) that utilizes a general lead frame having a die pad 653 and contains two integrated circuit chips 610a and 610b. The first chip 610a and the second chip 619 are edge pad types in which the rearranged bond pads 617a and 617b formed by rearranging the bond pads are formed at the tip ends.

The first tip 610a and the second tip 610b are attached to the upper surface and the lower surface of the die pad 653 with the adhesive 661, respectively. The rearranged bond pad 617a of the first chip 610a is wire-bonded to the upper surface of the lead 651 by the bonding wire 657a, and the rearranged bond pad 617b of the second chip 610b is wire bonded to the lower surface of the lead 651 by the bonding wire 657b. Has been done. The first chip 610a, the second chip 610b, the bonding wires 657a and 657b, and their joint portions are sealed by a sealing portion 659.

In such a dual die package type multi-chip package, the center pad type integrated circuit chip is changed to have an edge pad type rearranged bond pad, and the integrated circuit chip is attached to the upper surface and the lower surface of the die pad. It is shown that a package in a general form can be embodied.

(Sixth Example of Multi-Chip Package) FIG. 23 is a cross-sectional view showing a sixth embodiment of the multi-chip package according to the present invention. The multi-chip package 700 shown in FIG. 23 is a TSOP (Thin Small Outline) in which a plurality of integrated circuit chips different from each other are embedded by using a general lead frame having a die pad 753. Package) form. The back surface of the first chip 710a is attached to the upper surface of the die pad 753, and the second chip 710b is attached to the upper surface of the first chip 710a. The back surface of the third chip 710c is attached to the lower surface of the die pad 753, and the back surface of the fourth chip 710d is attached to the upper surface of the third chip 710c. In both cases, the upper and lower chips 710a to 710d are centered on the die pad 753, and the rearwardly arranged bond pads 717a to 717d face in opposite directions. Here, the first chip 710a and the second chip 710b, and the third chip 710c and the fourth chip 710d are different types of integrated circuit chips of different sizes, and are edge pads from the center pad type bond pad structure. It is an integrated circuit chip modified to a structure having a mold rearrangement bond pad.

Relocation of the first chip 710a and the second chip 710b The bond pads 717a and 717b are wire-bonded to the upper surface of the lead 751 with bonding wires 757a and 757b, and the third chip 710c and the fourth chip 710d are rearranged. The bond pads 717c and 717d are wire-bonded to the lower surface of the lead 751 with bonding wires 757c and 757d. The integrated circuit chips 710a to 710d, the bonding wires 757a to 757d, and their bonding portions are sealed by a sealing portion 753. Reference numerals 761, 762, 763, 764 are adhesives.

As is clear from such a multi-chip package, the multi-chip package according to the present invention has an integrated circuit chip having a center pad type bond pad arrangement structure and an integrated circuit chip structure having an edge pad type rearranged bond pad. It is shown that the TSOP package can be realized by changing as follows. Here, it is illustrated that two integrated circuit chips are mounted on the upper and lower sides of the die pad, but the present invention is not limited to this.

(Effect of the invention) As described above, according to the integrated circuit chip and the multi-chip package according to the present invention, the bond pad is removed in the peripheral region outside the cell region of the semiconductor substrate, moves to another layer above the cell region, and is peripheral. By reducing the width of the region, the chip size can be reduced. As a result, the number of integrated circuit chips obtained from wafers having the same diameter increases, and the degree of freedom in chip design increases.

Further, the center pad type chip can be converted to have an edge pad type pad arrangement structure, and various types of packages can be realized with a specific integrated circuit chip. In particular, an integrated circuit chip whose circuit is designed as a center pad type can be converted into a general package structure that is not a LOC type package, so that manufacturing cost can be reduced.

In addition, the interlayer insulating film under the bond pad allows the bond pad or the bond pad due to physical stress applied during the electrical interconnection process, such as contact with a probe for electrical property inspection and wire bonding or beam lead bonding. It is possible to prevent damage to the integrated circuit below it and a decrease in bonding force. In particular, HDP-SiO₂By forming a film, a more excellent effect can be obtained.

Further, since the bond pad can be formed so as to have a larger area in the upper part of the cell region in the outer region of the cell region, the limitation of the electrical property inspection can be overcome. Furthermore, if the center pad type integrated circuit chip is converted to the edge pad type, the distance between the bond pads will increase, and the manufacturing limit of the probe can be overcome to some extent.

Further, the multi-chip package according to the present invention can obtain various effects such as reduction of the mounting area by increasing the memory capacity at the package level and packaging the multi-chip package by stacking the same type or different types of chips.

<figref num="1">It is a top view which shows the general center pad type integrated circuit chip.</figref><figref num="2">It is a cross-sectional view taken along the line 2-2 of FIG.</figref><figref num="3">It is a top view which shows the general edge pad type integrated circuit chip.</figref><figref num="4">It is a sectional view taken along line 4-4 of FIG.</figref><figref num="5">It is sectional drawing which shows the manufacturing process of 1st Example of the integrated circuit chip which concerns on this invention.</figref><figref num="6">It is sectional drawing which shows the manufacturing process of 1st Example of the integrated circuit chip which concerns on this invention.</figref><figref num="7">It is sectional drawing which shows the manufacturing process of 1st Example of the integrated circuit chip which concerns on this invention.</figref><figref num="8">It is sectional drawing which shows the manufacturing process of 1st Example of the integrated circuit chip which concerns on this invention.</figref><figref num="9">It is a top view of the 1st Example of the integrated circuit chip which concerns on this invention.</figref><figref num="10">It is a partial cross-sectional view which shows the other connecting structure of the "A" part of FIG.</figref><figref num="11">FIG. 5 is a cross-sectional view showing a state in which wire bonding is performed on the integrated circuit chip of FIG.</figref><figref num="12">It is sectional drawing which shows the manufacturing process of the 2nd Example of the integrated circuit chip which concerns on this invention.</figref><figref num="13">It is sectional drawing which shows the manufacturing process of the 3rd Example of the integrated circuit chip which concerns on this invention.</figref><figref num="14">It is sectional drawing which shows the manufacturing process of the 3rd Example of the integrated circuit chip which concerns on this invention.</figref><figref num="15">It is sectional drawing which shows the manufacturing process of the 3rd Example of the integrated circuit chip which concerns on this invention.</figref><figref num="16">It is sectional drawing which shows 4th Example of the integrated circuit chip which concerns on this invention.</figref><figref num="17">It is sectional drawing which shows 5th Example of the integrated circuit chip which concerns on this invention.</figref><figref num="18">It is sectional drawing which shows 1st Example of the multi-chip package which concerns on this invention.</figref><figref num="19">It is sectional drawing which shows the 2nd Example of the multi-chip package which concerns on this invention.</figref><figref num="20">It is sectional drawing which shows the 3rd Example of the multi-chip package which concerns on this invention.</figref><figref num="21">It is sectional drawing which shows 4th Example of the multi-chip package which concerns on this invention.</figref><figref num="22">It is sectional drawing which shows 5th Example of the multi-chip package which concerns on this invention.</figref><figref num="23">It is sectional drawing which shows 6th Example of the multi-chip package which concerns on this invention.</figref>

Code description

10, 30, 50, 80, 90 integrated circuit chips 11 Semiconductor substrate 12 Bond pad wiring pattern 13 First interlayer insulating film 14 opening 15 Pad rewiring pattern 16 Protective film 17 Relocation Bond Pad 18 Final insulating film 20a, 20b Second interlayer insulating film 200, 300, 400, 500, 600, 700 multi-chip package 251, 351, 451 boards 253, 353, 453 Board circuit pattern 257, 357, 457, 557a, 557b, 657a, 657b, 757a, 757b, 757c, 757d Bonding wire 259, 359, 459, 559, 659, 759 Seal 261, 361, 461, 561, 661, 761, 762, 763, 764 Adhesive 263 Interchip insert 271, 371, 471 Solder balls 551, 651, 751 leads 563 Adhesive tape 653, 753 die pad