Enhanced electrically-aligned proximity communication

(Related application) U.S. Patent Application No. 10 / 879,607, for which this application claims priority, is the inventor Robert, referred to as "Enhanced Electrically Aligned Proximity Communication" filed on September 5, 2003, under 35 U.SC § 119. J. Drost, Ivan E. Claims priority to US Provisional Patent Application No. 60 / 500,661 by Sutherland and Ronald Ho (agent reference number SUN03-0272PSP). (Government license rights) U.S. Patent Application No. 10 / 879,607, for which this application claims priority, was made with U.S. Government support under Contract No. NBCH020055 conferred by the Defense Advanced Research Projects Administration. The United States Government has certain rights to the invention. (Field of invention) The present invention relates to a technique for communicating signals between semiconductor dies. More specifically, the present invention relates to methods and devices for communicating between semiconductor dies by routing electrical signals based on alignments between semiconductor dies.

(Related technology) The current advantage in semiconductor technology is that it allows large-scale systems containing tens of millions of transistors to be integrated into a single semiconductor chip. Incorporating such a large system into a single semiconductor chip increases the speed at which such a system can operate. This is because the signals between the components of the system do not have to cross chip boundaries and are less susceptible to redundant chip-to-chip transmission delays. In addition, incorporating large-scale systems into a single semiconductor chip significantly reduces production costs. This is because fewer semiconductor chips are needed to perform a given computer computing task.

Unfortunately, these advantages of semiconductor technology have not been consistent with the corresponding advantages of chip-to-chip communication technology. Semiconductor chips are typically embedded on a printed circuit board that includes a multi-layered signal line for interchip communication. However, the signal lines on the semiconductor chip are packed about 100 times more densely than the signal lines on the printed circuit board. As a result, only a small fraction of the signal line on the semiconductor chip can be routed across the printed circuit board to another chip. This problem is creating a bottleneck that continues to grow as the semiconductor integration density continues to increase.

Researchers have begun investigating other technologies for communicating between semiconductor chips. One promised technology involves embedding an array of capacitive transmitters and receivers on semiconductor chips to facilitate communication between the chips. In the printed circuit board, when the first chip is placed face-to-face with the second chip and the transmitter pad on the first chip is capacitively coupled to the receiver pad on the second chip. Allows the signal to be transmitted directly from the first chip to the second chip without the need to route the signal through the signal line.

However, proper chip alignment is not a simple matter. It is possible to align chips by assigning charges to the conductive plates on one chip and detecting specific patterns of charge induced in the plates on the facing chips. Existing systems provide a plurality of conductive elements on the first chip and a plurality of conductive elements on the second chip that are spaced differently from the conductive elements on the first chip. Improve this technology. If the conductive element on the first chip overlaps with the conductive element on the second chip, a vernier is generated, which allows the alignment between the chips to be determined, which Allows the chips to be placed so as to minimize misalignment problems.

However, this existing system has limitations. Even if assembled very carefully and mechanically, the chip can still leave some misalignment. Misalignment, in some cases, causes each receive pad to bridge the two transmit pads, thereby destroying the received signal. Theoretically, satisfactory communication requires an alignment such that the remaining misalignment is less than half the pitch between the pads. In practice, alignment requirements can be more stringent. Moreover, the effects of thermal expansion and mechanical vibration can make it difficult to achieve and maintain such accurate alignment.

<p> Without the problems listed above, methods and devices are needed to facilitate capacitive chip-to-chip communication.</p>

<p>(Summary) One embodiment of the present invention provides a system that facilitates capacitive chip-to-chip communication. During operation, the system first determines the alignment between the first semiconductor die and the second semiconductor die. The electrical signal is then selectively routed to at least one of the plurality of interconnect pads based on its alignment, thereby between the first semiconductor die and the second semiconductor die. Smooth communication. The plurality of interconnect pads may include a transmit pad, a receive pad, and a transmit / receive pad. This alignment can be determined continuously or at intervals. This interval is fixed or variable.</p><p> In a modification of this embodiment, the alignment is such that the plurality of conductive elements on the first semiconductor die are spaced apart from the conductive elements on the first semiconductor die. It is determined using the vernier that is formed when it overlaps with the conductive element of. By selectively charging each of the plurality of conductive elements on the first semiconductor die, the charge in one or more conductive elements on the second semiconductor die becomes conductive on the first semiconductor die. The element is guided when it overlaps with one or more conductive elements on the second conductive die. This alignment is determined by amplifying and analyzing the signal induced by the conductive element on the second semiconductor die.</p><p> In a further variant of this embodiment, the routing of electrical signals relates to utilizing a multiplexer.</p><p> In another embodiment of the invention, the electrical signal is selected from receive pads that may be more than one of the second array on the second semiconductor die, using the routing mechanism inside the second array. At least one selected from at least one receive pad that may be more than one in the first array on the first semiconductor die using the routing mechanism inside the first array. Routed to one transmit pad.</p><p> In a variant of this embodiment, the routing mechanism inside the first array and the routing mechanism inside the second array include a barrel shifter.</p><p> In another variant of this embodiment, the system compensates for misalignments that are substantially less than half the pitch of the first array. Here, this pitch is defined as the distance from the center of a certain transmission pad to the center of an adjacent transmission pad.</p><p> In a modification of this embodiment, the first semiconductor die contains a routing mechanism outside the first array, the second semiconductor die contains a routing mechanism outside the second array, or the first. The semiconductor die and the second semiconductor die contain an external routing mechanism for the first array and the second array, respectively. In this variant, the routing mechanism outside the first array and the routing mechanism outside the second array include a multiplexer, facilitating the correction of coarse misalignments between the transmit and receive pads, thereby facilitating the correction. , Facilitates communication between capacitive chips.</p><p> In another variant of this embodiment, the tiling mechanism spatially sends electrical signals at multiple inputs to the routing mechanism inside the first array during at least one cycle of the clock generated by the timing mechanism. Iterates, thereby spatially repeating the electrical signal at multiple transmit pads in the first array. In yet another variation of this embodiment, the de-tiling mechanism provides spatially repeated electrical signals at multiple outputs from the routing mechanism inside the second array, and thus the second. Converts spatially repeated electrical signals in multiple receive pads of the array into electrical signals during at least one cycle of the clock.</p><p> Some further modifications of this embodiment are provided.</p><p> The method according to the present invention is a method of routing an electric signal between a first semiconductor die and a second semiconductor die, and aligns the first semiconductor die with the second semiconductor die. A determination step and a step of routing the electrical signal based on the alignment, whereby the electrical signal is routed to different interconnect pads based on the alignment and the first semiconductor die and the said. Includes steps that correct misalignment with the second semiconductor die and facilitate communication between the first semiconductor die and the second semiconductor die via capacitive coupling. , Thereby achieving the above objectives.</p><p> The electrical signal may be routed to at least one transmit pad selected from a plurality of possible transmit pads in the first semiconductor die.</p><p> The electrical signal may be routed from at least one receive pad selected from a plurality of possible transmit pads on the second semiconductor die.</p><p> The electrical signal is routed to at least one transmit pad selected from a plurality of potential transmit pads on the first semiconductor die and from a plurality of potential receive pads on the second semiconductor die. You may.</p><p> The process of determining the alignment may be performed continuously.</p><p> The process of determining the alignment may be performed periodically at time intervals.</p><p> The spacing may be substantially fixed.</p><p> The interval may be substantially variable.</p><p> The step of determining the alignment includes a step of using an alignment measurement mechanism, wherein the alignment measurement mechanism includes a plurality of conductive elements in the first semiconductor die and a plurality of conductive elements in the second semiconductor die. Therefore, the plurality of conductive elements in the second semiconductor die have a different interval from the plurality of conductive elements in the first semiconductor die, whereby in the first semiconductor die. When the plurality of conductive elements overlap with the plurality of conductive elements in the second semiconductor die, the plurality of conductive elements in the first semiconductor die and the second semiconductor die form a vernier alignment structure. A charging mechanism configured to selectively charge each of the plurality of conductive elements in the semiconductor die and the plurality of conductive elements in the first semiconductor die, wherein the first semiconductor die has a plurality of conductive elements. When the conductive element overlaps one or more conductive elements in the second semiconductor die, the step of charging the conductive element in the first semiconductor die is one or more steps in the second semiconductor die. The charging mechanism that induces charging of the conductive element, the amplification mechanism configured to amplify the signal induced in the conductive element in the second semiconductor die, and the amplified signal are analyzed. It may include an analysis mechanism configured to determine the alignment between the first semiconductor die and the second semiconductor die.</p><p> Routing the electrical signal may include a multiplexer.</p><p> The device according to the present invention is a device for communication between a first semiconductor die and a second semiconductor die, and includes a plurality of transmission pads configured in a first array of the first semiconductor die. A plurality of receiving pads configured in the second array in the second semiconductor die, a routing mechanism inside the first array, and a routing mechanism inside the second array, the first array. The routing mechanism of the first array routes electrical signals to at least one transmit pad selected from the plurality of possible transmit pads of the first array, and the routing mechanism of the second array is the second array. It routes electrical signals from at least one receive pad selected from multiple possible receive pads in an array, thereby between the transmit pad of the first array and the receive pad of the second array. A routing mechanism inside the second array that corrects for misalignment and facilitates communication between the first semiconductor die and the second semiconductor die via capacitive coupling. Including, thereby achieving the above objectives.</p><p> The routing mechanism inside the first array and the routing mechanism inside the second array may include a barrel shifter.</p><p> The first array is one-dimensional on the same plane as the transmit pad width, the second array is one-dimensional on the same plane as the receive pad width, and the first array is one. The second array may have a pitch defined by the distance from the center of the transmit pad to the center of the adjacent transmit pad.</p><p> The routing mechanism inside the first array and the routing mechanism inside the second array may correct for misalignment to less than substantially half of the pitch.</p><p> The first array is two-dimensional, substantially coplanar with the surface of the first semiconductor die, and has a transmit pad width in the first direction and a transmit pad width in the second direction. The second array, however, is two-dimensional and is substantially coplanar with the surface of the second semiconductor die, with a receive pad width in the first direction and reception in the second direction. Having a pad width, the first array has a first pitch defined by the distance from the center of one transmit pad to the center of an adjacent transmit pad in the first direction, said first. One array has a second pitch defined by the distance from the center of one transmit pad to the center of an adjacent transmit pad in the second direction, and the second array is said to be the first. It may have a first pitch in the direction of and a second pitch in the second direction.</p><p> The routing mechanism inside the first array and the routing mechanism inside the second array corrects the misalignment to less than substantially half of the first pitch in the first direction and in the second direction. Misalignment may be corrected to less than substantially half of the second pitch.</p><p> Further including a routing mechanism outside the first array configured to route electrical signals to the routing mechanism inside the first array, the routing mechanism outside the first array is the first array. The coarse misalignment between the transmit pad of the second array and the receive pad of the second array may be corrected.</p><p> The first array is one-dimensional and the routing mechanism outside the first array includes a multiplexer, which has n inputs to the multiplexer and inside the first array. It may have m outputs to the routing mechanism.</p><p> The first array is two-dimensional with a first direction and a second direction, both directions being substantially coplanar with the surface of the first semiconductor die and outside the first array. The routing mechanism includes n inputs to the multiplexer and m outputs to the routing mechanism inside the first array corresponding to the first direction. It may include m outputs to the routing mechanism inside the first array corresponding to the second direction.</p><p> The routing mechanism outside the second array further includes a routing mechanism outside the second array configured to route electrical signals from the routing mechanism inside the second array, and the routing mechanism outside the second array is said to be the first. The coarse misalignment between the transmit pad of the array and the receive pad of the second array may be corrected.</p><p> The second array is one-dimensional, the routing mechanism outside the second array includes a multiplexer, which comprises m inputs from the routing mechanism inside the second array. It may have n outputs from the multiplexer.</p><p> The second array is two-dimensional with a first direction and a second direction, both directions being substantially coplanar with the surface of the second semiconductor die and the second array. The external routing mechanism includes a multiplexer, which comprises m inputs from the routing mechanism inside the second array corresponding to the first direction and the second direction corresponding to the second direction. It may include m inputs from the routing mechanism inside the array of 2 and n outputs from the multiplexer.</p><p> A routing mechanism outside the first array, wherein the routing mechanism outside the first array is an electrical signal to the routing mechanism inside the first array and at least one transmission of the first array. A routing mechanism outside the first array and a routing mechanism outside the second array that routes electrical signals to the pads, the routing mechanism outside the second array is inside the second array. The electrical signal from the routing mechanism and the electrical signal from at least one receiving pad of the second array are routed, and the routing mechanism outside the first array and the routing mechanism outside the second array are the same. Coarse misalignment between the transmit pads of the first array and the receive pads of the second array may be corrected.</p><p> The first array and the second array are one-dimensional, and the routing mechanism outside the first array includes a multiplexer, which comprises j inputs to the multiplexer and the first array. Includes k outputs to the routing mechanism inside the array, the routing mechanism outside the second array includes a multiplexer, and the multiplexer contains m inputs from the routing mechanism inside the second array. And n outputs from the multiplexer.</p><p> The first array and the second array are two-dimensional and have a first direction and a second direction, respectively, in both directions of the surface of the first semiconductor die and the second semiconductor die. The routing mechanism outside the first array comprises a multiplexer that is substantially coplanar with the surface of the multiplexer, and the multiplexer corresponds to j inputs to the multiplexer and the first direction. A routing mechanism outside the second array that includes k outputs to the routing mechanism inside the array and k outputs to the routing mechanism inside the first array corresponding to the second direction. Includes a multiplexer, which includes m inputs from the routing mechanism inside the second array corresponding to the first direction and inside the second array corresponding to the second direction. It may include m inputs from the routing mechanism and n outputs from the multiplexer.</p><p> The electrical signal was spatially repeated for at least the first timing mechanism that generated the clock signal and for multiple inputs to the routing mechanism inside the first array within at least one period of the clock signal. It may include a tying mechanism that converts the electrical signal into an electrical signal and spatially repeats the electrical signal for multiple transmit pads in the first array.</p><p> The first array is one-dimensional, and the spatially repeated electrical signal may be spatially repeated r times with respect to the s transmit pads of the first array.</p><p> The first array is two-dimensional with a first direction and a second direction, both directions being substantially coplanar with the surface of the first semiconductor die and spatially repeating. The electric signal is s in the first direction.₁R for 1 transmit pad₁Iteratively and spatially repeated, the s in the second direction₂R for 1 transmit pad₂It may be repeated spatially.</p><p> A tiling release mechanism that converts a spatially repeated electrical signal into the electrical signal within at least one period of the clock signal, wherein the spatially repeated electrical signal is the second array. It may further include an untiling mechanism that is spatially repeated for multiple outputs from the internal routing mechanism and spatially repeated for the multiple receive pads of the second array.</p><p> The second array is one-dimensional, and the spatially repeated electrical signal may be spatially repeated r times with respect to the s receiving pads of the second array.</p><p> The second array is two-dimensional with a first direction and a second direction, both directions being substantially coplanar with the surface of the second semiconductor die and spatially repeating. The electrical signal is s in the first direction.₁R for 1 receiving pad₁It is spatially repeated, and the spatially repeated electrical signal is s in the second direction.₂R for 1 receiving pad₂It may be repeated spatially.</p>

<p> According to the method and apparatus according to the present invention, capacitive chip-to-chip communication can be smoothly performed.</p>

(Detailed explanation) The following description is presented to allow any person skilled in the art to create and utilize the invention and is provided in the context of specific uses and requirements. Various modifications of the disclosed embodiments will be readily appreciated by those skilled in the art, and the general principles set forth herein do not deviate from the intent and scope of the invention of other embodiments and uses. Can be applied to. As such, the invention is not intended to be limited to the embodiments shown, and fits into a maximum range consistent with the principles and features described herein. (Alignment correction using the routing mechanism inside the array) FIG. 1 shows Embodiment 100 of the present invention that facilitates capacitive communication of data 108 in the form of electrical signals between a first semiconductor die 110 and a second semiconductor die 112. The routing mechanism 114 inside the first array 116 of the first semiconductor die 110 selectively routes electrical signals to at least one transmit pad 118. The first array 116 includes a plurality of transmission pads. The electrical signal is capacitively coupled to at least one receive pad 122 of the second array 124 of the second semiconductor die 112 via these transmit pads. The second array 124 includes a plurality of receiving pads. The electrical signal is selectively routed from the receive pad 122 using the internal routing mechanism 128 of the second array 124. The transmission pad 118 and the reception pad 122 are selected based on the alignment of the first semiconductor die 110 and the second semiconductor die 112. In this way, corrections for misalignment of the first semiconductor die 110 and the second semiconductor die 112 can be made, thereby facilitating capacitive coupling communication.

To facilitate communication of high bandwidth, low latency capacitive coupling between the first semiconductor die 110 and the second semiconductor die 112, the routing mechanism 114 inside the first array 116 and The routing mechanism 128 inside the second array 124 can be pipelined so that the electrical signals are routed in parallel. In embodiments of the present invention, the routing mechanism 114 inside the first array 116 and the routing mechanism 128 inside the second array 124 include a barrel shifter. Other routing mechanisms are possible, such as matrix-type addressing in first array 116 and second array 124, or routing of electrical signals using addressing with a look-up table using a bus such as I2C. is there.

1 coplanar with the surface of the first semiconductor die 110 or the second semiconductor die 112 that can be corrected using the internal routing mechanism 114 of the first array 116 and the internal routing mechanism 128 of the second array 124. Misalignment Dx in dimension is often limited. Similarly, misalignments Dx and Dy in two orthogonal dimensions that are coplanar with the surface of the first semiconductor die 110 or the second semiconductor die 112 that can be corrected are also often limited. These limitations are based on the permissible complexity inside the first array 116 and the second array 124. Compensation for larger misalignments requires an increase in the number of wires in the first and second arrays 124 and the number of leads connected to the first and second arrays 124. .. Also, the additional complexity within the first array 116 and the second array 124 can increase the latency associated with routing unwanted electrical signals. Misalignment in the two orthogonal dimensions is described below as an example.

Transmission pad width W in the first direction_T1130, transmit pad width W in the second direction_T2132, receive pad width W in the first direction_R1134, receive pad width W in the second direction_R2136, first pitch 138 on the first array 116 (defined as the distance from the center of the transmit pad to the center of the adjacent transmit pad in the first direction), (from the center of the transmit pad to the second direction) The first array 116 has a second pitch 142 (defined as the distance to the center of the adjacent transmit pad), and the second array 124 has a first pitch P.₁138 and second pitch P₂In the present invention having 142, the first pitch P₁138 and second pitch P₂142 determines the correctable misarrayment.

Receive pad width W_R1134 is the transmission pad width W_T1Less than 130, receive pad width W_R2136 is the transmission pad width W_T2If less than 132, first pitch P₁More than half of 138 or second pitch P₂Misalignment of more than half of 142 results in loss of coupled electrical signals at receive pad 122. In this case, therefore, sufficient communication is | Dx | &lt;&lt; 0.5P₁138 and | Dy | &lt;&lt; 0.5P₂Requires alignment like 142. In addition, 0.5P₁138 and 0.5P₂142 is the theoretical upper limit. Circuit detection thresholds and data rates can provide more precise alignment criteria.

Pads in the first array 116, the second array 124, and other embodiments of the invention may include so-called full size pads and so-called micropads. A full size pad has a larger pad width to pad pitch ratio (eg, transmit pad width W divided by the first pitch 138 in the first direction of the first array 116)._T1130). The spacing between full size pads, such as guard band 140, and the spacing between micropads may be the same (eg, 1 μm). The guard band 140 has a transmission pad width W from the first pad pitch 138._T1It is 130 minus.

The choice of full size pad or micropad presents a trade-off between capacitive communication signal strength, crosstalk and parasitic coupling. Full size pads can be used on both the first semiconductor die 110 and the second semiconductor die 112. The micropad can also be used in either the first semiconductor die 110 or the second semiconductor die 112. Alternatively, the micropad can be used in both the first semiconductor die 110 and the second semiconductor die 112. Alternatively, a full size pad and micropad combination can be used on both the first semiconductor die 110, the second semiconductor die 112 or the first semiconductor die 110 and the second semiconductor die 112. In addition, the micropad subsections in the first array 116 or the second array 124 may be connected to a group. (Alignment correction using a routing mechanism outside the array) FIG. 2 shows embodiment 200 of the present invention that facilitates capacitive communication between the first semiconductor die 110 and the second semiconductor die 112 by correcting for coarser misalignment. The external routing mechanism 210 of the first array 116 of the first semiconductor die 110 selectively routes electrical signals to the internal routing mechanism 114 of the first array 116 and thus to at least one transmit pad 118. .. Note that FIG. 2 and figures of other embodiments of the present invention are for illustration purposes only. Thus, the routing mechanism 114 inside the first array 116 can be next to the pad of the first array 116 that is integrated into the layer containing the pad or the layer below the pad.

In a variant of this embodiment, the first array 116 is one-dimensional, and the routing mechanism 210 outside the first array 116 has n inputs to the multiplexer (not shown) and the routing inside the first array 116. It includes a multiplexer with m output for mechanism 114, where n m. In a variant of this embodiment, the second array 124 has n outputs.

In another variant of this embodiment, the first array 116 has two orthogonal dimensions coplanar with the surface of the first semiconductor die 110, and the external routing mechanism 210 of the first array 116 N inputs to the multiplexer (not shown) and m outputs to the internal routing mechanism 114 of the first array 116 corresponding to the first direction, and the internal routing mechanism of the first array 116 corresponding to the second direction. Includes a multiplexer (not shown) with m output (not shown) for 114, where n m. In this variant of this embodiment, the second array 124 has n outputs.

FIG. 3 shows an embodiment 220 of the present invention that facilitates capacitive communication between the first semiconductor die 110 and the second semiconductor die 112 by correcting for coarser misalignment. In this embodiment, the external routing mechanism 230 of the second array 124 of the second semiconductor die 112 receives electrical signals from the internal routing mechanism 128 of the second array 124 and thus from at least one receiving pad 122. Selectively route.

In a variant of this embodiment, the second array 124 is one-dimensional, and the routing mechanism 230 outside the second array 124 is the m input from the routing mechanism 128 inside the second array 124 to the multiplexer ( Includes a multiplexer with (not shown) and n outputs (not shown), where m n. In a variant of this embodiment, the first array 116 has n inputs.

In another variant of this embodiment, the second array 124 has two orthogonal dimensions coplanar with the surface of the second semiconductor die 112, and the external routing mechanism 230 of the second array 124 M inputs from the internal routing mechanism 128 of the second array 124 corresponding to the first direction to the multiplexer (not shown), internal routing mechanism 128 of the second array 124 corresponding to the second direction from the multiplexer to the multiplexer Includes a multiplexer with m inputs (not shown), as well as n outputs (not shown), where m n. In this variant of this embodiment, the first array 116 has n inputs.

FIG. 4 shows embodiment 240 of the present invention that facilitates capacitive communication between the first semiconductor die 110 and the second semiconductor die 112 by correcting for coarser misalignment. The external routing mechanism 210 of the first array 116 of the first semiconductor die 110 selectively routes electrical signals to the internal routing mechanism 114 of the first array 116 and thus to at least one transmit pad 118. .. The external routing mechanism 230 of the second array 124 of the second semiconductor die 112 selectively routes electrical signals from the internal routing mechanism 128 of the second array 124 and thus from at least one receive pad 122. ..

In a variant of this embodiment, the first array 116 is one-dimensional, and the routing mechanism 210 outside the first array 116 has a j-output to the multiplexer (not shown) and the routing inside the first array 116. Includes a multiplexer with k output (not shown) for mechanism 114, where j k. Further, in this variant of this embodiment, the second array 124 is one-dimensional, and the routing mechanism 230 outside the second array 124 is from the routing mechanism 128 inside the second array 124 to the multiplexer. Includes a multiplexer with m inputs (not shown) and n outputs (not shown), where m n. In a further variant, j = n and k = m.

In another variant of this embodiment, the first array 116 has two orthogonal dimensions coplanar with the surface of the first semiconductor die 110, and the external routing mechanism 210 of the first array 116 The j-output to the multiplexer (not shown), the k-output to the internal routing mechanism 114 of the first array 116 corresponding to the first direction (not shown), and the first array 116 corresponding to the second direction. Includes a multiplexer with k output (not shown) for the internal routing mechanism 114, where j k. Further, in this variant, the second array 124 has two orthogonal dimensions coplanar with the surface of the second semiconductor die 112, and the external routing mechanism 230 of the second array 124 is the first. M input from the routing mechanism 128 inside the second array 124 corresponding to the direction to the multiplexer (not shown), m input from the routing mechanism 128 inside the second array 124 corresponding to the second direction to the multiplexer (not shown) Not included), and includes a multiplexer with n outputs (not shown), where m n. In a further variant, j = n and k = m.

In each of the embodiments of FIGS. 2 and 4, the first array 116 has two orthogonal dimensions coplanar with the surface of the first semiconductor die 110, and the routing mechanism 114 inside the first array 116 , L output for the first array 116 in the first direction, and l output for the first array in the second direction, where l m.

In each of the embodiments of FIGS. 3 and 4, the second array 124 has two orthogonal dimensions coplanar with the surface of the second semiconductor die 112, and the routing mechanism 128 inside the second array 124 , P inputs from the second array 124 in the first direction, and p inputs from the second array 124 in the second direction, where p k. In a further variant, l = p and m = k.

The external routing mechanism 210 of the first array 116, the external routing mechanism 230 of the second array 124, or the external routing mechanism 210 of the first array 116 and the external routing mechanism 230 of the second array 124. Capacitive coupling between the first semiconductor die 110 and the second semiconductor die 112 by using to correct the coarse misalignment between the first semiconductor die 110 and the second semiconductor die 112. Communication is smooth. (Alignment correction using control loop) FIG. 5 illustrates a structure 500 that determines alignment between a first semiconductor die (not shown) and a second semiconductor die (not shown). The first semiconductor die includes a plurality of conductive elements 510 with a first spacing 512. The second semiconductor die includes a plurality of conductive elements 514 with a second spacing 516 different from the first spacing 512. The vernier alignment structure is formed by an overlap 518 of the conductive element 510 and the conductive element 514.

When the conductive element 510 of the first semiconductor die is selectively charged using a charging mechanism (not shown), the charge has an overlap 518 between the conductive element 510 and the conductive element 514. In the case, it is guided to one or more conductive elements 514 of the second semiconductor die. As a result, the electrical signal induced in one or more conductive elements 514 can be amplified using an amplification mechanism (not shown) and analyzed using an analysis mechanism (not shown), the first semiconductor. Determine the alignment between the die and the second semiconductor die.

FIG. 6 shows embodiment 600 of the present invention in which misalignment correction is implemented as a closed path control system. The first semiconductor die 610 includes a first vernier alignment structure 612 in the first direction and a second vernier alignment structure 614 in the second orthogonal direction. The first vernier alignment structure 612 and the second vernier alignment structure 614 are used to determine the alignment between the first semiconductor die 610 and the second semiconductor die 616 described in structure 500 of FIG. Will be done. The measured alignment is transmitted to the control system 618, which may be included in the first semiconductor die 610 or outside the first semiconductor die 610.

Based on the chip alignment measured, the control system uses a routing mechanism 622 for at least one of the multiple transmit pads of the first array 624 of the first semiconductor die 610 to generate data 620 in the form of an electrical signal. Determine proper routing. In a variant of this embodiment, the closed path control system can also be used to control the routing of electronic signals using the routing mechanism 626 from the second array 628 of the second semiconductor die 616. In another variant of this embodiment, the closed path control system may route electrical signals from the second array 628 to the first array 624 based on alignment as well.

FIG. 6 shows the routing of electrical signals in this embodiment, which has a routing mechanism 622 inside the first array 624 as used in embodiment 100 shown in FIG. As mentioned above, in another embodiment, the electrical signal can be routed using the routing mechanism 626 inside the second array 628 as used in embodiment 100 shown in FIG. Other variations of this embodiment, such as those used in embodiment 200 shown in FIG. 2, used in embodiment 220 shown in FIG. 3, or used in embodiment 240 shown in FIG. , The external routing mechanism of the first array 624 or the second array 628 can be used to route electrical signals in a closed routing system.

In a modification of this embodiment, the alignment determination is performed continuously. In another variant of this embodiment, the alignment determination is performed periodically at intervals divided by a certain interval, where the intervals are either substantially fixed or substantially variable. is there.

This closed path control system allows for the correction of misalignments associated with the effects of thermal expansion and mechanical vibrations that can fluctuate over time. Thus, the misalignment between the first semiconductor die 610 and the second semiconductor die 616 can be accurate, thereby facilitating capacitive coupling communication. (Alignment correction using tiling and untiling) FIG. 7 shows the spatial tiling of electrical signals corresponding to data 108 (shown in FIG. 1) on multiple interconnect pads of an array in an embodiment of the invention that allows for greater misalignment correction. Shows 700. The electrical signals 710, 712, 714, 716, 718, 720, 722, 724 and 726 are spatially repeated on multiple interconnect pads during at least one cycle of the clock generated by the timing mechanism. .. While FIG. 7 shows tiling in two directions in a two-dimensional array, tiling can also be performed in one direction in the two-dimensional array or in one direction in the one-dimensional array. The spatial tiling 700 shown in Figure 7 interconnects up to ± 1.5 using three wires (in contrast to the nine wires needed to facilitate this amount of misalignment correction). Smooth correction of misalignment up to pad width (not shown).

In a variant of this embodiment, the tiling mechanism can be included in embodiments 100, 200 or 240 shown in FIGS. 1, 2 and 4, respectively, inside the first array 116 of the first semiconductor die 110. The electrical signal is spatially repeated at the input to the routing mechanism 114 of the clock, and thus the electrical signal is spatially repeated at multiple transmit pads during at least one cycle of the clock. In a one-dimensional variant of this embodiment, the electrical signal is repeated r times in the s transmit pad. In a two-dimensional variant of this embodiment, the electrical signal is s in the first direction.₁In the transmit pad, r₁Repeated times, s in the second direction₂In the transmit pad, r₂Repeated times.

In another variant of this embodiment, the tiling release mechanism may be included in embodiments 100, 220 or 240 shown in FIGS. 1, 3 and 4, respectively, in a second array of second semiconductor dies 112. The electrical signal is spatially repeated at multiple outputs from 124 internal routing mechanisms 128, thus spatially repeating at multiple receiving pads during at least one cycle of the clock. In a one-dimensional variant of this embodiment, the electrical signal is repeated r times in the s receiving pad. In a two-dimensional variant of this embodiment, the electrical signal is s in the first direction.₁In the receiving pad, r₁Repeated times, s in the second direction₂In the receiving pad, r₂Repeated times.

FIG. 8 shows an electrical circuit 800 with a barrel shifter that implements cyclically spatial tiling in one direction of this embodiment. Similar electrical circuits can also be used to implement tiling release embodiments. FIG. 9 shows such a cyclic tiling 900 of block 920 of array 910. Returning to FIG. 8, three wires 810, 812 and 814 can be used as examples. Wire 810 for the first electrical signal 816 during at least one cycle of the clock is more than once (one is shown) to allow further shifting of the array of interconnect pads 818. It repeats. The first electrical signal 816 is routed to the appropriate interconnect pad of the array 818 using a routing mechanism such as the multiplexer 824, thereby correcting for greater misalignment (up to ± 1.5 interconnect pad width (up to ± 1.5 interconnect pad width). (Not shown)) is possible. The same is true for the third electrical signal 822 and the second electrical signal 820 on wires 812 and 814.

Without electrical circuit 800, the routing mechanism 210 (shown in FIGS. 2 and 4) or the routing mechanism 230 outside the array of interconnect pads 818 (shown in FIGS. 3 and 4) is in the array of interconnect pads 818. Misalignment of half the width of the interconnect pad can be corrected unless it is further used to shift the electrical signal. The electrical circuit 800 does not require some additional complexity inside the array 818, such as multiplexing, nor does it require some additional reeds for the array 818.

The following description of embodiments of the present invention has been presented for purposes of illustration and illustration only. They are neither inclusive nor intended to limit the invention to the disclosed form. Therefore, many modifications and modifications will be understood by those skilled in the art. Moreover, the above disclosure is not intended to limit the invention. The scope of the present invention is defined by the appended claims. It will be understood by those skilled in the art that from the description of specific preferred embodiments of the present invention, an equivalent range can be implemented based on the description of the present invention and common general technical knowledge. The patents, patent applications and documents cited herein are to be incorporated by reference in their content as they are specifically described herein. Understood. (wrap up) One embodiment of the present invention provides a system that facilitates capacitive chip-to-chip communication. During operation, the system first determines the alignment between the first semiconductor die and the second semiconductor die. The electrical signal is then selectively routed to at least one of the plurality of interconnect pads based on the alignment, thereby communicating between the first semiconductor die and the second semiconductor die. To facilitate. The plurality of interconnect pads may include a transmit pad, a receive pad and a transmit / receive pad. Alignment can be determined by the time divided by continuous or at certain intervals, where the intervals are fixed or variable. Some variations of this embodiment are provided.

<figref num="1">FIG. 1 shows a first array of transmit pads that communicate with a second semiconductor die that has a routing mechanism inside a second array of receive pads according to an embodiment of the invention. Indicates a semiconductor die.</figref><figref num="2">FIG. 2 shows a first semiconductor die having a routing mechanism outside the first array of transmit pads that communicates with a second semiconductor die having a second array of receive pads in an embodiment of the present invention.</figref><figref num="3">FIG. 3 shows a first semiconductor die having a first array of transmit pads communicating with a second semiconductor die having a routing mechanism outside the second array of receive pads in an embodiment of the present invention.</figref><figref num="4">FIG. 4 shows a first array of transmit pads that communicate with a second semiconductor die that has a routing mechanism outside the second array of receive pads according to an embodiment of the present invention. Indicates a semiconductor die.</figref><figref num="5">FIG. 5 shows a structure for determining the alignment between the first semiconductor die and the second semiconductor die.</figref><figref num="6">FIG. 6 determines the alignment between the first semiconductor die and the second semiconductor die in the embodiment of the present invention and routes the electrical signal from the second array to the first array using a routing mechanism. The control loop to be used is shown.</figref><figref num="7">FIG. 7 shows the spatial tiling of the electrical signal corresponding to the data in the embodiment of the present invention.</figref><figref num="8">FIG. 8 shows an electrical circuit that implements spatial tiling of electrical signals in an embodiment of the present invention.</figref><figref num="9">FIG. 9 shows the spatial tiling of the electrical signal corresponding to the data in the embodiment of the present invention.</figref>

Code description

108 data 110 1st semiconductor die 112 Second semiconductor die 114 Routing mechanism 116 First array 118 transmit pad 122 Receive pad 124 Second array 128 Routing mechanism 130 Transmission pad width W in the first direction_T1132 Second direction transmit pad width W_T2134 First-direction receive pad width W_R1136 Receive pad width W in the second direction_R2138 First pitch 140 guard band 142 Second pitch