Semiconductor storage device

The present invention relates to, for example, a NAND flash memory using EEPROM, and more particularly to a semiconductor storage device capable of storing multi-valued data in one memory cell.

In the NAND flash memory, a plurality of memory cells arranged in the column direction are connected in series to form a NAND cell, and each NAND cell is connected to a corresponding bit line via a selection gate. Each bit line is connected to a latch circuit that latches write data and read data. All or half of the plurality of cells arranged in the low direction are selected at the same time, and all or half of the cells selected at the same time are collectively written or read. A plurality of NAND cells arranged in the low direction form a block, and an erasing operation is executed for each block. The erase operation sets the threshold voltage of the memory cell to a negative value. The write operation sets the threshold voltage positive by injecting electrons into the memory cell (see, for example, Patent Document 1).

By the way, in the NAND cell, the memory cells are connected in series. Therefore, during the read operation, the non-selected cell needs to be in the ON state, and a voltage (Vread) higher than the threshold voltage is applied to the gate electrode of the non-selected cell. Therefore, in the write operation, the threshold voltage set in the cell must not exceed Vread, and in the write sequence, the program and program verify read are repeated bit by bit, and the threshold distribution is controlled so as not to exceed Vread. doing.

Recently, with the increase in memory capacity, multi-valued memory that stores 2 bits or more in one cell has been developed. For example, in order to store 2 bits in one cell, it is necessary to set four threshold distributions within a range that does not exceed Vread. Therefore, it is necessary to control the threshold distribution narrower than when storing one bit or two threshold distributions in one cell. Furthermore, in order to store 3 bits and 4 bits in one cell, 8 and 16 threshold distributions must be set. Therefore, it is necessary to make the distribution width of the threshold voltage per one very narrow. As described above, in order to narrow the distribution width of the threshold voltage, it is necessary to strictly repeat the program and verify, which causes a problem that the writing speed becomes slow.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2004-192789</text></patcit>

<p> The present invention is to provide a semiconductor storage device capable of increasing the writing speed.</p>

<p> Aspects of the semiconductor storage device of the present invention are<u style="single">1st conductive type</u>A semiconductor substrate, a memory cell array connected to a word line and a plurality of memory cells connected in series connected in series are arranged in a matrix, a selection transistor for selecting the word line, and input data. A control circuit that controls the potentials of the word line and the bit line and controls the writing, reading, and erasing operations of data to the memory cell is provided, and the selection transistor is the semiconductor substrate.<u style="single">The first conductive type formed in the well of the second conductive type opposite to the first conductive type formed inside.</u>Formed on wells, at least from said memory cells<u style="single">The lower limit is negative</u>During the read operation to read the threshold voltage, the above<u style="single">1st conductive type</u>The well is supplied with the first negative voltage, the selected word line is supplied with the first voltage (first voltage first negative voltage), and the non-selected word line is supplied with the second voltage.<u style="single">, 0V is applied to the second conductive type well and the semiconductor substrate.</u>It is characterized by that.</p>

<p> According to the present invention, it is possible to provide a semiconductor storage device capable of increasing the writing speed.</p>

FIGS. 1 (a) and 1 (b) show the relationship between the conventional and the threshold voltage of the present embodiment. Figures 1 (a) and 1 (b) show the case of storing 2-bit, 4-value data.

In this embodiment, as shown in FIG. 1 (b), for example, a plurality of threshold voltages are set on the negative side of 0 V or less. In this way, by setting a plurality of threshold voltages on the negative side as well, the threshold distribution width per one can be widened without changing the Vread. Therefore, the number of programs and verifications can be reduced, and the writing speed can be increased.

In order to set such a threshold voltage, the following configuration is required. That is, since the gate electrode of the selected cell has a negative voltage, it is necessary to set the word line to a negative potential. Therefore, a high withstand voltage, for example, an N-channel MOS transistor constituting a low decoder is formed in a P-type well (referred to as P-well) region, and a negative voltage is supplied to this P-well region. At this time, Vread (for example, 5V) is supplied to the non-selected word line in the selected block to make the non-selected cell conductive.

In addition, writing methods called RLSB (Revised Local Self Boost) and REASB (Revised Erased Local Self Boost) have been devised so that erroneous writing does not occur in "1" writing (non-writing). In this writing method, among the NAND cells, the channel area of the cell in the vicinity of the writing cell is set to off, and the potential of the channel area is easily booted. Therefore, the ground potential is supplied to the word line. However, in the case of the present embodiment, when the cell is an erased cell, the threshold voltage is deeper on the negative side than in the conventional case, as shown by the data 0 in FIG. 1 (b). Therefore, it is necessary to supply a negative potential to the word line in order to turn off the channel region of the cell in the vicinity of the write cell.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows the configuration of the semiconductor storage device according to the present embodiment, specifically, for example, a NAND flash memory that stores four-value (2-bit) data.

The memory cell array 1 includes a plurality of bit lines, a plurality of word lines, and a common source line. For example, an electrically rewritable memory cell composed of an EEPROM cell is arranged in a matrix. A bit control circuit 2 for controlling a bit line and a word line control circuit 6 are connected to the memory cell array 1.

The bit line control circuit 2 reads the data of the memory cell in the memory cell array 1 via the bit line, detects the state of the memory cell in the memory cell array 1 via the bit line, and stores the memory via the bit line. A write control voltage is applied to the memory cells in the cell array 1 to write to the memory cells. A column decoder 3 and a data input / output buffer 4 are connected to the bit line control circuit 2. The data storage circuit in the bit line control circuit 2 is selected by the column decoder 3. The data of the memory cell read into the data storage circuit is output from the data input / output terminal 5 to the outside via the data input / output buffer 4.

Further, the write data input to the data input / output terminal 5 from the outside is input to the data storage circuit selected by the column decoder 3 via the data input / output buffer 4.

The word line control circuit 6 includes a low decoder 6-1. The word line control circuit 6 selects a word line in the memory cell array 1 via the low decoder 6-1 and applies a voltage required for reading, writing, or erasing the selected word line.

The memory cell array 1, the bit line control circuit 2, the column decoder 3, the data input / output buffer 4, and the word line control circuit 6 are connected to the control signal and control voltage generation circuit 7, and are connected to the control signal and control voltage generation circuit 7. Be controlled. The control signal and the control voltage generation circuit 7 are connected to the control signal input terminal 8 and are controlled by a control signal input from the outside via the control signal input terminal 8. The control signal and control voltage generation circuit 7 includes a negative voltage generation circuit 7-1 described later. This negative voltage generation circuit 7-1 generates a negative voltage when writing and reading data.

The bit line control circuit 2, the column decoder 3, the word line control circuit 6, the control signal and the control voltage generation circuit 7 constitute a write circuit and a read circuit.

FIG. 3 shows the configuration of the memory cell array 1 and the bit line control circuit 2 shown in FIG. A plurality of NAND cells are arranged in the memory cell array 1. One NAND cell is composed of a memory cell MC composed of, for example, 32 EEPROMs connected in series, and selection gates S1 and S2. The selection gate S2 is connected to the bit line BL0e, and the selection gate S1 is connected to the source line SRC. The control gates of the memory cells MC arranged in each row are commonly connected to the word lines WL0 to WL29, WL30, and WL31. Further, the selection gate S2 is commonly connected to the select line SGD, and the selection gate S1 is commonly connected to the select line SGS.

The bit line control circuit 2 has a plurality of data storage circuits 10. A pair of bit lines (BL0e, BL0o), (BL1e, BL1o) ... (BLie, BLio), (BL8ke, BL8ko) are connected to each data storage circuit 10.

The memory cell array 1 contains a plurality of blocks as shown by a broken line. Each block is composed of a plurality of NAND cells, and data is erased in units of this block, for example. Further, the erasing operation is performed simultaneously for the two bit lines connected to the data storage circuit 10.

In addition, a plurality of memory cells (memory cells in the range surrounded by a broken line) arranged every other bit line and connected to one word line constitute one sector. Data is written and read for each sector.

Of the two bit lines (BLie, BLio) connected to the data storage circuit 10 during read operation, program verification operation, and program operation, the address signal (YA0, YA1 ... YAi ..) supplied from the outside is supplied. One bit line is selected according to .YA8k). In addition, one word line is selected according to the external address.

FIGS. 4 (a) and 4 (b) show cross-sectional views of the memory cell and the selected transistor. Figure 4 (a) shows a memory cell. An n-type diffusion layer 42 as a source and drain of a memory cell is formed on the substrate 51 (P-well region 55 described later). A floating gate (FG) 44 is formed on the P-well region 55 via a gate insulating film 43, and a control gate (CG) 46 is formed on the floating gate 44 via an insulating film 45. .. Figure 4 (b) shows the selection gate. An n-type diffusion layer 47 as a source and a drain is formed in the P-well region 55. A control gate 49 is formed on the P-well region 55 via a gate insulating film 48.

FIG. 5 shows a cross-sectional view of the semiconductor storage device. For example, N-type wells (hereinafter referred to as N-wells) regions 52, 53, 54, 56 and P-well regions 57 are formed in the P-type semiconductor substrate 51. A P-well region 55 is formed in the N-well region 52, and a low-voltage N-channel MOS transistor LVNTr constituting the memory cell array 1 is formed in the P-well region 55. Further, a low-voltage P-channel MOS transistor LVPTr and a low-voltage N-channel MOS transistor LVNTr constituting the data storage circuit 10 are formed in the N-well region 53 and the P-well region 57.

A P-well region 58 is formed in the N-well region 56, and a high-voltage N-channel MOS transistor HVNTr constituting the low decoder 6-1 is formed in the P-well region 58. Further, in the N-well region 54, for example, a high-voltage P-channel MOS transistor HVPTr constituting a word line drive circuit or the like is formed. The high-voltage transistors HVNTr and HVPTr have, for example, a thicker gate insulating film than the low-voltage transistors LVNTr and LVPTr.

FIG. 6 shows the potential supplied to each well during erasing, programming, and reading. A negative potential, for example -2V, is supplied to the P-well 58 in which the N-channel MOS transistor constituting the low decoder 6-1 is formed during programming and data reading.

FIG. 7 is a circuit diagram showing an example of the data storage circuit 10 shown in FIG.

The data storage circuit 10 has a primary data cache (PDC), a secondary data cache (SDC), a dynamic data cache (DDC), and a temporary data cache (TDC). SDCs, PDCs, and DDCs hold input data at the time of writing, hold read data at the time of reading, temporarily hold data at the time of verification, and are used for manipulating internal data when storing multi-valued data. The TDC amplifies and temporarily holds bit line data when reading data, and is used for manipulating internal data when storing multivalued data.

The SDC is composed of clocked inverter circuits 61a and 61b and transistors 61c and 61d that form a latch circuit. The transistor 61c is connected between the input end of the clocked inverter circuit 61a and the input end of the clocked inverter circuit 61b. The signal EQ2 is supplied to the gate of the transistor 61c. The transistor 61d is connected between the output end of the clocked inverter circuit 61b and the ground. The signal PRST is supplied to the gate of the transistor 61d. Node N2a of the SDC is connected to the input / output data line IO via the column selection transistor 61e, and node N2b is connected to the input / output data line IOn via the column selection transistor 61f. A column selection signal CSLi is supplied to the gates of these transistors 61e and 61f. The node N2a of the SDC is connected to the node N1a of the PDC via transistors 61g and 61h. The signal BLC2 is supplied to the gate of the transistor 61g, and the signal BLC1 is supplied to the gate of the transistor 61h.

The PDC is composed of clocked inverter circuits 61i, 61j and transistors 61k. The transistor 61k is connected between the input end of the clocked inverter circuit 61i and the input end of the clocked inverter circuit 61j. The signal EQ1 is supplied to the gate of this transistor 61k. Node N1b of the PDC is connected to the gate of transistor 61l. One end of the current passage of the transistor 61l is grounded via the transistor 61m. The signal CHK1 is supplied to the gate of this transistor 61 m. Further, the other end of the current passage of the transistor 61l is connected to one end of the current passage of the transistors 61n and 61o constituting the transfer gate. The signal CHK2n is supplied to the gate of the transistor 61n. Further, the gate of the transistor 61o is connected to the connection node N3 of the transistors 61g and 61h. A signal COMi is supplied to the other end of the current passage of the transistors 61n and 61o. This signal COMi is a signal common to all the data storage circuits 10, and is a signal indicating whether or not the verification of all the data storage circuits 10 is completed. That is, as will be described later, when the verification is completed, the node N1b of the PDC becomes low level. In this state, if the signals CHK1 and CHK2n are set to high level, the signal COMi is set to high level when the verification is completed.

Further, the TDC is composed of, for example, a MOS capacitor 61p. The capacitor 61p is connected between the connection node N3 of the transistors 61g and 61h and the ground. Further, a DDC is connected to the connection node N3 via the transistor 61q. The signal REG is supplied to the gate of the transistor 61q.

The DDC is composed of transistors 61r and 61s. The signal VREG is supplied to one end of the current passage of the transistor 61r, and the other end is connected to the current passage of the transistor 61q. The gate of the transistor 61r is connected to the node N1a of the PDC via the transistor 61s. The signal DTG is supplied to the gate of the transistor 61s.

Further, one end of the current passage of the transistors 61t and 61u is connected to the connection node N3. A signal VPRE is supplied to the other end of the current passage of the transistor 61u, and a signal BLPRE is supplied to the gate. The signal BLCLAMP is supplied to the gate of the transistor 61t. The other end of the current passage of the transistor 61t is connected to one end of the bit line BLo via the transistor 61v, and is connected to one end of the bit line BLe via the transistor 61w. The other end of the bit wire BLo is connected to one end of the current path of the transistor 61x. The signal BlASo is supplied to the gate of this transistor 61x. The other end of the bit wire BLe is connected to one end of the current passage of the transistor 61y. The signal BlASe is supplied to the gate of the transistor 61y. A signal BLCRL is supplied to the other end of the current passages of these transistors 61x and 61y. Transistors 61x and 61y are turned on complementarily with transistors 61v and 61w according to the signals BlASo and BlASe to supply the potential of the signal BLCRL to the unselected bit lines.

Each of the above signals and voltages is generated by the control signal and control voltage generation circuit 7 shown in FIG. 2, and the following operations are controlled based on the control of the control signal and control voltage generation circuit 7.

FIG. 8 shows an example of the negative voltage generation circuit 7-1. The negative voltage generation circuit 7-1 is composed of, for example, a four-phase pump circuit PMP, a detection circuit DT, a control unit 7d, and an oscillation circuit 7e. The pump circuit PMP is composed of, for example, a plurality of P-channel MOS transistors MOSFETs and a plurality of capacitors Cp. Clock signals CLK1 to CLK4 are supplied to one end of each capacitor Cp. These clock signals CLK1 to CLK4 sequentially turn on the MOSFET and generate a negative voltage.

The detection circuit DT is connected to the output end of the pump circuit PMP. This detection circuit DT is composed of a constant current source 7a, a resistor 7b, and a differential amplifier 7c. The constant current source 7a and the resistor 7b are connected in series between the node to which the power supply VDD is supplied and the output end of the pump circuit PMP. One input end of the differential amplifier 7c is connected to the connection node of the constant current source 7a and the resistor 7b, and the reference voltage Vref is supplied to the other end. This reference voltage Vref is a voltage of about 1 V generated by, for example, a bandgap reference circuit. This detection circuit DT detects the output voltage of the pump circuit PMP based on the reference voltage Vref. This detection output signal is supplied to the control unit 7d. Control unit<u style="single">7d</u>Controls the oscillator circuit 7e according to the detection output signal. The oscillation circuit 7e is a control unit.<u style="single">7d</u>Oscillates or stops under the control of. In this way, the pump circuit PMP produces a constant negative voltage.

Further, the resistor 7b constitutes the trimming circuit 7f. The trimming circuit 7f switches the level of the negative voltage output from the pump circuit PMP by changing the resistance value of the resistor 7b according to the trimming signal TM. The trimming signal TM is generated at the time of reading data and at the time of program verification by, for example, the control signal and the control voltage generation circuit 7. Therefore, the negative voltage generation circuit 7-1 generates various levels of negative voltage when reading data and verifying the program.

Since this memory is a multi-valued memory, 2-bit data can be stored in one cell. 2-bit switching is performed by the address (1st page, 2nd page).

FIGS. 9 (a), 9 (b) and 9 (c) show the relationship between the data in the memory cell and the threshold value in the memory cell. As shown in FIG. 9 (c), when the erase operation is performed, the data in the memory cell becomes 0. Data 0 is a negative voltage of 0V or less. As will be described later, in order to apply the RLSB and REASB writing methods, verification is performed by the verify voltage z after erasing. When the threshold voltage is equal to or less than the verify voltage z, the writing operation is performed until the threshold voltage becomes the verify voltage z.

As shown in FIG. 9A, the data in the memory cell becomes data 0 and data 2 by writing on the first page. Further, as shown in FIG. 9B, after writing on the second page, the data in the memory cell becomes data 0, 1, 2, 3. In the present embodiment, the data in the memory cell is defined from the lower threshold voltage to the higher threshold voltage.

FIG. 10 schematically shows the writing order in this embodiment. As shown in FIG. 10, a write operation is performed page by page from a memory cell close to the source line in the block. In this case, in order to eliminate the influence of the threshold voltage of the adjacent memory cell written earlier, the writing order to the memory cell is defined as shown in FIG.

FIG. 11 shows a transfer gate that forms part of the low decoder 6-1. This transfer gate is composed of the plurality of N-channel MOS transistors HVNTr described above. Voltages SGS_DRV, CG0 to CG31, and SGD_DRV are supplied to one end of each transistor HVNTr, and the other end is connected to select line SGS, word line WL0 to WL31, and select line SGD. A signal TG is supplied to the gate of each transistor HVNTr. When the transistor HVNTr of each selection block is turned on according to the signal TG, a predetermined voltage is supplied to the word lines WL0 to WL31 of the cell.

The P-well area 58 in which the low decoder 6-1 is arranged may be separated for each block, or a plurality of or all blocks of low decoders may be arranged in one P-well area 58.

(Read operation) As shown in FIG. 9A, the data in the memory cell is 0 or 2 after the first page is written. Therefore, these data can be read by supplying the intermediate level "a" of these data to the word line and performing the read operation. Further, as shown in FIG. 9B, after writing the second page, the data in the memory cell is any one of 0, 1, 2, and 3. Therefore, these data can be read by supplying the intermediate levels "b", "c", and "d" of these data to the word line and performing the read operation. In this embodiment, for example, the levels "a" and "b" are negative voltages.

Set the memory cell well (Fig. 5, P-well area 55), source line and non-selected bit line to Vss (ground potential = 0V). If the P-well region 58 is separated into blocks, the P-well region 58 of the non-selected block is set to Vss or negative potential (eg -2V) and the transfer gate of the non-selected block (shown in FIG. 11) is turned off. And. One<u style="single">of</u>If multiple or all block low decoders are located in the P-well region 58, the P-well region 58 is set to a negative potential (eg -2V) and the transfer gate of the non-selected block (shown in FIG. 11) is turned off. To do. As a result, the word line of the non-selected block becomes a floating state, and the selected gate becomes Vss.

By supplying a negative potential (for example, -2V) to the P-well region 58 of the low decoder of the selection block and turning on the transfer gate of the selection block, the potential at the time of reading (for example, -2V) to the selection word line of the selection block. From 3V), Vread (eg 5V) to the non-selected word line of the selected block, Vsg (Vdd + Vth, eg 2.5V + Vth) to the selection gate SG1 of the selected block<u style="single">Is supplied</u>.. Here, when the potential at the time of reading is not negative, the P-well region may be Vss.

Next, the signal VPRE of the data storage circuit 10 shown in FIG. 7 is set to Vdd (for example, 2.5V), the signal BLPRE is set to Vsg (Vdd + Vth), the signal BLCLAMP is set to, for example (0.6V + Vth), and the bit line is set to, for example. Precharge to 0.6V. Next, set the select line SG2 on the source side of the cell to Vdd. When the threshold voltage of the memory cell is higher than the read potential, the cell is turned off and the bit line remains at a high level. Further, when the threshold voltage of the memory cell is lower than the potential at the time of reading, the cell is turned on, so that the potential of the bit line becomes Vss.

After that, the signal BLPRE of the data storage circuit 10 shown in FIG. 7 is once set to Vsg (Vdd + Vth), the node N3 of the TDC is precharged to Vdd, and then the signal BLCLAMP is set to (0.45V + Vth), for example. Set. Node N3 of the TDC is low level when the bit line potential is lower than 0.45V and high level when the bit line potential is higher than 0.45V. After setting the signal BLCLAMP to Vss, set the signal BLC1 to Vsg (Vdd + Vth) and read the potential of TDC into PDC. Therefore, when the threshold voltage of the cell is lower than the potential of the word line, the PDC is at a low level, and when it is high, the PDC is at a high level. The read operation is performed in this way.

(program) (1st page writing operation) FIG. 12 shows the write sequence of the first page, and FIG. 13 shows the write sequence of the second page.

In the program operation, the address is first specified, and as shown in Fig. 3, half of the memory cells (page 2) connected to one word line are selected. This memory can operate the program only in the order of the first page and the second page of these two pages. Therefore, first select the first page by address.

In the writing operation on the first page shown in FIG. 12, first, the writing data is input from the outside and stored in the SDCs in all the data storage circuits 10 (S11). After that, when a write command is input, the data of the SDC in all the data storage circuits 10 is transferred to the PDC (S12). When data 1 (do not write) is input from the outside, node N1a of PDC becomes high level, and when data 0 (write) is input, node N1a of PDC becomes low level. It becomes. Hereafter, the PDC data will be the potential of node N1a, and the SDC data will be the potential of node N2a.

(Program operation) (S13) In the data storage circuit 10 shown in FIG. 7, if the signal BLC1 is Vdd + Vth, the transistor 61h conducts. Therefore, when the data "1" (does not write) is stored in the PDC, the bit line becomes Vdd, and when the data "0" (does write) is stored, the bit line becomes Vss. .. Also, cells connected to the selected word line and on non-selected pages (bit lines are not selected) must not be written. Therefore, the bit lines connected to these cells are also set to Vdd in the same way as the bit lines to which the data 1 is supplied.

In this state, when the P-well region 58 is separated into blocks, the P-well region 58 of the non-selected block is set to Vss or a negative potential (for example, -2V), and the transfer gate of the non-selected block (see FIG. 11). Show) is turned off. If multiple or all block low decoders are located in one P-well region 58, the P-well region 58 is set to a negative potential (eg -2V) and the transfer gate of the non-selected block (shown in FIG. 11). Turn off. As a result, the word line of the non-selected block becomes a floating state, and the selected gate becomes Vss.

Further, the P-well region 58 of the low decoder of the selected block is set to a negative potential (for example, -2V), and by conducting the transfer gate of the selected block, the selection gate SGD of the selection block is slightly lower than Vdd (or Vdd). Potential) is supplied. Furthermore, if Vss is supplied to the selection gate SGS of the selection block, Vpgm (20V) is supplied to the selection word line, and Vpass (10V) is supplied to the non-selection word line. Since Vss and word line are Vpgm, writing is performed. On the other hand, when the bit line is Vdd, the channel of the cell is not Vss, but the channel is booted by coupling. Therefore, the potential difference between the gate and the channel becomes small, and writing is not performed.

When writing is performed in the order shown in FIG. 10, the number of written cells increases as the distance from the source line increases. Therefore, there is a problem that the channel is hard to boot and is erroneously written. In order to solve this, the above-mentioned RLSB writing method and REASB writing method have been developed. In the RLSB writing method, the word line next to the selected word line or the next word line one distance away from the selected word line is set to Vss, the selected word line is set to Vpgm, and the other word lines are set to Vpass or intermediate potential. In the REASB writing method, the word line next to the selected word line on the source side or the next word line one distance away from it is set to Vss, the selected word line is Vpgm, and the other word lines are Vpass or intermediate. Set to potential. In this way, the word line next to the selected word line or one word away from it is set to Vss to turn off the memory cell, and the channel directly under the selected cell is easily booted.

However, in the present embodiment, when the cell whose word line is Vss is an erase cell, it does not turn off because the threshold value is a negative voltage. Therefore, in the case of the present embodiment, in the RLSB writing method shown in FIGS. 14 (a) and 14 (b) and the REASB writing method shown in FIG. 14 (c), the word line is next to the selected word line or next to the selected word line. Set the word line to a negative potential, eg (-1.5V), instead of Vss. In writing on the first page, the data in the memory cell becomes data "0" and data "2".

(Program Verify Read) (S14) The program verify read is the same as the read operation, but reads by supplying the verify level "a'" slightly higher than the read level to the word line. By this verify read, when the threshold voltage of the memory cell reaches the verify level a', the PDC becomes the data 1 and the writing is not performed.

On the other hand, when the threshold voltage of the memory cell does not reach the verification level a', the PDC becomes the data 0. If all the PDC data of each data storage circuit 10 is not "1" (S15), the program is executed again (S13). The program operation and the verify operation are repeated until all the PDC data of each data storage circuit 10 becomes 1.

(2nd page writing operation) In the writing operation on the second page shown in FIG. 13, first, the writing data is input from the outside and stored in the SDCs in all the data storage circuits 10 (S21). After that, in writing on the first page, in order to confirm the written data, the read level a (for example, negative voltage) is set to the word line, and the data in the memory cell is read (S22). This read operation is as described above. When the cell threshold voltage is lower than the word line potential a, the PDC is at a low level, and when it is higher, the PDC is at a high level.

After this, the data cache is set (S23). That is, the writing on the second page is performed as shown in FIG. 9 (b).

When the data is "1" in the writing of the first page, and when the data is "1" in the writing of the second page, the writing of the second page is not performed.

When the data is "1" in the writing of the first page and the data is "0" in the writing of the second page, the data in the memory cell is set to "1" by the writing of the second page.

When the data is "0" in the writing of the first page, and when the data is "0" in the writing of the second page, the data of the memory cell is set to "2" by the writing of the second page.

When the data is "0" in the writing of the first page, and when the data is "1" in the writing of the second page, the cell data is set to "3" by the writing of the second page.

A data cache is set to perform this operation.

That is, when the data in the memory cell is set to "0" (data "1" on the first page, data "1" on the second page), PDC is set to high level, DDC is set to low level, and SDC is set to high level. To.

When the data in the memory cell is set to "1" (data "1" on the first page, data "0" on the second page), PDC is set to low level, DDC is set to high level, and SDC is set to high level.

When the data in the memory cell is set to "2" (data "0" on the first page, data "0" on the second page), PDC is set to low level, DDC is set to high level, and SDC is set to low level.

When the data in the memory cell is set to "3" (data "0" on the first page, data "1" on the second page), PDC is set to low level, DDC is set to low level, and SDC is set to low level.

Each data of PDC, DDC, SDC is set by supplying signals BLC1, BLC2, DTG, REG, and VREG in a predetermined order and transferring the data of PDC, DDC, SDC, and TDC. The specific operation will be omitted.

(Program operation) (S24) The program behavior is exactly the same as the program behavior on the first page. When the data "1" is stored in the PDC, the writing is not performed, and when the data "0" is stored, the writing is performed.

(Verify operation) (S25, S26, S27) Program verify read is the same as read operation. However, the verify levels "b'", "c'", and "d'" are set to a level slightly higher than the read level by adding a margin to the read level. The verify read is performed using the verify levels "b'", "c'", and "d'". For example, the verify level b' is a negative voltage , and the verify levels c' and d' are positive voltages.

The verification operation is executed in the order of, for example, the verification levels "b'", "c'", and "d'".

That is, first, the verification level "b'" is set on the word line, and it is verified whether or not the threshold voltage of the memory cell has reached the verification level "b'" (S25). As a result, when the threshold voltage of the memory cell reaches the verify level, the PDC becomes a high level and writing is not performed. On the other hand, if the verify read level is not reached, the PDC becomes low level and writing is performed in the next program.

After that, the verification level c' is set on the word line, and it is verified whether or not the threshold voltage of the memory cell has reached the verification level c' (S26). As a result, when the threshold voltage of the memory cell reaches the verify level, the PDC becomes a high level and writing is not performed. On the other hand, if the verify read level is not reached, the PDC becomes low level and writing is performed in the next program.

Next, the verification level d' is set on the word line, and it is verified whether or not the threshold voltage of the memory cell has reached the verification level d' (S27). As a result, when the threshold voltage of the memory cell reaches the verify level, the PDC becomes a high level and writing is not performed. On the other hand, if the verify read level is not reached, the PDC becomes low level and writing is performed in the next program.

In this way, the program operation and the verify operation are repeated until the PDCs of all the data storage circuits 10 reach a high level.

The specific verification operation will be described below.

(Verify (b')) (S25) In this program verification operation, the verification voltage b' is applied to the selected word line.

First, the read potential Vread is given to the non-selected word line and the select line SG1 in the selected block. The bit line is precharged with the signal BLCLAMP of the data storage circuit 10 as 1V + Vth and BLC2 as Vdd + Vth. When writing to the data 2 and 3 of the memory cell, the stored data of the SDC is 0. Therefore, the bit line is not precharged, and the bit line is precharged only when writing to the data 0 or 1 of the memory cell.

Next, set the select line SG2 on the source side of the cell to a high level. When the threshold voltage is higher than the potential "b'", the cell turns off and the bit line remains at a high level. Moreover, since the cell whose threshold voltage is lower than the potential "b'" is turned on, the bit line becomes Vss. During this bit line discharge, the node N3 of the TDC is temporarily set to Vss, the transistor 61q is turned on with the signal REG set to the high level, and the data of the DDC is transferred to the TDC.

Next, the signal DTG is set to the high level, the transistor 61s is turned on once, and the PDC data is transferred to the DDC. After this, the data of TDC is transferred to PDC. Next, the transistor 61u is turned on as the voltage Vdd + Vth to the signal BLPRE of the data storage circuit, and the node N3 of the TDC is precharged to Vdd. After that, the signal BLCLAMP is set to 0.9V + Vth, and the transistor 61t is turned on. Then, the node N3 of the TDC becomes low level when the bit line is low level, and becomes high level when the bit line is high level.

Here, when writing is performed, the low level is stored in the DDC, and when writing is not performed, the high level is stored in the DDC. Therefore, if the signal VREG is set to Vdd and the signal REG is set to high level, the node N3 of the TDC is forcibly set to high level only when writing is not performed. After this operation, the data of PDC is transferred to DDC, and the potential of TDC is read into PDC. The high level is latched in the PDC only when no writing is performed and when data "1" is written to the memory cell and the threshold voltage of the cell reaches the verify voltage "b'". When the low level is latched in the PDC, the threshold voltage of the cell does not reach the potential "b'", and the data "2" and "3" of the memory cell are written.

(Verify (c')) (S26) The cell to write the data "2" is written by the verify voltage "a'" lower than the original verify voltage "c'" on the first page. After that, the threshold voltage may rise due to the writing of the adjacent cell, and some cells have reached the original verification voltage c'. Therefore, first, the data "2" is verified. In this program verification operation, a verification voltage c' is applied to the selected word line.

First, the potential Vread is applied to the non-selected word line and the select line SG1 in the selected block, the signal BLCLAMP of the data storage circuit 10 shown in FIG. 7 is set to 1V + Vth, the signal REG is set to Vdd + Vth, and the bit line is set. Precharge. When writing data 0 or 3 to the memory cell, the DDC is set to low level. Therefore, the bit line is not precharged. Also, when writing data "1" and "2" to the memory cell, the DDC is set to a high level. Therefore, the bit line is precharged.

Next, set the select line SG2 on the source side of the NAND cell to a high level. When the cell threshold voltage is higher than "c'", the cell turns off. Therefore, the bit line remains at a high level. Also, cells whose cell threshold voltage is lower than "c'" are turned on. Therefore, the bit line becomes Vss. During the discharge of the bit wire, the node N3 of the TDC is once set to Vss. After that, the transistor 61q is turned on with the signal REG set to the high level, and the DDC data is transferred to the TDC.

Next, the signal DTG is set to Vdd + Vth, the transistor 61s is turned on once, and the PDC data is transferred to the DDC. After this, the data of TDC is transferred to PDC.

Next, the node N3 of the TDC is precharged to Vdd by setting the signal VPRE to Vdd and the signal BLPRE to Vdd + Vth. After that, the signal BLCLAMP is set to 0.9V + Vth and the transistor 61t is turned on. Node N3 of the TDC is low level when the bit line is low level, and high level when the bit line is high level.

Here, when writing is performed, a low level signal is stored in the DDC, and when writing is not performed, a high level signal is stored in the DDC. Therefore, if the signal VREG is set to Vdd and the signal REG is set to Vdd + Vth, the node N3 of the TDC is forcibly set to a high level only when writing is not performed.

After that, the data of PDC is transferred to DDC, and the potential of TDC is read into PDC. The high-level signal is latched in the PDC only when no write is performed and when the data "2" is written to the memory cell and the threshold voltage of the cell reaches the verify voltage "c'". When the low level is latched in the PDC, the threshold voltage of the cell does not reach "c'", and the data "1" and "3" are written to the memory cell.

(Verify (d')) (S27) In this program verification operation, the verification voltage d' is supplied to the selected word line. In this state, first, Vread is supplied to the non-selected word line and select line SG1 in the selected block, the signal BLCLAMP is 1V + Vth, the BLPRE is Vdd + Vth, and the transistor 61t and 61u are turned on to turn on the bit line. Precharge.

Next, set the select line SG2 on the source side of the cell to a high level. The bit line remains at a high level because cells with a threshold voltage above the potential d' are turned off. Further, since the cell whose threshold voltage is lower than the potential "d'" is turned on, the bit line becomes Vss. During this bit line discharge, the node N3 of the TDC is set to Vss, the signal REG is set to the high level, the transistor 61q is turned on, and the data of the DDC is transferred to the TDC.

Next, the signal DTG is set to a high level, the transistor 61s is turned on, and the PDC data is transferred to the DDC. After this, the data of TDC is transferred to PDC. Next, the signal BLPRE is set to Vdd + Vth, the transistor 61u is turned on, and the node N3 of the TDC is precharged to Vdd. After that, the signal BLCLAMP is set to 0.9V + Vth and the transistor 61t is turned on. Node N3 of the TDC is low level when the bit line is low level, and high level when the bit line is high level.

Here, when writing is performed, the low level is stored in the DDC, and when writing is not performed, the high level is stored in the DDC. Therefore, the signal VREG is set to Vdd, the signal REG is set to the high level, and the transistor 61q is turned on. Then, node N3 of TDC is forced to high level only when writing is not performed. After this operation, the data of PDC is transferred to DDC, and the potential of TDC is read into PDC. The high level is latched in the PDC only when no write is performed and when the data "3" is written to the memory cell and the threshold voltage of the cell reaches the verify voltage "d'". When the low level is latched by the PDC, the threshold voltage of the cell does not reach the potential d' and the data 1 and 2 of the memory cell are written.

If the PDC is at a low level, the write operation is performed again, and this program operation and the verify operation are repeated until the PDC data of all the data storage circuits reaches the high level (S28).

In the above program verification, three verifications were performed after one program. However, in the initial program loop, the threshold voltage does not rise. Therefore, the verification of the memory cell data 3, the verification of the memory cell data 3, and the verification of the memory cell data 2 can be omitted. Further, in the program loop near the end, the writing to the memory cell data 1 or the writing of the memory cell data 2 and the memory cell data 1 is completed. Therefore, these verification operations can be omitted. When the verification of the memory cell data 1 becomes unnecessary, it is no longer necessary to retain the data stored in the SDC. Therefore, it is also possible to read the data for writing the next data from the outside.

(Erase operation) The erasing operation is executed in block units shown by the broken line in FIG. Also, the two bit lines (BLie, BLio) connected to each data storage circuit 10 are executed at the same time. After erasing, the cell threshold becomes the memory cell data 0 as shown in FIG. 9 (c).

In the case of the RLSB and REASB methods, it is necessary to make the threshold voltage of the erase cell shallow. Therefore, after the erase operation, all the word lines in the block are selected, the program and the program verify read are performed, and the write operation is performed up to the verification level z as shown in FIG. 9 (c). At this time, in the program and program verify read operation, all word lines are selected, the potential of the selected word line at the time of verification is z + Vfix (for example, 0V), and the other operations are the same as those of the normal program and program verify read. To be executed by. In this way, the threshold voltage after erasing is set slightly shallow.

According to the above embodiment, a plurality of threshold voltages including data 0 are set on the negative voltage side lower than 0V. That is, the data "0" and "1" are set on the negative voltage side. Therefore, two data 2 and 3 may be set within the range of the read voltage Vread. Therefore, since the number of data set in the range of the read voltage Vread similar to the conventional one can be reduced, the threshold voltage distribution of each data can be widened. Therefore, the number of programs and verifications can be reduced, and the writing speed can be increased.

Further, at the time of writing, as described above, the writing voltage Vpgm is supplied to the word line of the selected cell, and at the time of program verification, the writing voltage Vpgm is gradually increased and repeated until the threshold voltage of the selected cell reaches a predetermined threshold voltage. Written. As shown in FIG. 1 (b), in the case of the present embodiment, the verification levels VC and VD can be slightly lowered as compared with the conventional case shown in FIG. 1 (a). Therefore, the write voltage Vpgm can be lowered, the withstand voltage of the peripheral circuit can be lowered, and the pump circuit that generates the write voltage Vpgm can be miniaturized.

In the above embodiment, the case of 2 bits and 4 values has been described. However, the present embodiment is not limited to this, and the above embodiment can be applied to cases of 3 bits, 8 values, 4 bits, 16 values or more. In the case of storing such multi-valued data, for example, in the case of 8-value, 4-value data may be set on the negative side, and in the case of 16-value data, 8-value data may be set on the negative side.

Further, in the above embodiment, the central portion of the plurality of threshold voltage distributions as multi-valued data is set to 0V. However, the present invention is not limited to this, and as shown in FIG. 15 (a), for example, the central part of the multi-valued data is set to the neutral threshold voltage (the threshold voltage when no electron exists in the floating gate). You may.

Furthermore, FIGS. 15 (b) and 15 (c) show the relationship between the differences B, C, and D between each threshold voltage and the neutral threshold voltage and the required data retention. As shown in FIGS. 15 (b) and 15 (c), as the distance from the neutral threshold voltage increases, the required data retention margin, that is, the verification levels VB, VC, VD and read levels shown in FIGS. 1 (a) and 1 (b). Difference between RB, RC and RD VB-RB, VC-RC and VD-RD need to be set large.

In the conventional case shown in Fig. 15 (b), the difference B from the neutral threshold voltage is 0.1V for VB-RB, 0.2V for difference C, 0.2V for VC-RC, 0.3V for difference D, and 0.3V for VD-RD. Yes, the total difference is 0.6V. Therefore, in the past, it was necessary to set a margin of 0.6V.

On the other hand, in the case of the present embodiment shown in FIG. 15 (c), the difference B is 0.2V for VB-RB, the difference C is 0.1V for VC-RC, and the difference D is 0.2V for VD-RD. Yes, the total difference is 0.5V. Therefore, a margin of 0.5V may be set.

In this way, since the total margin can be reduced, more data can be stored within the range of Vread.

In addition, it goes without saying that various modifications can be carried out without changing the gist of the present invention.

<figref num="1">The figure which shows the relationship of the threshold voltage between the conventional and this embodiment.</figref><figref num="2">The block diagram which shows an example of the semiconductor storage device which concerns on this embodiment.</figref><figref num="3">The circuit diagram which shows the structure of the memory cell array and the bit line control circuit shown in FIG.</figref><figref num="4">FIGS. 4 (a) and 4 (b) are cross-sectional views showing a memory cell and a selection transistor.</figref><figref num="5">The cross-sectional view which shows the semiconductor storage device which concerns on this embodiment.</figref><figref num="6">The figure which shows the potential supplied to each well at the time of erasing, programming, and reading which concerns on this embodiment.</figref><figref num="7">The circuit diagram which shows an example of the data storage circuit shown in FIG.</figref><figref num="8">The circuit diagram which shows an example of the negative voltage generation circuit shown in FIG.</figref><figref num="9">9 (a), (b), and (c) are diagrams showing the relationship between the data in the memory cell and the threshold value in the memory cell.</figref><figref num="10">The figure which shows the writing order in this embodiment.</figref><figref num="11">The figure which shows the transfer gate which constitutes a part of the low decoder shown in FIG.</figref><figref num="12">A flowchart showing the writing operation of the first page.</figref><figref num="13">A flowchart showing the writing operation on the second page.</figref><figref num="14">14 (a) and 14 (b) are diagrams showing the voltage of each part in the RLSB writing method, and FIG. 14 (c) is a diagram showing the voltage of each part in the REASP writing method.</figref><figref num="15">15 (a), (b), and (c) are diagrams showing a modified example of the present embodiment.</figref>

Code description

1 ... memory cell array, 2 ... bit line control circuit, 6 ... word line control circuit, 6-1 ... low decoder, 7 ... control signal and control voltage generation circuit, 7-1. .. Negative voltage generation circuit, 10 ... data storage circuit, 58 ... P well area, MC ... memory cell, WL0 ~ WL31 ... word line, BLOe, BLOo ... bit line, SGS, SGD ... selection gate, HVNTr ... transistor.