Semiconductor device and its making method

The present invention relates to a non-volatile memory and a method for manufacturing the same, and more particularly to a non-volatile memory having an ONO (Oxide Nitride Oxide) film and a method for manufacturing the same.

In recent years, non-volatile memory, which is a semiconductor device capable of rewriting data, has been widely used. In the technical field of such non-volatile memory, technological development for the purpose of miniaturization of memory cells is being promoted in order to increase the storage capacity.

As the non-volatile memory, a floating gate type flash memory that stores an electric charge in a floating gate has been widely used. However, as the miniaturization of memory cells progresses in order to realize a higher storage density, it becomes difficult to design a floating gate type flash memory. With the miniaturization of memory cells of floating flash memory, it is necessary to thin the tunnel oxide film. However, the thinning of the tunnel oxide film increases the leak current flowing through the tunnel oxide film, and the introduction of defects in the tunnel oxide film causes reliability problems such as the disappearance of the charge accumulated in the floating gate. Because.

To solve this, there are flash memories having ONO (Oxide / Nitride / Oxide) films such as MONOS (Metal Oxide Nitride Oxide Silicon) type and SONOS (Silicon Oxide Nitride Oxide Silicon) type. This is a flash memory that stores electric charges in a silicon nitride film layer called a trap layer sandwiched between silicon oxide film layers. Since this flash memory stores electric charges in the silicon nitride film layer which is an insulating film, even if the tunnel oxide film is defective, the electric charges do not disappear unlike the floating gate type. Further, it is possible to store a multi-valued bit in the trap layer of the same memory cell, which is advantageous for increasing the storage capacity of the non-volatile memory.

Hereinafter, a flash memory having a conventional ONO film and a manufacturing method thereof (hereinafter referred to as a conventional technique) will be described with reference to FIGS. 1 (a) to 1 (d).

FIGS. 1 (a) to 1 (d) show a conventional flash memory and a manufacturing method thereof as a cross-sectional view. The flash memory includes a memory cell and peripheral circuits, and the left side of the figure shows a memory cell area and the right side shows a peripheral circuit area.

In FIG. 1 (a), on the P-type silicon semiconductor substrate 100, the first silicon oxide film layer 110 which is a tunnel oxide film, the silicon nitride film layer 112 which is a trap layer, and the third protective film which is a protective film for injection. The silicon oxide film layer 114 is formed. Next, the photoresist 120 is applied and a general exposure technique is used to form the bit lines of the memory cell region and the source / drain region forming region opening 140. Here, the dimension of the opening 140 is L11.

Next, in FIG. 1 (b), an N-type low resistance layer 150 that becomes the bit wire and the source / drain region by ion-implanting, for example, arsenic (As) into the bit wire and the source / drain region and heat-treating the bit wire and the source / drain region. To form. At this time, the dimension of the low resistance layer 150 is L12. Further, the portion sandwiched between the set of source / drain regions 150 becomes the channel region 156.

Next, in FIG. 1 (c), the third silicon oxide film layer 114, which is a protective film, is removed to form the second silicon oxide film layer 116.

Next, in FIG. 1D, the second silicon oxide film 116, the silicon nitride film layer 112, and the first silicon oxide film layer 110 in the peripheral circuit region are removed. After that, a fourth silicon oxide film layer 170 serving as a gate oxide film is formed in the peripheral circuit forming region. Further, the gate metal 182 of the peripheral circuit, the control gate of the memory cell, and the polycrystalline silicon film layer to be the word line 180 are formed. After that, a memory cell and peripheral circuits are formed by a general manufacturing method, and a flash memory having an ONO film is completed.

Further, Patent Document 1 discloses a flash memory having an OMO film having a metal silicified layer as a part of the bit wire for the purpose of lowering the resistance value of the bit wire.

<patcit num="1"><text>Japanese Patent Application Laid-Open No. 2002-170891</text></patcit>

<p> However, in the prior art, it has been difficult to miniaturize the bit wire having the dimension L12 and the low resistance layer 150 in the source / drain region. The dimension L12 is larger than the dimension L11 of the opening 140 of the photoresist 120 by the lateral extent of ion implantation. The size L11 of the opening 140 is limited to about half the wavelength of the exposure device. For example, when a commonly used KrF exposure device is used, it is difficult to set L11 to 100 nm or less. Therefore, it is difficult to set L12 to 100 nm or less.</p><p> Further, when the dimension L12 of the low resistance layer 150 in the bit wire and the source / drain region is miniaturized, there is a problem that the resistance of the bit wire becomes high and the write / erase characteristics deteriorate.</p><p> As a solution to this problem, as in Patent Document 1, a first low resistance layer formed by ion implantation of a bit wire and a first low resistance layer are in contact with each other, and a low resistance layer is formed on a part of the first low resistance layer. There is a method of forming a second low resistance layer which is a metal silicified film. However, in Patent Document 1, the second low resistance layer cannot be continuously formed in the direction in which the current flows. In this case, the reduction of the resistance of the bit wire is incomplete. Further, since the metal silicified film is formed between the sidewall control gates, the metal silicified film cannot be formed on the first low resistance layer unless the width of the bit wire is widened. This contradicts the demand for miniaturization. Further, the memory cell cannot be completed unless two polycrystalline silicon film layers are formed. In general, since the gate in the peripheral circuit region is formed of one polycrystalline silicon film layer, a structure requiring two polycrystalline silicon film layers in a memory cell has a problem that the manufacturing process of the peripheral circuit becomes complicated.</p><p> On the other hand, in the prior art, it is difficult to further laminate a low resistance layer on the bit line region 150 because the photoresist is used as a mask. This is because a high temperature of 200 ° C. or higher is generally required for the formation of the low resistance layer, and such a temperature exceeds the glass transition temperature of the photoresist.</p><p> Therefore, an object of the present invention is to solve the above-mentioned problems, prevent high resistance of bit wires, enable miniaturization of memory cells, and provide a semiconductor device and a method for manufacturing the peripheral circuit, which is easy to manufacture. That is.</p>

<p> The present invention is formed in a semiconductor substrate, an ONO (oxide film / nitride film / oxide film) film formed on the semiconductor substrate, a control gate arranged on the ONO film, and the semiconductor substrate. The second low has a bit wire having a first low resistance layer and a second low resistance layer which is in contact with the first low resistance layer and is formed continuously in the direction in which a current flows. The resistance layer is a semiconductor device having a sheet resistance smaller than that of the first low resistance layer.</p><p> According to the present invention, the resistance of the bit wire can be reduced by continuously providing the bit wire with a second low resistance layer having a small sheet resistance in the direction in which the current flows, and the size of the bit wire can be reduced. , A semiconductor device that can be miniaturized can be provided.</p><p> In the present invention, the first low resistance layer is an impurity diffusion layer.</p><p> According to the present invention, it is possible to provide a semiconductor device capable of simplifying a manufacturing process by using an impurity diffusion layer for the first low resistance layer.</p><p> In the present invention, the second low resistance layer may have a metal silicified film layer.</p><p> According to the present invention, by using a low resistance metal silicified film layer for a bit wire, it is possible to provide a semiconductor device having a small resistance of the bit wire.</p><p> In the present invention, the second low resistance layer can have a structure having an epitaxially grown silicon layer.</p><p> According to the present invention, by using an epitaxially grown silicon layer having low resistance for a bit wire, it is possible to provide a semiconductor device having a small resistance of the bit wire.</p><p> The present invention has a word line connected to the control gate, and the control gate and the word line can be integrally formed of one polycrystalline silicon layer.</p><p> According to the present invention, since a memory cell can be formed by using a polycrystalline silicon film as a single layer, a semiconductor device that simplifies the manufacturing process of a peripheral circuit is provided by using this polycrystalline silicon film as a gate metal of a peripheral circuit. be able to.</p><p> In the present invention, the bit wire and the control gate can be configured to be insulated only by the upper oxide film of the ONO film.</p><p> According to the present invention, since the control gate and the bit wire are insulated by a high-quality silicon oxide film layer, it is possible to provide a semiconductor device having good insulation characteristics with a simple configuration.</p><p> The present invention further relates to an insulating film mask having a step of forming an ONO (oxide film / nitride film / oxide film) film on a semiconductor substrate and an opening on the ONO film in which a bit line forming region is selectively removed. A step of forming a layer, a step of forming a first low resistance layer by selectively injecting impurities into a silicon substrate in the bit line forming region using the insulating film mask layer as a mask, and a step of forming the bit line. A step of etching the ONO film in the region and a second layer formed in contact with the first low resistance layer of the bit line forming region and continuously in the direction of current flow, and having a smaller sheet resistance than the first low resistance layer. It is a method of manufacturing a semiconductor device including the step of forming the low resistance layer of 2.</p><p> According to the present invention, the resistance of the bit wire can be reduced by providing the bit wire with a second low resistance layer having a small sheet resistance, the size of the bit wire can be reduced, and the semiconductor device can be miniaturized. A manufacturing method can be provided.</p><p> In the present invention, the step of forming the insulating film mask layer includes a step of reducing the opening size of the opening by forming a spacer on the side surface of the opening.</p><p>According to the present invention, it is possible to provide a method for manufacturing a semiconductor device capable of further miniaturizing the size of a bit wire.</p><p> In the present invention, the insulating film mask layer is a silicon nitride film.</p><p> According to the present invention, since etching selectivity can be ensured with the upper oxide film of the ONO film, it is possible to provide a method for manufacturing a semiconductor device that can simplify the manufacturing process.</p><p> In the present invention, after the step of forming the second low resistance layer, a step of removing the upper oxide film of the ONO film, a nitride film of the ONO film, and a second low resistance under the opening. A step of forming a silicon oxide film layer so as to cover the layer is provided.</p><p> According to the present invention, since the control gate and the bit wire are insulated by a high-quality silicon oxide film layer, it is possible to provide a method for manufacturing a semiconductor device having good insulation characteristics with a simple configuration.</p><p> In the present invention, the step of forming the first low resistance layer selectively removes the upper oxide film and the nitride film below the ONO film in the bit line forming region, and then the semiconductor substrate. Includes a step of ion-implanting impurities into the membrane.</p><p> According to the present invention, since the step of forming the first low resistance layer is ion implantation through the first silicon oxide film, the lateral spread due to ion implantation can be reduced, and the semiconductor device can be further miniaturized. A manufacturing method can be provided.</p><p> In the present invention, the step of forming the second low resistance layer includes a step of forming a metal silicified film layer.</p><p> According to the present invention, by using a low resistance metal silicified film layer for a bit wire, it is possible to provide a method for manufacturing a semiconductor device having a small resistance of the bit wire.</p><p> The present invention includes, after the step of forming the metal silicate film layer, a step of selectively forming a resin on the metal silicate film layer and a step of removing the insulating film mask layer.</p><p> According to the present invention, it is possible to provide a method for manufacturing a semiconductor device that prevents the nitride film in the ONO film from being removed when the insulating film mask layer is removed.</p><p> In the present invention, the step of forming the second low resistance layer includes a step of epitaxially growing the low resistance silicon layer.</p><p> According to the present invention, by using an epitaxially grown silicon layer having low resistance for a bit wire, it is possible to provide a method for manufacturing a semiconductor device having a small resistance of the bit wire.</p>

<p> According to the present invention, it is possible to provide a semiconductor device and a manufacturing method thereof, which can prevent high resistance of bit wires, can miniaturize memory cells, and can easily manufacture peripheral circuits.</p>

<figref num="1">1 (a) to 1 (d) are cross-sectional views showing a flash memory having a prior art ONO film and a manufacturing method thereof.</figref><figref num="2">2 (a) to 2 (d) are cross-sectional views (No. 1) showing a flash memory having an ONO film according to the first embodiment of the present invention and a method for manufacturing the same.</figref><figref num="3">3 (e) to 3 (d) are cross-sectional views (No. 2) showing a flash memory having an ONO film according to the first embodiment of the present invention and a method for manufacturing the same.</figref><figref num="4">4 (a) to 4 (c) are cross-sectional views (No. 3) showing a flash memory having an ONO film according to the first embodiment of the present invention and a method for manufacturing the same.</figref><figref num="5">5 (a) to 5 (d) are cross-sectional views showing a flash memory having an ONO film according to a second embodiment of the present invention and a method for manufacturing the same.</figref>

Hereinafter, embodiments of the present invention will be described with reference to the drawings. (First Embodiment)

First, the first embodiment will be described with reference to FIGS. 2 (a) to 2 (d), FIGS. 3 (a) to 3 (d), and FIGS. 4 (a) to 4 (c). The first embodiment is an embodiment in which a metal silicified film layer is used as the second low resistance layer. These figures are cross-sectional views of the first embodiment, and the left side of the figure shows the memory cell area and the right side shows the peripheral circuit area.

In FIG. 2A, the first silicon oxide film layer 210, which is a tunnel oxide film, and the silicon nitride film layer 212, which is a trap layer, are sequentially formed on the P-type silicon semiconductor substrate 200 by a usual forming method. .. Here, the first silicon oxide film layer 210 is deposited by, for example, a thermal oxidation method, and the silicon nitride film layer 212 is deposited by, for example, a CVD method. Further, a third silicon oxide film layer 214, which is a protective layer for protecting the trap layer during the manufacturing process, is formed. Here, the third silicon oxide film layer is deposited at least 10 nm or more by, for example, a HTO (High Temperature Oxide) method or a CVD method using TEOS (tetraethylorthosililcate).

Next, in FIG. 2B, the insulating film mask layer 230 serving as a mask for forming the bit line and the source / drain region is formed. Here, the insulating film mask layer 230 is, for example, a silicon nitride film formed by a CVD method, and the thickness thereof is set to be sufficient for blocking ions of ion implantation described later. By using the silicon nitride film, the insulating film mask layer 230 can be easily removed thereafter, and the selectivity with the third silicon oxide film layer 214 can be ensured at the time of removal.

Then, the photoresist 220 is applied on the insulating film mask layer 230, and the opening 240 is formed in the bit line and the source / drain region by using a usual exposure method. At this time, the opening 240 has the opening size L21. Here, by forming an antireflection film (not shown) under the photoresist 220, a finer opening can be made possible.

Next, in FIG. 2C, the insulating film mask layer 230 is selectively dry-etched using the photoresist 220 as a mask to form an opening 242 in the insulating film mask layer 230. At this time, the opening 242 has an opening size L22 which is substantially the same as the opening size L21. After that, the photoresist 220 is removed by, for example, an ashing method.

Next, in FIG. 2D, a spacer is provided so as to cover the upper surface of the insulating film mask layer 230, the side surface of the opening 242 of the insulating film mask layer, and the surface of the third silicon oxide film layer below the opening 242. Form an insulating film (not shown). Here, the spacer insulating film is preferably an insulating film having the same film quality as the insulating film mask layer 230, and is, for example, a silicon nitride film formed by the CVD method. Its thickness is determined by the size that reduces the opening 242 of the insulating film mask layer. By using the silicon nitride film, the subsequent spacer 234 can be easily removed, and the selectivity with the third silicon oxide film layer 214 can be ensured at the time of removal.

After that, the spacer insulating film is etched back to leave the spacer 234 on the side surface of the opening 242 of the insulating film mask layer to form the opening 244 having the opening size L23. Although the method using the spacer 234 is not essential to the present invention, it is possible to form an opening 244 finer than the opening size L21 of the photoresist opening 240, and further miniaturization of the bit wire becomes possible.

Next, in FIG. 3A, the third silicon oxide film layer 214 and the silicon nitride film layer 212 are selectively etched using the opening 244 as a mask. For example, by ion-implanting arsenic (As) and heat-treating it, a first low resistance layer 250 is formed in the N-type bit line region and the source / drain region. At this time, the first low resistance layer 250 has the dimension L24. The portion sandwiched between the first low resistance layer 250, which is the source / drain region, becomes the channel region 256.

By etching the third silicon oxide film layer 214 and the silicon nitride film layer 212, the through film for ion implantation can be limited to the first silicon oxide film layer 210. As a result, the ion implantation energy can be reduced, and the lateral spread of ions can be reduced. As a result, a finer bit line can be provided. In addition, the commonly known pocket implantation method may be used for the ion implantation.

Next, in FIG. 3B, the first silicon oxide film layer 210 of the opening 244 is etched. Then, a petrified metal film layer 252 is formed as a second low resistance film layer on the bit line region and the source / drain region of the opening 244. As a metal silicified metal, for example, cobalt (Co) can be formed on a silicon substrate having an opening 244 by, for example, a sputtering method, and heat-treated by, for example, an RTA (Rapid Thermal Anneal) method to form cobalt silicified wood. At this time, since the opening 244 is formed by using the insulating film mask layer 230 and the spacer 234, which are insulating films, as masks, the step of forming the metal silicified film can be performed at a high temperature.

Next, in FIG. 3C, the resin 260 is applied so as to cover the upper surface of the insulating film mask layer 230, the side surface of the opening 244, and the surface of the silicified metal film layer 252 below the opening 244. Here, for example, HSQ (hydrogen-silsesquioxane) is used as the resin.

Next, in FIG. 3D, the resin 260 is removed by, for example, an ashing method, so that the resin buried portion 262 remains in the opening 244. Here, it is preferable that the buried portion 262 remains above the third silicon oxide film layer 214.

Next, in FIG. 4A, the insulating film mask layer 230 and the spacer 234 are removed by, for example, thermophosphoric acid. Since the side surface of the silicon nitride film layer 212 facing the opening 244 is protected by the resin remaining portion 262, the silicon nitride film layer 212 is not removed, and the insulating film mask layer 230 and the spacer 234 are easily removed. It becomes possible to do.

Next, in FIG. 4B, the resin buried portion 262 is removed by, for example, an ashing method, and the third silicon oxide film layer 214 is removed, for example, by a buffered hydrofluoric acid solution. Next, a second silicon oxide film layer 216 is formed as a top oxide film layer on the surface of the silicon nitride film layer 212 and the surface of the silicified metal film layer 252 under the opening 244 by, for example, a CVD method. At this time, the formation temperature is preferably a temperature at which oxidation of the metal silicified film layer is prevented, for example, 800 ° C. or lower, and is preferably formed by a plasma CVD method. As a result, during ion implantation, the second silicon oxide film layer, which is a good film quality that is not exposed to ions, can be used to insulate the metal silicified film layer 252 and the control gate 280, which are bit wires, resulting in good insulation. The characteristics are obtained.

Finally, in FIG. 4 (c), the second silicon oxide film layer 216, the silicon nitride film layer 212, and the first silicon oxide film layer 210 in the peripheral circuit region are selectively removed. A fourth silicon oxide film layer 270 is formed as a gate oxide film in the peripheral circuit region. A polycrystalline silicon film layer is formed on the surface of the fourth silicon oxide layer 270 in the peripheral circuit region and the surface of the second silicon oxide film layer in the memory cell region. In the memory cell area, the polycrystalline silicon layer is used as the control gate and word line 280, and in the peripheral circuit area, it is used as the gate electrode 282. After that, a memory cell and peripheral circuits are formed through a normal manufacturing process, and the flash memory according to the first embodiment is completed.

According to the first embodiment, the dimension L24 of the first low resistance layer 250 in the bit line region is larger than the dimension L23 of the spacer opening 244 by the lateral extent of ion implantation. However, the size L23 of the spacer opening 244 can be made approximately smaller than the size L21 of the photoresist opening by the width of the spacer. From this, even when a commonly used KrF exposure device is used, miniaturization to 100 nm or less is possible. Further, since the opening 244 is formed with an insulating film as a mask, the metal silicified film layer 252 can be formed by using a high temperature process in which the photoresist exceeds the glass transition temperature. As a result, it is possible to prevent the bit wire from increasing in resistance and to easily miniaturize the bit wire. Further, since the memory cell is formed of one polycrystalline silicon film layer, it can be shared with the gate electrode of the peripheral circuit, and the manufacturing process of the peripheral circuit can be easily performed. (Second embodiment)

Next, the second embodiment will be described with reference to FIGS. 5 (a) to 5 (d). The second embodiment uses a low-resistance silicon layer epitaxially grown as the second low-resistance layer. 5 (a) to 5 (d) are cross-sectional views of the second embodiment. The left side of the figure shows the memory cell area, and the right side shows the peripheral circuit area.

FIG. 5 (a) is the same diagram as FIG. 3 (a) of the first embodiment, and is the same manufacturing as FIGS. 2 (a) to 2 (d) and FIG. 3 (a) of the first embodiment. Manufactured by process. Here, 300 is a silicon semiconductor substrate, 310 is a first silicon oxide film layer which is a tunnel oxide film, 312 is a silicon nitride film layer which is a trap layer, and 314 is a third silicon oxide film layer which is a protective film, 330. Is an insulating film mask layer, 334 is a spacer, 344 is an opening for forming a bit wire region and a source / drain region, and 350 is an N-shaped bit wire and a source / drain region formed by ion implantation. The low resistance layer, 356, is the channel region.

Next, in FIG. 5 (b), a second low resistance layer 352 doped with, for example, arsenic (As) or phosphorus (P) is grown on the first low resistance layer under the opening 344 by an epitaxial method. Let me. By using the usual selective epitaxial method, the second low resistance layer is not formed on the insulating film mask 330 and the spacer 334 which are insulating films. At this time, the second low resistance layer 352 is embedded above the third silicon oxide film layer 314. Then, the insulating film mask layer 330 and the spacer 334 are removed with, for example, thermal phosphoric acid. Since the side surface of the opening 344 of the silicon nitride film layer 312 is covered with the second low resistance layer 352, the silicon nitride film layer 312 may be removed when the insulating film mask layer 330 and the spacer 334 are removed. Absent. Therefore, the insulating film mask layer 330 and the spacer 334 can be easily removed without forming the resin embedded portion 262 as in the first embodiment.

Next, in FIG. 5C, the third silicon oxide film layer 314, which is a protective film, is removed with, for example, a buffered hydrofluoric acid solution, and the upper part of the second low resistance layer 352 is a first oxide insulating film layer. Etch to a thickness of about 310. Then, a second silicon oxide film layer 316 is formed as a top oxide film.

Finally, in FIG. 5 (d), the flash memory according to the second embodiment is completed by performing the same manufacturing process as in FIG. 4 (c) of the first embodiment. Here, 370 is a fourth silicon oxide film layer which is a gate oxide film in the peripheral circuit region, 380 is a control gate and a word line in the memory cell region, and 382 is a gate electrode in the peripheral circuit region.

In the second embodiment, as in the first embodiment, the resistance of the bit wire can be reduced by the second low resistance layer 352, the bit wire can be miniaturized, and the peripheral circuit can be easily manufactured. can do. Further, the second embodiment has an advantage that the insulating film mask layer 330 and the spacer 334 can be easily removed without using the resin 260 as compared with the first embodiment.

Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications are made within the scope of the gist of the present invention described in the claims. Can be changed.