Model based distortion reduction for power amplifiers
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24 claims: 24 independent, 0 dependent
- 1信号処理方法であって、 デジタル信号を生成するステップと、 前記デジタル信号を第1のサンプルレートでアナログ信号に変換するステップと、 歪みを有する増幅されたアナログ信号を生成するステップと、 前記増幅されたアナログ信号をフィードバックデジタル信号に、第2のサンプルレートで変換するステップと、 前記歪みのモデルを前記フィードバックデジタル信号に基づいて更新するステップと、 を備え、 前記歪みのモデルは、前記第1のサンプルレートに対応する帯域幅で、前記増幅されたアナログ信号をモデル化し、前記第1のサンプルレートに対応する帯域幅は、前記第2のサンプルレートに対応する帯域幅よりも大きく、 さらに、前記歪みを補正するステップを含み、 前記歪みを補正するステップは、前記モデルを用いて前記デジタル信号を処理し、予測された歪みのデジタル信号を作成するステップと、前記予測された歪みのデジタル信号を前記デジタル信号から減算し、予め補正されたデジタル信号を作成するステップとであり、 前記予め補正されたデジタル信号は前記アナログ信号へ変換され、前記増幅されたアナログ出力信号内の歪みが低減され、 前記モデルを更新するステップは、生成された誤差信号に基づいて前記モデルを算出するステップであり、前記誤差信号は、前記フィードバックデジタル信号と、前記予め補正されたデジタル信号およびモデル処理された予め補正されたデジタル信号の和と、の差から算出される方法。
- 2信号処理方法であって、 デジタル信号を生成するステップと、 前記デジタル信号を第1のサンプルレートでアナログ信号に変換するステップと、 歪みを有する増幅されたアナログ信号を生成するステップと、 前記増幅されたアナログ信号をフィードバックデジタル信号に、第2のサンプルレートで変換するステップと、 前記歪みのモデルを前記フィードバックデジタル信号に基づいて更新するステップと、 を備え、 前記歪みのモデルは、前記第1のサンプルレートに対応する帯域幅で、前記増幅されたアナログ信号をモデル化し、前記第1のサンプルレートに対応する帯域幅は、前記第2のサンプルレートに対応する帯域幅よりも大きく、 さらに、前記歪みを補正するステップを含み、 前記歪みを補正するステップは、前記モデルを用いて前記デジタル信号を処理し、予測された歪みのデジタル信号を作成するステップと、前記予測された歪みのデジタル信号を前記デジタル信号から減算し、予め補正されたデジタル信号を作成するステップとであり、 前記予め補正されたデジタル信号は前記アナログ信号へ変換され、前記増幅されたアナログ出力信号内の歪みが低減され、 前記モデルを更新するステップは、生成された誤差信号に基づいて前記モデルを算出するステップであり、前記誤差信号は、前記モデル処理されたフィードバックデジタル信号と、前記フィードバックデジタル信号および前記予め補正されたデジタル信号の差と、の差から算出される方法。
- 3請求項 1または2 に記載の方法であって、 前記増幅されたアナログ出力信号内の前記歪みは、前記フィードバックデジタル信号のサンプルレートの半分より高い周波数において低減される方法。
- 4請求項 1または2 に記載の方法であって、さらに、 前記増幅されたアナログ信号を生成する前に前記アナログ信号をアップシフトするステップと、前記増幅されたアナログ信号をフィードバックデジタル信号に変換する前にダウンシフトするステップと、を含む方法。
- 5請求項1 または2 に記載の方法であって、 前記モデルは、メモリ効果を含む方法。
- 6請求項1 または2 に記載の方法であって、 前記モデルは、有限インパルス応答フィルタである方法。
- 7請求項1 または2 に記載の方法であって、 前記モデルは、無限インパルス応答フィルタである方法。
- 8請求項1 または2 に記載の方法であって、 前記モデルは、非線形低複雑度フィルタである方法。
- 9請求項1 または2 に記載の方法であって、 前記モデルは、適応的である方法。
- 10請求項1 または2 に記載の方法であって、 前記モデルは、適応的であり、適応には最小二乗適合が含まれる方法。
- 11請求項1 または2 に記載の方法であって、 前記モデルは、適応的であり、適応には再帰的最小二乗適合が含まれる方法。
- 12請求項1 または2 に記載の方法であって、 前記モデルを更新するステップは、選択可能なレートで行われる方法。
- 13信号処理システムであって、 デジタル信号の生成器と、 前記デジタル信号を第1のサンプルレートでアナログ信号に変換する第一変換器と、 歪みを有する増幅されたアナログ信号を生成する増幅器と、 前記増幅されたアナログ信号をフィードバックデジタル信号に、第2のサンプルレートで変換する第二変換器と、 前記歪みのモデルを前記フィードバックデジタル信号に基づいて更新する更新部と、 を備え、 前記歪みのモデルは、前記第1のサンプルレートに対応する帯域幅で、前記増幅されたアナログ信号をモデル化し、前記第1のサンプルレートに対応する帯域幅は、前記第2のサンプルレートに対応する帯域幅よりも大きく、 さらに、前記歪みを補正する手段を含み、 前記歪みの補正は、前記モデルを用いて前記デジタル信号を処理し、予測された歪みのデジタル信号を作成することと、前記予測された歪みのデジタル信号を前記デジタル信号から減算し、予め補正されたデジタル信号を作成することであり、 前記予め補正されたデジタル信号は前記アナログ信号へ変換され、前記増幅されたアナログ出力信号内の歪みが低減され、 前記モデルの更新は、生成された誤差信号に基づく前記モデルの算出であり、前記誤差信号は、前記フィードバックデジタル信号と、前記予め補正されたデジタル信号およびモデル処理され予め補正されたデジタル信号の和と、の差から算出されるシステム。
- 14信号処理システムであって、 デジタル信号の生成器と、 前記デジタル信号を第1のサンプルレートでアナログ信号に変換する第一変換器と、 歪みを有する増幅されたアナログ信号を生成する増幅器と、 前記増幅されたアナログ信号をフィードバックデジタル信号に、第2のサンプルレートで変換する第二変換器と、 前記歪みのモデルを前記フィードバックデジタル信号に基づいて更新する更新部と、 を備え、 前記歪みのモデルは、前記第1のサンプルレートに対応する帯域幅で、前記増幅されたアナログ信号をモデル化し、前記第1のサンプルレートに対応する帯域幅は、前記第2のサンプルレートに対応する帯域幅よりも大きく、 さらに、前記歪みを補正する手段を含み、 前記歪みの補正は、前記モデルを用いて前記デジタル信号を処理し、予測された歪みのデジタル信号を作成することと、前記予測された歪みのデジタル信号を前記デジタル信号から減算し、予め補正されたデジタル信号を作成することであり、 前記予め補正されたデジタル信号は前記アナログ信号へ変換され、前記増幅されたアナログ出力信号内の歪みが低減され、 前記モデルの更新は、生成された誤差信号に基づく前記モデルの算出であり、前記誤差信号は、前記モデル処理されたフィードバックデジタル信号と、前記フィードバックデジタル信号および前記予め補正されたデジタル信号の差と、の差から算出されるシステム。
- 15請求項 13または14 に記載のシステムであって、 前記増幅されたアナログ出力信号内の前記歪みは、前記フィードバックデジタル信号のサンプルレートの半分より高い周波数において低減されるシステム。
- 16請求項 13または14 に記載のシステムであって、さらに、 前記増幅されたアナログ信号を生成する前に前記アナログ信号をアップシフトするアップシフト部と、前記増幅されたアナログ信号を前記フィードバックデジタル信号に変換する前にダウンシフトするダウンシフト部と、を備えるシステム。
- 17請求項 13または14 に記載のシステムであって、 前記モデルは、メモリ効果を含むシステム。
- 18請求項 13または14 に記載のシステムであって、 前記モデルは、有限インパルス応答フィルタであるシステム。
- 19請求項 13または14 に記載のシステムであって、 前記モデルは、無限インパルス応答フィルタであるシステム。
- 20請求項 13または14 に記載のシステムであって、 前記モデルは、非線形低複雑度フィルタであるシステム。
- 21請求項 13または14 に記載のシステムであって、 前記モデルは、適応的であるシステム。
- 22請求項 13または14 に記載のシステムであって、 前記モデルは、適応的であり、適応には最小二乗適合が含まれるシステム。
- 23請求項 13または14 に記載のシステムであって、 前記モデルは、適応的であり、適応には再帰的最小二乗適合が含まれるシステム。
- 24請求項 13または14 に記載のシステムであって、 前記モデルの更新は、選択可能なレートで行われるシステム。
Independent claims24
23 paragraphs, as filed
Description of related application: This application claims priority based on US Provisional Patent Application No. 60/556658 (agent reference number OPTIP009 +, POWER AMPLIFIER LINEARIZING SYSTEM, submitted March 25, 2004) incorporated herein by reference. ..
In the design of power amplifiers, many factors must be balanced against each other, including specifications such as linearity, high efficiency, low cost, and high power. For example, the Doherty type described in LUMPED ELEMENT BASED DOHERTY POWER AMPLIFIER TOPOLOGY IN CMOS PROCESS (IEEE Int. Symp. Circuits and Systems, May 2003, pp. 445-448) by Tongchoi et al., Which is incorporated herein by reference. (Doherty-type) power amplifiers can provide high power efficiency at low cost, but can be non-linear. The improvement in linearity can be achieved by active compensation of the amplifier, where the difference between the actual output of the amplifier and the desired output is measured. Measuring the difference between the actual output and the desired output requires high quality, high speed and therefore expensive components. It is beneficial to improve the linearity of the power amplifier without the need for high quality, high speed and expensive parts.
Various embodiments of the present invention will be clarified by the following detailed description and accompanying drawings.
The present invention is implemented in various forms such as processing, devices, systems, compositions, computer-readable media such as computer-readable storage media, or computer networks in which program instructions are transmitted through optical or electronic communication lines. can do. As used herein, these implementations or any other form of the present invention may be referred to as technology. Components such as processors and memory that are described as being configured to perform a task include general components that are temporarily configured to perform a task at a given time, or to perform a task. Contains the specific components that are manufactured. In general, the order of the disclosed processing steps can be changed within the scope of the present invention.
One or more embodiments of the present invention will be described in detail below with reference to the accompanying drawings showing the principles of the present invention. Although the present invention will be described in relation to these embodiments, the present invention is not limited to any embodiment. The scope of the invention is limited only by the claims, and the present invention includes various alternatives, modifications and equivalents. In order to provide a full understanding of the present invention, many specific details will be described below. These details are exemplary and the invention can be practiced in accordance with the claims without using some or all of these specific details. In order not to obscure the present invention more than necessary, detailed description of known techniques in the technical field according to the present invention will be omitted.
A model-based distortion reduction in a power amplifier (power amplifier) is disclosed. The distortion introduced by the power amplifier can be reduced by adding a signal that pre-corrects the distortion to the input of the amplifier. The model can reduce the distortion to the bandwidth of the input channel of the power amplifier. This bandwidth is limited by components within the input channel that may include digital / analog converters. Since the model parameters can be generated at a low update rate (update rate) based on the feedback information, the feedback channel in this configuration can have a substantially lower bandwidth requirement.
FIG. 1A is a diagram showing an embodiment of input / output amplitude characteristics of a power amplifier. In the illustrated example, the ideal linearity of the power amplifier is represented by curve 100. In this curve 100, there is a linear relationship between the input amplitude and the output amplitude. Curve 102 represents a non-linear power amplifier, and there is a non-linear relationship between the input amplitude and the output amplitude.
FIG. 1B is a diagram showing an embodiment of input / output phase characteristics of a power amplification system. In the illustrated example, the ideal linearity of the power amplification system is represented by curve 104. In this curve 104, there is a linear relationship between the input phase and the output phase. Curve 106 represents a non-linear power amplification system, and there is a non-linear relationship between the input phase and the output phase.
FIG. 2 is a diagram showing an embodiment of a power amplifier. The power amplification system 200 includes a digital / analog converter 202 and an analog amplifier 204. Input digital signal (ν<sub>n</sub>) Is input to the digital / analog conversion ki 202. The signal is then transmitted to the analog amplifier 204 and the analog output signal (ω).<sub>n</sub>) Is output. In some embodiments, the analog amplifier 204 comprises its own non-linear compensation.
FIG. 3 is a diagram showing an embodiment of a power amplification system. The power amplification system 310 includes a digital signal processing unit 300, a digital / analog converter 302, an analog amplifier 304, and an analog / digital converter 306. Input digital signal (ν<sub>n</sub>) Is input to the digital signal processing unit 300, and the digital signal processing unit 300 corrects the distortion generated from the source 308 of the distortion by correcting the signal in advance. The source of distortion 308 includes a digital / analog converter 302 and an analog amplifier 304. The digital signal processing unit 300 outputs the signal to the digital / analog converter 302. The signal is transmitted to the analog amplifier 304 and the analog output signal (ω)<sub>n</sub>) Is output. The output signal is also transmitted to the analog / digital converter 306, and the feedback signal (φ)<sub>n</sub>) Is created. This feedback signal (φ<sub>n</sub>) Is transmitted to the digital signal processing unit 300. In some embodiments, the conversion rate of the analog-to-digital converter 306 is selectable. In some embodiments, the conversion speed of the analog / digital converter 306 is significantly lower than the conversion speed of the digital / analog converter 302. In some embodiments, the conversion rate of the analog-to-digital converter 306 is the output signal (ω).<sub>n</sub>) Is lower than the distortion bandwidth.
FIG. 4 is a diagram showing an embodiment of a power amplification system. The power amplification system 414 includes a digital signal processing unit 400, a digital / analog converter 402, an upshift 404, an analog amplifier 406, a downshift 408, and an analog / digital converter 410. Input digital signal (ν<sub>n</sub>) Is input to the digital signal processing unit 400, and the digital signal processing unit 400 corrects the distortion generated from the distortion source 412 by correcting the signal in advance. The source of distortion 412 includes a digital / analog converter 402, an upshift 404, and an analog amplifier 406. The digital signal processing unit 400 outputs a signal to the digital / analog amplifier 402. The signal is transmitted to an upshift 404, which upshifts the signal to a higher frequency band. The signal is transmitted to the analog amplifier 406 and the analog output signal (ω)<sub>n</sub>) Is output. The output signal is also transmitted to the downshift 408, which downshifts the signal to a lower frequency. The signal is transmitted to the analog / digital converter 410, and the feedback signal (φ)<sub>n</sub>) Is created. This feedback signal (φ<sub>n</sub>) Is transmitted to the digital signal processing unit 400. In some embodiments, upshifting the signal involves modulating the signal to different high frequencies, and downshifting the signal involves demodulating the signal to different low frequencies.
FIG. 5 is a diagram showing an embodiment of a signal processing system that preliminarily corrects a digital signal in order to reduce distortion in a power amplification system. Input digital signal (ν<sub>n</sub>) Enters the digital signal processing unit 500. Its input digital signal (ν<sub>n</sub>) Is transmitted to model 502, which calculates a signal tailored (fitted) to resemble (similar) the nonlinear distortion of the power amplification system. The signal calculated by the model is the input digital signal (ν)<sub>n</sub>) Is transmitted to the summation node 506, and a pre-corrected digital signal is created. The pre-corrected digital signal is the input digital signal (ν).<sub>n</sub>), The resulting distortion of the power system is removed. This reduces distortion in the output of the power amplification system. In various embodiments, the signal calculated by the model is an input digital signal (ν) in various ways, such as signal subtraction, signal inversion, signal phase shift, and other suitable techniques.<sub>n</sub>) Is removed. The error calculation unit 508 uses the input digital signal (ν).<sub>n</sub>) And feedback digital signal (φ<sub>n</sub>), The error signal is calculated. The error signal is input to the model adapter 510. The model adapter 510 is an input digital signal (ν).<sub>n</sub>), Create a model that can calculate the distortion of the power amplification system. In some embodiments, the model adapter 510 uses a least squares fit to calculate the model. In some embodiments, the model adapter 510 uses a recursive least squares fit to calculate the model. The model adapter 510 supplies model parameters to the model 502. In some embodiments, the model parameters are updated at a selectable rate. In some embodiments, the model corrects distortion with bandwidth up to half the frequency of the digital-to-analog converter's conversion rate. Therefore, distortion in the amplified analog output signal at frequencies higher than half the sample rate of the feedback digital signal, as would be expected when using standard feedback correction methods, can be reduced.
In some embodiments, the model adapter adapts the distortion model by minimizing the error signal. In some embodiments, the model includes a memory effect (memory effect). In some embodiments, the model may be a finite impulse response filter or an infinite impulse response filter. In some embodiments, the model is a non-linear filter. In some embodiments, the filter is incorporated herein by reference in U.S. Patent Application No. 11/061850 (agent reference number OPTIP006, LOW-COMPLEXITY NONLINEAR FILTERS, submitted February 18, 2005). A low-complexity nonlinear filter with linear pieces, as described in. The basis of this non-linear filter is a non-linear function:<img file="JP4909261B2_D0001.tif" />is this,<img file="JP4909261B2_D0002.tif" />If so, it is provided (implemented) as follows.<img file="JP4909261B2_D0003.tif" />It has a one-to-one relationship with<img file="JP4909261B2_D0004.tif" />This is a "weight" that changes as a non-linear function of the input variable.<img file="JP4909261B2_D0005.tif" />Input variable Y using<sub>n</sub>Form a "primary" combination of. The whole filter is<img file="JP4909261B2_D0006.tif" />Vector Y using<sub>n</sub>Contains a "linear" combination of the elements at time n. This filtering configuration is specifically designed to fit our interpretation that a non-linear channel is equivalent to a linear channel whose time constant is a function of the input vector (due to the effect of making the channel non-linear).
The implementation of nonlinear filters can be done in the form of low complexity, such as reducing the number of multiplications while maintaining the powerful ability to emulate very complex nonlinear distortion functions. Reduced complexity reduces costs, reduces power consumption, and reduces noise. The reduced complexity of the nonlinear filter eliminates the requirement for multiplication when the nonlinear coefficients are calculated in the following form:<img file="JP4909261B2_D0007.tif" />If expressed as follows<img file="JP4909261B2_D0008.tif" />It becomes as follows.<img file="JP4909261B2_D0009.tif" />This formula virtually does not require multiplication in the coefficient operation (each c)<sub>j</sub>β<sub>j</sub>The product of is pre-calculated and stored as a single coefficient). In this format, the filter input vector Y is the highest for each coefficient.<sub>n</sub>It is called a first-order nonlinear filter because it is multiplied by the first power of the elements of. In some embodiments, the model uses a second-order nonlinear filter:<img file="JP4909261B2_D0010.tif" />In this formula, each coefficient is a non-linear function of the input vector element, and each coefficient is multiplied by the square of the element or the cross-product of the two elements. In some embodiments, a second-order nonlinear filter that allows an output that is a function of the element or a cross-product of the two elements is:<img file="JP4909261B2_D0011.tif" />In some embodiments, the non-linear filter is a zero-order catastrophic filter:<img file="JP4909261B2_D0012.tif" />In some embodiments, implementations of higher order nonlinear filters are available, as well as combinations of first and second order nonlinear filters.
FIG. 6 is a diagram showing an embodiment of the error calculation unit. The error calculation unit 600 uses a) an input digital signal (ν) as an input.<sub>n</sub>) And b) Feedback digital signal (φ<sub>n</sub>) And. The error calculation unit 600 calculates an error signal by obtaining the difference between the two inputs. In some embodiments, a digital signal (ν)<sub>n</sub>) Is a feedback digital signal (φ) by the sum node 602.<sub>n</sub>) Is subtracted from. In some embodiments, the feedback digital signal (φ)<sub>n</sub>) Is a digital signal (ν) by the sum node 602<sub>n</sub>) Is subtracted from. Feedback digital signal (φ<sub>n</sub>) Is the input digital signal (ν)<sub>n</sub>), The error signal is zero.
FIG. 7 is a diagram showing an embodiment of a signal processing system that preliminarily corrects a digital signal in order to reduce distortion in a power amplification system. Input digital signal (ν<sub>n</sub>) Enters the digital signal processing unit 700. Input digital signal (ν<sub>n</sub>) Is transmitted to model 702, which calculates a signal tailored (fitted) to resemble (similar) the nonlinear distortion of the power amplification system. The signal calculated by the model is the input digital signal (ν)<sub>n</sub>) Is sent to the sum node 706 to create a pre-corrected digital signal. The pre-corrected digital signal is the input digital signal (ν).<sub>n</sub>), The resulting distortion of the power system is removed. This reduces distortion in the output of the power amplification system. In various embodiments, the signal calculated by the model is an input digital signal (ν) in various ways, such as signal subtraction, signal inversion, signal phase shift, and other suitable techniques.<sub>n</sub>) Is removed. The error calculation unit 710 uses a pre-corrected digital signal and a feedback digital signal (φ).<sub>n</sub>), The error signal is calculated. The error signal is input to the model adapter 708. The model adapter 708 is an input digital signal (ν).<sub>n</sub>), Create a model that can calculate the distortion of the power amplification system. In some embodiments, the model is adaptive. In some embodiments, the model adapter 708 uses least squares matching to calculate the model by bringing the error signal as close to zero as possible. In some embodiments, the model adapter 708 uses a recursive least squares fit to calculate the model by bringing the error signal as close to zero as possible. The model adapter 708 supplies model parameters to the model 702 and the error calculation unit 710.
FIG. 8 is a diagram showing an embodiment of the error calculation unit. The error calculation unit 800 uses a) a pre-corrected digital signal and b) a feedback digital signal (φ) as inputs.<sub>n</sub>) And c) model adapter output. The error calculation unit 800 is a feedback digital signal (φ).<sub>n</sub>) And the sum of the pre-corrected digital signal and the model-processed pre-corrected digital signal, the error signal is calculated. In some embodiments, the sum of the pre-corrected digital signal and the modeled pre-corrected digital signal created by the sum node 804 is a feedback digital signal (φ) by the sum node 806.<sub>n</sub>) Is subtracted from. The sum of the pre-corrected digital signal and the modeled pre-corrected digital signal is the input digital signal (ν).<sub>n</sub>) Is almost the same. Feedback digital signal (φ<sub>n</sub>) Also inputs the distortion that was not canceled (not canceled) by the pre-correction digital signal (ν)<sub>n</sub>) Is almost the same as the one added. Therefore, the feedback digital signal (φ<sub>n</sub>By subtracting the sum from), an error signal proportional to the distortion that was not canceled (not canceled) by the prior correction is obtained.
In some embodiments, the feedback digital signal (φ)<sub>n</sub>) Is subtracted by the sum node 806 from the sum of the pre-corrected digital signal and the modeled pre-corrected digital signal created by the sum node 804. The overall sign of the feedback error signal is not critical to zeroing the error signal. In some embodiments, the subtraction process of the two signals is accomplished by shifting the phase of one signal by 180 degrees and adding this to the other signal. In some embodiments, the subtraction process of the two signals is accomplished by inverting (inverting) one signal and adding it to the other signal.
FIG. 9 is a diagram showing an embodiment of the error calculation unit. The error calculation unit 900 uses a) a pre-corrected digital signal and b) a feedback digital signal (φ) as inputs.<sub>n</sub>) And c) model adapter output. The error calculation unit 900 is a model-processed feedback digital signal (φ).<sub>n</sub>) And the feedback digital signal (φ<sub>n</sub>) And the difference between the pre-corrected digital signal and the difference, the error signal is calculated.
In some embodiments, the feedback digital signal (φ)<sub>n</sub>) And the inverse value (inverse) of the pre-corrected digital signal feeds back the inverse value (inverse) of the pre-corrected digital signal (φ)<sub>n</sub>) Is achieved. In some embodiments, the modeled feedback digital signal (φ)<sub>n</sub>) Is the feedback digital signal (φ)<sub>n</sub>) Is subtracted from the pre-corrected digital signal from the output of the sum node 904, which is subtracted in the sum node 906. In some embodiments, the sign of the sum is different because the overall sign of the error signal is not important.
The output of the sum node 904 feeds back a pre-corrected digital signal to the digital signal (φ).<sub>n</sub>), That is, the input digital signal with residual distortion (uncorrected) is subtracted from the input digital signal with the modeled distortion subtracted. This produces the modeled strain plus the residual strain at the output of the sum node 904. The modeled feedback digital signal is subtracted from the output of the sum node 904. The modeled feedback digital signal is the modeled input digital signal (ν).<sub>n</sub>) And the modeled residual distortion (significantly smaller than other signals). Therefore, the output of the sum node 906 is approximately the digital input signal (ν) modeled and input from the output of the sum node 904.<sub>n</sub>) Is subtracted, which is the modeled and input digital input signal (ν).<sub>n</sub>) With residual distortion, and the input digital input signal (ν)<sub>n</sub>) Is subtracted. This produces an error signal proportional to the residual distortion at the output of the sum node 906.
Although the above-described embodiment has been described in some detail above for the purpose of clarifying the understanding, the present invention is not limited to the above-mentioned details. The present invention can be implemented in various ways. The disclosed embodiments are exemplary and not limiting.
<figref num="1A">It is a figure which shows the embodiment of the input / output amplitude characteristic of a power amplifier.</figref><figref num="1B">It is a figure which shows the embodiment of the input / output phase characteristic of a power amplification system.</figref><figref num="2">It is a figure which shows the embodiment of the power amplification system.</figref><figref num="3">It is a figure which shows the embodiment of the power amplification system.</figref><figref num="4">It is a figure which shows the embodiment of the power amplification system.</figref><figref num="5">It is a figure which shows the embodiment of the signal processing system which preliminarily corrects a digital signal which reduces distortion in a power amplification system.</figref><figref num="6">It is a figure which shows the embodiment of the error calculation part.</figref><figref num="7">It is a figure which shows the embodiment of the signal processing system which preliminarily corrects a digital signal which reduces distortion in a power amplification system.</figref><figref num="8">It is a figure which shows the embodiment of the error calculation part.</figref><figref num="9">It is a figure which shows the embodiment of the error calculation part.</figref>
Every citation, both waysCites: the store holds 7 of 8
| Document | Relation | Office | Cited during |
|---|---|---|---|
| US9484868B2 | Cited by | United States of America | Applicant |
| US9712122B2 | Cited by | United States of America | Applicant |
| WO01008319A1 | Cites | World Intellectual Property Organization (WIPO) | – |
| JP2003347944A | Cites | Japan | – |
| JP2003188747A | Cites | Japan | – |
| JP2004015769A | Cites | Japan | – |
| JP2003152464A | Cites | Japan | – |
| US20010050592A1 | Cites | United States of America | – |
| US06141390A | Cites | United States of America | – |
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| Yuanming Ding, Lianming Sun, Akira Sano,Adaptive nonlinearity predistortion schemes with application to OFDM system,Control Applications, 2003. CCA 2003. Proceedings of 2003 IEEE Conference on,IEEE,2003年 8月26日,vol. 2,p. 1130-1135 | Non-patent | – | – |
20 members in 8 offices
Priority claims14
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| 55665804 | United States of America | P | |
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| 2005009890 | United States of America | W | |
| 2005009890 | United States of America | W | |
| 9102205 | United States of America | A | |
| 9102205 | United States of America | A | |
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| US20050091022 | – | – | – |
| WO2005US09890 | – | – | – |
Members20
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| US2005212596A1 | United States of America | A1 | |
| AU2005228156A1 | Australia | A1 | |
| CA2560281A1 | Canada | A1 | |
| WO2005094537A2 | World Intellectual Property Organization (WIPO) | A2 | |
| EP1735906A2 | European Patent Office (EPO) | A2 | |
| KR20070026478A | Republic of Korea | A | |
| WO2005094537A3 | World Intellectual Property Organization (WIPO) | A3 | |
| CN101061633A | China | A | |
| JP2007531414A | Japan | A | |
| US7429892B2 | United States of America | B2 | |
| US2009021304A1 | United States of America | A1 | |
| EP1735906A4 | European Patent Office (EPO) | A4 | |
| US7688139B2 | United States of America | B2 | |
| CN101061633B | China | B | |
| US2010141490A1 | United States of America | A1 | |
| AU2005228156B2 | Australia | B2 | |
| US2012046925A1 | United States of America | A1 | |
| JP4909261B2This record | Japan | B2 | |
| US8248159B2 | United States of America | B2 | |
| US8330540B2 | United States of America | B2 |
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Numbers
- Publication
- 4909261
- Publication, DOCDB
- 4909261
- Publication, EPODOC
- JP4909261B
- Application
- 2007505189
- Application, DOCDB
- 2007505189
- Application, EPODOC
- JP20070505189
Titles2
- Japanese
- 電力増幅器におけるモデルに基づく歪み低減
- English
- Model-based distortion reduction in power amplifiers
Classification
- CPC, 5
- H03F1/0288
- H03F1/32
- H03F1/3247
- H03F2200/321
- H03F1/26
- IPC, 4
- H03F1 32
- H03F3 20
- H03F1 02
- H03F1 26