Non-volatile semiconductor memory device

The embodiments described herein relate to electrically rewritable non-volatile semiconductor storage devices.

NAND flash memory is known as a non-volatile semiconductor storage device that can be electrically rewritten and can be highly integrated. In NAND flash memory, a NAND cell unit is configured by connecting a plurality of memory cells in series so as to share a source / drain diffusion layer between adjacent memory cells. Both ends of the NAND cell unit are connected to the bit line and the source line via the selection gate transistor, respectively. With such a NAND cell unit configuration, the unit cell area is smaller than that of the NOR type, and a large capacity storage is possible.

A memory cell of an NAND flash memory has a charge storage layer (floating gate electrode) formed on a semiconductor substrate via a tunnel insulating film, and a control gate electrode laminated on the charge storage layer (floating gate electrode) via an intergate insulating film. , Data is stored non-volatile depending on the charge accumulation state of the floating gate electrode. For example, binary data storage is performed with data "0" as the state where the threshold voltage is high when the charge is injected into the floating gate electrode and data "1" when the threshold voltage is low when the charge is discharged from the floating gate electrode. Recently, the threshold voltage distribution to be written is subdivided, and multi-value storage such as 4-value and 8-value is also performed.

The data erasure operation of the NAND flash memory is executed in block units. The data erasure operation is performed by setting all word lines of the selected block to 0V and applying a positive boosted erasure voltage (for example, 18V to 20V) to the P-type well in which the memory cell array is formed. As a result, a negative threshold voltage state (erasure state) in which the charge of the floating gate electrode is released is obtained in all the memory cells of the selected block. Further, when erasing data in the NAND flash memory, it is possible to perform a verify read (erase verify operation) for confirming whether or not an erase state in a certain threshold voltage range has been obtained. If it is determined that the erasing is not sufficiently performed as a result of the erasing verification operation, the erasing voltage is gradually increased (stepped up) and the same erasing operation and erasing verifying operation are repeated.

A method of performing a so-called soft program operation is known in order to eliminate the over-erased state of memory cells after this batch erasure. The width of the threshold voltage distribution after the erasing operation can be narrowed by the soft program operation. As a result, the desired threshold voltage can be accurately written to the memory cell during the subsequent write operation.

By the way, when the writing / erasing operation is repeatedly performed on one memory cell, the tunnel insulating film deteriorates. If the erase operation and the soft program operation are executed without considering the deterioration state of the memory cell, the erase operation and the soft program operation may not be executed accurately.

<p><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2009-301616</text></patcit></p>

<p> The embodiments described below provide a non-volatile semiconductor storage device capable of suppressing the influence of deterioration of memory cells during erasing operation and soft program operation.</p>

<p> The non-volatile semiconductor storage device according to the embodiment of the present invention includes a memory cell array and a control unit. The memory cell array includes a memory string in which a plurality of memory cells are connected in series, a first selection transistor connected to one end of the memory string, a second selection transistor connected to the other end of the memory string, and a first selection transistor. It includes a bit line connected to the memory string via a second selection transistor, a source line connected to the memory string via a second selection transistor, and a word line connected to the control gate electrode of the memory cell. The control unit applies an erasure voltage to a predetermined range of memory cells for data erasure, an erasure verify operation to confirm whether data erasure is completed, and an erasure voltage when data erasure is not completed. Controls the control of repeating the step-up operation of increasing the value by a predetermined step-up value. When the number of times the erasing voltage is applied during a series of erasing operations is greater than the first number of times and less than the second number of times (first number of times &lt;second number of times), the control unit over-erases a predetermined range of memory cells. The software program operation that sets the first threshold voltage distribution state from the state is executed, and if the number of times the erasing voltage is applied is less than or equal to the first number or more than the second number, the soft program operation is not executed. Has been done.</p>

<figref num="1">It is a block diagram which shows the schematic structure of the non-volatile semiconductor storage device which concerns on embodiment.</figref><figref num="2">It is a circuit diagram which shows the structure of the memory cell array of the non-volatile semiconductor storage device which concerns on embodiment.</figref><figref num="3">It is a figure which shows the example of the data storage in the non-volatile semiconductor storage device which concerns on embodiment.</figref><figref num="4">It is a figure explaining the threshold voltage distribution at the time of the erasing operation which concerns on embodiment.</figref><figref num="5">It is a figure explaining the voltage at the time of the erasing operation which concerns on embodiment.</figref><figref num="6">It is a figure explaining the voltage at the time of the erase verification operation which concerns on embodiment.</figref><figref num="7">It is a figure explaining the threshold voltage distribution at the time of the soft program operation which concerns on embodiment.</figref><figref num="8">It is a voltage waveform diagram which shows the erasing operation and the soft program operation which concerns on a comparative example.</figref><figref num="9">It is a flowchart explaining the erasing operation and the software program operation which concerns on 1st Embodiment.</figref><figref num="10">It is a voltage waveform diagram which shows the voltage at the time of the erasing operation and the soft program operation which concerns on 1st Embodiment.</figref><figref num="11">It is a voltage waveform diagram which shows the voltage at the time of the erasing operation and the soft program operation which concerns on 2nd Embodiment.</figref><figref num="12">It is a voltage waveform diagram which shows the voltage at the time of the erasing operation and the soft program operation which concerns on 2nd Embodiment.</figref><figref num="13">It is a voltage waveform diagram which shows the voltage at the time of the erasing operation and the soft program operation which concerns on 2nd Embodiment.</figref><figref num="14">It is a figure explaining the threshold voltage distribution at the time of the erasing operation which concerns on 3rd Embodiment.</figref><figref num="15">It is a figure explaining the voltage at the time of the erase verification operation which concerns on 4th Embodiment.</figref><figref num="16">It is a figure explaining the voltage at the time of the erase verification operation which concerns on 4th Embodiment.</figref><figref num="17">It is a figure explaining the voltage at the time of the erase verification operation which concerns on 4th Embodiment.</figref>

Next, the non-volatile semiconductor storage device according to the embodiment will be described with reference to the drawings.

[First Embodiment] (Structure of Non-Volatile Semiconductor Storage Device According to First Embodiment) FIG. 1 is a block diagram showing a configuration of a NAND flash memory according to the first embodiment. FIG. 2 is an equivalent circuit diagram of the memory cell array of the NAND flash memory according to the first embodiment.

As shown in FIG. 2, the memory cell array 11 is configured by arranging NAND cell units NU in a matrix. Each NAND cell unit NU is connected to multiple (64 in the example of Fig. 2) electrically rewritable non-volatile memory cells MC0-MC63 connected in series, and both ends are connected to the bit line BL and the common source line CELSRC, respectively. It has selective gate transistors S1 and S2 for the purpose. Here, it is assumed that each memory cell MC has a laminated gate structure in which a gate insulating film, a floating gate electrode, an intergate insulating film, and a control gate electrode are laminated on a p-type well formed on a semiconductor substrate.

The control gate of the memory cell MC in the NAND cell unit NU is connected to a different word line WL0-WL63. The gates of the selection gate transistors S1 and S2 are connected to the selection gate lines SGD and SGS, respectively. A set of NAND cell units NU that share a word line constitutes a block that is a unit for data erasure. As shown in FIG. 2, a plurality of blocks BLK are arranged in the bit line direction. Each bit line BL is connected to a sense amplifier 12 described later. A memory cell MC commonly connected to one word line WL constitutes one page.

As shown in FIG. 1, the sense amplifier 12 is arranged in the bit line direction of the memory cell array 11 and is connected to the bit line BL to read data on a page-by-page basis and to hold a data latch that holds one page of write data. Also serves as. That is, reading and writing are performed on a page-by-page basis. The sense amplifier 12 is provided with a data cache that temporarily holds input / output data and a column selection circuit that performs column selection.

The row decoder 13 is arranged in the word line direction of the memory cell array 11, and selectively drives the word line WL and the selection gate lines SGD and SGS according to the row address. The row decoder 13 includes a word line driver and a selection gate line driver. Further, a column decoder 18 for controlling the column selection circuit in the sense amplifier 12 is provided along with the sense amplifier 12. The low decoder 13, the column decoder 18, and the sense amplifier 12 constitute a read / write circuit for reading and writing data of the memory cell array 11.

Data is transferred between the external input / output port I / O and the sense amplifier 12 by the input / output buffer 15 and the data line 14. That is, the page data read by the sense amplifier 12 is output to the data line 14, and is output to the input / output port I / O via the input / output buffer 15. The write data supplied from the input / output port I / O is loaded into the sense amplifier 12 via the input / output buffer 15.

The address data Add supplied from the input / output port I / O is supplied to the row decoder 13 and the column decoder 18 via the address register 17. The command data Com supplied from the input / output port I / O is decoded and set in the control signal generation circuit 16.

The chip enable signal / CE, address latch enable signal ALE, command latch enable signal CLE, write enable signal / WE, and read enable signal / RE external control signals are supplied to the control signal generation circuit 16. The control signal generation circuit 16 controls the overall operation of the memory operation based on the command Com and the external control signal, and also controls the internal voltage generation circuit 19 to obtain various internal voltages required for reading, writing, and erasing data. generate. These peripheral circuits constitute a control unit of the non-volatile semiconductor storage device of the embodiment.

[Data storage] Next, the outline of the data storage method of the non-volatile semiconductor storage device will be described with reference to FIG. FIG. 3 shows the relationship between the data stored in the memory cell MC and the threshold voltage.

FIG. 3A shows the relationship between the data (1, 0) and the threshold voltage distribution when the memory cell MC stores 1 bit (binary data). Figure 3 (b) shows the relationship between the data (11, 01, 10, 00) and the threshold voltage distribution when the memory cell MC stores 2 bits (quadruple data). Shown. Data "1" or "11" is assigned to the threshold voltage distribution E of the memory cell MC after the block is erased. Write data is assigned to the threshold voltage distributions A, B, and C, respectively.

In FIGS. 3 (a) and 3 (b), the read voltages VA, VB, and VC are voltages applied to the control gate (selected word line WL) of the selected memory cell MC selected when reading data. The read path voltage Vread is applied to the control gate (non-selected word line WL) of the non-selected memory cell MC when reading data, and conducts the non-selected memory cell MC regardless of the retained data. It shows the voltage. The voltage Vev is an erase verification voltage applied to the memory cell MC in order to confirm whether or not the erase is completed when the data in the memory cell MC is erased. The voltage Vev is, for example, a negative voltage (Vev &lt;0V). The magnitude relationship of each voltage described above is Vev &lt;VA &lt;VB &lt;VC &lt;Vread.

[Write operation] The write operation is performed on a page-by-page basis. Prior to the write operation, the bit line BL and the NAND cell unit NU are precharged according to the write data. Specifically, when writing data (moving the threshold voltage to the positive side), 0V is applied from the sense amplifier 12 to the bit line BL. This bit line voltage is transferred to the channel of the memory cell MC connected to the selection word line WL via the selection gate transistor S1 and the non-selection memory cell MC. Then, a write voltage (about 20 V) is applied to the selected word line WL in the selection block BLK. As a result, electric charge is injected into the floating gate electrode from the channel of the selected memory cell MC, and the threshold voltage of the memory cell MC moves to the positive side.

When no data is written to the selected memory cell MC, the power supply voltage Vdd is applied to the bit line BL. After this bit line voltage is transferred to the channel of the NAND cell unit NU, the channel becomes floating. When the write voltage described above is applied, the channel voltage rises due to capacitive coupling and no charge is injected into the floating gate electrode. Therefore, the threshold voltage of the memory cell MC does not change.

[Read operation] Data reading applies a reading voltage to the word line WL (selected word line) to which the selected memory cell MC in the NAND cell unit NU is connected. On the other hand, a read path voltage Vread (about 4V) is applied to the word line WL (non-selected word line) to which the non-selected memory cell MC is connected. At this time, the sense amplifier 12 detects whether or not a current flows through the NAND cell unit NU, and determines the data.

[Erase operation] FIG. 4 is a diagram for explaining the threshold voltage distribution during the erasing operation. 5 and 6 are diagrams for explaining the voltages applied during the erasing operation and the erasing verifying operation, respectively. As described above, the erasing operation is executed in block units. Here, erasing the memory cell MC of the selected block BLK may be referred to as erasing the block. As shown in Fig. 5, the elimination voltage Vera (20V or more) is applied to the cell well (CPWELL), and 0V is applied to all word lines WL in the selected block to draw the charge of the floating gate electrode of each memory cell MC to the cell well side. Therefore, the threshold voltage of the memory cell MC is lowered. At this time, in order to prevent the gate oxide films of the selection gate transistors S1 and S2 from being destroyed, the selection gate lines SGD and SGS are in a floating state. The bit line BL and the source line CELSRC are also floating. As a result, the threshold voltage of the memory cell MC is moved in the negative direction as shown in FIG.

[Erase verification operation] In the data erasure operation, after applying the erasure voltage Vera, a verify read operation (erase verify operation) is performed to confirm that the threshold voltage of the memory cell MC is equal to or less than the erasure verify voltage Vev.

FIG. 6 shows an example of reading whether or not the memory cell MC has been erased up to the threshold voltage Vev (for example, -1V). During the erase verify operation, a voltage of 1V is applied to the source line CELSRC, 0V is applied to all word lines of the selected block, and 2V is applied to the bit line BL. A predetermined voltage (for example, 4V) is applied to the selection gate lines SG1 and SG2 to make them conductive. The voltage application state shown in FIG. 6 is an example of a negative sense method in which a predetermined voltage is applied to the source line CELSRC and a negative voltage is applied to the selection word line WL to obtain a state similar to the case where reading is performed. The erase verification operation is not limited to the voltage value shown in FIG. 6, and it is sufficient if it can be detected that the threshold voltage of the memory cell MC is equal to or less than the erase verify voltage Vev.

When it is detected that the voltage of the bit line BL has dropped due to the current flowing from the bit line BL due to the voltage application state shown in FIG. 6, all the memory cell MCs in the NAND cell unit NU are sufficiently erased. It means that the erase operation is terminated. If the bit line voltage is maintained, it indicates that there are cells that are insufficiently erased, and the erase operation is performed again.

When the erasing operation is performed again, the erasing voltage Vera is set to a voltage larger by the step-up value ΔVera (&gt; 0) (step-up operation). Hereinafter, the erasure operation, the erasure verify operation, and the step-up operation are repeated until the data erasure is completed. As the number of repetitions increases, the erasing voltage Vera increases by Δ Vera.

[Soft program operation] As described above, the NAND flash memory erase operation collectively erases the memory cells MC in the block. Therefore, it is difficult to control the threshold voltage to an appropriate value for each memory cell MC. On the other hand, it is possible to suppress the variation in the threshold voltage of the memory cell MC by executing the soft program operation on the memory cell MC after the erasing operation.

[Soft program operation] FIG. 7 is a diagram for explaining the threshold voltage distribution during the operation of the soft program. Normally, the lower limit value control of the threshold voltage distribution is not performed in the above-mentioned erasing operation. Therefore, the threshold voltage distribution of the memory cell MC after the erasing operation is as shown in the threshold voltage distribution E'shown in FIGS. 4 and 7. In this case, the NAND cell unit NU may include a memory cell MC in an over-erased state. If there is a difference in the threshold voltage between the memory cell MCs, a data change (erroneous writing) may occur due to capacitive coupling between adjacent memory cell MCs in the subsequent operation. Therefore, a soft program operation using a weak write condition, that is, a soft program voltage Vsp (for example, 10 V to 15 V) lower than the normal write voltage (for example, 15 V to 20 V) is performed on all memory cell MCs to perform an over-erased state. To eliminate. As a result, the threshold voltage distribution of the memory cell MC becomes as shown in the threshold voltage distribution E shown in FIG. As a result of the soft program operation, the range of the threshold voltage distribution of the memory cell MC can be narrowed as a whole.

After this soft program operation, the soft program verify operation is performed. This is performed as an operation of confirming whether the threshold voltage of a predetermined number of memory cells MC exceeds the first software program verify voltage Vspv1. When the threshold voltage of a predetermined number of memory cells MC exceeds the first soft program verification voltage Vspv1 shown in FIG. 7, the first soft program verification pass is defined. The first software program verify voltage Vspv1 may be larger than the erase verification voltage or may be set to the same value.

If the number of memory cell MCs exceeding the first soft program verification voltage Vspv1 is less than the predetermined number, it indicates that the soft program operation is insufficient, and the soft program operation is performed again. When the soft program operation is performed again, the soft program voltage Vsp is set to a voltage larger by the step-up value ΔVsp (&gt; 0) (step-up operation). After that, the soft program operation, the soft program verification operation, and the step-up operation are repeated. As the number of repetitions increases, the soft program voltage Vsp increases by ΔVsp.

Further, in the soft program operation, if the threshold voltage of the memory cell MC rises too much, it is not possible to distinguish between the erase state and the write state. Therefore, when the threshold voltage of a predetermined number of memory cells MC exceeds the second soft program verification voltage Vspv2, the soft program operation is set as a fail.

The second soft program verify voltage Vspv2 can be set to a value larger than the first soft program verify voltage Vspv1. It is also possible to set the first soft program verify voltage Vspv1 and the second soft program verify voltage Vspv2 to the same value, and change the pass / fail conditions of the soft program operation depending on the number of memory cell MCs that have passed the verification. ..

In the first embodiment below, control of this software program operation will be described. First, the control of the soft program operation of the comparative example will be described with reference to FIG. 8, and then the control of the soft program operation of the first embodiment will be described.

FIG. 8 is a voltage waveform diagram showing an erasing operation, an erasing voltage step-up operation, a soft program operation, and a soft program voltage step-up operation of a comparative example. As described above, the voltage Vera is the voltage applied to the P-shaped well of the block in which the erasing operation is performed, and the voltage Vsp is the voltage applied to the word line WL in which the soft program operation is performed. Here, in the comparative example shown in FIG. 8, the soft program operation is executed after the erasing voltage Vera is applied seven times. Further, the comparative example shows that the erasing operation and the soft program operation are executed without considering the number of times the erasing voltage Vera is applied.

By the way, when the writing / erasing operation is repeatedly performed on one memory cell MC, the tunnel insulating film deteriorates. When the tunnel insulating film is deteriorated, the charge trapped in the charge storage layer is less likely to be released during the erasing operation, while the charge is easily injected during the soft program operation and the threshold voltage of the memory cell MC is likely to increase.

When executing the data erasure operation for one block, it is not preferable to execute the software program operation from the beginning even though the number of writes / erases is still small. For example, executing a soft program operation on a block that has a small number of writes / erases and can be erased accurately with only a small number of applied erase voltages Vera may slow down the erase operation.

On the other hand, when a soft program operation is executed on a block that has become easier to write due to a large number of writes / erases, an excessive charge may be injected into the memory cell MC due to the soft program voltage Vsp. If the gate insulating film is severely deteriorated, the threshold voltage distribution may exceed the second soft program verification voltage Vspv2 even with one soft program operation. As a result, the memory cell MC in the erased state returns to the written state again, and the erase operation cannot be completed normally.

[Erase operation and software program operation according to the first embodiment] From this point of view, in the first embodiment, a method of controlling whether or not to execute the software program operation is adopted. Whether or not to execute the soft program operation can be determined based on the number of times the erasing voltage Vera is applied during the erasing operation. Hereinafter, the erasing operation and the software program operation according to the present embodiment will be described with reference to FIGS. 9 and 10.

FIG. 9 is a flowchart illustrating the procedure of the erasing operation and the software program operation of the present embodiment. First, when the erasing operation is started, the erasing voltage Vera is applied to the P-type well in which the memory cell MC is formed (step S1). Next, an erase verification operation is performed to confirm that the threshold voltage of the memory cell MC is equal to or less than the erase verify voltage Vev (step S2). When it is determined by this erase verification operation that there is an insufficiently erased memory cell MC, the erase voltage Vera is set to a voltage larger by the step-up value ΔVera, and the erase voltage Vera is applied again. When it is determined that the memory cell MC in the predetermined range has been sufficiently erased by the erase verification operation, the number of times the erase voltage Vera applied up to that point is read out (step S3). The number of times the erasing voltage Vera is applied can be counted based on, for example, the signal used by the control signal generation circuit 16.

In the erasing operation of the present embodiment, when the number of times N of the erasing voltage Vera is applied is, for example, N 3 or 7 N, the erasing operation is terminated without executing the soft program operation. On the other hand, when the number of times N of application of the erasing voltage Vera is, for example, 3 &lt;N &lt;7, the soft program voltage Vsp is applied to execute the soft program operation (step S4). After that, the first soft program verify operation for confirming whether the threshold voltage of the predetermined number of memory cells MC exceeds the first soft program verify voltage Vspv1 is performed (step S4). If the soft program operation is insufficient, set the soft program voltage Vsp to a voltage larger by the step-up value ΔVsp and perform the soft program operation again.

When the first soft program verify operation is passed, the second soft program verify operation is performed to confirm whether or not the threshold voltage of a predetermined number of memory cells MC exceeds the second soft program verify voltage Vspv2 (step S6). When the number of memory cell MCs whose threshold voltage exceeds the second soft program verification voltage Vspv2 occurs in a predetermined number or more, the block cannot normally complete the erasing operation and the soft program operation, and is determined to be a defective block (step S7). .. On the other hand, when the second soft program verify operation is passed, the operation ends as if the erase operation and the soft program operation were executed correctly.

FIG. 10 is a voltage waveform diagram showing the voltage during the erasing operation and the soft program operation according to the first embodiment. As shown in FIGS. 10 (a) and 10 (c), when the number of times N of the erasing voltage Vera is applied is N 3 or 7 N, the soft program voltage Vsp is not applied and the operation ends. On the other hand, as shown in FIG. 10B, when the number of times N of application of the erasing voltage Vera is 3 &lt;N &lt;7, the soft program voltage Vsp is applied to execute the soft program operation. Further, as shown in FIG. 10 (b), the soft program voltage Vsp is stepped up when the soft program operation is executed (steps S4 and S5 in the flowchart of FIG. 9).

In the above-described embodiment, an example in which whether or not to execute the soft program operation is changed when the number of times N of application of the erasing voltage Vera is 3 or 7 times has been described. The boundary value at which whether or not to execute this software program operation is changed is not limited to 3 times and 7 times, and can be freely changed. The same applies to the following other embodiments.

[effect] In the erasing operation and the soft program operation according to the present embodiment, the soft program operation is not executed for a block that can be erased with sufficient accuracy only by the erasing voltage Vera with a small number of writes / erases and a small number of applications. .. Therefore, the erasing operation can be terminated quickly. On the other hand, the software program operation is not executed even for a block that is easy to write due to a large number of writes / erases. As a result, it is possible to prevent a situation in which the memory cell MC in the erased state returns to the written state again due to the software program operation and the erased operation cannot be normally completed. When the number of times the erasing voltage is applied is within a predetermined value, a soft program operation can be executed on the memory cell MC after the erasing operation to suppress the variation in the threshold voltage of the memory cell MC.

[Second Embodiment] Next, the non-volatile semiconductor storage device of the second embodiment will be described with reference to FIGS. 11 to 13. The overall configuration of the non-volatile semiconductor storage device of the present embodiment is the same as that of the first embodiment, and detailed description thereof will be omitted. Further, the parts having the same configuration as that of the first embodiment are designated by the same reference numerals, and duplicate description will be omitted.

At the time of the erasing operation in the first embodiment, the erasing operation was performed without changing the step-up value ΔVera of the erasing voltage Vera. On the other hand, in the present embodiment, the erasing operation is performed by changing the step-up value ΔVera of the erasing voltage Vera during the erasing operation. In the present embodiment, when the number of times the erasing voltage Vera is applied exceeds a predetermined number of times, the step-up value ΔVera is changed. Hereinafter, description will be made with reference to FIGS. 11 to 13.

11 to 13 are voltage waveform diagrams showing voltages during the erasing operation and the soft program operation according to the second embodiment. As shown in FIGS. 11 to 13 (a) and 13 (c), the soft program voltage Vsp is not applied even in this embodiment when the number of times N of the erasing voltage Vera is applied is N 3 or 7 N. End the operation. On the other hand, as shown in (b) of FIGS. 11 to 13, when the number of times N of application of the erasing voltage Vera is 3 &lt;N &lt;7, the soft program voltage Vsp is applied to execute the soft program operation.

Here, in the present embodiment, as shown in FIG. 11C, when the number of times the erasing voltage Vera is applied is the 11th or later, the step-up value is changed to ΔVera1 (&gt; ΔVera). If the erase verification operation is not passed even if the erase voltage Vera is applied many times, the memory cell MC in that range has deteriorated, and the charge trapped in the charge storage layer is less likely to be released. On the other hand, by setting the step-up value to ΔVera1, the potential difference between the charge storage layer and the channel can be made larger, and the charge can be easily released.

The change of the step-up value of the present embodiment is not limited to the one that increases the step-up value. As shown in FIG. 12 (c), the step-up value can be changed to ΔVera2 (&lt;ΔVera) when the erasing voltage Vera is applied 7 times or later. The memory cell MC in which the erasing voltage Vera is applied many times is deteriorated, and applying a high erasing voltage to the memory cell MC further deteriorates the memory cell MC. On the other hand, by setting the step-up value to ΔVera2, the potential difference between the charge storage layer and the channel is prevented from becoming too large. As a result, the erasing operation can be continued while suppressing the deterioration of the memory cell MC.

Moreover, the change of the step-up value is not limited to one time. As shown in FIGS. 13 (b) and 13 (c), the step-up value is changed to ΔVera2 (&lt;ΔVera) when the erasing voltage Vera is applied 5 times or later, and the step-up value is changed when the erase voltage Vera is applied 9 times or later. It can also be changed to ΔVera1 (&gt; ΔVera).

[effect] Even in the erasing operation and the soft program operation according to the present embodiment, the soft program operation is not executed for a block that can be erased with sufficient accuracy only by the erasing voltage Vera with a small number of writes / erases and a small number of applications. .. Therefore, the erasing operation can be terminated quickly. On the other hand, the software program operation is not executed even for a block that has become easier to write due to a large number of writes / erases. As a result, it is possible to prevent a situation in which the memory cell MC in the erased state returns to the written state again due to the software program operation and the erased operation cannot be normally completed. When the number of times the erasing voltage is applied is within a predetermined value, a soft program operation can be executed on the memory cell MC after the erasing operation to suppress the variation in the threshold voltage of the memory cell MC.

As described above, by increasing or decreasing the step-up value of the erasing voltage Vera, the erasing operation can be accelerated or the erasing operation can be performed while suppressing the deterioration of the memory cell MC. In this case, it is possible to freely select whether to increase or decrease the step-up value of the erasing voltage Vera according to the purpose of accelerating the erasing operation or suppressing deterioration of the memory cell MC. Further, the change timing and the increase / decrease range of the step-up value are not limited to the above-described embodiment. The timing of changing the step-up value and the amount of increase / decrease can be freely set in consideration of the speed of the erasing operation and the effect of suppressing the deterioration of the memory cell MC.

[Third Embodiment] Next, the non-volatile semiconductor storage device of the third embodiment will be described with reference to FIG. The overall configuration of the non-volatile semiconductor storage device of the present embodiment is the same as that of the first embodiment, and detailed description thereof will be omitted. Further, the parts having the same configuration as that of the first embodiment are designated by the same reference numerals, and duplicate description will be omitted.

This embodiment is also the same as the first and second embodiments in that it controls whether or not the soft program operation is executed by applying the soft program voltage Vsp based on the number of times the erasing voltage Vera is applied. Here, in the erasing operation in the second embodiment, the erasing operation is performed by changing the step-up value ΔVera of the erasing voltage Vera based on the number of times the erasing voltage Vera is applied. On the other hand, in the present embodiment, when the upper limit of the threshold voltage distribution of the memory cell MC of the erase block falls below a predetermined value, the step-up value ΔVera of the erase voltage Vera is changed. Hereinafter, description will be made with reference to FIG.

FIG. 14 is a diagram for explaining the threshold voltage distribution during the erasing operation according to the third embodiment. In the first embodiment described above, the erase verification operation is performed depending on whether or not the threshold voltage of the memory cell MC is equal to or less than the erase verify voltage Vev. On the other hand, in the present embodiment, two types of voltages, Vev1 (for example, 1V) and Vev2 (for example, 0V), are used as the erasure verification voltage. In the erasing operation of the present embodiment, the step-up value of the erasing voltage Vera is set to ΔVera until the upper limit of the threshold voltage distribution of the memory cell MC of the erasing block falls below the erase verification voltage Vev1.

As shown in FIG. 14 (a), the step-up value is changed to ΔVera1 (&gt; ΔVera) during the erasing voltage application operation (numbers 5 to 6) after the upper limit of the threshold voltage distribution falls below the erasure verification voltage Vev1. be able to. Further, as shown in FIG. 14 (b), when the erasing voltage application operation (number 3 to number 4, number 4 to number 5) after the upper limit of the threshold voltage distribution falls below the erasing verification voltage Vev1, the step-up value is set. It can also be changed to ΔVera2 (&lt;ΔVera).

[effect] Also in this embodiment, it is controlled whether or not the soft program operation is executed by applying the soft program voltage Vsp based on the number of times the erasing voltage Vera is applied. Therefore, the effect as described in the first embodiment described above can be obtained. Further, according to the erasing voltage step-up operation of the present embodiment, the following effects can be obtained. As shown in FIG. 14 (a), if the erase verification operation is not passed even if the erase voltage Vera is applied many times, the memory cell MC in that range is deteriorated. When a large amount of erasing voltage Vera is applied to this memory cell MC, deterioration further progresses. On the other hand, by setting the step-up value to ΔVera1 after the upper limit of the threshold voltage distribution falls below the erase verification voltage Vev1, the erase operation can be completed quickly and the deterioration of the memory cell MC can be suppressed. Further, as shown in FIG. 14 (b), by setting the step-up value to ΔVera2 after the upper limit of the threshold voltage distribution falls below the erase verification voltage Vev1, the threshold voltage can be adjusted immediately before the end of the erase operation. It can also be done in detail. As a result, the erasing operation can be completed with high accuracy.

Further, as shown in FIG. 14A, whether or not the soft program operation is executed may be determined by the number of times the erase voltage Vera is applied when the upper limit of the threshold voltage distribution falls below the erase verification voltage Vev1. As mentioned above, the degraded memory cell MC is more likely to be written. Therefore, the threshold voltage before the start of the erase operation of the deteriorated memory cell MC is higher than the threshold voltage before the start of the erase operation of the deteriorated memory cell MC. In that case, the deteriorated memory cell MC is located near the upper limit of the threshold voltage distribution. Here, the deterioration state of the memory cell can be determined by monitoring the fluctuation of the threshold voltage distribution at the initial stage (the period until the upper limit of the threshold voltage distribution falls below the erase verification voltage Vev1) in the erase operation. As a result, it becomes possible to more accurately determine the deterioration state of the memory cell MC, which is a reference for determining whether or not the software program operation is executed.

Further, as shown in FIG. 14 (b), whether or not the soft program operation is executed may be determined by the number of times the erase voltage Vera is applied when the upper limit of the threshold voltage distribution falls below the erase verification voltage Vev1. Here, the step-up value ΔVera2 is smaller than ΔVera. The setting of the step-up value ΔVera2 is intended to finely adjust the threshold voltage immediately before the end of the erasing operation. That is, the number of times the erase voltage Vera is applied after the upper limit of the threshold voltage distribution falls below the erase verification voltage Vev1 has little relation to the deterioration of the memory cell MC. Deterioration of the memory cell MC can be accurately determined by the number of times the erase voltage Vera is applied until the upper limit of the threshold voltage distribution falls below the erase verification voltage Vev1.

[Fourth Embodiment] Next, the non-volatile semiconductor storage device of the fourth embodiment will be described with reference to FIGS. 15 to 17. The overall configuration of the non-volatile semiconductor storage device of the present embodiment is the same as that of the first embodiment, and detailed description thereof will be omitted. Further, the parts having the same configuration as that of the first embodiment are designated by the same reference numerals, and duplicate description will be omitted.

This embodiment is also the same as the above-described embodiment in that it controls whether or not the soft program operation is executed by applying the soft program voltage Vsp based on the number of times the erasing voltage Vera is applied. Here, in the erasing operation in the second and third embodiments, the erasing operation is performed by changing the step-up value ΔVera of the erasing voltage Vera. On the other hand, in the present embodiment, the set voltage at the time of erasing verification operation is changed based on the number of times the erasing voltage Vera is applied. Hereinafter, FIGS. 15 to 17 and FIG. 6 showing the erasure verification voltage of the first embodiment will be described.

FIG. 6 shows the erasing verify voltage applied state of the first embodiment. Here, the voltage of the source line voltage VCELSRC and the voltage of the selected word line WL during the erase verification operation can be changed based on the state of the erase operation. For example, when the number of times the erasing voltage Vera is applied exceeds a predetermined number of times (for example, 10 times), the source line voltage VCELSRC during the erasing verify operation is lowered as shown in FIG. 15, or the voltage of the selected word line WL is changed. Can be raised. Either one or both of the voltage values may be changed. The voltage application state shown in FIG. 15 shows an example of reading whether or not the memory cell MC has been erased up to the threshold voltage Vev (for example, 0V).

When the number of times the erasing voltage Vera is applied exceeds a predetermined number of times (for example, 10 times), the source line voltage VCELSRC during the erasing verify operation is increased or the voltage of the selected word line WL is increased as shown in FIG. Can be lowered. Either one or both of the voltage values may be changed. The voltage application state shown in FIG. 16 shows an example of reading whether or not the memory cell MC has been erased up to the threshold voltage Vev (for example, -2V).

When the number of times the erasing voltage Vera is applied exceeds a predetermined number of times (for example, 10 times), the erasing verification operation of the memory cell MC connected to the even-numbered word line WL or the odd-numbered word line WL is performed as shown in FIG. An individual method may be adopted. In this case, a voltage (for example, 5V) that ensures that the memory cell MC conducts is applied to the word line WL that does not perform the erase verification operation. After the erase verification operation of the memory cell MC connected to the even word line WL or the odd word line WL is performed respectively, it is determined whether or not the verification pass is based on the result of the two operations.

[effect] Also in this embodiment, it is controlled whether or not the soft program operation is executed by applying the soft program voltage Vsp based on the number of times the erasing voltage Vera is applied. Therefore, the effect as described in the first embodiment described above can be obtained. Further, according to the erasing voltage step-up operation of the present embodiment, the following effects can be obtained. If the erase verification operation is not passed even if the erase voltage Vera is applied many times, the memory cell MC in that range has deteriorated. At this time, as shown in FIG. 15, if the applied voltage is changed so as to raise the erase verification voltage Vev, the erase operation ends quickly, and deterioration of the memory cell MC can be suppressed. In addition, the erase verification voltage Vev is set high in advance so that the erase operation ends quickly before the deterioration of the memory cell MC, while after the deterioration of the memory cell MC, the erase verify voltage is set as shown in FIG. It can be set low to ensure that the threshold voltage of the memory cell MC is negative. Then, by individually performing the erase verification operation of the memory cell MC connected to the even word line WL or the odd word line WL, the erase verify operation can be accurately executed. The voltage of the erase verification operation is not limited to the voltage values shown in FIGS. 15 to 17, and it is sufficient if it can be detected that the threshold voltage of the memory cell MC is equal to or less than the erase verify voltage Vev of a predetermined value.

Further, the condition of the first software program verification may be changed according to the change of the erasure verification voltage Vev shown in FIG. The conditions for the first soft program verification can be changed by increasing the first soft program verification voltage Vspv1 applied to the selected word line WL or decreasing the source line voltage VCELSRC at the time of soft program verification.

As an example, when the number of times the erasing voltage Vera is applied is, for example, N 3 or 7 N, the erasing operation is terminated without executing the soft program operation, and the number of times the erasing voltage Vera is applied N is, for example, 3 &lt;N &lt;7. At this time, consider the case where the soft program voltage Vsp is applied to execute the soft program operation. Further, when the number of times N of the erasing voltage Vera is applied exceeds 5, the voltage of the selected word line WL during the erasing verify operation shall be increased, or the source line voltage VCELSRC shall be decreased. Then, when the number of times N of the erasing voltage Vera is applied exceeds 5, the voltage of the selected word line WL during the soft program verification operation shall be increased, or the source line voltage VCELSRC shall be decreased.

In this case, when the erasing voltage Vera is applied four times N, the voltage of the source line voltage VCELSRC or the selected word line WL during the erasing verify operation is not changed. Also, the source line voltage VCELSRC or the selected word line WL voltage during soft program operation is not changed. On the other hand, when the number of times N of the erasing voltage Vera is applied is 5 to 6 times, the voltage of the source line voltage VCELSRC or the selected word line WL during the erasing verify operation is changed. In addition, the voltage of the source line voltage VCELSRC or the selected word line WL during the operation of the soft program is also changed. That is, it is possible to eliminate the inconsistency that the conditions at the time of erasure verification are relaxed but the conditions at the time of soft program verification are not relaxed. As a result, it is possible to optimize the determination of the threshold distribution after the erasing operation and the threshold distribution during the soft program operation.

[Other] Although some embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof. For example, in the above embodiment, a non-volatile semiconductor device that stores binary data and quaternary data in one memory cell MC has been described as an example, but the present invention is not limited to this, and the present invention is not limited to this. Needless to say, it can be applied to a multi-bit storage method rather than a method.

11 ... Memory cell array, 12 ... Sense amplifier, 13 ... Low decoder, 14 ... Data line, 15 ... Input / output buffer, 16 ... Control signal generation circuit, 17 ... Address Register, 18 ... column decoder, 19 ... internal voltage generation circuit.