Network connection device, switching circuit device, and method for learning and processing of address

This technology relates to a technology related to address learning in a network connection device such as a switch.

Conventionally, in a layer 2 (L2) switch, address learning for registering a source address (SA: Source Address) in FDB (Forwarding Data Base) has been performed by switch hardware. For example, as shown in FIG. 1, a switch LSI (Large Scale Integrated circuit), which is switch hardware, has a port, an FDB, and a management unit. Then, the FDB is searched by the source address (SA) of the packet received on the port (step (1001)), and the SA search result is notified to the management unit (step (1002)). The management department registers the SA in the FDB if it is not registered in the FDB (step (1003)). However, the management unit included in such a switch LSI can only perform simple SA registration, and cannot deal with cases where filtering by advanced processing such as authentication is required. As a case where filtering by advanced processing is required, for example, the VLAN of the received packet (Virtual Local Area Network) and the VLAN of the address to be registered There are cases where the IDs are different, cases where you want to register multiple entries with different VLAN IDs when registering SA for received packets, and cases where address translation is performed for ports with different domains.

In addition, there are the following techniques for performing address learning with such hardware. That is, the transfer processing required time of the packet is obtained from the packet length, the actual execution time of the transfer destination determination process is measured, and the difference time between the transfer process required time and the measured actual execution time of the transfer destination determination process is increased. It is decided whether or not to execute additional processing such as MAC address learning. According to this, compared to the case where additional processing such as MAC address learning is always performed, packet discard is reduced, and an inexpensive and cost-effective system can be configured. Further, it is possible to efficiently perform address learning without only learning about a specific address.

<p><patcit num="1"><text>Japanese Unexamined Patent Publication No. 2006-295550</text></patcit></p>

<p> As mentioned above, address learning using only hardware cannot support various address learning. Therefore, even if address learning by software is introduced, not all problems are simply solved.</p><p> Therefore, an object of the present technology is to enable appropriate software-based address learning in a network connection device such as a switch.</p>

<p> This network connection device performs a predetermined learning process for a specific address in response to a request from the switch unit and a switch unit that outputs a packet received from the first port among a plurality of ports to the second port. It has a processor that executes a management program. Then, the switch unit described above is an entry including the address of the device connected to the port, learning data indicating whether or not the processor has learned the address, and the identifier of the port to which the device is connected. Has a table to store. Then, when the source address of the specific device included in the packet received from the specific port is not registered in the above table, the switch unit is learning data indicating that the source address and the source address are being learned. When an entry containing the identifier of a specific port and the identifier of a specific port is registered in the above table, the processor is requested to learn the source address, and a second packet containing the source address of a specific device is received from the specific port. When an entry including a source address of a specific device and learning data indicating that learning is being performed is registered in the above table, the processor is not requested to learn the source address. Further, when a request for changing the training data of a specific entry in the table to trained is received from the processor, the training data of the specific entry in the table is set to trained.</p>

<p> Address learning by software can be appropriately performed in the network connection device.</p>

<figref num="1">FIG. 1 is a diagram for explaining the prior art.</figref><figref num="2">FIG. 2 is a diagram illustrating a technique that is a prerequisite for an embodiment of the present technique.</figref><figref num="3">FIG. 3 is a functional block diagram of the L2 switch according to the present embodiment.</figref><figref num="4">FIG. 4 is a diagram showing a configuration example of FDB.</figref><figref num="5">FIG. 5 is a diagram for explaining the structure of the queue in the present embodiment.</figref><figref num="6">FIG. 6 is a diagram showing a main processing flow of the present embodiment.</figref><figref num="7A">FIG. 7A is a diagram showing a processing flow of SA processing.</figref><figref num="7B">FIG. 7B is a diagram showing a state of FDB or the like for explaining SA processing.</figref><figref num="8">FIG. 8 is a diagram showing the states of the start pointer storage unit and the end pointer storage unit for explaining the SA processing.</figref><figref num="9">FIG. 9 is a diagram showing a state of FDB or the like for explaining SA processing.</figref><figref num="10">FIG. 10 is a diagram showing the states of the start pointer storage unit and the end pointer storage unit for explaining the SA processing.</figref><figref num="11">FIG. 11 is a diagram showing a processing flow of interrupt generation processing.</figref><figref num="12">FIG. 12 is a diagram showing a processing flow of internal resource access processing from the processor.</figref><figref num="13">FIG. 13 is a diagram showing a processing flow of address registration interrupt processing.</figref><figref num="14">FIG. 14 is a diagram showing a processing flow of address registration interrupt processing.</figref><figref num="15">FIG. 15 is a diagram showing a state of the FDB or the like for explaining the address registration interrupt processing.</figref><figref num="16">FIG. 16 is a diagram showing the states of the start pointer storage unit and the end pointer storage unit for explaining the address registration interrupt processing.</figref><figref num="17">FIG. 17 is a diagram showing a state of the FDB or the like for explaining the address registration interrupt processing.</figref><figref num="18">FIG. 18 is a diagram showing the states of the start pointer storage unit and the end pointer storage unit for explaining the address registration interrupt processing.</figref><figref num="19">FIG. 19 is a diagram showing a processing flow of DA processing.</figref>

[Premises of Embodiments of the present technology] As mentioned in the background technology, address learning using only hardware in the L2 switch cannot support advanced address learning patterns such as MAC VLAN authentication, and flexible address learning patterns such as switching the presence or absence of learning and changing the learning content. Therefore, it is conceivable to introduce a switch management processor separately from the switch LSI and execute a management program for executing various address learning on the switch management processor.

An example of such a case is shown in FIG. In the example of FIG. 2, the switch LSI has a plurality of ports, an FDB, and a management unit. The switch LSI is connected to the switch management processor by a communication path (bus or network), and the switch management processor executes a management program on the operating system (OS) and the OS. In such a configuration, the FDB is searched by the source address (SA) of the packet received on the port (step (1101)), and the SA search result is notified to the management unit (step (1102)). If the SA is not registered in the FDB, the management unit interrupts the processor with a learning request (step (1103)).

After that, information such as SA is passed from the management unit of the switch LSI to the management program executed by the switch management processor, and the contents of FDB are passed through the switch management processor and the management unit in response to a request from the management program. Or something. Address learning is performed by the management program using the data passed in this way, and as a result, a request instructing whether to register or discard the SA in the FDB is output from the switch management processor to the management unit of the switch LSI ( Step (1104)). Then, the management unit of the switch LSI registers the SA in the FDB or destroys the SA in response to the request from the switch management processor (step (1105)).

In address learning using such a management program, the latency of steps (1102) to (1105) is large, and the learning throughput is low. Then, if packets containing SAs that are not registered in FDB continue, learning will not be in time and learning will be missed. To address this, subsequent SA search results need to be masked or queued. However, when masking, new learning requests are naturally discarded during masking, resulting in omissions. In the case of simple queuing, learning requests for the same SA are continuously added to the queue. Things can happen. In this case, resources including the bandwidth between the switch LSI and the switch management processor are wasted, and there arises a problem that the throughput is further reduced.

In this way, address learning cannot be properly performed by simply causing the switch management processor to execute a management program for performing address learning separately from the switch LSI.

In the present embodiment, a configuration for solving such a specific problem is introduced.

[Specific contents of this embodiment] FIG. 3 shows a configuration example of the L2 switch 100 according to the present embodiment. The L2 switch 100 includes a switch LSI 110 and a switch management processor 120 connected to the switch LSI 110 by a communication path 131 and an interrupt signal line 132. The switch LSI 110 includes a port unit (ports 1 to 3 in FIG. 3) connected to a terminal device or the like (terminals 101 to 103 in FIG. 3), an FDB 111 connected to the port unit, and a management unit connected to the FDB 111. It has a tag storage unit 113 that is connected to the management unit 112 and functions as a queue for managing the order of address learning. As described below, the FDB 111 and the tag storage unit 113 may be integrated as shown by the dotted line in FIG. In addition, a learning state flag 1111 indicating whether or not address learning is in progress is newly added to FDB111 as described below. Further, the management unit 112 has a head pointer storage unit 1121 that stores a head pointer that functions as a queue for managing the order of address learning together with the tag storage unit 113, and a tail pointer storage unit 1122 that stores the tail pointer. Further, the switch management processor 120 executes the management program 121 on the OS.

Figure 4 shows an example of the data configuration of FDB111. As shown in FIG. 4, the output port information in which the identifier of the port to which the device of the MAC address is connected is registered in association with the MAC address which is the search key, and learning whether the MAC address is being learned. A learning state flag 1111 indicating whether or not it has been completed is registered. Each row of such a table is referred to as an entry below, and its storage position is referred to as an index below.

By using such FDB111, it is possible to filter duplicate address learning requests as described below. When a new SA is received, a new entry is registered in FDB111 and the learning status flag 1111 is set to "learning". As a result of address learning by the management program 121 When an entry update request is received from the switch management processor 120, the learning status flag 1111 is changed to "learned", and packet transfer based on the entry is started. On the other hand, when the entry deletion request is received from the switch management processor 120, the corresponding entry is deleted.

Specifically, when a packet (= MAC frame) is received from the port portion, an SA search is performed on the FDB 111 with the SA (= source MAC address) of the packet. At that time, if the corresponding entry does not exist in FDB111, a new entry in which the learning status flag 1111 indicates "learning" is added to FDB111, and address learning is performed. On the other hand, if the corresponding entry exists and the learning state flag 1111 is "learning", it is not necessary to perform address learning any more, so that the address learning request is suppressed. This makes it possible to filter duplicate address learning and improve the throughput of address learning. On the other hand, if the learning state flag 1111 is "learned", address learning is not particularly required and processing is performed as usual.

Further, when a packet is received from the port portion, a DA search is performed on the FDB 111 even at the destination address (DA: Destination address. = Destination MAC address) of the packet. At this time, if the corresponding entry does not exist, the packet is broadcast to all ports. If the corresponding entry exists and the learning state flag 1111 is "learning", the packet is broadcast to all ports in the same state as if the corresponding entry does not exist. That is, each device connected to each port is made to judge whether the packet is addressed to itself. On the other hand, if the corresponding entry exists and the learning status flag 1111 is "learned", the packet is forwarded to the corresponding port as usual.

Next, the queue for managing the order of address learning will be described with reference to FIG. In the tag storage unit 113, a pointer about the corresponding entry of FDB111 is stored. This pointer points to an entry for the next SA to perform address learning. In the example of FIG. 5, the pointer for the entry with the index Next0 is the index Next1 for the entry for the SA for which address learning should be performed next. The pointer of the entry of index Next1 is the index Next2 of the entry for the SA for which address learning should be performed next. The pointer of the entry of index Next2 is NULL because there is no SA to perform address learning next. Although not explicitly shown in FIG. 5, pointers for entries for which the learning state flag 1111 is "learned" are not used (that is, treated as Don't care).

Further, the management unit 112 holds a start pointer (Next0 in FIG. 5) that points to the entry of FDB111 that should perform address learning first, and a end pointer that points to the entry of FDB111 that should perform address learning last. (Next2 in Fig. 5) is held.

In this way, the entries being learned in FDB111 are managed in a queue structure to improve the access efficiency of the switch management processor 120. That is, since the access from the switch management processor 120 is limited to the first entry being learned in the queue structure, the overhead for access is reduced and the processing performance is improved.

In addition, since the number of addresses that can be originally learned is limited to the size of FDB111 (that is, the number of learned entries + the number of learning entries the total number of FDB entries), it is recommended to provide a tag (pointer area) in association with each entry of FDB111. It is efficient. Further, if the tag storage unit 113 is provided in the FDB 111, the free area of the FDB 111 can be used more efficiently.

Next, an outline of the operation of the L2 switch 100 according to the present embodiment shown in FIG. 3 will be described. For example, if terminal 101 is connected to port 1 and port 1 receives a packet with source address SA (MAC address = A1) from terminal 101, this SA (MAC address = A1) searches for FDB111 (step (step (step)). 1)). Then, the SA search result is notified to the management unit 112 (step (2)). If the SA search result indicates that the SA is not registered in FDB111, the management unit 112 adds an entry for the SA to FDB111 (step (3)). The learning status flag 1111 of the additional entry is "learning". In addition, the start pointer storage unit 1121, the end pointer storage unit 1122, and the tag storage unit 113 of the management unit 112 perform necessary processing for registering additional entries in the queue.

Further, when the queue size becomes 1 or more, the management unit 112 interrupts the switch management processor 120 via the interrupt signal line 132 (step (4)). The management program 121 of the switch management processor 120 that has received the interrupt accesses the management unit 112 of the switch LSI 110, identifies the first entry of the queue, acquires the data of the first entry of the queue via the communication path 131, and addresses it. Perform a predetermined process for learning (step (5)). As a result of predetermined address learning by the management program 121 of the switch management processor 120, an entry update request is made when the SA of the first entry in the queue can be registered, and an entry deletion request is made when the SA of the first entry in the queue cannot be registered. Output to the management unit 112 of the switch management processor 120 (step (6)).

If the request from the switch management processor 120 is an entry update request, the management unit 112 changes the learning status flag 1111 of the corresponding entry to "learned", and if the request is an entry deletion request, the management unit 112 deletes the corresponding entry in the FDB 111. (Step (7)).

For steps (5) to (7), the switch management processor 120 repeats the process until the queue is empty.

By carrying out such processing, address learning can be carried out without waste and without omission.

Hereinafter, the details of the processing of the L2 switch 100 will be described with reference to FIGS. 6 to 19. First, for example, a packet is received from any of terminals 101 to 103 on any of ports 1 to 3 (Fig. 6: Step S1). Then, SA processing of the received packet by SA is performed (step S3). This process will be described in detail below. In addition, DA processing of the received packet by DA is also performed (step S5). DA processing is processing for determining how to forward a received packet, and will be described in detail below. Such processing is performed every time a packet is received.

Next, SA processing will be described with reference to FIG. 7A. First, the SA of the received packet is searched for FDB111 (step S11). Since this step corresponds to step (1) in FIG. 3, it is also indicated by * (1) in FIG. 7A.

Then, it is determined whether the SA of the received packet is not registered in FDB111 (step S13). This step corresponds to step (2) in FIG. If the SA is already registered in FDB111, address learning for the SA is not performed regardless of whether the learning status flag 1111 of the entry of the SA is "learning" or "learned" (step S25). If it is "learning", duplicate address learning is avoided, and if it is "learned", learning is originally unnecessary, so nothing is done like this (displayed as a dotted block in Fig. 7), and the original processing Return to.

On the other hand, assuming that the SA of the received packet is not registered in the FDB 111, the management unit 112 indicates that the new entry (MAC address = SA, learning status flag 1111 = learning, pointer to the corresponding entry in the tag storage unit 113) in the FDB 111. = NULL) is added to index = New1 (step S15). This step corresponds to step (3) in FIG. In addition, FDB111 is in a state as shown in FIG. 7B.

Then, the management unit 112 determines whether the tail pointer is NULL (step S17). If the end pointer is NULL, it means that there was no entry to learn the address in the queue, and the new entry added this time becomes the start entry. If the end pointer is NULL, the management unit 112 sets the index (New1) of the additional entry in the start pointer (step S19). Then, the process proceeds to step S23. On the other hand, if the tail pointer is not NULL, a new entry must be set at the end because there is already an entry being trained. Therefore, the index (New1) of the additional entry is set in the pointer field of the entry pointed to by the tail pointer (that is, the corresponding field of the tag storage unit 113) (step S21). This means that the additional entry can be registered at the end of the queue. Then, the process proceeds to step S23.

In step S23, the management unit 112 sets the index (New1) of the additional entry in the tail pointer (step S23). Then, it returns to the original processing.

When steps S19 and S23 are executed, the index New1 is registered in the start pointer storage unit 1121 and the end pointer storage unit 1122, as shown in FIG. On the other hand, when steps S21 and S23 are executed, as shown in FIG. 9, for FDB111, the pointer field (corresponding field of the tag storage unit 113) for the entry that has been the last entry and the index is New0. , Register the index New1 of the entry added this time. Further, as shown in FIG. 10, the index Head0 of the first entry is stored in the start pointer storage unit 1121, and the index New1 of the entry added this time is registered in the end pointer storage unit 1122.

In this way, when a packet containing an unregistered SA is received, a new entry is registered in FDB111 and the new entry is set at the end of the queue.

Next, the processing of the management unit 112 that monitors the end pointer storage unit 1122 will be described with reference to FIG. The management unit 112 monitors the end pointer storage unit 1122 and determines whether the end pointer is NULL (Fig. 11: Step S31). If NULL, there is no address to learn, so wait until the tail pointer is registered. On the other hand, if the end pointer is registered, the management unit 112 asserts the address registration request interrupt to the switch management processor 120 (step S33). This step corresponds to step (4) in FIG. Then return to step S31.

When the tail pointer is set in this way, the address registration request interrupt is asserted to the switch management processor 120, and address learning is started.

In addition, the management unit 112 executes the following processing in response to a request from the switch management processor 120. Specifically, the management unit 112 determines whether or not some processing request has been received from the switch management processor 120 (FIG. 12: step S41), and if not, waits until it is received. On the other hand, when some processing request is received from the switch management processor 120, it is determined whether it is an access request to the pointer (specifically, the start pointer or the end pointer) in the management unit 112 (step S43). If it is an access request (read / write) to the pointer in the management unit 112, the management unit 112 accesses the pointer of the request destination and outputs the result to the switch management processor 120 (step S45). This step is, for example, part of step (5) of FIG. Then return to step S41.

On the other hand, if it is not an access request to the pointer in the management unit, the management unit 112 determines whether it is an access request to the FDB 111 (step S47). If it is an access request to FDB111, the management unit 112 accesses FDB111 according to the request and outputs the result to the switch management processor 120 (step S49). For example, in response to a request to read the contents of the entry, the contents of the entry may be read and output to the switch management processor 120, or the learning state flag 1111 of the entry may be changed or the entry may be changed in response to the request. Delete it. This step is part of step (7) in FIG. After step S49, the process returns to step S41. If it is not an access request to FDB111, the process returns to step S41.

The management unit 112 also operates as an interface with the switch management processor 120 in this way.

Next, the processing of the management program 121 of the switch management processor 120 will be described with reference to FIGS. 13 to 18. First, the switch management processor 120 receives an address registration interrupt from the switch LSI 110 via the interrupt signal line 132 (step S51). This step corresponds to step (4) in FIG. Then, the management program 121 executed by the switch management processor 120 instructs the management unit 112 of the switch LSI 110 to acquire the start pointer, and acquires the start pointer from the management unit 112 of the switch LSI 110 (step S53). This step corresponds to step (5) in FIG. 3 and is related to step S45 in FIG. Then, it is determined whether the start pointer is NULL (step S55). This step is effective when it is a confirmation of the end of the process and returns from the subsequent process. That is, it is not NULL at first. If the start pointer is NULL, the process ends.

If the start pointer is not NULL, the management program 121 instructs the management unit 112 to acquire the entry pointed to by the start pointer (for example, the index "Head1"), and the data of the entry pointed to by the start pointer from the management unit 112 of the switch LSI 110. (Step S57). Here, the pointer stored in the corresponding field of the tag storage unit 113 is also acquired at the same time. This step corresponds to a portion of step (5) of FIG. 3 and relates to step S49 of FIG. For example, as shown in FIG. 15, for the entry of the index "Head1", the MAC address is SB, the output port information is port 2, the learning state flag 1111 is learning, and the pointer of the corresponding field of the tag storage unit 113. Is New2.

After that, the management program 121 refers to the pointer field value (the value of the corresponding field of the tag storage unit 113) of the acquisition entry (for example, the entry whose index is "Head1") with respect to the head pointer storage unit 1121. ) Is set to the management unit 112 of the switch LSI 110 (step S59). This replaces the first entry with the next entry. As shown in FIG. 16, "New2" is registered in the start pointer storage unit 1121. However, if the pointer field value of the acquisition entry is "NULL" like the entry of the index "New2" in FIG. 15, it is instructed to set "NULL". This step also corresponds to a portion of step (5) of FIG. 3 and relates to step S43 of FIG. Then, the processing shifts to the processing of FIG. 14 via the terminal B.

Moving on to the description of the process of FIG. 14, a predetermined judgment process (that is, address learning process) is performed using the contents of the acquisition entry (step S61). For example, it is determined whether it matches a specific address / VLAN combination, and if it is applicable, registration is rejected. In addition, there are various variations such as acquiring IP packet information as well as FDB111 entry to determine whether or not to register. However, such a process itself is not the gist of the present embodiment and is a conventionally known process, and will not be described further.

Then, the management program 121 determines whether to register the determination result SA (SB in the example of FIG. 15) in step S61 (step S63), and when registering the SA, the acquisition entry (index Head1"" An entry update request is output to the management unit 112 of the switch LSI 110 so as to change the learning status flag 1111 of the entry) to learned (step S65). This step corresponds to step (7) in FIG. 3 and relates to step S49 in FIG. Then, the process proceeds to step S69. If such a process is performed, FDB111 and the like change from the state shown in FIG. 15 to the state shown in FIG.

On the other hand, when the SA is not registered, the management program 121 outputs an entry deletion request to the management unit 112 of the switch LSI 110 so as to delete the acquisition entry (entry of the index Head1) (step S67). This step corresponds to step (7) in FIG. Then, the process proceeds to step S69.

In step S69, the management program 121 determines whether the start pointer is NULL. Judgment is made based on whether or not the management unit 112 of the switch LSI 110 is instructed to set NULL as the start pointer in step S59. If the start pointer is not NULL, the process returns to step S51 in FIG. 13 via terminal C.

On the other hand, if the start pointer is NULL, the management program 121 instructs the management unit 112 of the switch LSI 110 to set the end pointer to NULL (step S71). As a result, it is determined that there is no entry for address learning in the queue of the switch LSI 110. That is, as shown in FIG. 16, NULL is registered in both the start pointer storage unit 1121 and the end pointer storage unit 1122 in the management unit 112. This step relates to step S45 of FIG. Then, the process returns to step S51 in FIG. 13 via the terminal C.

By performing such processing, address learning can be appropriately performed from the first entry in the queue of the switch LSI 110. Furthermore, the queue is updated appropriately so that address learning is performed for entries that should be learned in order if they exist.

Next, DA processing will be described with reference to FIG. First, the DA of the received packet is searched for FDB111 (step S81). Then, it is determined whether the DA is not registered in FDB111 (step S83). If the DA is not registered in FDB111, it means that it is not known which port the device related to the DA is connected to, so the packet is forwarded to all ports except the port that received the packet (step). S89). Then, it returns to the original processing.

On the other hand, if the DA has already been registered in FDB111, the learning status flag 1111 is set in the present embodiment, so this is confirmed. And if the learning state flag 1111 indicates that it is learning, it has not yet decided whether or not to register for this address, and there may be devices on other ports that should process this packet. Therefore, the process proceeds to step S89, and the packet is forwarded to all ports except the port that received the packet.

On the other hand, when the learning state flag 1111 indicates that learning has been completed, the packet is output to the output port included in the entry (step S87). If it has already been learned, the corresponding entry may be used, so the packet is output in this way. Then, it returns to the original processing.

By performing the above processing, if the DA is not registered in FDB111 as learned, it is determined whether the packet should be forwarded to all ports and received by the device connected to those ports. It is designed to let you.

As described above, by properly managing the learning state flag 1111, duplicate address learning can be efficiently filtered, and when the processing speed of the switch management processor 120 is slow by properly managing the queue. However, the address learning request will not be missed. That is, by adding the minimum resources of the learning state flag 1111 and the tag storage unit 113, the efficiency of address learning is improved and there is no omission. As a result, even if advanced address learning is performed by the switch management processor 120, the performance impact due to it can be suppressed to a very small value.

Although the embodiment of the present technology has been described above, the present technology is not limited to this. For example, the functional block diagram shown in FIG. 3 is an example, and in some cases, the switch LSI 110 and the switch management processor 120 may be integrated. Even in such a case, the present embodiment works.

Further, as for the processing flow, as long as the processing result does not change, the processing order may be changed or the processing may be executed in parallel.

The present embodiment can be summarized as follows.

The network connection device according to the first aspect of the present technology has a switch unit that outputs a packet received from the first port among a plurality of ports to the second port, and a specific switch unit in response to a request from the switch unit. It has a processor that executes a management program that executes a predetermined learning process for an address. Then, the switch unit described above contains an entry including the address of the device connected to the port, learning data indicating whether or not the processor has learned the address, and the identifier of the port to which the device is connected. It has a table to store. Then, when the source address of the specific device included in the packet received from the specific port is not registered in the above table, the switch unit is learning data indicating that the source address and the source address are being learned. When an entry containing the identifier of a specific port and the identifier of a specific port is registered in the above table, the processor is requested to learn the source address, and a second packet containing the source address of a specific device is received from the specific port. When an entry including a source address of a specific device and learning data indicating that learning is being performed is registered in the above table, the processor is not requested to learn the source address. Further, when a request is received from the processor to change the training data of a specific entry in the table to trained, the training data of the specific entry in the table is set to trained.

By managing the training data in the table as described above in this way, it becomes possible to appropriately filter duplicate address learning, and efficient address learning can be performed by the processor.

In some cases, the switch unit and the processor described above are separate hardware modules. In such a case, the configuration as described above is particularly effective due to the problem of latency.

Further, when the switch unit described above receives the second packet including the specific destination address from the specific port, the specific destination address and the learning data indicating that the learning is being performed are displayed in the above table. If the included entry is registered, the second packet may be output to a plurality of ports excluding a specific port. In this way, during learning, it is uncertain whether the destination address can really be registered, so it is the device that corresponds to the device connected to each port by broadcasting the packet. It makes you judge whether or not.

Further, it may have a mechanism for managing the learning order of the entries indicating that the learning data is being learned in the table described above. By maintaining such a configuration, even when the processing speed of the processor is low, the addresses can be learned in the correct order without omission.

Further, in the mechanism described above, a pointer field is provided for each entry, and the pointer field is associated with an entry indicating that the training data is being learned, and a pointer to the entry to be learned next. May be registered. Further, a pointer to the entry to be learned first and a pointer to the entry to be learned last may be separately held. In this way, the mechanism described above can be realized with a simple configuration, and the above table also functions as a request queue for address learning. The pointer field may be integrated with the table described above, or it may be held in a different memory or recording area. When integrated, processing is easier and memory utilization efficiency is higher.

When such a pointer field or the like is used, the switch unit described above is used for the last entry to be learned when the pointer to the last entry to be learned is already registered. The address of the newly registered entry in the above table may be registered in the pointer field, and the address of the newly registered entry in the above table may be registered as a pointer to the last entry to be learned. Then, after requesting the processor to learn the source address, in response to the request for the start pointer from the processor, the address of the first entry indicated by the pointer to the entry to be learned first is output to the processor, and the processor In response to the first entry acquisition request that specifies the address of the first entry from, the data of the first entry and the address stored in the pointer field associated with the first entry are read from the above table and output to the processor. Furthermore, in response to the address setting request stored in the pointer field associated with the first entry from the processor, the address included in the above address setting request is registered as a pointer to the entry to be learned first. It may be. By doing so, the order of learning can be managed appropriately.

Further, the switching circuit device for a network connection device according to the second aspect of the present technology performs a predetermined learning process for the address of the device connected to a port among a plurality of ports and a specific address. It has a table for storing entries including learning data indicating whether or not the processor executing the management program has learned a specific address, and an identifier of the port to which the device is connected, and a management unit. .. Then, when the source address of the specific device included in the packet received from the specific port is not registered in the above table, the management unit indicates that the source address and the source address are being learned. The entry including the identifier of the specific port and the identifier of the specific port is registered in the above table, and the processor is requested to learn the source address. In addition, when a second packet containing the source address of a specific device is received from a specific port, an entry containing the source address of the specific device and learning data indicating that learning is being performed is registered in the above table. If so, the processor is not required to learn the source address. Further, when a request is received from the processor to change the training data of a specific entry in the table to trained, the training data of the specific entry in the table is set to trained.

The following additional notes will be further disclosed with respect to the embodiments including the above embodiments.

(Appendix 1) A switch unit that outputs packets received from the first port out of multiple ports to the second port, A processor that executes a management program that executes a predetermined learning process for a specific address in response to a request from the switch unit, and a processor. Have, The switch unit It has a table that stores an entry including an address of a device connected to the port, learning data indicating whether or not the processor has learned the address, and an identifier of the port to which the device is connected. And When the source address of the specific device included in the packet received from the specific port is not registered in the table, the source address and the learning data indicating that the source address is being learned and the specific An entry including a port identifier is registered in the table, and the processor is requested to learn the source address. When a second packet containing the source address of the specific device is received from the specific port, the table contains an entry containing the source address of the specific device and learning data indicating that learning is being performed. If registered, the processor is not required to learn the source address, and the processor is not required to learn the source address. When a request is received from the processor to change the trained data of a specific entry in the table to trained, the trained data of the specific entry in the table is set to trained in the table. Network connection device.

(Appendix 2) The switch part When an entry including the specific destination address and learning data indicating that learning is being performed is registered in the table when a second packet including the specific destination address is received from the specific port. Outputs the second packet to the plurality of ports excluding the specific port. The network connection device described in Appendix 1.

(Appendix 3) The network connection device according to Appendix 1 or 2, further comprising a mechanism for managing the learning order of entries indicating that the learning data is being learned in the table.

(Appendix 4) In the mechanism A pointer field is provided for each entry. In the pointer field, a pointer to the entry to be learned next is registered in association with the entry indicating that the learning data is being learned. In addition, it holds a pointer to the entry to be learned first and a pointer to the entry to be learned last. The network connection device described in Appendix 3.

(Appendix 5) A switch unit that outputs packets received from the first port among a plurality of ports to the second port, and a management program that executes a predetermined learning process for a specific address in response to a request from the switch unit are executed. It is an address learning processing method executed by a network connection device having a processor to be used. A specific port in a table that stores an entry containing an address of a device connected to the port, learning data indicating whether or not the processor has learned the address, and an identifier of the port to which the device is connected. When the source address of the specific device included in the packet received from is not registered, the source address, the learning data indicating that the source address is being learned, and the identifier of the specific port are included. A request step that registers an entry in the table and requests the processor to learn the source address. When a second packet containing the source address of the specific device is received from the specific port, the table contains an entry containing the source address of the specific device and learning data indicating that learning is being performed. If registered, the step of suppressing the request for learning the source address from the processor and When a request is received from the processor to change the trained data of a specific entry in the table to trained, a step of setting the trained data of the specific entry in the table to trained in the table, and Address learning processing method including.

(Appendix 6) In the switch section A pointer field is provided for each entry. In the pointer field, a pointer to the entry to be learned next is registered in association with the entry indicating that the learning data is being learned. In addition, it holds a pointer to the entry to be learned first and a pointer to the entry to be learned last. In the request step If a pointer to the last entry to be learned has already been registered, the address of the entry newly registered in the table in the request step is entered in the pointer field for the last entry to be learned. Register and The address of the entry newly registered in the table in the request step is registered as a pointer to the last entry to be learned. After the request step, in response to a request for a start pointer from the processor, a step of outputting the address of the first entry indicated by the pointer to the first entry to be learned to the processor. In response to the first entry acquisition request from the processor that specifies the address of the first entry, the data of the first entry and the address stored in the pointer field associated with the first entry are read from the table. Steps to output to the processor and In response to the address setting request stored in the pointer field associated with the first entry from the processor, the address included in the address setting request is used as a pointer to the entry to be learned first. Steps to register and The address learning processing method described in Appendix 5, which further includes.

(Appendix 7) The address of the device connected to a certain port among a plurality of ports, and the learning data indicating whether or not the processor that executes the management program that executes a predetermined learning process for the specific address has learned the specific address. , A table that stores entries containing the identifier of the port to which the device is connected, Has a management department The management department When the source address of the specific device included in the packet received from the specific port is not registered in the table, the source address and the learning data indicating that the source address is being learned and the specific An entry including a port identifier is registered in the table, and the processor is requested to learn the source address. When a second packet containing the source address of the specific device is received from the specific port, the table contains an entry containing the source address of the specific device and learning data indicating that learning is being performed. If registered, the processor is not required to learn the source address, and the processor is not required to learn the source address. When a request is received from the processor to change the trained data of a specific entry in the table to trained, the trained data of the specific entry is set to trained in the table. Switching circuit equipment for network connection equipment.

100 L2 switch 110 switch LSI 120 switch management processor 111 FDB 112 Administration 113 Tag storage 1111 Learning status flag 1121 First pointer storage 1122 End pointer storage 121 Management program