Information recording and replaying apparatus

The present invention relates to an information recording / reproducing device having a high recording density.

With the spread of small mobile devices in recent years, the demand for small, large-capacity non-volatile memory has been increasing rapidly year by year toward the realization of a ubiquitous society in the future. Among them, NAND flash memory and small HDD (Hard Disk Drive) have achieved rapid evolution of recording density and are creating a large market.

However, in the near future, both NAND flash memory and small HDDs will have a problem of limited recording density. In particular, small HDDs are said to have a limit in tracking accuracy, and NAND flash memory has a limit in miniaturization and an increase in process cost due to a reduction in the minimum line width. There is a strong demand for the development of technology that overcomes this limit of recording density, and recently, a new solid-state memory has been proposed aiming at significantly exceeding the limit of recording density.

In the world, as a new solid-state memory, an ON state (amorphous state) and an OFF state (crystal state) are caused by a change in the film state (amorphous state and crystalline state) of a recording material called PRAM (Phase change RAM). Memory using the above has been proposed and is being developed to the practical level (for example, T. Gotoh, K. Sugawara and K. Tanaka, Jpn. J. Appl. Phys., 43, 6B, 2004, L818. , And A. Sawa, T. Fuji, M. Kawasaki and Y. Tokura, Appl. Phys. Lett., 85, 18, 4073 (2004)).

Recently, research and development of a new solid-state memory called RRAM (Resistive RAM) has been carried out, and storage materials such as NiO and CuO have been reported. This RRAM applies a voltage pulse to the storage material and uses the resistance change of the storage material to repeatedly change the low resistance state (set state) and high resistance state (reset state), and this state is converted into binary data (binary data (reset state). The information is recorded or deleted by changing to 0 or 1). The greatest feature of this memory is that it can operate in principle even if the element size is reduced to about 10 nm. In this case, a recording density of about 10 Tbpsi (tera bite par square inch) can be achieved, which is high. It is considered as one of the candidates for recording density.

In addition, a so-called MEMS memory using MEMS (micro electro mechanical systems) technology has been proposed (for example, P. Vettiger, G. Cross, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, See W. Haberle, MA Lants, HE Rothuizen, R. Stutz and GK Binnig, IEEE Trans. Nanotechnology 1, 39 (2002)). Since this MEMS memory does not require wiring in the recording unit, there is a possibility that a dramatic recording density can be realized. Recently, a combination of this MEMS technology and various recording principles has been proposed, and power consumption, recording / playback density, and operating speed have been studied (for example, P. Vettiger, T. Albrecht, M. Despont, U. Drechsler, U. Durig, B. Gotsmann, D. Jubin, W. Haberle, MA Lants, HE Rothuizen, R. Stutz, D. Wiesmann and GK Binnig, P. Bachtold, G. Cherubini, C. Hagleitner, T. Loeliger, A. Pantazi, H. Pozidis and E. Eleftheriou, in Technical Digest, IEDM03 pp.763- See 766) However, the current situation is that a new information recording medium using a new resistance-changing recording material has not been realized. The reasons for this are that the repeated deterioration in memory switching is large, the thermal stability of each resistance state is low, and the heat resistance (process resistance) of the recording layer / electrode layer due to the post-annealing process is a problem. ..

The present invention proposes a technique for sufficiently ensuring the film characteristics of a recording medium while achieving a high recording density.

The information recording / reproducing device according to the example of the present invention is<u style="single">A diode and a laminated structure are formed with the diode,</u>It contains at least one type of main group element and one type of transition element, and has different electrical resistivity due to the movement of the main group element.<u style="single">Two</u>It is provided with a recording layer in which the state of the above is recorded, and an electrode layer arranged at one end of the recording layer and applying a voltage or a current to the recording layer.<u style="single">The electrode layer has a first region in contact with the recording layer, the recording layer has a second region in contact with the electrode layer, the first and second regions face each other, and the first region is in the second region.</u>It contains a main group element having a concentration higher than that of the main group element as an additive. The information recording / reproducing device according to the example of the present invention is<u style="single">It forms a laminated structure with a diode and a diode, contains at least one type of main group element and one type of transition element, and is placed at one end of the recording layer and a recording layer in which two states with different electrical resistivitys are recorded due to the movement of the typical element. It is provided with an electrode layer that applies a voltage or a current to the recording layer. The recording layer has a first region in contact with the electrode layer and a second region other than the first region. The first and second regions have different compositions, and the first region is within the second region. It contains a typical element having a concentration higher than that of the typical element of the above as an additive.</u>

According to the present invention, it is possible to realize a non-volatile information recording / reproducing device that sufficiently secures the film characteristics of a recording medium while achieving a high recording density.

<figref num="1">FIG. 1 is a diagram showing a recording principle.</figref><figref num="2">FIG. 2 is a diagram showing the first basic structure.</figref><figref num="3">FIG. 3 is a diagram showing a structure as a comparative example.</figref><figref num="4">FIG. 4 is a diagram showing a structure as a comparative example.</figref><figref num="5">FIG. 5 is a diagram showing a second basic structure.</figref><figref num="6">FIG. 6 is a diagram showing a third basic structure.</figref><figref num="7">FIG. 7 is a diagram showing a probe type solid-state memory.</figref><figref num="8">FIG. 8 is a diagram showing the classification of recording media.</figref><figref num="9">FIG. 9 is a diagram showing a state at the time of recording.</figref><figref num="10">FIG. 10 is a diagram showing a recording operation.</figref><figref num="11">FIG. 11 is a diagram showing a reproduction operation.</figref><figref num="12">FIG. 12 is a diagram showing a cross-point type solid-state memory.</figref><figref num="13">FIG. 13 is a diagram showing the structure of the memory cell array.</figref><figref num="14">FIG. 14 is a diagram showing the structure of the memory cell array.</figref><figref num="15">FIG. 15 is a diagram showing the structure of the memory cell array.</figref><figref num="16">FIG. 16 is a diagram showing the structure of memory cells.</figref><figref num="17">FIG. 17 is a diagram showing the structure of memory cells.</figref><figref num="18">FIG. 18 is a diagram showing the structure of memory cells.</figref><figref num="19">FIG. 19 is a diagram showing the structure of the memory cell.</figref><figref num="20">FIG. 20 is a diagram showing the structure of memory cells.</figref><figref num="21">FIG. 21 is a diagram showing an application example to a flash memory.</figref><figref num="22">FIG. 22 is a circuit diagram showing a NAND cell unit.</figref><figref num="23">FIG. 23 is a diagram showing the structure of the NAND cell unit.</figref><figref num="24">FIG. 24 is a diagram showing the structure of the NAND cell unit.</figref><figref num="25">FIG. 25 is a diagram showing the structure of the NAND cell unit.</figref><figref num="26">FIG. 26 is a circuit diagram showing a NOR cell.</figref><figref num="27">FIG. 27 is a diagram showing the structure of the NOR cell.</figref><figref num="28">FIG. 28 is a circuit diagram showing a two-tracel unit.</figref><figref num="29">FIG. 29 is a diagram showing the structure of the two-tracel unit.</figref><figref num="30">FIG. 30 is a diagram showing the structure of the two-tracel unit.</figref>

Hereinafter, the best mode for carrying out the example of the present invention will be described in detail with reference to the drawings.

1. Overview In order to put a new solid-state memory into practical use, it is necessary to develop a recording medium or recording element having good heat resistance. Here, to improve the heat resistance means that the main group element as a diffuse ion in the recording layer does not diffuse into the electrode layer even if the post-annealing treatment (heat treatment) is performed after the recording medium or the recording element is formed. It means that the concentration of the main group element as a diffuse ion in the recording layer is kept constant before and after the post-annealing treatment.

Therefore, in the information recording / reproducing device according to the example of the present invention, a recording layer containing a typical element as a main group ion and recording two or more states having different electrical resistivitys due to the movement of the typical element, and one end of the recording layer. The electrode layer is provided with an electrode layer that applies voltage or current to the recording layer, and the electrode layer uses a typical element having a concentration higher than that of the typical element in the recording layer as an additive (dopant) in a region in contact with the recording layer. Includes.

Further, in the information recording / reproducing device according to the example of the present invention, a recording layer containing a typical element as a main group ion and recording two or more states having different electric resistances due to the movement of the typical element, and one end of the recording layer. The recording layer is provided with an electrode layer that is arranged and applies a voltage or current to the recording layer, and the composition of the recording layer is different between a region in contact with the electrode layer and another region, and the region in contact with the electrode layer is within the other region. It contains a main group element with a concentration higher than that of the main group element.

The intention of forming such a structure is the same as that of a typical element as a diffusion ion contained in the recording layer in advance in the region of the electrode layer in contact with the recording layer or in the region of the recording layer in contact with the electrode layer. By including an element having a concentration higher than the concentration of the element, these regions are made into a diffusion prevention region that blocks the diffusion of the element from the recording layer to the electrode layer.

Further, in order to effectively show the function as a diffusion prevention region, the diffusion ions contained in the recording layer in the region of the electrode layer in contact with the recording layer or in the region of the recording layer in contact with the electrode layer. It is preferable to add the same elements as the main group elements until saturated.

Here, the concentration of a typical element as a diffuse ion in the recording layer means the concentration after the post-annealing treatment (heat treatment) performed after forming the recording medium or the recording element. Further, in the example of the present invention, a recording medium or a recording element in which two or more states having different electrical resistivitys are recorded due to the movement of a typical element as a diffusion ion is targeted. That is, it is considered that the concentration of the main group element as a diffuse ion in the recording layer is dynamically changing. Therefore, the concentration of a typical element as a diffuse ion in the recording layer means the concentration when the recording medium or the recording element is in the initial state.

As described above, the same element as the typical element as a diffusion ion contained in the recording layer in the region of the electrode layer in contact with the recording layer or in the region of the recording layer in contact with the electrode layer, and its concentration. By including an element having a higher concentration than that, it is possible to prevent the element from diffusing from the recording layer to the electrode layer. Therefore, the improvement of the film characteristics improves the stability of the switching operation and the set / reset state. The thermal stability of the resistance value can be ensured.

The main group element is preferably an element selected from the group of Zn, Cd, Hg, Al, Ga, In, Ti, Be, Mg, and Ca. The electrode layer is mainly composed of elements selected from the group of Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, W, Ru, Ni, Pd, Pt, Cu, Ag and Au. Is preferable. The thickness of the electrode layer is preferably 20 nm or less.

The recording layer is, for example, chemical formula: A_xM_yX₄Includes materials represented by (0.1 x 2.2, 1.5 y 2). However, A is a typical element selected from the group of Zn, Cd, and Hg, M is a transition element selected from the group of Cu, Mo, W, Mn, Tc, Re, and Fe, and X is O, N. It is an element selected from the group of.

The recording layer preferably has a crystal structure selected from the group of spinel structure, ilmenite structure, wolfamite structure, and delafosite structure. The thickness of the recording layer is preferably 50 nm or less.

The post-annealing process is, for example, N₂Performed in an atmosphere at a temperature of 600 ° C.

2. Basic principle The basic principle of the recording operation of the recording layer used in the present invention will be described.

In the following, the recording layer is assumed to be in one of two states having different electrical resistivityes, and will be described in a system in which two types of ions are present.

The initial state of the recording layer is an insulator (high resistance state), for example, an electrical resistivity of 10.⁷It shall be in the state of Ω · cm. Then, by applying a potential difference to both ends of the recording layer, a part of the cation element existing inside the recording layer moves to the cathode (negative electrode) side.

As a result, when the recording layer is positioned on the anode (positive electrode) side and the conductive oxide layer is positioned on the cathode side, the cation element discharged from the recording layer is introduced into the conductive oxide layer and is conductive. In the oxide layer, the proportion of cationic elements is relatively higher than the proportion of anionic elements.

At the same time, the conductive oxide layer receives electrons from the cathode in order to maintain electrical neutrality, and the valence of the transition element in the conductive oxide layer decreases, resulting in a compound in a low oxidation state.

Further, in the recording layer on the anode side, the ratio of the cation element is relatively smaller than the ratio of the anion element, so that the compound is in a highly oxidized state by emitting electrons to the anode.

As a result, the recording layer is in a low resistance state, for example, the electrical resistivity is 10.³It becomes the state of Ω cm.

This is the set operation.

When a current is applied to the recording layer in the low resistance state, a large current flows even if the potential difference is low due to the low resistance, but the Joule heat generated at this time raises the temperature of the recording layer.

The high-energy metastable state raised by the previous set operation will be returned to the insulator (high resistance state), which is the low-energy stable state before the set, by the thermal energy.

This is the reset operation.

Here, it is preferable that the resistivity of the conductive oxide layer does not change when the resistance of the recording layer changes as described above, but the resistivity of the conductive oxide layer is the minimum of the resistivity of the recording layer. If it is made sufficiently smaller than the value, there is no problem even if the electrical resistivity of the conductive oxide layer changes.

In the information recording / reproducing device having the conductive oxide layer of the present invention, in principle, Pbpsi (Peta bit per square inch) class can be realized, and further significant improvement in light disturb resistance can be realized.

3. Basic structure FIG. 1 shows the structure of the recording unit which is a premise of the present invention. 11 is an electrode layer, 12 is a recording layer, 13A is an electrode layer (or protective layer), and 14 is a metal layer. Large white circles are anion typical elements (oxygen ions), small black circles are cation transition elements (maternal cations) Y, and small white circles are typical elements (cations) X as diffuse ions.

The recording layer 12 is, for example, ZnMn having a spinel structure.₂O₄In this case, Zn corresponds to a main group element as a diffuse ion, Mn corresponds to a cation transition element, and O corresponds to an anion typical element.

When a voltage is applied to the recording layer 12 to generate a potential gradient in the recording layer 12, a part of the cation X moves in the crystal. Here, in the example of the present invention, the recording layer 12 is used as an insulator (high resistance state phase), the recording layer 12 is phase-changed by the potential gradient, and the recording layer 12 is made conductive (low resistance state phase). Information is recorded by. For example, the potential of the electrode layer 13A is relatively lower than the potential of the electrode layer 11. If the electrode layer 11 has a fixed potential (for example, a ground potential), a negative potential may be applied to the electrode layer 13A.

At this time, a part of the cation X in the recording layer 12 moves to the electrode layer (cathode) 13A side, and the cation X in the recording layer (crystal) 12 decreases relative to the oxygen ion. The cation X that has moved to the electrode layer 13A side receives an electron from the electrode layer 13A and precipitates as a metal X atom to form the metal layer 14.

Inside the recording layer 12, oxygen ions become excessive, increasing the valence of the cation Y left without diffusing. At this time, if the cation X is selected so that the electric resistance decreases when the valence increases, the electric resistance decreases due to the movement of the cation X in both the metal layer 14 and the recording layer 12, so that the recording layer 12 Information recording (set operation) is completed by changing the phase to the low resistance state phase as a whole.

Further, the recording layer 12 having the metal layer 14 is Joule-heated by a large current pulse to promote the redox reaction of the recording layer 12. Due to the residual heat after blocking the large current pulse, some of the X atoms in the metal layer 14 emit electrons to the electrode layer 13A and are arranged as cations X at the void sites in the crystal of the recording layer 12, so that the recording layer 12 changes to an insulator (reset operation).

Therefore, in the example of the present invention, the initial state of the recording layer 12 and the metal layer 14 is set to a conductor (low resistance state phase), the recording layer 12 is phase-changed by Joule heating of a large current pulse, and the recording layer 12 has an insulating property. (High resistance state phase).

Since the cation X enters the recording layer 12, the oxygen ion becomes deficient, and the valence of the cation Y in the recording layer 12 is reduced.

The above process is a kind of electrolysis, and an oxidizing agent is generated by electrochemical oxidation on the electrode layer (anode) 11 side, and a reducing agent is generated by electrochemical reduction on the electrode layer (cathode) 13A side. I can think.

In order to put this operating principle into practical use, it must be confirmed that the reset operation does not occur at room temperature (securing a sufficiently long retention time) and that the power consumption of the reset operation is sufficiently small.

The former can be dealt with by setting the valence of cation X to 2 or more. This can prevent the movement of cation X at room temperature and in the absence of a potential gradient.

Further, since the crystal lattice does not collapse, the latter can be dealt with by finding the movement path of the cation X moving in the recording layer 12.

The diffusion cation X will be described.

As described above, since the diffusion cation X is arranged at the void site of the recording layer 12, if the diffusion cation X is divalent, the diffusion of the diffusion cation X and the thermal stability are satisfied at the same time, so that the diffusion is diffused. The cation X is preferably divalent. As the diffusion cation X, it is preferable to use Zn, Cd, Hg, Mg, Ca, Sr, Cu, Ni, Co, Fe, Mn, Cr and V.

Further, since an oxidizing agent is generated on the electrode layer (anode) 11 side after the set operation, the electrode layer 11 is made of a material that is difficult to be oxidized (for example, an electrically conductive nitride, an electrically conductive oxide, etc.). Is preferable. Moreover, as such a material, a material having no ionic conductivity is preferable.

Such materials are shown below, and among them, LaNiO from the viewpoint of overall performance including good electrical conductivity.₃Can be said to be the most preferable material.

(a) MN M is at least one element selected from the group Ti, Zr, Hf, V, Nb, Ta. N is nitrogen.

(b) MO_x M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt. At least one element that is made. It is assumed that the molar ratio x satisfies 1 x 4.

(c) AMO₃ A is at least one element selected from the group La, K, Ca, Sr, Ba, Ln (Lanthanide).

M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt. At least one element that is made.

O is oxygen.

(d) A₂MO₄ A is at least one element selected from the group K, Ca, Sr, Ba, Ln (Lanthanide).

M is selected from the group of Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Os, Pt. At least one element that is made.

O is oxygen.

Further, since a reducing agent is generated on the protective layer (cathode) 13 side after the setting operation, it is preferable that the protective layer 13 has a function of preventing the recording layer 12 from reacting with the atmosphere.

Such materials include, for example, amorphous carbon, diamond-like carbon, SnO.₂There are semiconductors such as.

The electrode layer 13A may function as a protective layer for protecting the recording layer 12, or a protective layer may be provided instead of the electrode layer 13A. In this case, the protective layer may be an insulator or a conductor.

Further, in order to efficiently heat the recording layer 12 in the reset operation, a heater layer (resistivity is about 10) is placed on the cathode side, here, on the electrode layer 13A side.^-5A material of Ω cm or more) may be provided.

Further, in order to control the orientation of the ion diffusion path of the recording layer 12 perpendicularly to the film surface of the recording layer 12, M is used as the base layer of the electrode layer / recording layer.₃N₄, M₃N₅, MN₂, M₄O₇, MO₂, M₂O₅It is preferable to have a material represented by (M is at least one element selected from Si, Ge, Sn, Zr, Hf, Nb, Ta, Mo, W, Ce, and Tb).

The above operation shows an example in which the initial state of the recording layer 12 is a metal state, but the same applies to the case where the initial state of the recording layer 12 is an insulator state.

Next, the basic structure of the recording unit according to the example of the present invention will be described.

Figure 2 shows the first basic structure. The recording layer contains a typical element TE as a diffuse ion and takes two or more states of different electrical resistivity due to the movement of the typical element TE. The recording layer is, for example, ZnMn₂O₄Is.

The electrode layer is arranged at one end of the recording layer and is provided to apply a voltage or current to the recording layer.

Then, the electrode layer contains as an additive (dopant) a typical element TE having a concentration higher than the concentration of the main group element TE in the recording layer in the region X in contact with the recording layer. The region X of the electrode layer in contact with the recording layer has a diffusion prevention function of preventing the diffusion of elements in the recording layer.

Therefore, even if the post-annealing treatment (heat treatment) is performed after the recording layer / electrode layer is formed, the main group element TE as a diffusion ion in the recording layer does not diffuse into the electrode layer, and the inside of the recording layer before and after the post-annealing treatment. The concentration of the main group element TE as a diffuse ion can be kept constant.

Therefore, the above-mentioned set / reset operation can be stably performed.

3 and 4 show a structure as a comparative example. FIG. 3 shows the concentration distribution of the main group element TE as a diffusion ion before the post-annealing treatment, and FIG. 4 shows the concentration distribution of the main group element TE as a diffusion ion after the post-annealing treatment.

In the comparative example, as shown in FIG. 3, before the post-annealing treatment, the main group element TE as a diffusion ion is uniformly contained in the recording layer, and the electrode layer is in the region in contact with the recording layer or recorded. There is no peak in the concentration of the main group element TE as a diffuse ion in the region of the layer in contact with the electrode layer.

Therefore, as shown in FIG. 4, after the post-annealing treatment, almost all of the main group element TE as diffuse ions in the recording layer is diffused in the electrode layer, so that the above-mentioned set / reset operation is stably performed. I can't do it.

In the first basic structure shown in FIG. 2, the typical element TE as a diffusion ion existing in the region of the electrode layer in contact with the recording layer or in the region of the recording layer in contact with the electrode layer during the post-annealing treatment is present. It diffuses slightly into the electrode layer. However, this does not significantly change the concentration profile of the main group element TE as a diffusion ion, and even after the post-annealing treatment, the region of the electrode layer in contact with the recording layer or the region of the recording layer in contact with the electrode layer. It has a peak in the concentration of the main group element TE as a diffuse ion.

That is, in the first basic structure, unlike the comparative example, the concentration distribution of the main group element TE as a diffuse ion in the recording layer does not change before and after the post-annealing treatment.

Therefore, as already described, the above-mentioned set / reset operation can be stably performed.

FIG. 5 shows the second basic structure. The recording layer contains the main group element TE as a diffusion ion, and takes two or more states of different electrical resistivitys due to the movement of the main group element TE. The recording layer is, for example, ZnMn₂O₄Is.

The electrode layer is arranged at one end of the recording layer and is provided to apply a voltage or current to the recording layer.

The region X of the recording layer in contact with the electrode layer contains the main group element TE as a diffuse ion having a higher concentration than the other regions of the recording layer. That is, the region X of the recording layer in contact with the electrode layer is a recording layer having a composition different from that of the other regions of the recording layer. The region X of the electrode layer in contact with the recording layer has a diffusion prevention function of preventing the diffusion of elements in the recording layer.

In this case as well, as in the first basic structure, even if the recording layer / electrode layer is formed and then post-annealed (heat treated), the main group element TE as a diffuse ion in the recording layer is diffused into the electrode layer. Instead, the concentration of the main group element TE as a diffuse ion in the recording layer can be kept constant before and after the post-annealing treatment.

Therefore, the above-mentioned set / reset operation can be stably performed.

FIG. 6 shows the third basic structure. The third basic structure differs from the first and second basic structures described above in that electrode layers are arranged at one end and the other end of the recording layer, respectively.

The recording layer contains the main group element TE as a diffusion ion, and takes two or more states of different electrical resistivitys due to the movement of the main group element TE. The recording layer is, for example, ZnMn₂O₄Is.

The first and second electrode layers are provided to sandwich the recording layer and to apply a voltage or current to the recording layer for the movement of the main group element TE.

At least one of the concentration distribution of the main group element near the interface between the first electrode layer and the recording layer and the concentration distribution of the main group element near the interface between the second electrode layer and the recording layer is shown in FIG. Structure) or the same concentration distribution as shown in Fig. 5 (second basic structure).

Here, the reason why the concentration distribution of FIG. 2 or FIG. 5 is applied to at least one of the two interfaces is that the main group element as a diffuse ion in the recording layer diffuses in the electrode layer depending on the material constituting the electrode. This is because it can be difficult.

If the first and second electrode layers are made of the same material and there is a risk of main group elements diffusing into the first and second electrode layers, then of course, at each of the two interfaces, Figure 2 or Figure. It is preferable to apply the concentration distribution of 5.

4. Embodiment Next, some embodiments that seem to be the best will be described. In the following, two examples of the present invention will be described, one is applied to a probe type solid-state memory and the other is applied to a cross-point type solid-state memory.

(1) Probe type solid-state memory A. Structure 7 and 8 show a probe-type solid-state memory according to the example of the present invention.

An electrode layer 21 is arranged on the semiconductor substrate 20, and a recording unit 22 having a data area and a servo area is arranged on the electrode layer 21. The recording unit (recording medium) 22 is composed of, for example, the recording layer 12 shown in FIG. The recording unit 22 is solidly formed in the central portion of the semiconductor substrate 20.

The servo area is arranged along the edge of the semiconductor substrate 20.

The data area and servo area are composed of a plurality of blocks. A plurality of probes 24 are arranged on the data area and the servo area corresponding to the plurality of blocks. Each of the plurality of probes 24 has a sharpened shape.

The plurality of probes 24 form a probe array and are formed on one side of the semiconductor substrate 23. The plurality of probes 24 can be easily formed on one side of the semiconductor substrate 23 by using the MEMS technology.

The position of the probe 24 on the data area is controlled by the servo burst signal read from the servo area. Specifically, the driver 27 reciprocates the semiconductor substrate 20 in the X direction and controls the positions of the plurality of probes 24 in the Y direction to execute the access operation.

The recording medium is independently formed for each block so that the recording medium rotates in a circle like a hard disk, and each of the plurality of probes 24 is moved in the radial direction of the recording medium, for example, in the X direction. You may do so.

Each of the plurality of probes 24 has a function as a recording / erasing head and a function as a playback head. The multiplex drivers 25 and 26 supply a predetermined voltage to the plurality of probes 24 during recording, playback and erasing.

B. Recording / playback operation The recording / playback operation of the probe-type solid-state memory of FIGS. 7 and 8 will be described.

FIG. 9 shows a recording operation (set operation). The recording unit (recording medium) 22 is formed on the electrode layer 21 on the semiconductor chip 20. The recording unit 22 is covered with the protective layer 13B.

For information recording, the tip of the probe 24 is brought into contact with the surface of the protective layer 13B, a voltage pulse is applied to the recording unit 30 of the recording unit (recording medium) 22, and a potential gradient is generated in the recording unit 30 of the recording unit 22. It is done by letting. In this example, the potential of the probe 24 is relatively lower than the potential of the electrode layer 21. If the electrode layer 21 has a fixed potential (for example, a ground potential), a negative potential may be applied to the probe 24.

The voltage pulse may be generated, for example, by using an electron source or a hot electron source and emitting electrons from the probe 24 toward the electrode layer 21.

At this time, for example, as shown in FIG. 10, in the recording unit 30 of the recording layer 12, a part of the diffused ions moves to the probe (cathode) 24 side, and the diffused ions in the crystal are relative to the anions. Decreases to. Further, the diffused ion that has moved to the probe 24 side receives an electron from the probe 24 and precipitates as a metal.

In the recording unit 30 of the recording layer 12, anions become excessive, and as a result, the valence of the transition element ions left in the recording layer 12 is increased. That is, since the recording unit 30 of the recording layer 12 has electron conductivity due to the injection of carriers due to the phase change, information recording (set operation) is completed.

The voltage pulse for recording information can also be generated by creating a state in which the potential of the probe 24 is relatively higher than the potential of the electrode layer 21.

According to the probe-type solid-state memory of this example, information can be recorded in the recording unit 30 of the recording medium in the same manner as the hard disk, and by adopting a new recording material, the information can be recorded more than the conventional hard disk or semiconductor memory. High recording density can be achieved.

FIG. 11 shows the reproduction operation. The reproduction operation is performed by passing a voltage pulse through the recording unit 30 of the recording layer 12 and detecting the resistance value of the recording unit 30 of the recording layer 12. However, the voltage pulse is set to a minute value such that the material constituting the recording unit 30 of the recording layer 12 does not cause a phase change.

For example, the read current generated by the sense amplifier S / A is passed from the probe 24 to the recording unit 30 of the recording layer 12, and the resistance value of the recording unit 30 is measured by the sense amplifier S / A. Using the new materials already described, the resistance ratio between the high resistance state and the low resistance state is 10³The above can be secured.

In the reproduction operation, continuous reproduction is possible by scanning the recording medium with the probe 24.

The erasing (reset) operation is performed by heating the recording unit 30 of the recording layer 12 with a large current pulse to promote the redox reaction in the recording unit 30 of the recording layer 12. Alternatively, it can also be performed by applying a voltage pulse in the direction opposite to that at the time of setting to the recording layer 12.

The erasing operation can be performed for each recording unit 30, or can be performed for each of a plurality of recording units 30 or blocks.

C. Summary According to such a probe type solid-state memory, higher recording density and lower power consumption can be realized as compared with the current hard disk and flash memory.

(2) Cross-point solid-state memory A. Structure FIG. 12 shows a cross-point solid-state memory according to the example of the present invention.

Word line WL_i-1, WL_i, WL_{i + 1}Extends in the X direction and bit line BL_j-1, BL_j, BL_{j + 1}Extends in the Y direction.

Word line WL_i-1, WL_i, WL_{i + 1}One end of is connected to the word line driver &amp; decoder 31 via the MOS transistor RSW as a selection switch, and the bit line BL_j-1, BL_j, BL_{j + 1}One end of is connected to the bit line driver &amp; decoder &amp; read circuit 32 via the MOS transistor CSW as a selection switch.

At the gate of the MOS transistor RSW, the selection signal R for selecting one word line (low)_i-1, R_i, R_{i + 1}Is input, and at the gate of the MOS transistor CSW, a selection signal C for selecting one bit line (column)_j-1, C_j, C_{j + 1}Is entered.

Memory cell 33 is the word line WL_i-1, WL_i, WL_{i + 1}And bit line BL_j-1, BL_j, BL_{j + 1}It is placed at the intersection with. It is a so-called cross-point type cell array structure.

A diode 34 is added to the memory cell 33 to prevent a sneak current during recording / playback.

FIG. 13 shows the structure of the memory cell array portion of the cross-point solid-state memory of FIG.

Word line WL on semiconductor chip 30_i-1, WL_i, WL_{i + 1}And bit line BL_j-1, BL_j, BL_{j + 1}Are arranged, and the memory cell 33 and the diode 34 are arranged at the intersection of these wirings.

The feature of such a cross-point type cell array structure is that it is not necessary to individually connect MOS transistors to the memory cells 33, which is advantageous for high integration. For example, as shown in FIGS. 14 and 15, memory cells 33 can be stacked to form a memory cell array in a three-dimensional structure.

A structural example of the memory cell 33 will be described.

FIG. 16 shows a first example of a memory cell. Word line WL_iA diode 34 is formed on the diode 34, and a memory cell 33 is formed on the diode 34. The memory cell 33 has a stack structure of an electrode layer 11A / a recording layer 12 / an electrode layer 11B. Bit line BL on memory cell 33_jIs formed.

The electrode layer 11B contains a typical element as a diffuse ion in the recording layer 12, that is, zinc (Zn) as an additive (dopant). Moreover, the amount (concentration) is higher than the amount (concentration) of zinc (Zn) in the recording layer 12.

FIG. 17 shows a second example of a memory cell. Word line WL_iA diode 34 is formed on the diode 34, and a memory cell 33 is formed on the diode 34. The memory cell 33 has a stack structure of an electrode layer 11A / a recording layer 12 / an electrode layer 11B. Further, the recording layer 12 is composed of a composition-different recording layer 12B existing in a region in contact with the electrode layer 11B and a recording layer main body 12A existing in another region. Bit line BL on memory cell 33_jIs formed.

Recording layer body 12A and composition difference The recording layer 12B is composed of the same material, and the only difference between them is the composition ratio of the elements that compose them. For example, the recording layer body 12A is ZnMn.₂O₄The composition difference recording layer 12B is ZnMnO.₃Is.

However, the amount (concentration) of zinc (Zn), which is a typical element as a diffuse ion in the composition difference recording layer 12B, is higher than the amount (concentration) of zinc (Zn) in the recording layer body 12A.

FIG. 18 shows a third example of a memory cell. The third example has a structure in which the first example and the second example are combined.

Word line WL_iA diode 34 is formed on the diode 34, and a memory cell 33 is formed on the diode 34. The memory cell 33 has a stack structure of an electrode layer 11A / a recording layer 12 / an electrode layer 11B. Further, the recording layer 12 is composed of a composition-different recording layer 12B existing in a region in contact with the electrode layer 11B and a recording layer main body 12A existing in another region. Bit line BL on memory cell 33_jIs formed.

Recording layer body 12A and composition difference The recording layer 12B is composed of the same material, and the only difference between them is the composition ratio of the elements that compose them. For example, the recording layer body 12A is ZnMn.₂O₄The composition difference recording layer 12B is ZnMnO.₃Is.

However, the amount (concentration) of zinc (Zn), which is a typical element as a diffuse ion in the composition difference recording layer 12B, is higher than the amount (concentration) of zinc (Zn) in the recording layer body 12A.

Further, the electrode layer 11B contains a typical element as a diffuse ion in the recording layer 12, that is, zinc (Zn) as an additive (dopant). Moreover, the amount (concentration) is higher than the amount (concentration) of zinc (Zn) in the recording layer main body 12A.

FIG. 19 shows a fourth example of a memory cell. The fourth example is an application example of the first example, and its feature is that it is used as an additive (dopant) in the electrode layers 11A and 11B existing at both ends of the recording layer 12 and as diffuse ions in the recording layer 12. The point is that it contains typical elements.

Word line WL_iA diode 34 is formed on the diode 34, and a memory cell 33 is formed on the diode 34. The memory cell 33 has a stack structure of an electrode layer 11A / a recording layer 12 / an electrode layer 11B. Bit line BL on memory cell 33_jIs formed.

The electrode layers 11A and 11B contain a typical element as a diffuse ion in the recording layer 12, that is, zinc (Zn) as an additive (dopant). Moreover, the amount (concentration) is higher than the amount (concentration) of zinc (Zn) in the recording layer 12.

FIG. 20 shows a fifth example of a memory cell. The fifth example is an application example of the second example, and the feature is that the recording layers 12A and 12B having different compositions are arranged at both ends of the recording layer main body 12A, respectively.

Word line WL_iA diode 34 is formed on the diode 34, and a memory cell 33 is formed on the diode 34. The memory cell 33 has a stack structure of an electrode layer 11A / a recording layer 12 / an electrode layer 11B. Further, the recording layer 12 is formed from the composition difference recording layer 12B existing in the region in contact with the electrode layer 11B, the composition difference recording layer 12C existing in the region in contact with the electrode layer 11A, and the recording layer main body 12A existing in other regions. It is composed. Bit line BL on memory cell 33_jIs formed.

Recording layer body 12A and composition difference The recording layers 12B and 12C are composed of the same material, and the only difference between them is the composition ratio of the elements that compose them. For example, the recording layer body 12A is ZnMn.₂O₄The composition difference recording layers 12B and 12C are ZnMnO.₃Is.

However, the amount (concentration) of zinc (Zn), which is a typical element as a diffuse ion in the recording layers 12B and 12C having different compositions, is higher than the amount (concentration) of zinc (Zn) in the recording layer body 12A.

Further, the composition ratios of the two recording layers 12B and 12C having different compositions may be different.

By the way, the memory cell 33 stores data of 1 bit or more. In addition, the diode 34 is a word line WL._iBit line BL, not between memory cell 33_jIt may be placed between the memory cell 33 and the memory cell 33.

In addition, word line WL_iBetween the diode 34 and the memory cell 33 and the bit line BL_jBarrier metal may be placed at least one between and.

Further, the diode 34 is preferably omitted when the set / reset operation is performed only by the direction of the voltage.

B. Recording / playback operation The recording / playback operation will be described with reference to FIGS. 12, 13 and 16. Here, it is assumed that the memory cell 33 surrounded by the dotted line A is selected and the recording / playback operation is executed for this memory cell 33.

For information recording (set operation), a voltage may be applied to the selected memory cell 33, a potential gradient may be generated in the selected memory cell 33, and a current pulse may be passed. Therefore, for example, the word line WL_iPotential is bit line BL_jCreate a state that is relatively lower than the potential of. Bit line BL_jIf is a fixed potential (for example, ground potential), the word line WL_iShould be given a negative potential.

At this time, in the recording layer 12 of the selected memory cell 33 surrounded by the dotted line A, a part of the diffused ions is a word line (cathode) WL._iMoving to the side, the diffuse ions in the recording layer 12 decrease relative to the anions. Also, word line WL_iThe diffused ion that has moved to the side is the word line WL_iReceives electrons from and precipitates as metal.

The recording layer 12 of the selected memory cell 33 surrounded by the dotted line A has an excess of anions, resulting in an increase in the valence of transition element ions in the recording layer 12. That is, the selected memory cell 33 surrounded by the dotted line A becomes electron-conducting due to the injection of carriers due to the phase change, so that the information recording (set operation) is completed.

When recording information, the non-selected word line WL_i-1, WL_{i + 1}And non-selected bit lines BL_j-1, BL_{j + 1}It is preferable to bias all of them to the same potential.

Also, during standby before recording information, all word lines WL_i-1, WL_i, WL_{i + 1}And all bit lines BL_j-1, BL_j, BL_{j + 1}Is preferably precharged.

In addition, the voltage pulse for information recording is the word line WL._iPotential is bit line BL_jIt may be generated by creating a state relatively higher than the potential of.

Since the erase (reset) operation utilizes the Joule heat generated by passing a large current pulse through the selected memory cell 33 and its residual heat, for example, the word line WL_iThe potential of the bit line BL_jIt is relatively higher than the potential of. Bit line BL_jIf is a fixed potential (for example, ground potential), the word line WL_iShould be given a positive potential.

At this time, a part of the cations moves into the recording layer 12 of the selected memory cell 33 surrounded by the dotted line A. Therefore, the valence of the cation (transition element) in the conductive oxide layer 15 increases, and the valence of the cation (transition element) in the recording layer 12 decreases.

As a result, the memory cell 33 changes from the low resistance state to the high resistance state, and the reset operation (erasing) is completed.

Here, the erasing operation can also be performed by the following method.

However, in this case, as described above, it is preferable to remove the diode 34 from the semiconductor memories of FIGS. 12, 13, and 16.

For example, word line WL_iThe potential of the bit line BL_jIt should be relatively lower than the potential of. Bit line BL_jIf is a fixed potential (for example, ground potential), the word line WL_iShould be given a negative potential.

At this time, in the selected memory cell 33 surrounded by the dotted line A, a part of the cations in the conductive oxide layer 15 moves into the recording layer 12. Therefore, the valence of the cation (transition element) in the conductive oxide layer 15 increases, and the valence of the cation (transition element) in the recording layer 12 decreases.

As a result, the memory cell 33 changes from the low resistance state to the high resistance state, and the reset operation (erasing) is completed.

In addition, even when erasing, the unselected word line WL_i-1, WL_{i + 1}And non-selected bit lines BL_j-1, BL_{j + 1}It is preferable to bias all of them to the same potential.

Also, during standby before erasing, all word lines WL_i-1, WL_i, WL_{i + 1}And all bit lines BL_j-1, BL_j, BL_{j + 1}Is preferably precharged.

The read operation is performed by passing a current pulse through the selected memory cell 33 surrounded by the dotted line A and detecting the resistance value of the memory cell 33. However, the current pulse needs to be a small value so that the material constituting the memory cell 33 does not change the resistance.

For example, the read current (current pulse) generated by the read circuit is bit line BL._jThe resistance value of the memory cell 33 is measured by a read circuit. If the new material already explained is adopted, the difference in resistance value in the set / reset state is 10³The above can be secured.

C. Summary According to such a cross-point type solid-state memory, higher recording density and lower power consumption can be realized as compared with the current hard disk and flash memory.

(3) Other In the present embodiment, the probe type solid-state memory and the cross-point type solid-state memory have been described, but the materials and principles proposed in the example of the present invention can be applied to the current recording medium such as a hard disk or a DVD. Is.

5. Application to flash memory (1) Structure The example of the present invention can also be applied to a flash memory.

FIG. 21 shows a memory cell of a flash memory.

The memory cell of the flash memory is composed of a MIS (metal-insulator-semiconductor) transistor.

A diffusion layer 42 is formed in the surface region of the semiconductor substrate 41. A gate insulating layer 43 is formed on the channel region between the diffusion layers 42. A recording unit (ReRAM: Resistive RAM) 44 according to the present invention is formed on the gate insulating layer 43. A control gate electrode 45 is formed on the recording unit 44.

The semiconductor substrate 41 may be in a well region, and the semiconductor substrate 41 and the diffusion layer 42 have conductive types opposite to each other. The control gate electrode 45 becomes a word wire and is composed of, for example, conductive polysilicon.

The recording unit 44 is composed of, for example, the recording layer of FIG. 2, and the control gate electrode 45 is composed of, for example, the electrode layer of FIG.

(2) Basic operation The basic operation will be described with reference to FIG. The set (write) operation is executed by applying the potential V1 to the control gate electrode 45 and applying the potential V2 to the semiconductor substrate 41.

The difference between the potentials V1 and V2 needs to be large enough for the recording unit 44 to undergo a phase change or a resistance change, but the direction thereof is not particularly limited.

That is, either V1&gt; V2 or V1 &lt;V2 may be used.

For example, assuming that the recording unit 44 is an insulator (large resistance) in the initial state (reset state), the gate insulating layer 43 is substantially thickened, so that the threshold value of the memory cell (MIS transistor) is reached. Will be higher.

When potentials V1 and V2 are applied from this state to change the recording unit 44 into a conductor (small resistance), the gate insulating layer 43 is substantially thinned, so the threshold value of the memory cell (MIS transistor) is set. , Lower.

Although the potential V2 is given to the semiconductor substrate 41, the potential V2 may be transferred from the diffusion layer 42 to the channel region of the memory cell instead.

The reset (erase) operation is performed by applying the potential V1'to the control gate electrode 45, applying the potential V3 to one of the diffusion layers 42, and applying the potential V4 (&lt;V3) to the other of the diffusion layers 42.

The potential V1'is set to a value that exceeds the threshold value of the memory cell in the set state.

At this time, the memory cell is turned on, electrons flow from the other side of the diffusion layer 42 toward one side, and hot electrons are generated. Since this hot electron is injected into the recording unit 44 via the gate insulating layer 43, the temperature of the recording unit 44 rises.

As a result, the recording unit 44 changes from a conductor (small resistance) to an insulator (large resistance), so that the gate insulating layer 43 is substantially thickened, and the threshold value of the memory cell (MIS transistor) is set. , Get higher.

As described above, since the threshold value of the memory cell can be changed by a principle similar to that of the flash memory, the information recording / reproducing device according to the example of the present invention can be put into practical use by utilizing the technique of the flash memory.

(3) NAND flash memory FIG. 22 shows a circuit diagram of the NAND cell unit. FIG. 23 shows the structure of the NAND cell unit according to the example of the present invention.

An N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a. The NAND cell unit according to the example of the present invention is formed in the P-shaped well region 41c.

The NAND cell unit is composed of a NAND string consisting of a plurality of memory cell MCs connected in series and a total of two select gate transistors ST connected to both ends of the NAND string.

The memory cell MC and the select gate transistor ST have the same structure. Specifically, these are an N-type diffusion layer 42, a gate insulating layer 43 on the channel region between the N-type diffusion layer 42, a recording unit (ReRAM) 44 on the gate insulating layer 43, and a recording unit 44. It is composed of the upper control gate electrode 45.

The state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the above-mentioned basic operation. On the other hand, the recording unit 44 of the select gate transistor ST is fixed to the set state, that is, to the conductor (small resistance).

One of the select gate transistors ST is connected to the source line SL and the other one is connected to the bit line BL.

Before the set (write) operation, it is assumed that all the memory cells in the NAND cell unit are in the reset state (high resistance).

The set (write) operation is performed one by one from the memory cell MC on the source line SL side to the memory cell on the bit line BL side.

V1 (plus potential) is given to the selected word line (control gate electrode) WL as a writing potential, and Vpass is given to the non-selected word line WL as a transfer potential (potential at which the memory cell MC is turned on).

The select gate transistor ST on the source line SL side is turned off, the select gate transistor ST on the bit line BL side is turned on, and the program data is transferred to the channel area of the memory cell MC selected from the bit line BL.

For example, when the program data is 1, the write-protection potential (for example, the same potential as V1) is transferred to the channel area of the selected memory cell MC, and the recording unit 44 of the selected memory cell MC Prevent the resistance value from changing from a high state to a low state.

When the program data is 0, V2 (&lt;V1) is transferred to the channel area of the selected memory cell MC, and the resistance value of the recording unit 44 of the selected memory cell MC is changed from a high state to a low state. Change to.

In the reset (erase) operation, for example, V1'is given to all word lines (control gate electrodes) WL, and all memory cell MCs in the NAND cell unit are turned on. Also, the two select gate transistors ST are turned on, V3 is given to the bit line BL, and V4 (&lt;V3) is given to the source line SL.

At this time, since hot electrons are injected into the recording unit 44 of all the memory cell MCs in the NAND cell unit, the reset operation is collectively executed for all the memory cell MCs in the NAND cell unit.

In the read operation, the read potential (plus potential) is given to the selected word line (control gate electrode) WL, and the memory cell MC data 0, 1 to the non-selected word line (control gate electrode) WL. Gives a potential that always turns on regardless of ".

It also turns on the two select gate transistors ST and supplies a read current to the NAND string.

When a read potential is applied, the selected memory cell MC is turned on or off according to the value of the data stored in the selected memory cell MC. Therefore , for example , data can be read by detecting a change in the read current. it can.

In the structure of FIG. 23, the select gate transistor ST has the same structure as the memory cell MC. For example, as shown in FIG. 24, the select gate transistor ST has a recording unit (recording layer). It is also possible to use a normal MIS transistor without forming it.

FIG. 25 is a modified example of the NAND flash memory.

This modification is characterized in that the gate insulating layer of the plurality of memory cells MC constituting the NAND string is replaced with the P-type semiconductor layer 47.

As the integration becomes higher and the memory cell MC becomes finer, the P-type semiconductor layer 47 is filled with the depletion layer in a state where no voltage is applied.

At the time of setting (writing), a positive write potential (for example, 3.5 V) is applied to the control gate electrode 45 of the selected memory cell MC, and a positive transfer potential (for example, 3.5 V) is applied to the control gate electrode 45 of the non-selected memory cell MC. For example, give 1V).

At this time, the surface of the P-type well region 41c of the plurality of memory cells MC in the NAND string is inverted from P-type to N-type, and a channel is formed.

Therefore, as described above, if the select gate transistor ST on the bit line BL side is turned on and the program data "0" is transferred to the channel area of the memory cell MC selected from the bit line BL, the set operation can be performed. it can.

For resetting (erasing), for example, if a negative erasing potential (for example, -3.5V) is applied to all the control gate electrodes 45 and a ground potential (0V) is applied to the P-type well region 41c and the P-type semiconductor layer 47, the reset (erasing) can be performed. This can be performed collectively for all memory cell MCs that make up the NAND string.

At the time of reading, a positive read potential (for example, 0.5V) is applied to the control gate electrode 45 of the selected memory cell MC, and the memory cell MC data 0 to the control gate electrode 45 of the non-selected memory cell MC. A transfer potential (for example, 1V) that is always turned on regardless of "1" is given.

However, it is assumed that the threshold voltage Vth "1" of the memory cell MC in the "1" state is within the range of 0V &lt;Vth "1" &lt;0.5V, and the threshold voltage Vth "0" of the memory cell MC in the "0" state. Is assumed to be in the range of 0.5V &lt;Vth 0 &lt;1V.

It also turns on the two select gate transistors ST and supplies a read current to the NAND string.

In such a state, the amount of current flowing through the NAND string changes according to the value of the data stored in the selected memory cell MC, and the data can be read by detecting this change.

In this modification, the hole doping amount of the P-type semiconductor layer 47 is larger than that of the P-type well region 41c, and the fermi level of the P-type semiconductor layer 47 is 0.5 that of the P-type well region 41c. It is preferable that it is as deep as V.

This is because when a positive potential is applied to the control gate electrode 45, the inversion from the P-type to the N-type starts from the surface portion of the P-type well region 41c between the N-type diffusion layers 42, and a channel is formed. To do so.

By doing so, for example, at the time of writing, the channel of the non-selected memory cell MC is formed only at the interface between the P-type well region 41c and the P-type semiconductor layer 47, and at the time of reading, a plurality of memories in the NAND string are formed. The channel of the cell MC is formed only at the interface between the P-type well region 41c and the P-type semiconductor layer 47.

That is, even if the recording unit 44 of the memory cell MC is a conductor (set state), the diffusion layer 42 and the control gate electrode 45 are not short-circuited.

(4) NOR type flash memory FIG. 26 shows a circuit diagram of the NOR cell unit. FIG. 27 shows the structure of the NOR cell unit according to the example of the present invention.

An N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a. The NOR cell according to the example of the present invention is formed in the P-type well region 41c.

The NOR cell is composed of one memory cell (MIS transistor) MC connected between the bit line BL and the source line SL.

The memory cell MC is a control on the N-type diffusion layer 42, the gate insulating layer 43 on the channel region between the N-type diffusion layer 42, the recording unit (ReRAM) 44 on the gate insulating layer 43, and the recording unit 44. It is composed of a gate electrode 45.

The state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the above-mentioned basic operation.

(5) 2-tiger type flash memory FIG. 28 shows a circuit diagram of the two tracell units. FIG. 29 shows the structure of the two-trace unit according to the example of the present invention.

The 2-tracel unit was recently developed as a new cell structure that combines the characteristics of a NAND cell unit and the characteristics of a NOR cell.

An N-type well region 41b and a P-type well region 41c are formed in the P-type semiconductor substrate 41a. In the P-shaped well region 41c, the two tracell units according to the example of the present invention are formed.

The two-trace unit consists of one memory cell MC connected in series and one select gate transistor ST.

The memory cell MC and the select gate transistor ST have the same structure. Specifically, these are an N-type diffusion layer 42, a gate insulating layer 43 on the channel region between the N-type diffusion layer 42, a recording unit (ReRAM) 44 on the gate insulating layer 43, and a recording unit 44. It is composed of the upper control gate electrode 45.

The state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the above-mentioned basic operation. On the other hand, the recording unit 44 of the select gate transistor ST is fixed to the set state, that is, to the conductor (small resistance).

The select gate transistor ST is connected to the source line SL, and the memory cell MC is connected to the bit line BL.

The state (insulator / conductor) of the recording unit 44 of the memory cell MC can be changed by the above-mentioned basic operation.

In the structure of FIG. 29, the select gate transistor ST has the same structure as the memory cell MC, but for example, as shown in FIG. 30, the select gate transistor ST is formed with a recording unit (recording layer). It is also possible to use a normal MIS transistor without using it.

6. Conclusion According to the present invention, a non-volatile information recording / reproducing device having high recording density and low power consumption can be realized.

The example of the present invention is not limited to the above-described embodiment, and each component can be modified and embodied without departing from the gist thereof. In addition, various inventions can be constructed by appropriately combining a plurality of components disclosed in the above-described embodiment. For example, some components may be deleted from all the components disclosed in the above-described embodiment, or components of different embodiments may be combined as appropriate.

According to the information recording / reproducing device according to the example of the present invention, although it is an extremely simple mechanism, it is possible to record information with a recording density that cannot be reached by the prior art, and at the same time, to realize high-speed operation. become. Therefore, the example of the present invention has great industrial merits as a next-generation technology that breaks down the barrier of recording density of the current non-volatile memory.