Method for forming semiconductor device

The present invention relates to a semiconductor device in which a thin film transistor (hereinafter, also referred to as TFT) is formed on a glass substrate, particularly a central processing unit (CPU), and a method for manufacturing the same.

A conventional CPU is formed by stacking IC (integrated circuit) chips formed on a so-called silicon wafer, which is a semiconductor element using a single crystal semiconductor substrate. Such CPUs are manufactured with operating speeds exceeding 1 GHz, and the frequency is increasing. In the future, it is expected to realize an integrated circuit that can secure a higher operating frequency.

Further, development of an active matrix type semiconductor device having a TFT formed on an inexpensive glass substrate is underway. In particular, the technology of integrally forming an integrated circuit on a pixel part and a glass substrate, so-called system-on-panel, is regarded as important, and from that trend, research on the formation of a large-scale integrated circuit using a thin-film semiconductor film is also being promoted. ing. In particular, TFTs using polycrystalline semiconductor membranes are expected as semiconductor devices for system-on-panel use because of their high mobility.

There are the following techniques for forming a TFT on such a glass substrate.

Regarding the method for manufacturing an insulated gate type silicon semiconductor device showing good characteristics on a substrate having poor heat resistance, the surface of the silicon semiconductor film formed on the glass substrate via the undercoat film is exposed to an oxidizing atmosphere such as oxygen, and further. There is a method of forming an ultra-thin oxide film on the surface by irradiating with strong light, and then forming a gate insulating film by a plasma CVD method or the like (see Patent Document 1).

Further, in order to realize a high-performance semiconductor device having a contact structure in which good ohmic contact is realized, when forming a wiring having a laminated structure of three or more layers and forming a contact hole reaching this wiring, a second There is a method of forming a contact structure in which good ohmic contact is realized by making the conductive layer of the above function as an etching stopper (see Patent Document 2).

Further, regarding the method of etching the gate electrodes having the first layer and the second layer to produce a so-called GOLD structure TFT, a resist pattern serving as an etching mask for the gate electrodes is formed by a photolithography process, and the gate of the second layer is formed. There is a method of taper etching only the electrode film. The resist pattern has a highly precisely controlled taper angle (see Patent Document 3).<patcit num="1"><text>Japanese Unexamined Patent Publication No. 7-94756</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2000-252473</text></patcit><patcit num="3"><text>JP-A-2002-33273</text></patcit>

<p> However, since the conventional CPU is formed on a silicon wafer, expensive equipment is required. Furthermore, it was less flexible. Further, when a CPU or the like is formed by using a TFT formed on a glass substrate, it cannot be realized due to problems of sodium contained in the glass and heat resistance of the glass itself.</p><p> In addition, when operating the CPU at high speed, it is necessary to make the gate length (gate length) of the TFT smaller. However, since the glass substrate has a large deflection, it is difficult to etch the gate electrode to a gate length sufficient to operate as a CPU.</p><p> Therefore, it is an object of the present invention to form a CPU by a TFT formed on a glass substrate. In particular, it is an object to form a CPU having a fine TFT having a TFT gate length of 1 μm or less.</p>

<p> In view of the above problems, the present invention is to form a conductive film on a crystalline semiconductor film formed on a glass substrate, form a mask having a taper on the conductive film, and etch the conductive film using the mask. It is characterized in that a thin film transistor having a gate length of 1.0 μm or less is formed. In particular, the crystalline semiconductor film is characterized by using laser irradiation when crystallizing the amorphous semiconductor film formed on the glass substrate.</p><p> As laser light, Ar laser, Kr laser, excimer laser, YAG laser, Y₂O₃Laser, YVO₄Laser, YLF laser, YAlO₃One or more of laser, glass laser, ruby laser, Alexandride laser, Ti: sapphire laser, copper steam laser or gold steam laser can be used.</p><p> Further, a continuous oscillation type laser (also referred to as a CW laser) or a pulse oscillation type laser (also referred to as a pulse laser) can be used. The beam shape of the laser is preferably linear, and the length of the long axis may be 200 to 350 μm. Further, the laser may have an incident angle θ1 (0 ° &lt;θ1 &lt;90 °) with respect to the semiconductor film.</p><p> The present invention is also characterized in that the conductive film is etched using a mask having a taper. A mask having a taper means a state in which the base of the mask and the hypotenuse (end face) of the mask have a certain angle θ2. The angle θ2 is preferably 20 ° &lt;θ2 &lt;85 °, preferably 45 ° &lt;θ2 &lt;60 °. Masks with such a taper can be formed from an organic or inorganic material. Specifically, a resist can be used as the organic material, and a silicon oxide film can be used as the inorganic material. Further, the mask having a taper may have a tapered end face, and the shape of the upper surface of the mask may be flat or convex, that is, the upper surface may have any shape.</p><p> Further, the present invention has a laminated structure in which at least the first conductive film and the second conductive film are laminated in this order. When the second conductive film is etched using the mask, the first conductive film can be used as a so-called etching stopper. By using the first conductive film as an etching stopper, the length of the second conductive film in the channel length direction, that is, the length corresponding to the gate length can be reduced to 1.0 μm or less.</p><p> A TFT with a gate length of 1.0 μm or less is sometimes called a submicron TFT. In such a submicron TFT, an opening (also referred to as a contact hole) formed in an insulating film for connecting an impurity region formed in the semiconductor film and a wiring (corresponding to a source electrode or a drain electrode). The diameter of the) is also reduced. Further, when the shape of the contact hole is vertical, the movement of the carrier between the gate electrode and the contact hole (that is, the wiring) can be reduced. Therefore, it is preferable to intentionally form the end portion of the resist for forming the contact hole so as not to have a tapered shape. Further, if the selection ratio between the resist and the insulating film that opens the contact hole is high, the etching rate of the insulating film is high and the contact hole can be formed vertically. Therefore, the resist end may have a tapered shape. Absent.</p><p>Depending on the material of the insulating film forming the contact hole, the material of the mask for forming the contact hole can be selected from an organic material or an inorganic material. Specifically, in the case of an insulating film made of an inorganic material, a mask made of an organic material such as a resist may be used, and in the case of an insulating film made of an organic material, a mask made of an inorganic material such as silicon oxide may be used.</p><p> Further, in the case of the submicron TFT, the film thickness of the gate insulating film provided between the semiconductor film and the gate electrode becomes thin. Therefore, if the surface of the semiconductor film is washed with hydrofluoric acid or the like before the gate insulating film is formed, grooves, recesses, etc. may be formed in the base film, particularly the base film provided in contact with the semiconductor film. , The step coverage of the thinned gate insulating film is reduced. Therefore, it is preferable to nitrid the base film before cleaning the surface of the semiconductor film with fluorine or the like to prevent the formation of grooves and recesses due to the cleaning.</p><p> A semiconductor device, particularly a CPU (Central Processing Unit), can be formed by using the thin film transistor formed as described above. Since the semiconductor device and CPU formed in this way have a thin film transistor having a gate length of 1.0 μm or less, high-speed operation can be performed.</p>

<p> As in the past, manufacturing a CPU using a silicon wafer requires expensive equipment, but in the case of a CPU using a TFT formed on a glass substrate, it can be realized with only inexpensive equipment, and a low-cost CPU can be realized. Can be made. Further, a CPU using a thin film transistor on a glass substrate is lighter than a CPU using a silicon wafer, which is preferable for carrying or mounting.</p><p> According to the present invention, not only peripheral circuits such as a display unit and a drive circuit unit, but also information processing circuits such as a CPU and a memory can be integrally formed on the same substrate.</p>

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, those skilled in the art can easily understand that the present invention can be carried out in many different modes, and that the forms and details thereof can be variously changed without departing from the spirit and scope of the present invention. Will be done. Therefore, the interpretation is not limited to the description of the present embodiment. In all the drawings for explaining the embodiment, the same parts or parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) In this embodiment, a specific manufacturing process will be described.

As shown in FIG. 1 (A), the undercoat film 101 is formed on the substrate 100 having an insulating surface. For the substrate 100, for example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a quartz substrate, a SUS substrate, or the like can be used. In addition, substrates made of flexible synthetic resins such as PET (polyethylene terephthalate), PES (polyethylene monkey file), and PEN (polyethylene naphthalate) and acrylics are generally different from other substrates. Although the heat resistant temperature tends to be lower than that of the other, it can be used as long as it can withstand the processing temperature in the manufacturing process.

The base film 101 is provided to prevent alkali metals such as Na and alkaline earth metals contained in the substrate 100 from diffusing into the semiconductor film and adversely affecting the characteristics of the semiconductor element. Therefore, it is formed by using an insulating film such as silicon oxide, silicon nitride, or silicon nitride, which can suppress the diffusion of alkali metal or alkaline earth metal into the semiconductor film. In this embodiment, SiH is used by plasma CVD method.₄, NH₃, N₂O and H₂The silicon oxide film (SiNO) formed using the above as a reaction gas is 10 to 200 nm (50 nm in this embodiment), SiH.₄And N₂Silicon oxide film (SiON) formed using O as a reaction gas is laminated in the order of 50 to 200 nm (100 nm in this embodiment). The undercoat film 101 may have a single-layer structure, and for example, a silicon nitride film can be formed so as to have a film thickness of 10 to 400 nm (preferably 50 to 300 nm).

When using a substrate that contains some alkali metal or alkaline earth metal, such as a glass substrate, stainless steel substrate (SUS substrate), or plastic substrate, it is not necessary to provide a base film from the viewpoint of preventing the diffusion of impurities. Although it is effective, it is not always necessary to provide it when the diffusion of impurities such as a quartz substrate does not pose a problem.

An amorphous semiconductor film 102 is formed on the base film 101. The film thickness of the amorphous semiconductor film 102 is 25 to 100 nm (preferably 30 to 60 nm). Further, as the amorphous semiconductor, not only silicon but also silicon germanium can be used, and when silicon germanium is used, the concentration of germanium is preferably about 0.01 to 4.5 atomic%. In this embodiment, a semiconductor film containing 66 nm silicon as a main component (also referred to as amorphous silicon film or amorphous silicon) is used.

Next, a metal element is added to the amorphous semiconductor film 102. Here, addition means forming a metal element on the surface of the amorphous semiconductor film 102 so that at least the crystallization of the amorphous semiconductor film is promoted. It is preferable to form a metal element because it can be crystallized at a low temperature.

For example, when a Ni solution (including an aqueous solution or an acetic acid solution) is applied onto the amorphous semiconductor film 102 by a coating method such as a spin coating method or a dip method, and the film 103 containing Ni (however, it cannot be observed as a film because it is extremely thin). There is also). At this time, in order to improve the wettability of the surface of the amorphous semiconductor film 102 and spread the solution over the entire surface of the amorphous semiconductor film, UV light irradiation in an oxygen atmosphere, a thermal oxidation method, and hydroxyl radicals are included. It is desirable to form an oxide film (not shown) in 10 to 50 Å (1 to 5 nm) by treatment with ozone water or hydrogen peroxide. Further, Ni ions may be implanted into an amorphous semiconductor film by an ion implantation method, heated in a water vapor atmosphere containing Ni, or sputtered with Ar plasma using a Ni material as a target. In this embodiment, an aqueous solution containing 10 ppm of Ni acetate is applied by a spin coating method.

Then, the amorphous semiconductor film 102 is heat-treated at 500 to 550 ° C for 2 to 20 hours to crystallize the amorphous semiconductor film and form a crystalline semiconductor film. At this time, it is preferable to change the heating temperature so as to gradually increase the temperature. Since hydrogen and the like of the amorphous semiconductor film are generated by the first low-temperature heating step, so-called hydrogen brewing that reduces film roughness during crystallization can be performed. Further, a magnetic field may be applied to crystallize the crystal together with the magnetic energy, or a high-power microwave may be used. In the present embodiment, heat treatment is performed at 500 ° C. for 1 hour using a vertical furnace, and then heat treatment is performed at 550 ° C. for 4 hours.

Since the heat treatment is performed using the metal element in this way, crystallization can be performed at a low temperature. Therefore, a crystalline semiconductor film can be formed on the glass substrate. Furthermore, the semiconductor film can be formed on a plastic substrate that can withstand the heat treatment temperature. As a result, a flexible semiconductor device can be formed, which can contribute to the realization of a so-called sheet computer.

As shown in FIG. 1 (B), after the oxide film formed on the surface of the crystalline semiconductor film is removed by etching with hydrofluoric acid or the like, a laser beam (laser beam) is applied to the crystallized amorphous semiconductor film 102. ) 105 is irradiated. As lasers, Ar laser, Kr laser, excimer laser, YAG laser, Y₂O₃Laser, YVO₄Laser, YLF laser, YAlO₃One or more of laser, glass laser, ruby laser, Alexandride laser, Ti: sapphire laser, copper steam laser or gold steam laser can be used. Further, a continuous oscillation type laser (CW laser) or a pulse oscillation type laser (pulse laser) can be used. The beam shape of the laser is preferably linear, and the length of the long axis may be 200 to 350 μm. Further, the laser may have an incident angle θ1 (0 ° &lt;θ1 &lt;90 °) with respect to the semiconductor film.

In the present embodiment, a 6.4 W CW laser 105 is incident on the semiconductor film at θ1 = 25 degrees in the atmosphere, the long axis of the laser beam is 300 μm, and the laser beam is irradiated at a scanning speed of 40 cm / sec. Then, the region having a width (length in the direction perpendicular to the laser irradiation direction) of 210 μm becomes a region with good crystal growth, and the long axes of the laser beams may be overlapped by 90 μm for irradiation.

In such laser irradiation, a marker can be formed in order to accurately superimpose and control the irradiation start position and irradiation end position. The marker may be formed on the substrate by the same material at the same time as the amorphous semiconductor film.

Then, a gettering step is performed to reduce or remove the metal element. In this embodiment, a method of gettering (capturing) a metal element using an amorphous semiconductor film as a gettering sink will be described. First, an oxide film is formed on a crystalline semiconductor film by irradiation with UV light in an oxygen atmosphere, a thermal oxidation method, treatment with ozone water containing hydroxyl radicals, hydrogen peroxide, or the like. Then, using the plasma CVD method, SH is used as the raw material gas.₄, Ar, pressure is 0.3 Pascal, RF power is 3KW, substrate temperature is 150 ° C, and an amorphous semiconductor film is formed with a film thickness of 150 nm.

Then, heat treatment is performed at 550 ° C for 4 hours in a nitrogen atmosphere to reduce or remove metal elements. Then, the amorphous semiconductor film and the oxide film serving as the gettering sink can be removed with hydrofluoric acid or the like to obtain a crystalline semiconductor film in which metal elements have been reduced or removed.

As described above, the crystalline semiconductor film can be formed, but the crystalline semiconductor film may be formed only by laser irradiation. Since the laser light can pass through a transparent substrate such as a glass substrate depending on its wavelength, the selection range of the substrate can be expanded. Further, crystallization only by laser irradiation is preferable because the step of adding a metal element and the step of gettering can be eliminated.

As shown in FIG. 1 (C), the crystalline semiconductor film is patterned into a predetermined shape to obtain island-shaped semiconductor films 106a to 106e. At the time of patterning, a photoresist is applied to the crystalline semiconductor film, a predetermined mask shape is exposed, and the mask is fired to form a mask on the crystalline semiconductor film. Using this mask, a crystalline semiconductor film is patterned by a dry etching method. The gas of the dry etching method is CF₄And O₂And can be used.

Then, if necessary, impurities are added to the crystalline semiconductor film. For example, boron (B) is added by the doping method. Then, the threshold value, which is the electrical characteristic of the thin film transistor, can be brought closer to zero. That is, the crystalline semiconductor film can be brought into a more intrinsic state.

After that, an insulating film, a so-called gate insulating film 108, is formed so as to cover the crystalline semiconductor films 106a to 106e. Before forming the gate insulating film 108, it is advisable to clean the surface of the island-shaped semiconductor film with hydrofluoric acid or the like. As a result, the interface state between the semiconductor film surface and the gate insulating film can be kept good. The gate insulating film 108 is formed of an insulating film containing silicon with a thickness of 10 to 150 nm, preferably 20 to 40 nm by using a plasma CVD method or a sputtering method. In this embodiment, SiH is used as the raw material gas by the plasma CVD method.₄, N₂Using O, the temperature of the film forming chamber is set to 400 ° C, and a silicon oxide film is formed with a thickness of 20 nm. At this time, in order to reduce the film thickness of the gate insulating film, it is advisable to reduce the film thickness. As a result, it is possible to reduce the formation of a film having poor film quality at the initial stage of film formation. Of course, the gate insulating film is not limited to the silicon oxide nitride film, and an insulating film containing other silicon may be used as a single layer or a laminated structure.

After that, the conductive films 109a and 109b to be the gate electrodes 109 are formed on the crystalline semiconductor film via the gate insulating film 108. Of course, the gate electrode 109 may be a single layer or a laminated layer. The conductive films 109a and 109b may be formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or compound material containing the element as a main component. In the present embodiment, a tantalum nitride film having a thickness of 10 to 50 nm, for example, 30 nm is formed as the first conductive film 108a so as to cover the gate insulating film 108, and a film thickness of 200 to 400 nm is formed as the second conductive film 108b. For example, a 370 nm tungsten film is sequentially laminated.

Then, as shown in FIG. 2A, the first conductive film 109a and the second conductive film 109b are etched using a mask. First, a photoresist is applied onto the second conductive film by a spin coating method or the like. As the photoresist, either a positive type or a negative type can be used. At this time, a photoresist to which an absorbent is added may be used. In the present embodiment, a positive novolak type to which a light absorber is added is used.

Then, the coated photoresist is heat-treated, so-called prebaked. The heating temperature of the pre-bake shall be 50 to 120 ° C, which is lower than the post-bake that will be performed later. In this embodiment, prebaking is performed with a heating temperature of 90 ° C and a heating time of 90 sec.

Then, using an exposure machine, exposure is applied to transfer the mask to the photoresist. In this embodiment, a stepper is used as the exposure machine. The exposure time may be 150 to 250 msec, and is set to 205 msec because a gate length of 0.8 μm is required in this embodiment. In addition, when the gate length is 0.6 μm, the exposure time is 320 μm, and when the gate length is 1.0 μm, the exposure time is 175 μm. That is, the exposure time can be determined by the desired gate length.

After that, the exposed photoresist is developed and heat-treated by dropping a developing solution onto the photoresist or spraying it from a spray nozzle. In this embodiment, NMD-3 is used as a developing solution and the developing time is 60 seconds.

After that, in the present embodiment, the developed photoresist is heat-treated at 125 ° C. for 180 seconds, that is, so-called post-baking is performed. As a result, the moisture remaining in the photoresist can be removed, and at the same time, the stability against heat can be improved. Then, a resist mask 110 having a tapered shape having an angle θ2 on the end face is formed on the second conductive film. The shape of the resist mask may be fan-shaped or trapezoidal, that is, the shape of the upper surface of the resist mask is not limited.

It is also possible to form a resist mask having a tapered shape on the end face by controlling the resist shape by attaching a pattern equal to or less than the limit of the exposure resolution to the mask itself. This is because if a pattern equal to or less than the limit of the exposure resolution is attached, the exposure accuracy of the end face of the resist mask is lowered, so that the end face of the resist mask is not exposed vertically but is exposed in a tapered shape.

By having the end face of the resist mask having a tapered shape in this way, it is possible to prevent the formation of reaction products that adhere to the side surface of the resist mask by the etching step.

As shown in FIG. 2 (B), the second conductive film 109b is etched using the resist mask 110. In this embodiment, CF is used as the gas.₄, Cl, O₂The second conductive film 109b is etched by a dry etching method using the above. At this time, a tapered shape is formed at the end of the second conductive film 109b, similar to the taper of the resist mask 110. Further, the first conductive film 109a functions as a so-called etching stopper so that the gate insulating film and the semiconductor film are not etched.

The etched second conductive film 109b has a gate length 113 of 0.2 μm or more and 1.0 μm or less. At this time, the resist mask 110 may also be retracted by several μm. In the present embodiment, the resist mask 110 is retracted by 0.4 μm to form a second conductive film having a gate length of 0.8 μm.

As shown in FIG. 2C, the first conductive film 109a is etched with the resist mask 110 provided. At this time, the first conductive film 109a is etched under the condition that the selective ratio between the gate insulating film 108 and the first conductive film 109a is high. In this embodiment, Cl is used as the gas.₂Is used to etch the first conductive film 109a. Then, the first conductive film 109a can be etched while maintaining the gate insulating film 108 in the thin film state. By this step, the resist mask 110 and the second conductive film 109b are also slightly etched and may become thinner. As described above, the gate electrode 109 having a very small gate length of 1.0 μm or less is formed.

After that, O the resist mask 110₂It is removed by ashing or a resist stripping solution to form a resist mask 115 for adding impurities. Specifically, as shown in FIG. 3A, a resist mask 115 is formed in a region to be a p-channel type TFT. As the method for producing the resist mask 115 may refer to the above description, detailed description thereof will be omitted.

Next, phosphorus (P), which is an impurity element, is self-consistently added to the region of the n-channel TFT using the gate electrode 109 as a mask. In this embodiment, phosphine (PH)₃) Is doped at 60-80 kV. Then, impurity regions 116a to 116c are formed in the region of the n-channel type TFT. At this time, phosphine is added so as to be uniform in the depth direction with respect to the semiconductor film. However, an impurity region may be formed so as to overlap the gate electrode 109 due to the wraparound of the impurity element at the time of addition. However, the length of the impurity region overlapping the gate electrode 109 in the channel length direction is set to 0.1 to 0.3 μm.

As shown in FIG. 3 (B), a resist mask 117 is formed in a region to be an n-channel TFT. Then, boron (B), which is an impurity element, is added in a self-aligned manner using the gate electrode 109 as a mask in the region to be a p-channel type TFT. In this embodiment, B₂H₆Is doped at 30-45 kV. Then, impurity regions 118a to 118b are formed in the region that becomes the p-channel type TFT. After that, O the resist mask 117₂Remove with ashing or resist stripping solution.

After that, as shown in FIG. 3C, an insulating film, so-called sidewalls 119a to 119c, is formed so as to cover the side surface of the gate electrode. The sidewall can be formed by an insulating film having silicon by using a plasma CVD method or a reduced pressure CVD (LPCVD) method. In this embodiment, SiH is used as the raw material gas by the reduced pressure CVD (LPCVD) method.₄, N₂Using O, a nitrided silicon oxide film, so-called silicon oxide nitride (SiON), is formed at a pressure of 2 Torr (266 pascals) and a temperature of 400 ° C. When forming a sidewall using the plasma CVD method, SiH is used as the raw material gas.₄, N₂A silicon oxide film (SiON) nitrided at a pressure of 1 Torr (133 Pascals) can be formed using O. Then, the silicon oxide film (SiON) is etched to form a sidewall having a tapered shape.

The etching conditions for forming a sidewall using the reduced pressure CVD method are as follows. As the first etching condition, CHF is used as the raw material gas.₃, He is used to generate plasma over several seconds, for example, 3 seconds. At this time, the electrode on the side facing the substrate arranged in the film forming apparatus is 475 W, and the electrode on which the substrate is arranged is 300 W. Ions of the etching gas can be accelerated by the voltage applied to the electrodes on which the substrate is arranged. As the second etching condition, CHF is used as the raw material gas.₃, He is used to apply a voltage for several tens of seconds, for example, 60 seconds. The etching time can be determined so that the process ends when the height of the film to be etched reaches a predetermined value (100 nm in the present embodiment). At this time, the electrode on the side facing the substrate arranged in the film forming apparatus is 475 W, and the electrode on which the substrate is arranged is 300 W. As a third etching condition, CHF is used as the raw material gas.₃, He is used to apply a voltage for several tens of seconds, for example, 31 seconds from the time when the film on the surface to be etched is considered to have disappeared. At this time, the electrode on the side facing the substrate arranged in the film forming apparatus is 50 W, and the electrode on which the substrate is arranged is 450 W.

The etching conditions for forming a sidewall using the plasma CVD method are as follows. As the first etching condition, CHF is used as the raw material gas.₃, He is used to generate plasma over several seconds, for example, 3 seconds. At this time, the electrode on the side facing the substrate arranged in the film forming apparatus is 475 W, and the electrode on which the substrate is arranged is 300 W. As the second etching condition, CHF is used as the raw material gas.₃, He is used to apply a voltage for several tens of seconds, for example, 50 seconds. The etching time can be determined so that the process ends when the height of the film to be etched is 100 nm remaining. At this time, the electrode on the side facing the substrate arranged in the film forming apparatus is 900 W, and the electrode on which the substrate is arranged is 150 W. As a third etching condition, CHF is used as the raw material gas.₃, He is used to apply a voltage for several tens of seconds, for example, 30 seconds from the time when the film on the surface to be etched is considered to have disappeared. At this time, the electrode on the side facing the substrate arranged in the film forming apparatus is 50 W, and the electrode on which the substrate is arranged is 300 W.

The end portion of the sidewall formed as described above does not have to have a tapered shape, and preferably has a vertical shape, that is, a rectangular shape. This is because forming the sidewall in a rectangular shape can prevent the concentration of impurities added next from having a concentration gradient below the sidewall.

Using these sidewalls 119a to 119c, a high-concentration impurity region is formed in the impurity region of the n-channel TFT 120a to 120c. That is, the gate electrodes 109 and the sidewalls 119a to 119c are used as masks to form the high-concentration impurity regions 120a to 120c in a self-aligned manner. At this time, a resist mask 121 is formed on the p-channel type TFT. In this embodiment, phosphine (PH)₃) Is doped with 15 to 25 kV to form high-concentration impurity regions, so-called source regions and drain regions. After that, O the resist mask 121₂Remove with ashing or resist stripping solution.

After that, heat treatment is performed to activate the impurity region. In this embodiment, it is heated to 550 ° C in a nitrogen atmosphere.

As shown in FIG. 4A, the first insulating film 122 is formed so as to cover the gate insulating film 108 and the gate electrode 109. The first insulating film may be an insulating film having nitrogen, and in the present embodiment, 100 nm silicon nitride is formed by the plasma CVD method. After that, heat treatment is performed to activate the product. In this embodiment, heat treatment is performed at 410 ° C. for 1 hour in a nitrogen atmosphere. As a result, film roughness and the like caused by the addition of impurities can be reduced.

Then, the second insulating film 123 is formed so as to cover the first insulating film 122. The second insulating film 123 includes an inorganic material (silicon oxide, silicon nitride, silicon oxide nitride, etc.), a photosensitive or non-photosensitive organic material (polymethyl, acrylic, polyamide, polyimideamide, resist or benzocyclobutene), silicon. A material whose skeletal structure is composed of a bond of (Si) and oxygen (O), contains at least hydrogen as a substituent, and has at least one of fluorine, an alkyl group, or an aromatic hydrocarbon as a substituent. So-called siloxanes and their laminated structures can be used. As the organic material, a positive photosensitive organic resin or a negative photosensitive organic resin can be used. For example, when positive photosensitive acrylic is used as the organic material, an opening having a curvature can be formed at the upper end portion by etching the photosensitive organic resin by the exposure treatment by the photolithography step. In this embodiment, SiH is used as the raw material gas.₄, N₂A nitrided silicon oxide film formed by a plasma CVD method using O is formed to a film thickness of 600 nm. At this time, the temperature of the substrate is heated to 300 to 450 ° C, and in the present embodiment, it is heated to 400 ° C.

As shown in FIG. 4 (B), openings, so-called contact holes, are formed in the gate insulating film 108, the first insulating film 122, and the second insulating film 123 to form wirings 125a to 125e connected to the impurity region. To do. At the same time, a wiring to be connected to the gate electrode is formed. At this time, since the diameter of the opening is about 1.0 μm, the opening should be opened vertically. Therefore, the end of the resist mask is intentionally formed so as not to have a tapered shape, that is, to be vertical. Further, if the selection ratio between the resist and the insulating film that opens the contact hole is high, the insulating film is etched quickly, so that the resist end portion may have a tapered shape. In the present embodiment, since the silicon oxide film nitrided to the second insulating film 123 is used, a resist mask formed so that the ends are vertical, that is, not intentionally tapered, is used. , An opening is formed by a dry etching method. CHF for etching gas₃, He is used to perform etching with a first etching time of several sec, for example, 3 sec, a second etching time of 100 to 130 sec, for example 117 sec, and a third etching time of 200 to 270 sec, for example 256 sec. At this time, the flow rate of the etching gas can be determined according to the etching status of the opening.

When an organic material or siloxane is used for the second insulating film 123, since the side surface of the opening is vertical, a resist mask having a higher hardness than a resist mask made of an organic material, for example, an inorganic material such as a silicon oxide film. It is preferable to use a resist mask formed from silicon.

Then O the resist mask₂Remove with ashing or resist stripping solution.

Then, wirings 125a to 125e are formed in the opening. For wiring, a film composed of elements of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W) or silicon (Si) or an alloy film using these elements may be used. In the present embodiment, titanium film / titanium nitride film / titanium-aluminum alloy film / titanium film (Ti / TiN / Al-Si / Ti) are laminated at 60/40/300 / 100 nm, respectively, and then formed into a desired shape. Patterning and etching are performed to form wiring, that is, source electrode and drain electrode.

As described above, it is possible to form an n-channel type thin film transistor having an LDD structure formed so as to have a low-concentration impurity region and having a gate length of 1.0 μm or less. Further, a p-channel type thin film transistor having a so-called single drain structure formed so as not to have a low-concentration impurity region and having a gate length of 1.0 μm or less is completed. The p-channel thin film transistor can have a single drain structure because deterioration due to hot carriers and short-channel effect are unlikely to occur. Of course, in the present invention, the p-channel type thin film transistor may have an LDD structure. Further, the n-channel type thin film transistor and the p-channel type thin film transistor may have a so-called GOLD structure in which the low-concentration impurity region overlaps with the gate electrode instead of the LDD structure. A TFT having a gate length of 1.0 μm or less can also be referred to as a submicron TFT.

Then, a semiconductor device having a thin film transistor formed as described above, a CPU in the present embodiment can be manufactured, and a high-speed operation with an operating frequency of 30 MHz is possible at a drive voltage of 5 V.

Other semiconductor devices include integrated circuits and semiconductor display devices, especially the pixel part of semiconductor display devices such as liquid crystal display devices, DMDs (Digital Micromirror Devices), PDPs (Plasma Display Panels), and FEDs (Field Emission Display). A thin film transistor formed as in the present embodiment can also be used for the drive circuit unit.

(Embodiment 2) The interface characteristics between the semiconductor film and the gate insulating film have a great influence on the electrical characteristics of the TFT. Therefore, the surface of the semiconductor film is cleaned with hydrofluoric acid or the like before forming the gate insulating film. At this time, since the semiconductor film is patterned so as to have a predetermined shape, the hydrofluoric acid treatment partially removes the base film, particularly the base film provided on the side surface of the semiconductor film, and grooves and recesses are formed. It ends up. If the gate insulating film and the gate electrode are formed in such a shape, the step covering property is not sufficient, which causes a poor withstand voltage of the gate insulating film. In particular, as the film thickness of the gate insulating film becomes thinner, the withstand voltage defect becomes a remarkable problem. Therefore, in the present embodiment, a method for producing a gate insulating film in the case of thinning the film will be described.

As shown in FIG. 5A, the substrate 100, the base film 101, and the amorphous semiconductor film 102 are formed in the same manner as in the first embodiment. The amorphous semiconductor film 102 is crystallized, and the island-shaped semiconductor films 106a to 106e are formed using the resist mask 130.

After that, as shown in FIG. 5 (B), before removing the resist mask 130 used for patterning the island-shaped semiconductor film, it is exposed to a nitrogen atmosphere to partially surface the base film 101 and the island-shaped semiconductor. The side surfaces of the films 106a to 106e are nitrided. In this embodiment, nitrogen (N)₂), Or ammonia (NH₃) Is used to form a nitride region 131 on a part of the surface of the base film 101 and on the side surfaces of the island-shaped semiconductor films 106a to 106e. The nitriding region is silicon nitride (SiN) or silicon oxide (SiON) depending on the material of the base film or the semiconductor film. In the present embodiment, silicon oxide (SiON) is formed on a part of the surface of the base film 101, and silicon nitride (SiN) is formed on the side surface of the semiconductor film. The nitriding region 131 shown in FIG. 5B is a schematic diagram and may differ from the actual nitriding region. As a result, it is possible to prevent the formation of grooves and recesses even when the surface of the island-shaped semiconductor film is washed with hydrofluoric acid or the like before the formation of the gate insulating film.

Then, as shown in FIG. 5 (C), the gate insulating film 108 is formed as in the first embodiment. Since the following steps may refer to the first embodiment, detailed description thereof will be omitted.

Then, a semiconductor device having the thin film transistor formed as described above, and in the present embodiment, a CPU can be manufactured. Other semiconductor devices include integrated circuits and semiconductor display devices, and are particularly formed in the pixel sections and drive circuit sections of semiconductor display devices such as liquid crystal display devices, DMDs, PDPs, and FEDs as in the present embodiment. A thin film transistor can also be used.

(Embodiment 3) In the present embodiment, the configuration of the CPU will be described with reference to a block diagram.

The CPU shown in FIG. 6 has an arithmetic circuit (ALU: Arithmetic logic unit) 601, a control unit (ALU Controller) 602 for the arithmetic circuit, an instruction analysis unit (Instruction Decoder) 603, and an interrupt control unit (Interrupt Controller) on the board 600. ) 604, Timing control unit (Timing Controller) 605, Register (Register) 606, Register control unit (Register Controller) 607, Bus interface (Bus I / F) 608, Rewritable ROM 609, ROM interface (ROM I / F) Mainly has 620. The ROM 609 and ROM I / F 620 may be provided on separate chips.

Various circuits as described above can be configured by using a thin film transistor formed by the methods shown in the first and second embodiments.

Of course, the CPU shown in FIG. 6 is only an example in which the configuration is simplified, and the actual CPU has a wide variety of configurations depending on the application.

Instructions input to the CPU via the bus interface 608 are input to the instruction analysis unit 603, decoded, and then sent to the operation circuit control unit 602, interrupt control unit 604, register control unit 607, and timing control unit 605. Entered.

The control unit 602, interrupt control unit 604, register control unit 607, and timing control unit 605 for the arithmetic circuit perform various controls based on the decoded instructions. Specifically, the control unit 602 for the arithmetic circuit generates a signal for controlling the operation of the arithmetic circuit 601. Further, the interrupt control unit 604 determines and processes an interrupt request from an external input / output device or a peripheral circuit based on its priority and mask state during CPU program execution. The register control unit 607 generates the address of the register 606, and reads or writes the register 606 according to the state of the CPU.

Further, the timing control unit 605 generates a signal for controlling the operation timing of the arithmetic circuit 601, the control unit 602 for the arithmetic circuit, the instruction analysis unit 603, the interrupt control unit 604, and the register control unit 607. For example, the timing control unit 605 includes an internal clock generation unit that generates an internal clock signal CLK2 (622) based on the reference clock signal CLK1 (621), and supplies the clock signal CLK2 to the above-mentioned various circuits.

Further, in the present embodiment, a CPU has been described as an example as a semiconductor device, but the thin film transistor formed on the glass substrate of the present invention is a display device in which each pixel is provided with a light emitting element typified by an organic light emitting element. Can be produced. Other semiconductor devices include integrated circuits and semiconductor display devices, and can be used particularly for pixel sections and drive circuit sections of semiconductor display devices such as liquid crystal display devices, DMDs, PDPs, and FEDs. Specific examples of semiconductor devices manufactured by applying the present invention include digital cameras, sound reproduction devices such as car audio, notebook personal computers, game machines, portable information terminals (mobile phones, portable game machines, etc.), and homes. Examples thereof include an image playback device provided with a recording medium such as a game machine for games.

In particular, since the thin film transistor formed by the present invention has a small gate length, it can be expected that the drive voltage will be reduced by using it in the drive circuit section. Further, the thin film transistor having a small gate length of the present invention can cope with a pixel portion in which high definition is advanced, that is, the interval between pixels is small.

As a result, in the case of a glass substrate, it can be realized with inexpensive equipment, and a low-cost CPU and other semiconductor devices can be manufactured.

(Embodiment 4) In this embodiment, the form of the CPU will be described.

FIG. 7 shows a display device in which a pixel unit, a CPU, and other circuits are formed on the same substrate, a so-called system on panel. A scanning line drive circuit 702 for selecting the pixels of the pixel unit 701 and the pixels of the pixel unit 701 and a signal line drive circuit 703 for supplying a video signal to the selected pixels are provided on the substrate 700. The CPU 704 and other circuits, such as the control circuit 705, are connected by wiring routed from the scan line drive circuit 702 and the signal line drive circuit 703. The control circuit includes an interface. Then, a connection portion with the FPC terminal is provided at the end of the board to exchange with an external signal.

As other circuits, a video signal processing circuit, a power supply circuit, a gradation power supply circuit, a video RAM, a memory (DRAM, SRAM, PROM) and the like can be provided on the substrate. Further, these circuits may be formed by an IC chip and mounted on a substrate. Further, it is not always necessary to form the scanning line driving circuit 702 and the signal line driving circuit 703 on the same substrate. For example, only the scanning line driving circuit 702 is formed on the same substrate, and the signal line driving circuit 703 is formed by an IC chip. It may be implemented.

Figure 8 (A) shows the form of the packaged CPU. A thin film transistor array 801 having a CPU function formed on a substrate 800 is provided with electrodes (source electrodes, drain electrodes, or electrodes formed on them via an insulating film, etc.) 802 provided on the surface of the CPU. The face down state is set to the side. As the substrate 800, glass or plastic can be used. Further, a wiring board provided with a wiring 803 made of copper or an alloy thereof, for example, a printed circuit board 807 is prepared. The printed circuit board 807 is provided with a connection terminal (pin) 804. Then, the electrode 802 and the wiring 803 are connected via an anisotropic conductive film 808 or the like. After that, it is covered with a resin 805 such as epoxy resin from above the substrate 800 to complete a packaged CPU. Alternatively, the outer circumference may be surrounded by plastic or the like while being kept hollow.

In FIG. 8 (B), unlike FIG. 8 (A), the electrode 802 provided on the surface of the CPU is in a face-up state on the upper side. Then, the substrate 800 is fixed on the printed circuit board 807, and the electrode 802 and the wiring 803 are connected by the wire 818. Connecting with wires in this way is called wire bonding. Then, the electrode 802 and the bump 814 connected to the wiring 803 are connected. After that, while keeping it hollow, the outer circumference is surrounded by plastic 815 etc., and it is completed as a packaged CPU.

FIG. 8C shows an example of fixing a thin film transistor array 801 having a CPU function on a flexible substrate, for example, an FPC (Flexible printed circuit). The thin film transistor array 801 formed on the substrate 810 and having the function of a CPU is placed in a face-down state in which the electrode 802 provided on the surface of the CPU is on the lower side. Glass, quartz, metal, bulk semiconductor, and plastic can be used for the substrate 810, but in FIG. 8C, it is preferable to use a highly flexible plastic. In addition, a flexible FPC817 provided with a wiring 803 made of copper or an alloy thereof will be prepared. Then, the electrode 802 and the wiring 803 are connected via the anisotropic conductive film 808. After that, it is covered with a resin 805 such as epoxy resin from above the substrate 800 to complete a packaged CPU.

CPUs packaged in this way are protected from the outside and are more portable. Then, the CPU can be mounted at a desired location, and particularly when it has flexibility as shown in FIG. 8 (C), the degree of freedom in the mounting position is increased. It can also assist CPU functionality by packaging.

As described above, the CPU formed by the thin film transistor on the glass substrate can take various forms. Since the CPU formed by the thin film transistor on the glass substrate is lightweight, the burden of carrying and mounting can be reduced.

(Embodiment 5) In this embodiment, a manufacturing process different from that of the above embodiment will be described.

As shown in FIG. 9A, a resist mask 110 is formed in the same manner as in the above embodiment, and the conductive film 109b is etched using this.

Then, as shown in FIG. 9B, the resist mask 110 is removed. Then, as shown in FIG. 9C, the conductive film 109a is etched using the etched conductive film 109b. As described above, the conductive film 109a may be etched without using the resist mask.

Subsequent steps can refer to the above embodiments.

When the conductive film 109a is etched with the etched conductive film 109b after removing the resist mask as in the present embodiment, the conductive film can be etched without being affected by the shape of the resist mask. it can.

A semiconductor device having a thin film transistor formed as described above, for example, a CPU can be manufactured, and high-speed operation becomes possible.

<figref num="1">The figure which shows the manufacturing process of the thin film transistor of this invention.</figref><figref num="2">The figure which shows the manufacturing process of the thin film transistor of this invention.</figref><figref num="3">The figure which shows the manufacturing process of the thin film transistor of this invention.</figref><figref num="4">The figure which shows the manufacturing process of the thin film transistor of this invention.</figref><figref num="5">The figure which shows the manufacturing process of the thin film transistor of this invention.</figref><figref num="6">A block diagram of a CPU, which is one of the semiconductor devices of the present invention.</figref><figref num="7">The figure which shows the display device which mounted the CPU which is one of the semiconductor devices of this invention.</figref><figref num="8">The figure which packaged the CPU which is one of the semiconductor devices of this invention.</figref><figref num="9">The figure which shows the manufacturing process of the thin film transistor of this invention.</figref>