Amplifier circuit and display device

The present invention relates to an amplifier circuit that stabilizes an input signal and outputs a stabilized output signal, particularly a correction of the output signal.

Conventionally, flat panel type display devices such as liquid crystal display devices have become widespread. In particular, a small and lightweight display device is indispensable for a mobile device, and for example, a liquid crystal display device is mainly used in a mobile phone or the like.

In this liquid crystal display device, since a high-definition image is also displayed, an active matrix type having a pixel circuit for each display pixel and capable of high-definition display is used.

Here, in a liquid crystal display device or the like, a data line is arranged corresponding to each row of pixels arranged in a matrix, and a data signal of each pixel is supplied to each pixel via the data line. The data line is relatively long and has a capacity to hold the data signal. Therefore, when the data signal is supplied to this data line, the current supply capacity of the buffer amplifier is increased and the signal is stabilized in advance. Such an amplifier circuit is described in, for example, Patent Document 1.

<patcit num="1"><text>Japanese Unexamined Patent Publication No. 11-150427</text></patcit>

<p> Here, the buffer amplifier has a difference in input / output due to variations in the characteristics of the transistors constituting the buffer amplifier. Regarding display data, when the voltage changes, the display brightness changes, so there is a demand to minimize the voltage change.</p>

<p> The present invention comprises a buffer amplifier that stabilizes an input signal and outputs a stabilized output signal, a first switch that turns on and off the input of an input signal to the input end of the buffer amplifier, and one end of the buffer amplifier. A first capacitor connected to the input end and the other end connected to the output end of the buffer amplifier via a second switch.<u style="single">Supply of the input signal to the second capacitor whose one end is connected to the other end of the first capacitor and the other end is connected to a power supply having a constant voltage, and to the other end of the first capacitor and one end of the second capacitor. The potential of one end of the first capacitor which has a third switch which turns on and off, turns on the first switch and the second switch, turns off the third switch, and connects to the input end of the buffer amplifier. Is the potential of the input signal, the potential of the midpoint between the other end of the first capacitor and one end of the second capacitor is the potential of the output signal, the first switch is turned on, and the third switch is turned on. While it is off, the second switch is turned off to charge the first capacitor with the voltage difference between the input signal and the output signal, all the first to third switches are turned off, and the first switch is turned off. A potential drop equivalent to the potential drop that occurs at one end of the first capacitor connected to the input end of the buffer amplifier is generated at the midpoint between the other end of the first capacitor and one end of the second capacitor.</u>After that, with the first switch and the second switch turned off, the third switch is turned on and the input signal is supplied to the other end of the first capacitor to supply the input signal to the input end of the buffer amplifier. It is characterized in that a voltage obtained by adding the difference between the input signal and the output signal is supplied to the signal.</p><p><u style="single"></u>Further, in the input signal, for a plurality of bits of a digital signal, a plurality of capacitors weighted to capacitance values corresponding to each bit are charged according to the value of each bit of the digital signal, and the plurality of capacitors are charged. It is an analog output obtained by averaging the voltages, and it is preferable to supply the output signal to a data line having a predetermined capacitance. Further, it is preferable that the first switch, the second switch and the third switch are TFTs.</p><p> Also,<u style="single">The present invention</u>A display device in which a data line is arranged corresponding to each row of pixels arranged in a matrix and a data signal of each pixel is supplied to each pixel via the data line. The data signal is stabilized and then the data signal is stabilized. It has an amplifier circuit that supplies data to the data line, and this amplifier circuit<u style="single">Described in any one of claims 1 to 4.</u>It is characterized by using the amplifier circuit of.</p>

<p> According to the present invention, the input end of a buffer amplifier<u style="single">To</u>A buffer amplifier by supplying a voltage obtained by adding the difference between the input signal and the output signal to the input signal.<u style="single">Out of</u>The force level can be corrected to an appropriate one. Further, by providing the second capacitor, it is possible to suppress the voltage change at the input end of the buffer amplifier when the first switch is turned off.</p>

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

"overall structure" FIG. 1 is a diagram showing a configuration for supplying video data in the liquid crystal display device according to the embodiment to a pixel circuit.

In this embodiment, the 6-bit video line 10 sequentially transfers a digital luminance signal of 64 gradations for each pixel according to a pixel clock. Actually, it has three video lines of R (red), G (green), and B (blue), and the video data of each color is supplied in parallel and supplied to the pixels of the corresponding color. , Only one color is shown in the figure.

The input terminal of the switch 12 provided corresponding to each row of pixels is connected to the video line 10. The output of the horizontal transfer register 14 is connected to the control end of the switch 12. Here, the horizontal transfer register 14 sequentially transfers the horizontal start signal (STH) by a pixel clock synchronized with the timing of each pixel of the video data supplied to the video line, and corresponds to each row of pixels. It has a register. In this description, since the display of one type of RGB color is described, the display bit and the pixel are the same. Further, the transfer clock supplied to the horizontal transfer register has twice the period of the normal pixel clock, and in many cases, two clocks (CKH, XCKH) whose phases are inverted are used.

That is, when the video data of the pixels of the first row is supplied to the video line 10, the horizontal start signal STH is captured in the first horizontal transfer register 14, and the corresponding switch 12 is turned on. Then, the horizontal start (STH) signal is sequentially transferred in the horizontal transfer register 14 by the pixel clock, so that the switch 12 corresponding to the pixel is sequentially turned on for the video data for each pixel supplied to the video line 10. Will be done. The switch 12 is configured by connecting a p-channel transistor (TFT) and an n-channel transistor (TFT) in parallel, and each of them is turned on and off at the same time by the non-inverting output and the inverting output of one register of the horizontal transfer register 14.

The input terminal of the 6-bit SRAM 16 is connected to the output terminal of each switch 12, and the input terminal of the 6-bit SRAM 18 is connected to the output terminal of these SRAM 16. Therefore, the pixel-by-pixel video data sequentially supplied to the video line 10 is taken into the corresponding SRAM 16 by turning on the switches 12 in order. Then, when the video data for one line (one horizontal scanning line) is taken into each SRAM 16, the video data for one line is simultaneously transferred to the corresponding SRAM 18, and this is repeated for each horizontal scanning period. .. Therefore, in each horizontal scanning period, one line of video data is captured in SRAM 16, then transferred to SRAM 18, and the transferred video data is held in SRAM 18 in the next horizontal scanning period and output from here. become. Then, this operation is repeated.

The input end of the digital-to-analog converter (DAC) 20 is connected to the output end of SRAM 18. The DAC 20 converts the 6-bit video data supplied from the SRAM 18 into a 64-gradation analog video signal. Since the DAC20 performs so-called AC drive that changes the voltage application direction to the liquid crystal at a predetermined cycle, the voltage application directions to the liquid crystal are opposite to each other with reference to the common electrode potential of the liquid crystal element2. Outputs a video signal of one polarity). As will be described later, in the present embodiment, since the dot inversion method is used as the AC drive method, the direction (polarity) of the voltage applied to the liquid crystal is reversed in the adjacent pixels in the horizontal and vertical directions, and 1 As for the liquid crystal of one pixel, it is inverted every frame.

Also, each DAC<u style="single">20</u>The input end of the amplifier (Amp) 22 is connected to the output end of the amplifier 22, and the output end of the amplifier 22 is connected to the data line DL via the changeover switch 24. This data line DL extends in a row (vertical scanning direction), and the corresponding one row of pixel circuits 100 are connected to each other. In this example, since the source of the pixel TFT in the pixel circuit 100 is connected to the data line DL, it is also called a source line.

Therefore, the analog video signal output from the DAC 20 is supplied to the data line DL, and the pixel circuit 100 in the corresponding line captures the analog video signal, so that the display is performed according to the analog video signal captured in each pixel.

"SRAM configuration" In this embodiment, each column has two SRAMs 16 and 18 that hold 6-bit digital video data. Further, the dynamic range of the video data is set to be relatively small, and there is a demand for the data to be input to the DAC 20 to have a slightly larger dynamic range. Therefore, for example, the level shift of the 5V amplitude to the 8V amplitude is performed.

In the present embodiment, the latch circuit and the level shifter are combined to form the SRAM 16, and the level shift is also performed in the SRAM 16.

FIG. 2 shows the configuration of the latch type level shift circuit (SRAM 16) and the latch circuit (SRAM 18) that latches the output of the SRAM 16 according to the present embodiment. Here, the video data is 6-bit digital data, and only 1 bit is shown.

Digital video data with 5V amplitude is supplied to switch 610. This switch 610 is controlled by a clock synchronized with the dot clock, and captures video data supplied to the input end for each display pixel (dot). For example, when the corresponding switch 12 of the video line 10 in FIG. 1 is on, the switch 610 is turned on to capture video data. The switch 610 may be used as the switch 12.

The first latch 620 is connected to the output end of the switch 610. The first latch 620 has a 5V amplitude and is composed of two inverters 622,624 operating at 5V in which the inputs and outputs of the first latch 620 are connected to each other. In this example, since the output from the switch 610 is supplied to the input side of the inverter 622, the inverted signal is input to the inverter 624. Therefore, the input state of the inverter 622 is determined by the output state of the switch 610, and the state of the pair of output sides of the inverter 622 is also determined.

Here, in this example, it is preferable to increase the capacity of the inverter 622 as compared with the inverter 624. As a result, even when the input video data is inverted, the output of the inverter 622 is easily inverted and this data can be latched.

The pair of outputs (opposite polarities) of the first latch 620 are input to the voltage-driven level shifter 630. This level shifter 630 has a configuration in which two series connections of three transistors arranged between 8V VDD and 0V VSS are arranged in parallel.

Between VDD and VSS, a series connection of p-channel TFT632a, p-channel TFT634a, and n-channel TFT636a and a series connection of p-channel TFT632b, p-channel TFT634b, and n-channel TFT636b are arranged. Then, the output of the switch 610 latched by the latch circuit 620 is supplied to the gates of the TFT 634a and the TFT 636a, and the inverting signal of the output of the switch 610 latched by the latch circuit 620 is supplied to the gates of the TFT 634b and the TFT 636b. To. Further, the gate of TFT632a is connected to the midpoint between TFT634b and TFT636b, and the gate of TFT632b is connected to the midpoint between TFT634a and TFT636a.

With such a configuration, depending on the output of the latch 620, the gate of the TFT 632a is at the midpoint between the TFT 634b and the n-channel TFT 636b, and the gate of the TFT 632b is at the H level at one of the mid-points of the TFT 634a and the n-channel TFT 636a. Become L level. For example, when the output of switch 610 is H level (1), the midpoint between TFT634b and n-channel TFT636b is H-level, and the midpoint between TFT634a and n-channel TFT636a is L-level.

The output from the midpoint between TFT634b and n-channel TFT636b and the midpoint between TFT634a and n-channel TFT636a is input to the second latch 640. The second latch 640 is configured by connecting the inverter 642 and the inverter 644, and the output at the midpoint between the TFT 634b and the n-channel TFT 636b is input to the input of the inverter 642, and the midpoint between the TFT 634a and the TFT 636a is input to the input of the inverter 644. The output of the inverter 642 (the input of the inverter 644) is the output of the second latch 640.

Therefore, the data input to the switch 610 is latched by the first latch 620, and the level-shifted signal by the level shifter 630 and the level-shifted and inverted signal are latched by the second latch 640 as an 8V signal. The first latch 620, the level shifter 630, and the second latch 640 constitute SRAM 16. Therefore, at the output of SRAM 16, a signal whose 5V amplitude is level-shifted to 8V amplitude is obtained. By providing the latch circuits on the input side and the output side of the level shifter 630 in this way, the latch operation and the level shift operation can be performed at the same time. Therefore, the power consumption can be reduced as compared with the case where these are performed separately.

The output of the second latch 640 is inverted by the inverter 650. When compared with the configuration shown in FIG. 1, up to this inverter 650 corresponds to SRAM 16, which means that the input video data is stored according to the dot clock, level-shifted, and output. ..

The output of the inverter 650 is supplied to the latch 670 via the switch 660. The switch 660 opens only for a predetermined period after the data for one horizontal scanning line is taken into the SRAM 16. The latch 670 is composed of an inverter 672 and an inverter 674 in which the inputs and outputs of the latch 670 are connected to each other. The output of the switch 660 is input to the inverter 672, and the output is the output of the latch 670. Then, the output of the latch 670 is inverted by the inverter 680 and output. Therefore, the latch 670 and the inverter 680 make up the SRAM 18. That is, in one horizontal scanning line, when the video data of each pixel is stored in each SRAM 16, the switch 660 is opened, and the video data at this time is set in the SRAM 18. For example, during the horizontal blanking interval, all SRAM 16 data is collectively transferred to RAM 18.

As described above, according to the present embodiment, the SRAM 16 can also perform level shift when storing data. Therefore, efficient operation can be achieved.

"Configuration of high-order bit conversion of DAC20" FIG. 3 shows the configuration of the high-order bit conversion of the DAC20. The reference voltage generation circuit 300 has two reference voltage amplifiers 300a and 300b. In both of the reference voltage amplifiers 300a and 300b, the power supply voltage VCC and GND are divided into resistors by 10 resistors R0 to R9 to generate 9 reference voltages v0 to v8. The reference voltage amplifiers 300a and 300b operate alternately every one horizontal scanning period. Therefore, the polarities of the nine reference voltages v0 to v8 are reversed every horizontal period. That is, when the reference amplifier 300a is operating, v8 is close to VCC and v0 is close to GND, and when the reference amplifier 300b is operating, the opposite is true. In addition, switching between the reference amplifiers 300a and 300b for each horizontal period is performed by the signal FRP. For example, when the signal FRP is H level, the reference amplifier 300a operates, and when the signal FRP is L level, the reference amplifier 300b operates.

Data D5-D3 is input to four decoders, upper H side decoder 310, upper L side decoder 312, lower H side decoder 314, lower L side decoder 316, and these decoders 310 to 316 also have reference voltages v0 to v8. Each is supplied. The upper H side decoder 310 selects and outputs the reference voltage v8 to v1 according to the eight types of data D5-D3 111 to 000, and the upper L side decoder 312 selects and outputs the reference voltage v8 to v1. Select and output the reference voltage v7 to v0 according to the eight types. Therefore, the output VH of the upper H side decoder 310 has a voltage one step higher than the output VL of the upper L side decoder 312 (when v8 is on the VCC side). On the other hand, the lower H side decoder 314 selects and outputs the reference voltage v0 to v7 according to the eight types of data D5-D3 111 to 000, and the lower L side decoder 316 has the data D5-D3 111 to 111 ~. Select and output the reference voltage v1 to v8 according to the eight types of 000. Therefore, the output VH of the lower H side decoder 314 has a voltage one step lower than the output VL of the lower L side decoder 316 (when v8 is on the VCC side).

In this way, the upper decoders 310 and 312 output the output voltages VH and VL deviated by the voltage corresponding to the bit of D3. The lower decoders 314 and 316 have the same polarity as the upper decoders 310 and 312 (the output analog signals VH and VL are larger or smaller in the direction of change depending on whether the input digital data is larger or smaller). Although the direction of change is reversed, the lower H-side decoder 314 and the lower L-side decoder 316 output the same voltage VH and VL, which are different by one bit of D3.

When the output of the upper decoders 310 and 312 is supplied to the odd-numbered column data line DL, the output of the lower decoders 314 and 316 is supplied to the even-numbered column data line DL.

In this way, by reversing the supply of the reference voltage between the upper decoders 310 and 312 and the lower decoders 314 and 316, one reference voltage generation circuit 300 is used to use both the upper and lower decoders of the panel. Digital-to-analog conversion can be performed in. Therefore, by alternately supplying the outputs of the upper decoders 310 and 312 and the lower decoders 314 and 316 to the data line DL, the polarity of the video signal can be inverted for each data line DL. Further, by alternately using the reference voltage amplifiers 300a and 300b for each horizontal line, the polarity of the video signal supplied to each data line DL can be changed for each horizontal scanning line. Therefore, the dot inversion drive in the liquid crystal display device can be achieved. Then, in the case of performing such driving, since the reference voltage generation circuit 300 can be integrated into one, the circuit can be simplified and the power consumption can be reduced.

"Lower significant bit conversion of DAC20 and amplifier 22 configuration" When VH and VL are obtained from the upper 3 bits (D5-D3) as described above, eight kinds of voltages corresponding to D2-D0 are obtained with respect to the voltage difference between VH and VL. FIG. 4 shows the configuration for this purpose. D2 is input as it is to the gate of TFT410-2, and is inverted and input to the gate of TFT412-2. VH is supplied to one end of TFT410-2, and VL is supplied to one end of TFT412-2. The other end of TFT410-2,412-2 is connected to one end of capacitor 430-2 via the charge control TFT420-2. The other end of capacitor 430-2 is connected to ground.

Therefore, when D2 is H level (1), TFT410-2 is turned on and VH is selected. Charging control Capacitor 430-2 is charged to VH when TFT420-2 is on. On the other hand, if D2 is L level (0), the capacitor 430 is charged to VL.

D1 and D0 have basically the same configuration as D2. Therefore, VH or VL is charged to the corresponding capacitors 430-1,430-0 according to the values of D1 and D0.

Further, a charge control TFT420-r is provided, and the charge control TFT420-r charges the VL directly to the corresponding capacitor 430-r regardless of the data. The charge control TFT420-r, 420-0,420-1,420-2 is turned on and off by the signal Charge.

The capacitance values of the capacitors 430-r, 430-0,430-1,430-2 are set to be C, C, 2C, and 4C. Note that C is, for example, 0.5pF, and in this case, 4C is 2pF.

Further, the upper end of the capacitor 430r, 430-0,430-1,430-2 is connected by three coupling TFT440-1,440-2,440-3, and the upper end of the capacitor 430-r becomes the output end via the TFT440-r. ing.

Then, a signal Combine is supplied to the gates of TFT440-1,440-2,440-3 and TFT440-r for coupling.

By such a circuit, if all D2-D0 are "0", all the capacitors 430-2,430-1,430-0,430-r are charged to VL. Therefore, the output voltage becomes VL. Here, VL is a value selected by D5-D3 and a voltage specified by D5-D0 as described above.

If D0 is "1", the charge of (VH-VL) and C is extra charged, the voltage obtained by 1 / 8C of this is added to VL, and VL + (VH-VL) / 8 is output. To. If D2 is "1", the charge of (VH-VL) · 4C is extra charged, and the voltage obtained by adding 1 / 8C of this is added to VL to output VL + 4 (VH-VL) / 8. To. Then, if all of D0, D1 and D2 are "1", VL + 7 (VH-VL) / 8 is output. Therefore, the voltage in units of (VH-VL) is added to VL according to the value of D0-D3, and the voltage corresponding to the value of D5-D0 is obtained at the output.

The voltage obtained at this output is the voltage between VCC and GND, and the polarity is reversed between the upper and lower sides of the panel (odd and even columns), and the polarity is changed every 1 horizontal period. Inverted.

Here, in the present embodiment, the size of the charge control TFT 420-r, 420-0, 420-1, 420-2 is set to 1: 1: 2: 4. That is, the capacitors 430-r, 430-0,430-1,430-2 charged by the charge control TFT420-r, 420-0,420-1,420-2 have a capacitance value of 1: 1: 2: 4, and the charge control TFT420- The amount of current flowing by r, 420-0, 420-1, 420-2 also corresponds to this ratio. Therefore, by setting the size of the charge control TFT420-r, 420-0,420-1,420-2 to 1: 1: 2: 4 as in the present embodiment, the corresponding capacitors 430-r, 430-0,430-1,430- The amount of charge charged to 2 can be set accurately to the capacitance value x voltage value, and the output voltage can be made accurate. Moreover, the change in voltage due to the MOS capacity of the transistor (charge control TFT) can be made the same.

"Configuration of amplifier 22" Configuration example 1 of the amplifier 22 will be described with reference to FIG. This amplifier 22 has a configuration for output correction. The output from the coupled TFT440-r is input to the buffer amplifier 452 via the switch TFT450, which is turned on and off by the signal φ01. On the other hand, one end of the correction capacitor 454 is connected to the input end of the buffer amplifier 452, and the other end of the correction capacitor 454 is connected to the ground GND via the voltage drop control capacitor 456.

Further, a voltage VL is supplied to the input end of the buffer amplifier 452 via a TFT 460 that is turned on and off by the charging signal Charge. Further, the voltage VL is supplied to the midpoint of the capacitors 454 and 456 by the TFT 462 turned on and off by the charging signal Charge, and the input side (DAC output end) of the switch TFT 450 is connected by the TFT 470 turned on and off by the signal φ03. Furthermore, the output end of the buffer amplifier 452 is connected via TFT 472.

The operation of such a circuit will be described with reference to FIGS. 5A and 5B. First, the input end of the buffer amplifier 452 and the midpoint of the capacitors 454, and 456 are set to the voltage VL by turning on the TFT 460,462 by the signal Charge. In this state, the capacitors 430-r, 430-0, 430-1, 430-2 are charged as described above, the charge amount is fixed, the Charge goes down, then the Combine goes up, and the data is input to the output end of the DAC20. The analog voltage Vin corresponding to the data appears.

Then, in step 1, the signal φ01 becomes the H level while the Combine is in the H level, and the switch TFT450 is turned on. As a result, the input end of the buffer amplifier 452 is set to the output voltage Vin of the DAC 20.

Next, in step 2, the TFT 472 is turned on by setting the signal φ02 to the H level. As a result, the midpoint between the capacitors 454 and 456 is set to the output voltage Vout of the buffer amplifier 452. The buffer amplifier 452 operates so that the output voltage matches the input voltage, but an error occurs due to its characteristics, and this is compensated for in the present embodiment. Here, if the error voltage in the buffer amplifier 452 is ΔV, it can be expressed as the output voltage Vout = Vin + ΔV.

In step 3, the signal φ02 is returned to the L level. As a result, the input end side (upper side) of the buffer amplifier 452 of the capacitor 454 is fixed to Vin, the capacitor 456 side (lower side) is fixed to Vout, and the capacitor 454 is charged with ΔV.

In step 4, the signal φ01 is set to L level and the switch TFT450 is turned off. Here, when this switch TFT450 is turned off, the gate potential changes from H level to L level, and the voltage at the input end of the buffer amplifier 452 drops slightly due to the gate capacitance (Cgs) of this switch TFT450. Here, the capacitor 454 is charged only by ΔV, and the capacitor 456 is charged only by Vout-GND. Therefore, the midpoint voltage of these capacitors 454,456 and the input end voltage of the buffer amplifier 452 cannot move so much. Assuming that the voltage dropped at the input end of the buffer amplifier 452 due to the switch TFT 450 being turned off is a, the voltage at the input end of the buffer amplifier 452 is Vin-a. Further, the voltage at the midpoint of the capacitors 454 and 456 is lower than that of a, but decreases according to a. Assuming that the voltage drop at the midpoint of the capacitors 454 and 456 is a', the voltage there is Vin + ΔV-a'.

In step 5, the signal φ03 is set to the H level, and the midpoint voltage of the capacitors 454,456 is set to Vin. As a result, the midpoint voltage of the capacitors 454 and 456 changes by Vin- (Vin + ΔV-a'). Therefore, the input voltage of the buffer amplifier 452 also changes by the same amount, and becomes Vin-a + Vin-Vin-ΔV + a', and Vin-ΔV- (a-a'). Although it depends on the capacitance value settings of the capacitors 454 and 456, a and a'are originally close values, and it is easy to make them almost the same. Assuming a = a', the input voltage of the buffer amplifier 452 is approximately Vin-ΔV. Therefore, the output of the buffer amplifier 452, which had Vout = Vin + ΔV when Vin was input, becomes Vout Vin because the input is lowered by ΔV, and the error is compensated.

"Other configurations for the lower bits of DAC20" FIG. 6 shows another configuration example for the lower bits of the DAC20. In this example, Pre-Charge is used instead of the signal Combine.

TFT410-2,412-2,410-1,412-1,410-0,412-0 are provided corresponding to D2-D0, and either VH or VL is selected respectively, and these are capacitors via the charge control transistor 420-2,420-1,420-0. It is supplied to one end side (upper side) of 430-2,430-1,430-0. Further, VL is directly supplied to the capacitor 430-r, and one end side (upper side) is always set to VL.

The other end side (lower side) of the capacitors 430-2,430-1,430-0,430-r is commonly connected to be the output of the DAC 20.

Then, TFT510-2 and 512-2 are connected in series between both ends of capacitor 430-2, TFT510-1 and 512-1 are connected in series between both ends of capacitor 430-1 and between both ends of capacitor 430-0. Is a series connection of TFT 510-0 and 512-0, and a series connection of TFT 510-r and 512-r is arranged between both ends of the capacitor 430-r. And at the midpoint between TFT510-2 and 512-2 series connection, TFT510-1 and 512-1 series connection, TFT510-0 and 512-0 series connection, and TFT510-r and 512-r series connection. , All are supplied with VL, and all the gates of these TFTs are supplied with signal Pre-Charge.

In such a circuit, by first setting the signal Pre-Charge to H level, both ends of all capacitors 430-2,430-1,430-0,430-r are set to VL.

Then, after setting the signal Pre-Charge to L level, turn on the charge control TFT420-2,420-1,420-0, and set VH or VL according to the data D2-D0 to one end of the corresponding capacitor 430-2,430-1,430-0. Supply to the side. As a result, the other end of the capacitors 430-2,430-1,430-0 to which VH is supplied tries to shift, but the amount of charge of each capacitor at that time is proportional to the capacitance value of the capacitors 430-2,430-1,430-0. As in the above case, the voltage at the output end is a voltage shifted from VL to VH by the amount corresponding to the value determined by D2-D0.

Also in this configuration, the charge control TFT420-2,420-1,420-0 has a transistor size corresponding to the capacitance ratio of the capacitors 430-2,430-1,430-0.

"Changeover switch 24" The configuration of the changeover switch 24 is shown in FIG. This changeover switch 24 has a first changeover unit 24a and a second changeover unit 24b, which are used for two standby signals, a WHITE signal and a BLACK signal, and a normal display of 64 gradations, which is the output of the DAC 20. Select and output one of the video signals.

First, the first switching unit 24a is switched by a mode signal indicating whether it is a normal mode or a standby mode (low power mode), and in the case of the normal mode, a video signal for normal display is selected and output.

On the other hand, in the standby mode, the standby signal is selected by the first switching unit 24a. 1st switching unit 24<u style="single">a</u>The output of the second switching unit 24b is supplied to the input terminal of the standby signal of. Then, the second switching unit 24b selects and outputs either a WHITE signal or a BLACK signal. Therefore, in the standby mode, either the WHITE signal or the BLACK signal selected by the second switching unit 24b is output via the first switching unit 24a.

Here, the second switching unit 24b is SRAM.<u style="single">18</u>The signal of MSB (5th bit of 0-5 bits) at the 6-bit output of is supplied. In the standby mode, the display is a display such as a simple symbol, and two types of display, white and black, are used, and either white or black is determined by the 5th bit of the video data. This is because that. If, for example, black is 000000 and white is 111111, the determination can be made by any bit. However, depending on the video data, the data in the entire range may not be used, and it is preferable to determine by an appropriate bit. That is, for each pixel, whether the pixel data is white or black is determined by an appropriate 1 bit in the pixel data, whereby either the WHITE signal or the BLACK signal is selected in the second switching unit 24b. Also, in this example, SRAM<u style="single">18</u>As a switching control signal, the predetermined bit of is supplied to the first switching unit 24a, and the 1st or 0 of the bit causes the first switching unit.<u style="single">1</u>Switching unit 24a is being switched.

In this way, in the normal display mode, the normal video signal from the DAC 20 is fed to the data line DL, and in the standby mode, either the WHITE signal or the BLACK signal is fed to the data line DL. To.

Even in a full-color display device having pixels of each RGB color, the display itself becomes white by supplying a high-brightness signal to all the pixels, and a black display by supplying a low-brightness signal to all. Become. In addition, since each RGB color pixel can be turned on and off, it is possible to display eight colors of R, G, B, R + G, R + B, G + B, white, and black.

In the standby mode, a multi-tone video signal for normal display is not required. Therefore, in the present embodiment, by selecting a separately prepared WHITE signal or BLACK signal from the digital video data, it is decided not to use the analog video signal, and the operation of the DAC 20 and the amplifier 22 is stopped to reduce the power consumption. Reduce. It is preferable to turn off the power of the amplifier 22, and it is preferable to turn off the power of the amplifier that generates the reference voltage of the DAC. As described above, in the standby mode, the processing of the analog signal becomes unnecessary, so that the power can be saved by completely stopping the operation of the analog circuit.

Here, in the liquid crystal, so-called AC drive is performed in which the direction of voltage application to the liquid crystal is reversed at predetermined intervals for the purpose of preventing seizure. Therefore, when using a normally black (black display is displayed when no voltage is applied) liquid crystal, the BLACK signal is a constant voltage similar to the supply electrode voltage, and the WHITE signal is separated from the common electrode at regular intervals. When the voltage is set and a normally white (white display is displayed when no voltage is applied) liquid crystal is used, the opposite signal is obtained.

Here, in the case of normal white, as shown in FIG. 8, the WHITE signal is a 1/2 VDD signal, and the BLACK signal is a signal that alternately repeats VSS and VDD every one horizontal scan, and this voltage is It is applied to the pixel electrode of the liquid crystal element. The voltage VCOM of the common electrode is set to almost the same voltage as the WHITE signal. This inverts the polarity (voltage greater than or less than VCOM) of the video signal supplied to the black display pixel for each row of pixels. Then, in the next frame, the polarity of the video signal for the corresponding line is inverted, so that the voltage application direction to the liquid crystal is inverted for each frame for the pixel that continues to display one black.

In particular, the dot inversion method that inverts the direction of the voltage applied to the liquid crystal for each dot is preferable even in the above-mentioned one line.

"Specific circuit configuration of switch 24" FIG. 9 shows a specific circuit configuration of the switch 24. The BLACK signal (LP_BLACK) is supplied to one end (drain or source) of the TFT 210, and the other end (source or drain) of the n-channel TFT 210 is connected to one end (source or drain) of the p-channel TFT 212. A WHITE signal (WHITE) is supplied to the other end (drain or source) of the TFT 210 of this p-channel. Then, the fifth bit (D5) of the video data is supplied to the gate of TFT210,212. Therefore, when D5 is "1", TFT210 is turned on, and when D5 is "0", TFT212 is turned on.

At the connection point between the TFT 210 and the TFT 212, one end of the n-channel TFT 214 is connected, and the other end of the TFT 214 is connected to the data line DL. The gate of TFT214 is supplied with an LP_ENB signal that becomes H level in standby mode. Therefore, in standby mode, the TFT 214 is turned on and either the BLACK signal or the WHITE signal is supplied to the data line DL.

Further, the 64-gradation analog video signal supplied from the DAC 20 via the amplifier 22 is supplied to one end of the n-channel TFT 216, and the other end of the TFT 216 is connected to the data line DL. The gate of the TFT 216 is supplied with an RGB_ENB signal that is set to the H level in the normal display mode. Therefore, in the normal display mode, the TFT 216 is turned on and a 64-gradation video signal is supplied to the data line DL.

In this way, the video data D5 selects either the WHITE signal or the BLACK signal, and the LP_ENB signal and the RGB_ENB signal select the video signal, or the WHITE signal or the BLACK signal, which is supplied to the data line DL. Will be done.

"Precharge configuration" Further, FIG. 9 shows a configuration for precharging the data line DL. That is, an n-channel TFT 230 is arranged between the data line DLs, and by turning on the TFT 230, adjacent data line DLs are connected to each other. This TFT 230 is located between all data line DLs. Further, an n-channel TFT232 is arranged between the line for supplying the WHITE signal and each data line DL, and by turning on this TFT232, the WHITE signal is supplied to the data line DL.

A DSG signal is supplied to the gates of the two TFT 230 and TFT 232. Therefore, by setting the signal DSG to the H level, both TFT230 and 232 are turned on, adjacent data lines DLs are connected to each other, and a WHITE signal is supplied here.

Here, this WHITE signal is a (1/2) VDD signal as shown in FIG. Therefore, each data line DL can be precharged to (1/2) VDD by setting the DSG signal to the H level during the horizontal blanking interval. The precharge is performed before setting the data in one horizontal scanning period such as the horizontal blanking interval in the data line DL.

In particular, in the case of the dot inversion method in which the polarity of the data described later is inverted between adjacent pixels (dots), the voltage value of the video signal set in the adjacent data line DL is in the opposite direction with the common electrode voltage VCOM as the boundary. ing. Therefore, by turning on TFT230 and connecting adjacent data line DLs, the voltage becomes close to the common electrode voltage VCOM. That is, in the display of natural images and the like, the brightness of adjacent pixels is often close, and therefore, by connecting the data line DLs set to the voltage for displaying the adjacent pixels, there is no need to supply power from the outside. , Can be set to a voltage close to VCOM. For example, in the all-black display, the data line DL is set alternately in VSS and VDD, and by connecting these, efficient precharging can be performed.

Further, in the present embodiment, TFT232 is provided, and each data line DL is set to (1/2) VDD. As a result, the power (charge amount) required for writing the video signal to the data line DL after that can be reduced to save power.

In the example of FIG. 9, the TFT230 and 232 were turned on and off by the DSG signal of one control line, and the TFT230 and 232 were turned on at the same timing. However, after turning on the TFT230 with the control lines separated, the TFT232 was turned on. It is also preferable to do so. The voltage supplied by TFT232 was set to (1/2) VDD, but the common electrode voltage VCOM.<u style="single">Other voltages may be used as long as the voltage is close to.</u>

Further, when the TFT 230 is provided, the TFT 232 can be omitted. That is, by turning on the TFT 230, adjacent data line DLs can be connected to each other via the TFT 230, and the same effect can be obtained. Also, only one of TFT230 or TFT232 can be provided.<u style="single">To.</u>

"Pixel circuit and dot inversion" Here, a format in which two capacitance lines are provided for one line and the voltages of these two capacitance lines are inverted for each frame with opposite polarities is preferable, and this configuration will be described below.

FIG. 10 shows a schematic configuration of a pixel circuit in which two capacitance lines are provided. The pixel circuits 1 are arranged in a matrix over the entire display area. The matrix arrangement may be zigzag rather than a perfect grid. The display may be monochrome or full color. In the case of full color, the pixels are usually three colors of RGB, but it is also preferable to add pixels of a specific color including white as needed.

As shown in the figure, one pixel circuit 1 has an n-channel pixel TFT 110 whose source is connected to the data line DL, a liquid crystal element 112 connected to the drain of this pixel TFT 110, and a holding capacity 114. .. A gate line GL arranged for each horizontal scanning line is connected to the gate of the pixel TFT 110.

The liquid crystal element 112 is configured such that pixel electrodes individually provided for each pixel are connected to the drain of the pixel TFT 110, and common electrodes common to all pixels are arranged to face the pixel electrodes so as to sandwich the liquid crystal. The common electrode is connected to the common electrode power supply VCOM.

Further, in the holding capacity 114, a portion extending the semiconductor layer constituting the drain of the pixel TFT 110 serves as one electrode as it is, and a part of the capacitance lines SC formed to face each other via the oxide film serves as a counter electrode. The portion of the holding capacity 114 that becomes the electrode may be separated from the portion of the pixel TFT 110 to form a separate semiconductor layer, and both may be connected by metal wiring.

Here, there are two capacitance lines SC for one line (horizontal scanning line), SC-A and SC-B, and the holding capacitance of each pixel circuit is SC-A and SC-B in the horizontal scanning direction. Are connected alternately to. In the pixel circuit shown in this figure, the holding capacity 114 is connected to the capacitance line SC-A, and the holding capacitance 114 of the adjacent pixel is connected to the capacitance line SC-B.

A vertical driver 120 is connected to the gate line GL, and this vertical driver 120 sequentially selects one gate line GL for each horizontal period to make it H level. The vertical driver 120 has a shift register, receives a signal STV indicating the start of one vertical scanning period, sets the first stage of the shift register to the H level, and then shifts the H level one by one by, for example, a clock signal. By doing so, the gate line GL of each horizontal scanning line is sequentially selected one by one to make it H level. Here, for example, the H level of the gate line GL is the VDD potential, the L level is the VSS potential, and these power supply voltages VDD and VSS are supplied to the vertical driver 120, thereby the output of the vertical driver of the gate line GL. H level and L level are set.

The SC driver 122 outputs two voltage levels to the two holding capacitance lines SC-A and SC-B.

Although not shown, the display device is also provided with, for example, a horizontal driver to control the sequential supply of the input video signal to the data line DL. That is, in this example, the horizontal driver outputs the sampling clock for each pixel according to the clock of the video signal for each pixel, and the switch is turned on and off by this sampling clock to make the video signal (data signal) for one horizontal scanning line. Latch. Then, the data signal for each pixel of the latched 1 horizontal scanning line is output to the data line DL over the 1 horizontal scanning period.

Actually, there are three types of video signals, RGB, and each pixel in the vertical direction is a pixel of the same color of any one of R, G, and B. Therefore, a data signal of any one color of RGB is set in the data line DL.

Then, in the apparatus of this embodiment, the AC application method of the dot inversion method is adopted. That is, at each pixel (dot) in the horizontal scanning direction, the voltage applied to the pixel electrode of the liquid crystal element 112 is applied as a data signal having the opposite polarity to the voltage VCOM of the common electrode.

The data signal with the first polarity is shown on the left side of FIG. 11, and the hypotenuse of the triangle written as Vvideo shows the data signal (write voltage) according to the brightness. The data signal has a Vb potential difference (dynamic range) from the black level to the white level, and the voltage applied to the pixel electrodes after the voltage shift is white when the voltage is far away from VCOM and black when the voltage is close. It has become. Therefore, in this example, the black level is VCOM-Vb / 2 and the white level is VCOM + Vb / 2. In the adjacent pixels, as shown on the right side of FIG. 11, the second polarity is opposite to the first polarity, the black level is VCOM + Vb / 2, and the white level is VCOM-Vb / 2. It has become.

Then, as shown in FIG. 12, after the on-period to the pixel TFT 110 is completed and the data writing is completed, the capacitance lines SC-A and SC-B are shifted by a predetermined voltage ΔVsc. In this example, a normally black vertical orientation (VA) type liquid crystal is used. For the pixel on the left side of FIG. 11, the capacitance line SC-A is connected, and Vsc shifts the voltage in the higher direction by ΔVsc. Further, for the pixel on the right side of FIG. 11, the capacitance line SC-B is connected, and Vsc shifts the voltage in the lower direction by ΔVsc.

As a result, as shown in FIG. 12, the data signal applied to the pixel electrode is shifted by a voltage corresponding to ΔVsc, and this is applied to and from VCOM. Here, ΔVsc is set to a voltage corresponding to the threshold voltage Vath at which the change in transmittance starts according to the applied voltage of the liquid crystal, and the voltage after the shift enables display by the liquid crystal element 112. Become. Further, the dynamic range of the data signal is set so that the dynamic range after shifting is the potential difference from the black level to the white level in the display.

In FIG. 11, Va (W) is the shift amount of the white level data signal, and Va (B) is the shift amount of the black level data signal, and these shift amounts are determined by ΔVsc. Vb is the potential difference (dynamic range) between the black level and white level of the data signal, and Vb'is the dynamic range after shifting.

"Overall operation" The operation of importing the video data into SRAMs 16 and 18 in FIG. 1 will be described with reference to the timing chart in FIG. 1 The horizontal scanning period consists of a data period in which video data is supplied to the video line 10 (Fig. 1) and a horizontal blanking interval (blanking period). The horizontal sync signal Hsync synchronizes for the horizontal scan period. The dot clock Dotclock is a signal synchronized with one dot of video data, and the horizontal start signal STH is a horizontal transfer register using XCKH (and CKH), which is a horizontal transfer clock with a frequency of 1/2, as the horizontal transfer clock. Transferred to 14 (Figure 1). Note that the enable signal ENB transfers the STH in the horizontal transfer register 14 only during the period when the video data is being supplied.

The STH is transferred to the first stage of the horizontal transfer register 14 as shown by SR01 in FIG. 13, and is subsequently transferred in the order of SR02 and SR03. In this example, the video data acquisition ends at 130 steps. Here, the video data is imported into SRAM 16 (FIG. 1) by AND01a to AND130a. Here, AND01a is a signal that becomes H level in the latter half of SR01 obtained by AND (logical product) of SR01 and SR01a (the same signal as SR02), and corresponds to the video data of the first dot of the video data. There is. Therefore, the video data of the first dot is taken into the SRAM 16 of the first stage by this AND01a. By AND01a ~ AND130a, one line of video data is imported into the corresponding SRAM 16.

In this example, the number of stages of the horizontal transfer register 14 is set to 133, and one line of video data captured in SRAM 16 is transferred to SRAM 18 by SR133.

Next, the operation of writing from the DAC 20 to the pixel circuit 100 will be described based on the timing chart of FIG.

First, when the blanking period ends, one line of video data is set in SRAM 18 as described above. So DAC<u style="single">20</u>Performs digital-to-analog conversion, but the capacitor 430 must be charged for the lower 3 bits. Therefore, the signal Charge is set to H level and charging is started. After charging is completed, set Charge to L level and signal Combine to H level. As a result, a 64-gradation analog video signal can be obtained at the output of the DAC 20.

During the period when the analog signal is output from the DAC 20, the output correction process of the amplifier 22 is performed as described above. Here, the timings of the signals φ01 to φ03 used in the configuration of FIG. 4 are shown, which are the same as those shown in FIG. 5A.

On the other hand, in switch 24, RGB_ENB is set to H level while Combine is H level, and the amplifier<u style="single">22</u>The analog video signal that is the output of is supplied to the data line DL, and the pixel circuit 100 of the corresponding line captures the analog video signal. Note that RGB_ENB prevents changes in the video signal on the data line DL by returning to the L level before Combine.

The gate line GL becomes H level in the data period, and in each pixel circuit 100, the gate line GL becomes H level toward the end of the period in which RGB_ENB is H level, and the data voltage in the pixel circuit 100 is determined.

On the other hand, during the blanking period, the signal DSG becomes H level and each data line DL is precharged to (1/2) VDD. Further, since the FRP is inverted during the blanking period, the polarity of the reference voltage in the DAC 20 is inverted, and the polarity of the analog video data is inverted.

<figref num="1">It is a figure which shows the structure for supplying the video data in the liquid crystal display device which concerns on embodiment to a pixel circuit.</figref><figref num="2">It is a figure which shows the structure of the latch type level shift circuit (SRAM16), and the latch circuit (SRAM18) which latches the output of this SRAM16.</figref><figref num="3">The configuration of the high-order bit conversion of DAC20 is shown.</figref><figref num="4">It is a figure which shows the structure of the high-order bit conversion of DAC20 and the structure of the configuration example of amplifier 22.</figref><figref num="5A">It is a figure for demonstrating operation of the circuit of amplifier 22.</figref><figref num="5B">It is a figure for demonstrating operation of the circuit of amplifier 22.</figref><figref num="6">It is a figure which shows the other configuration example about the lower bit of DAC20.</figref><figref num="7">It is a figure which shows the structure of the changeover switch 24.</figref><figref num="8">It is a figure which shows the waveform of a WHITE signal and a BLACK signal.</figref><figref num="9">It is a figure which shows the structure for the precharge of a data line.</figref><figref num="10">It is a figure which shows the schematic structure of the structure of the pixel circuit which provides two capacitance lines.</figref><figref num="11">It is a figure for demonstrating the voltage application state to the liquid crystal.</figref><figref num="12">It is a figure which shows the waveform of various signals.</figref><figref num="13">It is a timing chart about video data acquisition.</figref><figref num="14">It is a timing chart about analog video signal output.</figref>

Code description

10 video lines, 12 switches, 14 horizontal transfer registers, 22 amplifiers, 24 switches, 26 data lines.