Multilayer printed wiring board

The present invention relates to a multilayer printed wiring board, and improves electrical characteristics and reliability without causing malfunction or error even if a high-frequency IC chip, especially an IC chip in a high-frequency region of 3 GHz or higher, is mounted. We propose a multi-layer printed wiring board that can be used.

In the build-up type multilayer printed wiring board that constitutes the package for IC chips, interlayer insulating resin is formed on both sides or one side of the core substrate on which through holes are formed, and via holes for interlayer conduction are laser or photo. It is opened by etching to form an interlayer resin insulating layer. A conductor layer is formed in the via hole and on the interlayer resin insulating layer by plating or the like, and a pattern is formed through etching or the like to create a conductor circuit. Further, by repeatedly forming the interlayer insulating layer and the conductor layer, a build-up multilayer printed wiring board can be obtained. If necessary, solder bumps and external terminals (PGA / BGA, etc.) are formed on the surface layer to form a substrate or package substrate on which an IC chip can be mounted. The IC chip is electrically connected to the board by mounting C4 (flip chip).

Conventional techniques for build-up type multilayer printed wiring boards include JP-A-6-260756 and JP-A-6-275959. In both cases, lands are formed on a core substrate in which through holes are filled with a resin, an interlayer insulating layer having via holes on both sides is provided, a conductor layer is provided by an additive method, and the lands are connected to the lands. A multi-layer printed wiring board with high density and fine wiring can be obtained.

<patcit num="1"><text>Japanese Patent Application Laid-Open No. 6-260756</text></patcit><patcit num="2"><text>Japanese Patent Application Laid-Open No. 6-275959</text></patcit>

<p> However, as the frequency of IC chips increases, the frequency of malfunctions and errors has increased. Especially when the frequency exceeds 3GHz, the degree is increasing. Sometimes it stopped working at all beyond 5GHz. Therefore, a computer equipped with the IC chip as a CPU cannot perform desired functions and operations such as image recognition, switch switching, and data transmission to the outside, which should function.</p><p> When these IC chips and boards were non-destructively inspected and disassembled, problems such as short circuits and openness did not occur on the IC chips and boards themselves, and when IC chips with low frequencies (especially less than 1 GHz) were mounted. There were no malfunctions or errors.</p><p> In order to solve the above-mentioned problems, the present inventors propose to make the thickness of the conductor on the core substrate thicker than the thickness of the conductor layer on the interlayer insulating layer as described in Japanese Patent Application No. 2002-233775. did. However, in the above-mentioned invention, when an attempt is made to produce a core substrate having a fine wiring pattern, the insulation interval between the wiring patterns becomes narrow, resulting in a printed wiring board having poor insulation reliability. The object of the first invention is to provide an IC chip in a high frequency region, particularly a multilayer printed wiring board that can form a printed circuit board or a packaged circuit board with high insulation reliability without causing malfunction or error even if it exceeds 3 GHz. It is to propose.</p><p> In the second invention, as a countermeasure against malfunction at high frequency, the present inventor examined using a multilayer core substrate as a core substrate and providing a thick conductor layer in the multilayer core substrate. This multilayer printed wiring board will be described with reference to FIG. 35. The multilayer printed wiring board 10 uses a multilayer core substrate 30. On the signal circuit 34S, power supply circuit 34P, and ground circuit 34E on the surface of the multilayer core substrate 30, the interlayer insulating layer 50 in which the via hole 60 and the conductor circuit 58 are formed, and the via hole 160 and the conductor circuit 158 are formed. An interlayer insulating layer 150 is provided. A solder resist layer 70 is formed on the upper layer of the via hole 160 and the conductor circuit 158, and bumps 76U and 76D are formed on the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. ing.</p><p> The upper power supply circuit 34P of the multilayer core substrate 30 is formed as a plane layer for power supply, and the lower ground circuit 34E is formed as a plane layer for grounding. Further, on the front surface side inside the multilayer core substrate 30, a dummy land 16D extending from the inner layer ground circuit 16E and the power supply through hole 36THP extends from the power supply circuit 16P and the power supply through hole 36THE on the back surface. Dummy land 16D is formed. A dummy land is a conductor circuit extending from a through hole, and is a wiring pattern that does not conduct with other wiring in the same layer, or a wiring pattern that electrically connects the same potential (Fig.). It means 16D1) in 36 (A). The upper ground circuit 16E is formed as a plane layer for grounding, and the lower power supply circuit 16P is formed as a plane layer for power supply. FIG. 36 (A) shows the X4-4 cross section in FIG. 35, and FIG. 36 (B) shows the X5-X5 cross section. Through holes 36 are provided for connecting the front and back surfaces of the multilayer core substrate 30. The dummy land 16D is provided around the through hole 36 which is not connected to the ground circuit 16E and the power supply circuit 16P. Around the dummy land, there is a non-conductor forming portion (non-conductor forming portion removed 35) for ensuring insulation between the dummy land and other wiring patterns, and is adjacent as shown in FIG. 36 (A). When through holes of the same potential are located at the positions where the through holes are formed, a dummy land 16D1 formed collectively around the through holes may be formed.</p><p> In the multi-layer printed wiring board with this configuration, by thickening the ground circuits 16E and 16P of the multi-layer core board 30, the third voltage drop of the IC voltage drops that occurs multiple times after the switch is turned on is mainly caused. It turned out to be improved. However, it was found that the first and second voltage drops were not significantly improved.</p><p> The second invention has been made to solve the above-mentioned problems, and the purpose thereof is an IC chip in a high frequency region, particularly a printed circuit board or a package board in which malfunctions and errors do not occur even if the frequency exceeds 3 GHz. The purpose is to propose a multi-layer printed wiring board that can constitute the above. In particular, the purpose is to improve the first and second voltage drops that occur after the switch is turned on.</p>

<p>[First invention] As a result of diligent research toward the realization of the above object, the inventors have come up with the first invention having the following contents as a gist. That is, The first invention is in a multilayer printed wiring board in which an interlayer insulating layer and a conductor layer are formed on a core substrate and electrically connected via a via hole.<u style="single">The thickness of the conductor layers on the front and back surfaces of the multilayer core substrate is thinner than the thickness of the conductor layer of the inner layer.</u>At least one of the sums of the thicknesses of the conductor layers for power supply or grounding of the core substrate is in the multilayer printed wiring board characterized by being thicker than the thickness of the conductor layer on the interlayer insulating layer.</p><p> That is, the core substrate is a multilayer core substrate, and the sum of the conductor layers is increased instead of increasing the thickness of the conductor layers only on the front and back surfaces of the core substrate. In the case of a multilayer core substrate, the thickness obtained by adding the conductor layers on the front and back sides of the core substrate and the conductor layers on the inner layer is the thickness that contributes to the power supply to the IC and its stabilization. In this case, it is applied when the conductor layer of the surface layer and the conductor layer of the inner layer are electrically connected and have electrical connections at two or more places. That is, by increasing the sum of the thicknesses of the conductor layers of the multilayer core substrate and using the conductor layer of the core as the conductor layer for the power supply, the ability to supply power to the IC chip can be improved. .. Further, by using the conductor layer of the core as the ground layer, it is possible to reduce the signal to the IC chip and the noise superimposed on the power supply, and to stably supply the power supply to the IC. Therefore, when the IC chip is mounted on the multilayer printed circuit board, the loop inductance from the IC chip to the substrate to the power supply can be reduced. Therefore, the power supply shortage in the initial operation is reduced, so that the power supply shortage is less likely to occur, and therefore, even if an IC chip in the high frequency region is mounted, malfunctions and errors in the initial startup are not caused. Moreover, since noise is reduced, malfunctions and errors do not occur. Further, by using the multilayer core substrate, the thickness of each conductor layer of the multilayer core substrate can be reduced while maintaining the sum of the thicknesses of the conductor layers of the multilayer core substrate. That is, as a result, even if a fine wiring pattern is formed, the insulation interval between the wiring patterns can be surely secured, so that it is possible to provide a printed wiring board having high insulation reliability. As another effect, by increasing the thickness of the conductor layer for power supply or grounding of the core substrate, the strength of the core substrate is increased, and even if the core substrate itself is thinned, the warp and the generated stress are applied to the substrate itself. It becomes possible to alleviate with.</p><p> Further, the same effect is obtained when power is supplied to the IC chip via the IC chip-board-capacitor or power supply layer-power supply. The loop inductance described above can be reduced. Therefore, there is no loss in the power supply of the capacitor or dielectric layer. In the first place, IC chips consume electric power instantaneously to perform complicated arithmetic processing and operations. Even if an IC chip in the high frequency region is mounted by supplying power from the power supply layer to the IC chip, the power supply can be supplied without mounting a large number of capacitors in response to a power shortage (a situation where a voltage drop occurs) in the initial operation. Can be supplied. In the first place, in order to use an IC chip in the high frequency region, a power supply shortage (voltage drop) occurs during initial operation, but in an IC chip with a low frequency, the capacity of the mounted capacitor or the built-in dielectric layer is sufficient.</p><p> In particular, when the sum of the thicknesses of the conductor layers used as the power supply layer of the core substrate is thicker than the thickness of the conductor layer on the interlayer insulating layer on one side or both sides of the core substrate, the above effect is maximized. Can be done. The conductor layer on the interlayer insulating layer in this case is a conductor layer on the interlayer insulating layer in the build-up portion of the so-called build-up printed wiring board (58, 158 in FIG. 8 in the present application). ..</p><p> The power supply layer of the core substrate may be arranged on the surface layer, the inner layer, or both of the substrate. It may be arranged on at least one layer or a plurality of layers among the front surface, the back surface, and the inner layer of the substrate. In the case of the inner layer, it may be multi-layered over two or more layers. The remaining layer should be the ground layer. Basically, if the sum of the conductor layers for the power supply of the core substrate is thicker than that of the conductor layer of the interlayer insulating layer, the effect is obtained. It is desirable to alternately arrange the conductor layers for power supply and the conductor layers for grounding in order to improve the electrical characteristics. However, it is desirable to form it in the inner layer. When formed on the inner layer, the power supply layer is arranged between the IC chip and the external terminal or capacitor. Therefore, the distance between the two is uniform, the cause of obstruction is reduced, and the power supply shortage is suppressed.</p><p> Further, in the present invention, in a multilayer printed wiring board in which an interlayer insulating layer and a conductor layer are formed on a core substrate and electrically connected via a via hole. The multilayer printed wiring board is characterized in that α2 &lt;α1 40α2 when the sum of the thicknesses of the conductor layers for power supply of the multilayer core substrate is α1 and the thickness of the conductor layer on the interlayer insulating layer is α2.</p><p>When α1 α2, there is no effect on power shortage. In other words, it is not clear that the degree of voltage drop that occurs during the initial operation is suppressed. A study was also conducted on the case where α1&gt; 40α2 was exceeded, and the result was that it took time to supply power to the IC because the substrate became thicker. That is, it can be understood that it is the critical point of the effect of the present application. Even if it is made thicker than this, no improvement in electrical effect can be expected. Further, if this thickness is exceeded, it becomes difficult to form a land or the like for connecting to the core substrate when the conductor layer is formed on the surface layer of the core substrate. Further, when the interlayer insulating layer of the upper layer is formed, the unevenness becomes large and the interlayer insulating layer is wavy, so that the impedance may not be matched. However, there are cases where there is no problem even in that range (α1&gt; 40α2).</p><p> It is more desirable that α1 of the sum of the thicknesses of the conductor layers for the power supply of the multilayer core substrate is 1.2 α2 α1 40 α2. Within that range, it has been confirmed that IC chip malfunctions and errors do not occur due to insufficient power supply (voltage drop).</p><p> The core substrate in this case is a resin substrate in which a core material is impregnated with glass epoxy resin or the like, a ceramic substrate, a metal substrate, a composite core substrate using a composite of resin, ceramic, and metal, and a conductor layer in the inner layer of those substrates. Refers to a substrate provided with a structure, a substrate using a multilayer core substrate having three or more multilayered conductor layers formed therein, and the like.</p><p> In order to increase the sum of the thicknesses of the conductor layers for the power supply of the multilayer core substrate, a method of a printed wiring board in which a conductor layer generally performed such as plating and sputtering is formed on a substrate in which metal is embedded is used. The formed one may be used.</p><p> Further, in the present invention, in a multilayer printed wiring board in which an interlayer insulating layer and a conductor layer are formed on a core substrate and electrical connection is performed via a via hole, the thickness of the conductor layer for grounding the multilayer core substrate. When the sum of is α3 and the thickness of the conductor layer on the interlayer insulating layer is α2, α3 and α2 are in a multilayer printed wiring board characterized in that α2 &lt;α3 40 α2. Within this range, noise superimposed on the signal power supply to the IC chip can be reduced. In addition, it becomes possible to stably supply power to the IC. Furthermore, the effect increases when the range of 1.2α1 &lt;α3 40α2 is set.</p><p> If the multilayer printed wiring board is made of materials having the same thickness and is laminated, a layer or substrate having a power supply layer as a conductor layer in the printed circuit board is defined as a core substrate.</p><p> Further, the multilayer core substrate has a conductor layer relatively thick in the inner layer and a conductor layer relatively thin in the surface layer, and the conductor layer in the inner layer is mainly a conductor layer for a power supply layer or a conductor layer for grounding. Is preferable. (Relatively thick and thin means that the thickness of all conductor layers is compared, and if there is a tendency, in this case, the inner layer is relatively thick compared to other conductor layers, and the surface layer is However, the surface conductor layer may be used as a conductor layer for power supply or grounding, one side is for power supply and the other side is for grounding. It may be used as a conductor layer of. That is, by arranging the thick conductor layer on the inner layer side, even if the thickness is arbitrarily changed, the resin layer can be formed so as to cover the conductor layer of the inner layer, so that the core is flat. Sex is obtained. Therefore, the conductor layer of the interlayer insulating layer does not swell. Even if a thin conductor layer is arranged on the surface layer of the multilayer core substrate, it is possible to secure a sufficient thickness of the conductor layer as the conductor layer of the core by adding the thickness of the conductor layer of the inner layer. By using these as a conductor layer for a power supply layer or a conductor layer for grounding, it is possible to improve the electrical characteristics of a multilayer printed wiring board.</p><p> When a multi-layer core substrate is formed, the inner conductor layer is formed so that the thickness of the conductor layer is relatively thick and the surface conductor layer is used as a power supply layer so as to sandwich the inner conductor layer. Moreover, it is also desirable that it is used as a signal line. With this structure, the above-mentioned power supply can be strengthened.</p><p> Further, since the microstrip structure can be formed by arranging the signal lines between the conductor layers in the core substrate, the inductance can be reduced and impedance matching can be achieved. Therefore, the electrical characteristics can also be stabilized. Further, it is more desirable to make the conductor layer of the surface layer relatively thin. The core substrate may have a through-hole pitch of 600 μm or less.</p><p> In the multilayer core substrate, a resin layer is interposed on both sides of an electrically isolated metal plate to form an inner conductor layer, and a resin layer is interposed outside the inner conductor layer to form a surface conductor layer. It is preferably formed. Sufficient mechanical strength can be ensured by arranging an electrically isolated metal plate in the central portion. Further, a resin layer is interposed on both sides of the metal plate to form an inner conductor layer, and further, a resin layer is interposed outside the inner conductor layer to form a surface conductor layer, thereby forming a surface conductor layer on both sides of the metal plate. By providing symmetry, it is possible to prevent warpage and swell from occurring in a heat cycle or the like. In a multilayer core substrate, an insulating layer is interposed on both sides of a metal plate having a low thermal expansion coefficient such as 36 alloy or 42 alloy, and an inner conductor layer is interposed, and an insulating layer is further interposed outside the inner conductor layer. A surface conductor layer may be formed. By arranging an electrically isolated metal plate in the center, the coefficient of thermal expansion in the XY direction of the multi-layer printed wiring board can be made close to the coefficient of thermal expansion of the IC, and at the connection between the IC and the multi-layer printed wiring board. The local heat cycle property of the resin layer is improved. Further, by interposing an insulating layer on both sides of the metal plate to form an inner conductor layer, and further interposing an insulating layer on the outside of the inner layer conductor layer to form a surface conductor layer, on both sides of the metal plate. By providing symmetry, it is possible to prevent warpage and swell from occurring in a heat cycle or the like.</p><p> In FIG. 10, the vertical axis shows the voltage of the IC chip, and the horizontal axis shows the passage of time. Figure 10 is a model of a printed wiring board that is equipped with a high-frequency IC chip of 1 GHz or higher and does not have a capacitor for power supply. Line A shows the time course of the voltage of the 1 GHz IC chip, and line B shows the time change of the voltage of the 3 GHz IC chip. In this figure, the third voltage drop is shown among the voltage drops that occur a plurality of times after the switch is turned on. The change over time requires a large amount of power supply instantly when the IC chip starts to start up. If the supply is insufficient, the voltage will drop (point X, point X'). After that, the power supply to be supplied is gradually satisfied, so that the voltage drop is eliminated. However, when the voltage drops, it is easy to cause malfunction or error of the IC chip. In other words, it is a problem that occurs because the function of the IC chip does not function sufficiently and does not start due to insufficient power supply. This power shortage (voltage drop) increases as the frequency of the IC chip increases. Therefore, it takes time to eliminate the voltage drop, and a time lag occurs in order to perform the desired function and activation.</p><p> In order to compensate for the above-mentioned power supply shortage (voltage drop), the power supply shortage or voltage drop can be reduced by connecting to an external capacitor and discharging the power supply accumulated in the capacitor. FIG. 11 shows a model of a printed circuit board equipped with a capacitor. Line C shows the change in voltage over time in a 1 GHz IC chip with a small-capacity capacitor mounted. The degree of voltage drop is smaller than that of wire A without a capacitor. Further, the wire D is a capacitor having a larger capacity than that of the wire C, and shows a change with time like the wire C. Furthermore, the degree of voltage drop is becoming smaller than that of line C. As a result, the desired IC chip can also function and start up. However, as shown in FIG. 10, when the IC chip becomes a higher frequency region, a larger capacitor capacity is required, and therefore it is necessary to set a region for mounting the capacitor, so that the voltage can be secured. It becomes difficult, it is not possible to improve the operation and function, and it becomes difficult in terms of high density.</p><p> The graph in FIG. 12 shows the state of the voltage drop when α1 / α2 is changed, where the sum of the thicknesses of the conductor layers for the power supply of the multilayer core substrate is α1 and the thickness of the conductor layer on the interlayer insulating layer is α2. In FIG. 12, line C shows a change in voltage over time at α1 = α2 on a 1 GHz IC chip with a small-capacity capacitor mounted. In addition, line F is a 1 GHz IC chip with a small-capacity capacitor mounted, and shows the change over time in voltage at α1 = 1.5α2. Line E is a 1 GHz IC chip with a small-capacity capacitor mounted. Shows the change over time of the voltage at α1 = 2.0α2. As the sum of the thicknesses of the conductor layers of the core becomes thicker, the power supply shortage or the voltage drop becomes smaller. Therefore, it can be said that the occurrence of malfunctions in the functions and operations of the IC chip is reduced. By increasing the sum of the thicknesses of the conductor layers for power supply of the core substrate, the volume of the conductor layers is increased. As the volume increases, the conductor resistance decreases, so there is no loss to the voltage and current in the transmitted power supply. Therefore, the transmission loss between the IC chip and the power supply is reduced, and the power supply is supplied, so that malfunctions and errors do not occur. In this case, the factor due to the sum of the thicknesses of the conductor layers for power supply is particularly large, and the effect is obtained by making the sum of the thicknesses of the conductor layers for power supply in the core substrate thicker than the thickness of the conductor layer on the interlayer insulating layer. Play.</p><p> Further, even if the board has electronic components such as a capacitor, a dielectric layer, and a resistor built in the core board, the effect is remarkable. By incorporating it, the distance between the IC chip and the capacitor or dielectric layer can be shortened. Therefore, the loop inductance can be reduced. Power shortage or voltage drop can be reduced. For example, even in a core substrate having a built-in capacitor or a dielectric layer, the thickness of the conductor layer of the core substrate and the conductor layer of the power supply layer can be made thicker than the thickness of the conductor layer on the interlayer insulating layer to serve as the main power supply. Since the conductor resistance of both the built-in capacitor and the power supply of the dielectric layer can be reduced, the transmission loss can be reduced, and the effect of the substrate having the built-in capacitor can be further exhibited.</p><p> The material of the core substrate was verified with a resin substrate, and it was found that the same effect was obtained with ceramic and metal core substrates. In addition, the material of the conductor layer was also made of a metal made of copper, but it has not been confirmed that the effects are offset and the occurrence of malfunctions and errors increases with other metals, so the material of the core substrate is used. It seems that the effect does not affect the difference or the difference in the material forming the conductor layer. More preferably, the conductor layer of the core substrate and the conductor layer of the interlayer insulating layer are formed of the same metal. Since the characteristics and physical properties such as electrical characteristics and coefficient of thermal expansion do not change, the effects of the present application can be achieved.</p><p>[Effect of the first invention] According to the first invention, the resistance in the conductors of the IC chip, the substrate, and the power supply can be reduced, and the transmission loss is reduced. Therefore, the transmitted signal and power supply exert the desired ability. Therefore, since the functions and operations of the IC chip operate normally, no malfunction or error occurs. It is possible to reduce the resistance in the conductors from the IC chip to the substrate to the ground, reduce the superposition of noise on the signal line and power line, and prevent malfunctions and errors. It was also found that the first invention reduces the degree of power supply shortage (voltage drop) that occurs at the initial startup of the IC chip, and even if an IC chip in the high frequency region, especially an IC chip of 3 GHz or higher, is mounted, there is a problem. It turns out that it can be started without. Therefore, the electrical characteristics and electrical connectivity can also be improved. Then, by making the core substrate multi-layered and increasing the sum of the thicknesses of the conductor layers, it is possible to obtain a printed wiring board having excellent insulation reliability. Further, the resistance in the circuit of the printed circuit board can be made smaller than that of the conventional printed circuit board. Therefore, even if a bias is applied and a reliability test (high temperature and high humidity bias test) is performed under high temperature and high humidity, the time for destruction is long, so that the reliability can be improved. In addition, since the resistance of the conductor layer for power supply is low, heat generation can be suppressed even if a large amount of electricity flows. The same applies to the ground layer. In this respect as well, malfunctions are less likely to occur, and the reliability of the printed wiring board after IC mounting is improved.</p><p>[Second invention] As the second invention, as a result of diligent research toward the realization of the above object, the inventors have come up with an invention having the following contents as a gist. That is, In the second invention, an interlayer insulating layer and a conductor layer are formed on a three or more multilayer core substrate having a plurality of through holes connecting the front surface and the back surface and having a conductor layer on the front surface and the back surface and a conductor layer on the inner layer. In a printed wiring board that is formed and electrically connected through a via hole. The plurality of through holes are composed of a large number of power supply through holes, a large number of ground through holes, and a large number of signal through holes that are electrically connected to the power supply circuit, the ground circuit, or the signal circuit of the IC chip. When the power supply through hole penetrates the grounding conductor layer of the inner layer of the multilayer core substrate, among a large number of power supply through holes, at least directly under the IC, or 70% or more of the power supply through hole is the grounding conductor. Layers do not have conductor circuits extending from power through holes, or / and When the grounding through hole penetrates the power supply conductor layer of the inner layer of the multilayer core substrate, among a large number of grounding through holes, at least directly under the IC, or 70% or more of the grounding through hole is a power supply conductor. The technical feature of the layer is that it does not have a conductor circuit extending from the ground through hole.</p><p> However, it is not necessary that all through holes directly under the IC be through holes having the above-mentioned characteristics, and the present invention may be applied to some through holes. That is, an interlayer insulating layer and a conductor layer are formed on a three or more multilayer core substrates having a plurality of through holes connecting the front surface and the back surface and having a conductor layer on the front surface and the back surface and a conductor layer on the inner layer. In a printed wiring board where electrical connections are made through holes The plurality of through holes are composed of a large number of power supply through holes, a large number of ground through holes, and a large number of signal through holes that are electrically connected to the power supply circuit, the ground circuit, or the signal circuit of the IC chip. When the power supply through hole penetrates the ground conductor layer of the inner layer of the multilayer core substrate, among a large number of power supply through holes, some power supply through holes directly under the IC are used as a power source in the ground conductor layer. There is no conductor circuit extending from the through hole for grounding, and when the through hole for grounding penetrates the conductor layer for power supply in the inner layer of the multilayer core substrate, a part of the large number of through holes for grounding directly under the IC. The ground through hole is a printed wiring board whose technical feature is that the power supply conductor layer does not have a conductor circuit extending from the ground through hole.</p><p> Further, a power supply through hole having no conductor circuit extending from the power supply through hole in the ground conductor layer and a ground through hole having no conductor circuit extending from the ground through hole in the power supply conductor layer are latticed. It is characterized in that it is arranged in a shape or a staggered pattern. In this case, it is preferable that the power supply through holes and the ground through holes are alternately located. Hereinafter, a power supply through hole that does not have a conductor circuit extending from the power supply through hole in the ground conductor layer is a power supply through hole that does not have a dummy land, and a conductor circuit that extends from the ground through hole in the power supply conductor layer. A through hole for earth that does not have a dummy land is called a through hole for earth that does not have a dummy land, or simply a through hole that does not have a dummy land.</p><p> Further, the technical feature is that the sum α1 of the thicknesses of the conductor layers for the power supply of the multilayer core substrate is α2 &lt;α1 40α2 with respect to the thickness α2 of the conductor layer on the interlayer insulating layer. Further, it is a technical feature that the sum α3 of the thicknesses of the conductor layers for grounding of the multilayer core substrate is α3 &lt;α1 40α2 with respect to the thickness α2 of the conductor layer on the interlayer insulating layer.</p><p>[Effect of the second invention] In the second invention, of the through holes for power supply and / and ground, the through holes directly under the IC or 70% or more do not have dummy lands in the inner layer of the multilayer core substrate. As the first effect of the second invention, since the through-hole intervals are narrow pitches, finening is possible. As a result, the size of the printed wiring board can be reduced. As a second effect, since the distance between the power supply through hole and the ground through hole can be narrowed, the mutual inductance can be reduced. Therefore, the power shortage due to the first and second power drops in the initial operation of the IC is mainly reduced. Power shortages are less likely to occur, and even if an IC chip in the high frequency region is mounted, malfunctions and errors during initial startup are less likely to occur.</p><p> The third effect is that the wiring length that supplies power to the IC transistors is shortened, so the voltage drop of the IC is unlikely to occur. On the other hand, in the multilayer printed wiring board having a dummy land, the wiring length for supplying power to the IC transistor becomes long. This is because electricity easily flows on the surface of the conductor, so that the wiring length when the dummy land is provided is the wiring length of the dummy land surface added to the wiring length of the through hole. The same effect can be obtained even if the through hole without a dummy land is a part directly under the IC. This is because electricity flows preferentially through wiring with low resistance, so even if there are some through holes that do not have dummy lands, power can be supplied to the IC transistors via the through holes that do not have dummy lands. Is. However, the power supply through hole and the ground through hole having no dummy land are preferably 30% or more, more preferably 50% or more, respectively, with respect to the all power supply through hole and the all ground through hole, respectively. If the number of through holes having no dummy land is small, electricity is concentrated in such through holes, so that the effect of the present invention is reduced. Further, it is preferable that the power supply through holes having no dummy lands and the ground through holes having no dummy lands are arranged in a grid pattern or a staggered pattern. In this case, it is more preferable that they are arranged alternately. This is because the mutual inductance is reduced, so that the power is supplied to the transistor of the IC in a short time.</p><p> The fourth effect is that the conductor area of the inner power supply layer and the ground layer in the multilayer core can be increased, so that the conductor resistance of both conductor layers is reduced, so that the power supply to the IC transistor is smoothly performed. Because there is no dummy land, the power supply layer and ground layer can be formed closer to the through hole (see Fig. 37). Comparing the periphery of the through hole V and the periphery of W in FIG. 37, since there is no dummy land in W, the conductor layer can be formed in the vicinity of the through hole, so that more conductor layers are formed than in the periphery of V. From the above effects, according to the multilayer printed wiring board of the present invention even if simultaneous switching is performed, the IC transistor is unlikely to run out of power, so that malfunction is unlikely to occur. Further, the thickness of the conductor layers on the front and back surfaces of the multilayer core substrate and the conductor layer on the inner layer is increased. In particular, it is preferable to increase the thickness of the inner conductor layer. As this effect, the volume of the conductor itself can be increased by thickening the conductor layer. By increasing the volume, the resistance in the conductor can be reduced. Therefore, by using the conductor layer as the power supply layer, the ability to supply power to the IC chip is improved. Further, by using the conductor layer as the ground layer, it is possible to reduce the signal to the IC chip and the noise superimposed on the power supply. Therefore, when the IC chip is mounted on the printed wiring board, the inductance from the IC chip to the board to the power supply can be reduced, and the third voltage drop in the initial operation can be mainly improved. Further, as shown in FIG. 34, the first and second voltages are obtained because the area (opposing area) and the distance between the through holes having opposite potentials and the conductor layer are increasing and the two are approaching each other. The descent is further reduced. Since the through hole does not have a dummy land, for example, the distance between the power supply through hole having no dummy land and the ground layer having a reverse potential is close. Further, since the ground layer is thick, the distance between the power supply through hole and the ground layer becomes long. Therefore, it is possible to improve the power supply drop as compared with simply using a multilayer printed wiring board having no dummy land. The distance of X shown in FIG. 34 is preferably 15 to 150 μm. If it is 15 μm or less, the insulation reliability will decrease. On the other hand, if it exceeds 150 μm, the effect of improving the voltage drop becomes small. In this way, when the through hole penetrates the inner layer having another potential of the multilayer core substrate, it is generated at the initial operation by increasing the conductor thickness without providing a dummy land directly under the IC or in the through hole of 70% or more. The main voltage drop (1st to 3rd voltage drop) can be improved. Therefore, even if a high-frequency IC chip is mounted on the printed wiring board, it does not cause a malfunction or an error at the initial startup. The same effect can be obtained even if there is a part of the through hole that does not have a dummy land directly under the IC.</p><p> A multi-layer core structure in which no dummy land is provided in the inner layer is particularly effective when the conductor thickness of the inner layer is made thicker than the conductor thickness of the front and back surfaces of the multi-layer core substrate to secure the sum (α1) of the thicknesses of the conductor layers of the core. is there. The reason is that through-hole lands are indispensable for the front and back conductor layers in order to establish an electrical connection with the build-up layer formed on the conductor layers. If the conductor layers on the front and back sides are thick, it is necessary to widen the insulation interval between the through-hole lands and other through-hole lands or other conductor circuits in order to ensure insulation reliability. This is because the pitch between holes cannot be narrowed. Further, if the conductor thickness on the front and back surfaces of the multilayer core substrate is increased, the interlayer insulating layer formed on the multilayer core substrate is wavy, so that impedance matching cannot be performed.</p><p> The thickness of the conductor layer of the core is the sum of the conductor layer of the surface layer and the conductor layer of the inner layer of the multilayer core substrate. In this case, it is applied when the conductor layer of the surface layer and the conductor layer of the inner layer are electrically connected and have electrical connections at two or more places. If the area is about the size of a pad or land, the thickness of the conductor layer in that area is not the total thickness. The conductor layer is preferably a power supply layer or a ground layer. In this case, a multilayer core substrate composed of three layers (surface layer + inner layer) may be used. A multilayer core substrate having three or more layers may be used. If necessary, an electronic component storage multilayer core substrate formed by embedding components such as a capacitor, a dielectric layer, and a resistor in the inner layer of the multilayer core substrate may be used.</p><p> Further, when the conductor layer of the inner layer of the multilayer core substrate is thickened, it is better to arrange the corresponding conductor layer directly under the IC chip. By disposing it directly under the IC chip, the distance between the IC chip and the power supply layer can be minimized, and therefore the inductance can be further reduced. As a result, power is supplied more efficiently, and in particular, the third voltage drop is eliminated. Also at this time, it is desirable that the sum of the thicknesses of the conductor layers of the multilayer core substrate is α1, and the thickness of the conductor layer on the interlayer insulating layer is α2, where α2 &lt;α1 40α2.</p><p> The thickness of the conductor layer of the inner layer of the multilayer core substrate is made thicker than that of the conductor layer on the interlayer insulating layer. As a result, even if a thin conductor layer is arranged on the surface of the multilayer core substrate, a sufficient thickness can be secured as the conductor layer of the core by adding the thick conductor layer of the inner layer. That is, even if a large amount of power is supplied, it can be started without any problem, so that it does not cause malfunction or malfunction. Also at this time, it is desirable that the sum of the thicknesses of the conductor layers of the multilayer core substrate is α1, and the thickness of the conductor layer on the interlayer insulating layer is α2, where α2 &lt;α1 40α2.</p><p> FIG. 28 shows the temporal change of the IC voltage from the moment the power is turned on. The vertical axis shows the IC voltage, and the horizontal axis shows the passage of time. Figure 28 is a model of a printed wiring board that mounts a high-frequency IC chip of 1 GHz or higher and does not have a capacitor for power supply. Line B shows the change of voltage to the 1 GHz IC chip with time, and line A shows the change of voltage to the 3 GHz IC chip with time. The change over time requires a large amount of power supply instantly when the IC chip starts to start up. If the supply is insufficient, the voltage will drop (point X, point X': first voltage drop). After that, once the voltage rises, then falls again (second voltage drop), then rises and then falls (third voltage drop), and then the voltage gradually rises while repeating small amplitudes. However, when the voltage drops, it is easy to cause malfunction or error of the IC chip. In other words, it is a problem that occurs because the function of the IC chip does not function sufficiently and does not start due to insufficient power supply. This power shortage (voltage drop) increases as the frequency of the IC chip increases. Therefore, it takes time to eliminate the voltage drop, and a time lag occurs in order to perform the desired function and activation.</p><p> FIG. 29 shows the temporal change of the voltage of the IC when the high frequency IC chip is mounted on the printed wiring board of the conventional structure and the printed wiring board of the present invention. Since the voltage of the IC cannot be measured directly, a measurement circuit was formed so that the voltage could be measured on the printed wiring board. The multi-layer core (conventional structure) of A has 4 layers, all through holes have dummy lands, and the conductor thickness of each layer for power supply is the same, 15 μm (the power supply layer of the core substrate is 2 layers). , The conductor thickness on the through-hole insulation layer is 30 μm). The multilayer core of B has four layers like A, but has a conductor layer for power supply of 15 μm on the surface layer and 30 μm on the inner layer, and the through hole for power supply directly under the IC is for power supply in the ground layer of the inner layer of the multilayer core. It does not have a conductor circuit extending from the through hole, and the ground through hole directly under the IC does not have a conductor circuit extending from the ground through hole in the power supply layer of the inner layer of the multilayer core. In C, in the multilayer core of B, the conductor thickness of the inner layer is set to 75 μm. In the conductor layer of the multilayer core, the power supply layer and the ground layer are alternately arranged. A, B, and C are multi-layer printed wiring boards in which interlayer insulation layers and conductor layers are alternately built up on the multi-layer core. From FIG. 29, it can be seen that the voltage drops of the first and second times are improved by adopting the multilayer core structure having no conductor circuit extending from the through hole of the present invention. Therefore, it can be said that the occurrence of malfunctions in the functions and operations of the IC chip is reduced. Further, it can be seen that the voltage drops of the first and second times are further improved by increasing the conductor thickness of the inner layer. When the thickness of the inner layer circuit was 40 to 150 μm, the result was similar to 75 μm.</p><p> In the multilayer core substrate, even when the thickness of the conductor layer of the power supply layer of all the layers of the multilayer core substrate is thicker than the thickness of the conductor layer on the interlayer insulating layer, the power supply layer of all the layers of the multilayer core substrate Even when the thickness of the conductor layer is equal to or less than the thickness of the conductor layer on the interlayer insulating layer, the total thickness of the total thickness of the conductors of all the layers is larger than the thickness of the conductor layer on the interlayer insulating layer. When it gets thicker, it has that effect.</p>

A. First Example (First Example-1) The multilayer printed wiring board according to the first embodiment-1 of the present invention will be described with reference to FIGS. 1 to 9. First, the configuration of the multilayer printed wiring board 10 according to the first embodiment-1 will be described with reference to FIGS. 8 and 9. FIG. 8 shows a cross-sectional view of the multilayer printed wiring board 10, and FIG. 9 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG. 8 and placed on the daughter board 94. As shown in FIG. 8, the multilayer printed wiring board 10 uses the multilayer core substrate 30. A conductor circuit 34 and a conductor layer 34P are formed on the front surface side of the multilayer core substrate 30, and a conductor circuit 34 and a conductor layer 34E are formed on the back surface side. The upper conductor layer 34P is formed as a plane layer for power supply, and the lower conductor layer 34E is formed as a plane layer for grounding. Further, an inner conductor circuit 16 and a conductor layer 16E are formed on the inner front surface side of the multilayer core substrate 30, and a conductor circuit 16 and a conductor layer 16P are formed on the back surface side. The upper conductor layer 16E is formed as a plane layer for grounding, and the lower conductor layer 16P is formed as a plane layer for power supply. The connection with the plane layer for power supply is made by through holes or via holes. The plain layer may be a single layer on only one side, or may be arranged in two or more layers. It is desirable that it is formed of 2 to 4 layers. Since no improvement in electrical characteristics has been confirmed for 5 or more layers, the effect is about the same as for 4 layers even if there are more layers. When the number of inner layers is 5 or more, the thickness of the core substrate becomes thick, so that the electrical characteristics may deteriorate. In particular, the fact that the two layers are formed makes it difficult for warpage to occur because the elongation rates of the substrates are uniform in terms of rigidity matching of the multilayer core substrate. An electrically isolated metal plate 12 is housed in the center of the multilayer core substrate 30. (Although the metal plate 12 also serves as a core material, no electrical connection such as through holes or via holes is made. Mainly, the rigidity against warpage of the substrate is improved.) The metal plate In 12, the conductor circuit 16 and the conductor layer 16E of the inner layer, the conductor circuit 16 and the conductor layer 16P on the back surface are further connected to the front surface side via the insulating resin layer 14, and the conductor circuit 34 is further connected to the front surface side via the insulating resin layer 18. , Conductor layer 34P , The conductor circuit 34 and the conductor layer 34E are formed on the back surface. The multilayer core substrate 30 is connected to the front surface side and the back surface side via a through hole 36. It is also electrically connected to the inner layer.

On the conductor layers 34P and 34E on the surface of the multilayer core substrate 30, the interlayer resin insulating layer 50 in which the via hole 60 and the conductor circuit 58 are formed, and the interlayer resin insulating layer in which the via hole 160 and the conductor circuit 158 are formed are formed. 150 and are arranged. A solder resist layer 70 is formed on the upper layer of the via hole 160 and the conductor circuit 158, and bumps 76U and 76D are formed on the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. ing.

As shown in FIG. 9, the solder bump 76U on the upper surface side of the multilayer printed wiring board 10 is connected to the land 92 of the IC chip 90. Further, a chip capacitor 98 is mounted. On the other hand, the lower external terminal 76D is connected to the land 96 of the daughter board 94. The external terminals in this case refer to PGA, BGA, solder bumps, and the like.

Manufacturing process of the multilayer printed wiring board of the first embodiment-1 A. Preparation of resin film for interlayer resin insulation layer Bisphenol A type epoxy resin (epoxy equivalent 455, oiled shell epoxy company Epicoat 1001) 29 parts by weight, cresol novolac type epoxy resin (epoxy equivalent 215, Dainippon Ink and Chemicals Co., Ltd. Epicron N-673) 39 parts by weight, triazine 30 parts by weight of a structure-containing phenol novolac resin (phenolic hydroxyl group equivalent 120, phenolite KA-7052 manufactured by Dainippon Ink and Chemicals Co., Ltd.) was heated and dissolved in 20 parts by weight of ethyldiglycolacetate and 20 parts by weight of solvent naphtha while stirring. There, 15 parts by weight of terminal epoxidized polybutadiene rubber (Denalex R-45EPT manufactured by Nagase Kasei Kogyo Co., Ltd.) and 1.5 parts by weight of 2-phenyl-4, 5-bis (hydroxymethyl) imidazole pulverized product, 2.5 parts by weight of finely pulverized silica, silicon. An epoxy resin composition was prepared by adding 0.5 parts by weight of a phenolic defoaming agent. The obtained epoxy resin composition was applied onto a PET film having a thickness of 38 μm using a roll coater so that the thickness after drying was 50 μm, and then dried at 80 to 120 ° C. for 10 minutes to form layers. A resin film for a resin insulating layer was produced.

B. Preparation of resin filler Bisphenol F type epoxy monomer (manufactured by Yuka Shell Co., Ltd., molecular weight: 310, YL983U) 100 parts by weight, the surface is coated with a silane coupling agent, the average particle size is 1.6 μm, and the maximum particle diameter is 15 μm or less. Take 170 parts by weight of particles (CRS 1101-CE manufactured by Adtech) and 1.5 parts by weight of leveling agent (Perenol S4 manufactured by San Nopco) in a container and stir and mix to obtain a viscosity of 44 to 49 Pa at 23 ± 1 ° C. A resin filler of s was prepared. As a curing agent, 6.5 parts by weight of an imidazole curing agent (2E4MZ-CN manufactured by Shikoku Chemicals Corporation) was used. As the filler resin, other epoxy resins (for example, bisphenol A type, novolac type, etc.), polyimide resins, phenol resins, and other thermosetting resins may be used.

C. Manufacture of multi-layer printed wiring boards The manufacturing method of the multilayer printed wiring board 10 shown in FIG. 8 will be described with reference to FIGS. 1 to 7. (1) &lt;Metal layer forming process&gt; An opening 12a penetrating the front and back is provided in the inner metal layer (metal plate) 12 having a thickness of 20 to 400 μm shown in FIG. 1 (A) (FIG. 1 (B)). In the first example, a 20 μm metal plate was used. As the material of the metal layer, a material containing a metal such as copper, nickel, zinc, aluminum, or iron can be used. Here, if a 36 alloy or 42 alloy having a low coefficient of thermal expansion is used, the coefficient of thermal expansion of the core substrate can be brought close to the coefficient of thermal expansion of the IC, so that thermal stress can be reduced. The opening 12a is drilled by punching, etching, drilling, laser or the like. In some cases, the entire surface of the metal layer 12 having the opening 12a formed may be coated with the metal film 13 by electroplating, electroless plating, replacement plating, or sputtering (FIG. 1 (C)). The metal plate 12 may be a single layer or a plurality of layers of two or more layers. Further, it is desirable that the metal film 13 forms a curved surface at the corner portion of the opening 12a. As a result, there are no points where stress is concentrated, and problems such as cracks around the points are less likely to occur. The metal plate 12 does not have to be built in the core substrate.

(2) &lt;Process of forming inner layer insulating layer and conductor layer&gt; An insulating resin is used to cover the entire metal layer 12 and fill the inside of the opening 12a. As a forming method, for example, a B-stage resin film having a thickness of about 30 to 400 μm is sandwiched between metal plates 12 (Fig. 1 (D)), and a copper foil having a thickness of 12 to 275 μm is laminated on the outside thereof. The insulating resin layer 14 and the conductor layer 16 can be formed by thermocompression bonding and curing (FIG. 1 (E)). In some cases, coating, a mixture of coating and film crimping, or only the open portion may be coated and then formed with a film. As the material, it is desirable to use a prepreg in which a thermosetting resin such as a polyimide resin, an epoxy resin, a phenol resin, or a BT resin is impregnated in a core material such as a glass cloth or an aramid non-woven fabric. Alternatively, a resin may be used. In the first example, a 50 μm prepreg was used. The conductor layer 16 may be formed on a metal foil by plating or the like.

(3) &lt;Circuit formation process of inner metal layer&gt; There may be two or more layers. A metal layer may be formed by an additive method. The inner conductor layers 16, 16P, and 16E were formed from the inner metal layer 16 through a tenting method, an etching process, and the like (Fig. 1 (F)). The thickness of the inner conductor layer at this time was 10 to 250 μm. However, it may exceed the above range. In the first embodiment, the inner layer of the conductor layer for power supply is 25 μm thick. In this circuit formation process, as a test pattern (pattern for evaluating the insulation resistance of the core substrate), the conductor width / spacing between conductors = 150 μm / 150 μm comb teeth for measuring the insulation resistance so that the insulation reliability of the core substrate can be evaluated. Formed a pattern. At this time, when the power supply through hole electrically connected to the power supply of the IC penetrates the ground layer of the inner layer circuit, it is not necessary to have a wiring pattern extending from the power supply through hole. Similarly, the ground through hole electrically connected to the IC ground does not have to have a wiring pattern extending from the ground through hole when penetrating the power supply layer of the inner layer circuit. With such a structure, the through-hole pitch can be narrowed. Further, since the distance between the through hole and the inner layer circuit is narrow, the mutual inductance is reduced.

(4) &lt;Process of forming outer layer insulating layer and conductor layer&gt; Insulating resins are used to cover the entire inner conductor layers 16, 16P, 16E and to fill the gaps between their circuits. As a forming method, for example, a B-stage resin film having a thickness of about 30 to 200 μm and a metal foil having a thickness of 10 to 275 μm are laminated on both sides of the intermediate substrate formed up to (3) in this order, and then heat-bonded. Then, it is cured to form the outer layer insulating resin layer 18 of the core substrate and the outermost conductor layer 34α of the core substrate (Fig. 2 (B)). In some cases, coating, a mixture of coating and film crimping, or only the opening may be applied and then formed with a film. The surface can be flattened by applying pressure. Further, a B-stage prepreg using a glass cloth or an aramid non-woven fabric as a core material may be used. In the first example, a prepreg having a thickness of 200 μm was used. As a method other than forming the metal foil, a single-sided copper-clad laminate is laminated. Two or more layers may be formed on the metal foil by plating or the like. A metal layer may be formed by an additive method.

(5) &lt;Through hole forming process&gt; Through-hole 36α with an opening diameter of 50 to 400 μm that penetrates the front and back of the substrate is formed (Fig. 2 (C)). As a forming method, it is formed by a drill, a laser, or a composite of a laser and a drill (the outermost insulating layer is opened with a laser, and in some cases, the opening with the laser is used as a target mark, and then with a drill. Open and penetrate). The shape is preferably one having a straight side wall. In some cases, it may be tapered.

In order to ensure the conductivity of the through hole, it is desirable to form the plating film 22 in the through hole 36α for the through hole, roughen the surface (FIG. 2 (D)), and then fill the filling resin 23 (Fig. 2 (D)). Figure 2 (E)). As the filling resin, an electrically insulated resin material (for example, one containing a resin component, a curing agent, particles, etc.) and a conductive material for which metal particles are electrically connected (for example,). Any of metal particles such as gold and copper, resin materials, hardeners, etc.) can be used. After filling, it was temporarily dried to remove excess filling resin adhering to the electrolytic copper plating film 22 on the substrate surface by polishing, and dried at 150 ° C. for 1 hour to completely cure. As the plating, electrolytic plating, electroless plating, panel plating (electroless plating and electrolytic plating) and the like can be used. The metal is formed because it contains copper, nickel, cobalt, phosphorus, and the like. The thickness of the plated metal is preferably formed between 5 and 30 μm.

As the filling resin 23 to be filled in the through-hole through hole 36α, it is desirable to use an insulating material made of a resin material, a curing agent, particles, or the like. As the particles, inorganic particles such as silica and alumina, metal particles such as gold, silver and copper, and resin particles are blended alone or in combination. Those having a particle size of 0.1 to 5 μm and having the same diameter or a mixture of composite diameters can be used. The resin material is a single or a mixture of epoxy resin (for example, bisphenol type epoxy resin, novolak type epoxy resin, etc.), thermosetting resin such as phenol resin, photosensitive ultraviolet curable resin, thermoplastic resin, and the like. Can be used. As the curing agent, an imidazole-based curing agent, an amine-based curing agent, or the like can be used. In addition to that, a curing stabilizer, a reaction stabilizer, particles and the like may be contained. A conductive material may be used. In this case, a conductive paste made of metal particles, a resin component, a curing agent, or the like is a conductive material. In some cases, a material having a conductive metal film formed on the surface layer of an insulating material such as solder or an insulating resin may be used. It is also possible to fill the inside of the through hole 36α for through holes by plating. This is because the conductive paste is cured and shrunk, so that recesses may be formed on the surface layer.

(6) &lt;Process of forming the outermost conductor circuit&gt; The lid plating 25 may be formed directly above the through hole 36 by covering the entire surface with a plating film (FIG. 3 (A)). After that, the conductor circuits 34, 34P, and 34E of the outer layer are formed through a tenting method, an etching process, and the like (Fig. 3 (B)). As a result, the multilayer core substrate 30 is completed. In the first embodiment, the thickness of the conductor layer for power supply on the surface of the multilayer core substrate is 15 μm. At this time, although not shown, electrical connection with the conductor layer 16 or the like of the inner layer of the multilayer core substrate may be made by a via hole, a blind through hole, or a blind via hole.

(7) The multilayer core substrate 30 on which the conductor circuit 34 is formed is blackened and reduced to form a roughened surface 34β on the entire surface of the conductor circuit 34, the conductor layers 34P, and 34E (FIG. 3 (C). )).

(8) A layer of the resin filler 40 is formed on the non-formed portion of the conductor circuit of the multilayer core substrate 30 (Fig. 4 (A)).

(9) In order to polish one side of the substrate after the above treatment by polishing with a belt sander or the like so that the resin filler 40 does not remain on the outer edges of the conductor layers 34P and 34E, and then remove the scratches caused by the above polishing. , The entire surfaces of the conductor layers 34P and 34E (including the land surface of the through hole) were further polished with a buff or the like. Such a series of polishing was performed on the other surface of the substrate in the same manner. Next, the resin filler 40 was cured by heat treatment at 100 ° C. for 1 hour and at 150 ° C. for 1 hour (FIG. 4 (B)). Further, it is not necessary to fill the conductor circuits with resin. In this case, the insulating layer is formed and the conductor circuits are filled with a resin layer such as an interlayer insulating layer.

(10) The entire conductor circuit is sprayed on both sides of the multilayer core substrate 30 with an etching solution, and the surfaces of the conductor circuit 34, the conductor layers 34P and 34E and the land surface of the through hole 36 are etched. A roughened surface 36β was formed on the surface (Fig. 4 (C)).

(11) On both sides of the multilayer core substrate 30, a resin film 50γ for an interlayer resin insulating layer is placed on the substrate, temporarily crimped and cut, and then further attached using a vacuum laminator device to insulate the interlayer resin. A layer was formed (Fig. 5 (A)).

(12) Next, with a CO2 gas laser with a wavelength of 10.4 μm, under the conditions of beam diameter 4.0 mm, top hat mode, pulse width 3.0 to 7.9 μsec, mask through-hole diameter 1.0 to 5.0 mm, and 1 to 3 shots. An opening 50a for a via hole having a diameter of 80 to 100 μm was formed in the interlayer resin insulating layer (Fig. 5 (B)).

(13) The substrate 30 is immersed in a solution containing 60 g / l of permanganate at 80 ° C. for 10 minutes to form a roughened surface 50α on the surface of the interlayer resin insulating layer 50 including the inner wall of the opening 50a for the via hole. (Fig. 5 (C)). The roughened surface was formed between 0.1 and 5 μm.

(14) Next, the substrate 30 after the above treatment was immersed in a neutralizing solution (manufactured by Shipley) and then washed with water. Further, by applying a palladium catalyst to the surface of the roughened substrate (roughening depth 3 μm), the catalyst nucleus was attached to the surface of the interlayer resin insulating layer and the inner wall surface of the via hole opening.

(15) Next, the substrate to which the catalyst was applied was immersed in the electroless copper plating aqueous solution to form an electroless copper plating film having a thickness of 0.6 to 3.0 μm over the entire rough surface, and the opening 50a for the via hole was formed. A substrate having an electroless copper plating film 52 formed on the surface of the interlayer resin insulating layer 50 including the inner wall is obtained (FIG. 5 (D)). Electroless copper plating solution Copper sulphate: 0.03 mol / l EDTA: 0.200 mol / l HCHO: 0.18g / l NaOH: 0.100 mol / L α, α'-bipyridyl: 100 mg / l Polyethylene glycol: 0.10g / l Plating conditions 40 minutes at a liquid temperature of 34 ° C

(16) A commercially available photosensitive dry film was attached to a substrate on which the electroless copper plating film 52 was formed, a mask was placed on the substrate, exposed to light, and then developed to provide a plating resist 54 (FIG. 6 (FIG. 6). A)). In order to evaluate the influence of the waviness of the interlayer insulating layer generated by the conductor thickness of the multilayer core substrate on a part of the interlayer insulating layer, the wiring pattern after plating formation (minimum line spacing, line width forming ability evaluation). The plating resist was formed so that the conductor width / spacing between conductors = 5/5 μm, 7.5 / 7.5 μm, 10/10 μm, 12.5 / 12.5 μm, and 15/15. The thickness of the plating resist used was between 10 and 30 μm.

(17) Next, the substrate 30 was electrolytically plated, and an electrolytic copper plating film 56 having a thickness of 5 to 20 μm was formed on the non-formed portion of the plating resist 54 (FIG. 6 (B)). [Electroplating solution] Sulfuric acid 2.24 mol / l Copper sulphate 0.26 mol / l Additive 19.5 ml / l (Atotech Japan, Capalacid GL) [Electroplating conditions] Current density 1 A / dm²Time 90 ± 5 minutes Temperature 22 ± 2 ° C

(18) Furthermore, after peeling and removing the plating resist with about 5% KOH, the electroless plating film under the plating resist is etched and removed with a mixed solution of sulfuric acid and hydrogen peroxide to dissolve and remove it, and an independent conductor. Circuit 58 and via hole 60 were used (Fig. 6 (C)).

(19) Then, the same treatment as in (12) above was performed to form roughened surfaces 58α and 60α on the surfaces of the conductor circuit 58 and the via hole 60. The thickness of the conductor layer on the interlayer insulating layer of this example was 20 μm (Fig. 6 (D)).

(20) By repeating the above steps (11) to (19), a further upper layer conductor circuit was formed to obtain a multilayer wiring board (FIG. 7 (A)).

(21) Next, a commercially available solder resist composition 70 is applied to both sides of the multilayer wiring board to a thickness of 12 to 30 μm, and dried at 70 ° C for 20 minutes and at 70 ° C for 30 minutes. After that (Fig. 7 (B)), a photomask with a thickness of 5 mm on which the pattern of the solder resist opening was drawn was brought into close contact with the solder resist layer 70 and 1000 mJ / cm.² It was exposed to ultraviolet rays and developed with a DMTG solution to form an opening 71 having a diameter of 200 μm (Fig. 7 (C)). Further, heat treatment is performed at 80 ° C for 1 hour, 100 ° C for 1 hour, 120 ° C for 1 hour, and 150 ° C for 3 hours to cure the solder resist layer and have an opening. Then, a solder resist pattern layer having a thickness of 10 to 25 μm was formed.

(22) Next, the substrate on which the solder resist layer 70 was formed was immersed in an electroless nickel plating solution to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. Further, the substrate was immersed in an electroless gold plating solution to form a gold plating layer 74 having a thickness of 0.03 μm on the nickel plating layer 72 (FIG. 7 (D)). In addition to the nickel-gold layer, a single layer of tin or a precious metal layer (gold, silver, palladium, platinum, etc.) may be formed.

(23) After that, a solder paste containing tin-lead is printed on the opening 71 of the solder resist layer 70 on the surface on which the IC chip of the substrate is placed, and tin-is further formed in the opening of the solder resist layer on the other surface. After printing a solder paste containing antimony, an external terminal was formed by reflowing at 200 ° C to manufacture a multi-layer printed wiring board with solder bumps (Fig. 8).

The IC chip 90 is attached via the solder bump 76U, and the chip capacitor 98 is mounted. Then, it is attached to the daughter board 94 via the external terminal 76D (Fig. 9).

According to the above-mentioned 1st Example-1, 1st Example-2 to 1st Example-28 and 1st Comparative Example-1 to 1st Comparative Example-3 were prepared. However, in each of the examples and comparative examples, the thickness of the conductor layer of the core substrate, the number of layers of the conductor layer of the core substrate, the number of through holes without dummy lands, the region without dummy lands, and the conductor on the interlayer insulating layer. The thickness of the layer was changed. When changing the thickness of the inner conductor layer, the thickness of the copper foil was changed in FIG. 1 (E). When changing the thickness of the conductor layers on the front and back of the core substrate, the thickness of the copper foil in FIG. 2 (B) and the plating thickness in FIGS. 2 (D) and 3 (A) were changed. The number of layers of the conductor layer of the core substrate was changed by repeating the circuit formation, the roughening of the circuit surface, and the lamination of the prepreg and the copper foil a predetermined number of times after the step of FIG. 2 (B). When changing the number of through holes that do not have dummy lands or the region that does not have dummy lands, when forming an etching resist for etching copper foil during circuit formation (tenting method) in Fig. 1 (F). This was done by changing the exposure mask (see FIGS. 19 and 38, FIG. 19 shows an example without dummy lands, and FIG. 38 shows an example with all dummy lands). The thickness of the conductor layer on the interlayer insulating layer was changed by changing the plating thickness in FIG. 6 (B). Below, the number of core layers of each example and comparative example, the thickness of the conductor layer for power supply, the thickness of the conductor layer on the interlayer insulating layer, the number of through holes without dummy lands, the region and the like are shown.

(First Example-1) Thickness of conductor layer for power supply in the inner layer of 4-layer core board: 25 μm 4-layer core Substrate surface power conductor layer thickness: 15 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 40 μm Thickness of conductor layer on interlayer insulation layer: 20 μm

(First Example-2) Thickness of conductor layer for power supply in the inner layer of 4-layer core board: 15 μm 4-layer core Substrate surface power conductor layer thickness: 9 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 24 μm Thickness of conductor layer on interlayer insulation layer: 20 μm

(First Example-3) Thickness of conductor layer for power supply in the inner layer of 4-layer core substrate: 45 μm 4-layer core Substrate surface power conductor layer thickness: 15 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 60 μm Thickness of conductor layer on interlayer insulation layer: 20 μm

(First Example-4) Thickness of conductor layer for power supply in the inner layer of 4-layer core board: 60 μm 4-layer core Substrate surface power conductor layer thickness: 15 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 75 μm Thickness of conductor layer on interlayer insulation layer: 20 μm

(First Example-5) Thickness of conductor layer for power supply of each inner layer of 14-layer core substrate: 100 μm 14-layer core Substrate surface power conductor layer thickness: 15 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 615 μm Thickness of conductor layer on interlayer insulation layer: 20 μm

(First Example-6) Thickness of conductor layer for power supply of each inner layer of 18-layer core substrate: 100 μm 18-layer core Substrate surface power conductor layer thickness: 15 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 815 μm Thickness of conductor layer on interlayer insulation layer: 20 μm

(First Example-7) Thickness of conductor layer for power supply in the inner layer of 4-layer core board: 15 μm 4-layer core Substrate surface power conductor layer thickness: 45 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 60 μm Thickness of conductor layer on interlayer insulation layer: 20 μm

(First Example-8) Thickness of conductor layer for power supply in the inner layer of 4-layer core board: 15 μm 4-layer core Substrate surface power conductor layer thickness: 60 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 75 μm Thickness of conductor layer on interlayer insulation layer: 20 μm

(First Example-9) Thickness of conductor layer for power supply in the inner layer of 4-layer core board: 50 μm 4-layer core Substrate surface power conductor layer thickness: 15 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 65 μm Thickness of conductor layer on interlayer insulation layer: 20 μm

(First Example-10) Thickness of conductor layer for power supply in the inner layer of 4-layer core board: 150 μm 4-layer core Substrate surface power conductor layer thickness: 15 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 165 μm Thickness of conductor layer on interlayer insulation layer: 20 μm In the step (formation of outer layer insulating layer and conductor layer) of (4) above, a prepreg having a thickness of 300 μm was used.

(First Example-11) Thickness of conductor layer for power supply in the inner layer of 4-layer core board: 175 μm 4-layer core Substrate surface power conductor layer thickness: 15 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 190 μm Thickness of conductor layer on interlayer insulation layer: 20 μm In the step (formation of outer layer insulating layer and conductor layer) of (4) above, a prepreg having a thickness of 300 μm was used.

(First Example-12) Thickness of conductor layer for power supply in the inner layer of 4-layer core board: 200 μm 4-layer core Substrate surface power conductor layer thickness: 15 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 215 μm Thickness of conductor layer on interlayer insulation layer: 20 μm In the step (formation of outer layer insulating layer and conductor layer) of (4) above, a prepreg having a thickness of 300 μm was used.

(First Example-13) In the first embodiment-3, a part of the power supply through hole and the ground through hole is a through hole having no dummy land shown in (3) &lt;Circuit forming step of inner layer metal layer&gt;. The area is directly below the IC, and the number of power supply through holes without dummy lands is 50% of all power supply through holes, and the number of ground through holes without dummy lands is all ground through holes. On the other hand, it was set to 50%.

(First Example-14) In the first embodiment-3, the through holes for all power supplies and the through holes for all grounds directly under the IC are the through holes having no dummy land shown in (3) &lt;Circuit forming process of inner layer metal layer&gt;. did.

(First Example-15) In the first embodiment-9, a part of the power supply through hole and the ground through hole is a through hole having no dummy land shown in (3) &lt;Circuit forming step of inner layer metal layer&gt;. The area is directly below the IC, and the number of power supply through holes without dummy lands is 50% of all power supply through holes, and the number of ground through holes without dummy lands is all ground through holes. On the other hand, it was set to 50%.

(First Example-16) In the ninth embodiment-9, the through holes for all power supplies and the through holes for all grounds directly under the IC are the through holes having no dummy land shown in (3) &lt;Circuit forming process of inner layer metal layer&gt;. did.

(First Example-17) In the first embodiment-4, a part of the power supply through hole and the ground through hole is a through hole having no dummy land shown in (3) &lt;Circuit forming step of inner layer metal layer&gt;. The area is directly below the IC, and the number of power supply through holes without dummy lands is 50% of all power supply through holes, and the number of ground through holes without dummy lands is all ground through holes. On the other hand, it was set to 50%.

(First Example-18) In the first embodiment-4, the through holes for all power supplies and the through holes for all grounds directly under the IC are the through holes having no dummy land shown in (3) &lt;Circuit forming process of inner layer metal layer&gt;. did.

(First Example-19) In the first embodiment-10, a part of the power supply through hole and the ground through hole is a through hole having no dummy land shown in (3) &lt;Circuit forming step of inner layer metal layer&gt;. The area is directly below the IC, and the number of power supply through holes without dummy lands is 50% of all power supply through holes, and the number of ground through holes without dummy lands is all ground through holes. On the other hand, it was set to 50%.

(First Example-20) In the first embodiment-10, the through holes for all power supplies and the through holes for all grounds directly under the IC are the through holes having no dummy land shown in (3) &lt;Circuit forming process of inner layer metal layer&gt;. did.

(First Example-21) In the first embodiment-11, a part of the power supply through hole and the ground through hole is a through hole having no dummy land shown in (3) &lt;Circuit forming step of inner layer metal layer&gt;. The area is directly below the IC, and the number of power supply through holes without dummy lands is 50% of all power supply through holes, and the number of ground through holes without dummy lands is all ground through holes. On the other hand, it was set to 50%.

(First Example-22) In the first embodiment-11, the through holes for all power supplies and the through holes for all grounds directly below the IC are the through holes having no dummy land shown in (3) &lt;Circuit forming step of inner layer metal layer&gt;. did.

(First Example-23) In the first embodiment-12, a part of the power supply through hole and the ground through hole is a through hole having no dummy land shown in (3) &lt;Circuit forming step of inner layer metal layer&gt;. The area is directly below the IC, and the number of power supply through holes without dummy lands is 50% of all power supply through holes, and the number of ground through holes without dummy lands is all ground through holes. On the other hand, it was set to 50%.

(First Example-24) In the first embodiment-12, the through holes for all power supplies and the through holes for all grounds directly under the IC are the through holes having no dummy land shown in (3) &lt;Circuit forming process of inner layer metal layer&gt;. did.

(First Example-25) In the first embodiment-7, a part of the power supply through hole and the ground through hole is a through hole having no dummy land shown in (3) &lt;Circuit forming step of inner layer metal layer&gt;. The area is directly below the IC, and the number of power supply through holes without dummy lands is 50% of all power supply through holes, and the number of ground through holes without dummy lands is all ground through holes. On the other hand, it was set to 50%.

(First Example-26) In the first embodiment-7, the through holes for all power supplies and the through holes for all grounds directly under the IC are the through holes having no dummy land shown in (3) &lt;Circuit forming process of inner layer metal layer&gt;. did.

(First Example-27) Thickness of conductor layer for power supply of each inner layer of 6-layer core board: 32.5 μm 6-layer core Substrate surface power conductor layer thickness: 15 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 80 μm Thickness of conductor layer on interlayer insulation layer: 20 μm

(First Example-28) Thickness of conductor layer for power supply in the inner layer of 4-layer core board: 125 μm 4-layer core Substrate surface power conductor layer thickness: 15 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 140 μm Thickness of conductor layer on interlayer insulation layer: 20 μm

(First Example-29) In the first embodiment-27, a part of the power supply through hole and the ground through hole is a through hole having no dummy land shown in (3) &lt;Circuit forming step of inner layer metal layer&gt;. The area is directly below the IC, and the number of power supply through holes without dummy lands is 50% of all power supply through holes, and the number of ground through holes without dummy lands is all ground through holes. On the other hand, it was set to 50%.

(First Example-30) In the first embodiment-29, the through holes for all power supplies and the through holes for all grounds directly under the IC are the through holes having no dummy land shown in (3) &lt;Circuit forming process of inner layer metal layer&gt;. did.

(1st Comparative Example-1) Thickness of conductor layer for power supply in the inner layer of 4-layer core substrate: 10 μm 4-layer core Substrate surface power supply conductor layer thickness: 10 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 20 μm Thickness of conductor layer on interlayer insulation layer: 20 μm (1st Comparative Example-2) Thickness of conductor layer for power supply of each inner layer of 18-layer core substrate: 100 μm 18-layer core Substrate surface power conductor layer thickness: 40 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 840 μm Thickness of conductor layer on interlayer insulation layer: 20 μm (1st Comparative Example-3) Thickness of conductor layer for power supply of each inner layer of 22-layer core board: 100 μm 22-layer core Substrate surface power conductor layer thickness: 15 μm Sum of the thicknesses of the conductor layers for the power supply of the core substrate: 1015 μm Thickness of conductor layer on interlayer insulation layer: 20 μm In the multilayer printed wiring boards of the first embodiment and the first comparative example, all the through holes have dummy lands if there is no description about the dummy lands.

An IC chip with a frequency of 3.1 GHz is mounted on the multilayer printed wiring board of 1st Example-1 to 1st Example-12, 1st Example-27, 28 and 1st Comparative Example-1 to 1st Comparative Example-3. Then, the same amount of power was supplied, and the amount of voltage drop when the device was started (the amount of voltage drop corresponding to the third of the multiple voltage drops) was measured. Since it is not possible to directly measure the voltage of the IC in the IC, a measurable circuit was formed on the printed wiring board to measure the voltage of the IC. The values of the voltage drop at this time are shown in FIGS. 13 and 15. This is the value of the fluctuating voltage drop when the power supply voltage is 1.0V. In addition, HAST test (85 ° C, humidity) was applied to the printed wiring boards of 1st Example-1 to 1st Example-12, 1st Example-28 and 1st Comparative Example-1 to 1st Comparative Example-3. 85%, 3.3V was applied). The evaluation pattern is a test pattern for evaluating insulation resistance formed on the core substrate. The results are shown in Fig. 13. The test time is 115 hours, and the pass is an insulation resistance value of 10 after 115 hours.⁷It is Ω or more, and if it is less than that, it is defective. Further, in the first embodiment-3, 4, 7, 8, the evaluation of the minimum line spacing and line width forming ability evaluation pattern (see the above step (16) of the first embodiment-1) during the production of the printed wiring board. Was done. This result is shown in FIG. 14 as the forming ability. In the figure, indicates that there was no short circuit, and × indicates that there was a short circuit in the adjacent wiring.

The results of the voltage drop and the insulation resistance after HAST for various α1 / α2 are shown in FIGS. 13 and 15. The results after the HAST test are marked with Yes for passing and x for defects. In addition, FIG. 17 shows a graph of the amount of voltage drop for various α1 / α2.

In the results shown in FIGS. 13 and 15, when the power supply voltage is 1.0V and the fluctuation allowable range is ± 10% (third voltage drop amount), the voltage behavior is stable and the IC chip Does not cause malfunction. That is, in this case, if the amount of voltage drop is within 0.1 V, the IC chip will not malfunction due to the voltage drop. Therefore, if it is 0.09V or less, the stability will increase. Therefore, the ratio of (the sum of the thicknesses of the conductor layers for the power supply of the multilayer core substrate / the thickness of the conductor layer on the interlayer insulating layer) should exceed 1.0. Further, if the range is 1.2 (sum of the thicknesses of the conductor layers for the power supply of the multilayer core substrate / the thickness of the conductor layer on the interlayer insulating layer) 40, it is within the fluctuation allowable range. However, when the value exceeds 8.25, it starts to rise, and when it exceeds 40, the voltage drop exceeds 0.1V. It is presumed that this is because the conductor layer of the multilayer core substrate becomes thicker and the number of inner layers increases, so that the through-hole length becomes longer and it takes time to supply power to the IC.

However, even if (the sum of the thicknesses of the conductor layers for the power supply of the multilayer core substrate / the thickness of the conductor layer on the interlayer insulating layer) is in the above range, the conductor layer of only one layer is thickened. In Nos. 11 and 12, the insulation reliability of the core substrate was inferior to that in the other examples, and they were defective (see FIG. 13). For this reason, instead of thickening only one layer, the core is multi-layered and the sum of the thicknesses of the conductor layers for power supply is within the above range, so that malfunction does not occur even if a high-frequency IC is mounted. It can be seen that a printed wiring board having excellent insulation reliability can be obtained.

When the test patterns for evaluating the insulation of the core substrates of the first examples-11 and 12 were analyzed, the intervals between the lines were narrowed. It is speculated that this caused the insulation resistance to fall below the standard. Further, it can be seen from the comparison between the first examples-3 and 4 and the first examples-7 and 8 in FIG. 14 that the thickness of the conductor layers on the front and back surfaces of the multilayer core substrate should be thinner than the thickness of the inner conductor layer. .. This is because if a thick conductor layer is formed on the front and back surfaces, the interlayer agent undulates due to the effect, and thus fine wiring cannot be formed on the interlayer insulating layer.

Whether or not the IC chip mounted on the multilayer printed wiring board manufactured according to the first embodiment-1 to 12, 27, 28 and the first comparative example-1 to 3 malfunctions by the method described below. It was confirmed. As the IC chip, one of the IC chips selected from Nos. 1 to 3 below was mounted on each multilayer printed wiring board, and simultaneous switching was performed 100 times to evaluate the presence or absence of malfunction. The results are shown in Fig. 15. No.1: Drive frequency: 3.06GHz, Bus clock (FSB): 533MHz No.2: Drive frequency: 3.2GHz, Bus clock (FSB): 800MHz No.3: Drive frequency: 3.46GHz, bus clock (FSB): 1066MHz

From the result of mounting the No. 1 IC chip, it can be seen that if the ratio of α1 / α2 is in the range of 1.2 to 40, no malfunction is observed in the IC. It is presumed that this is because the conductor resistance of the power supply layer is low, so power is supplied to the IC instantly. From the result of mounting the No. 2 IC chip, it can be seen that when the drive frequency of the IC becomes higher, it is necessary to supply power to the IC in a shorter time, so that there is a more suitable range. The reason why the malfunction occurred in the first embodiment-11 and 12 in which the inner conductor layer of the multi-layer core is thick and in the first embodiment-5 and 6 in which the number of inner layer layers is large is that the power supply is caused by the thick core substrate. In addition to the delay, it is speculated that the signal may have deteriorated when transmitting through-holes for signals (through-holes electrically connected to the signal circuit of the IC (not shown)). When the signal through hole penetrates the four-layer core, the through hole is an insulating layer (insulating layer between the surface power supply layer and the inner ground layer in FIG. 9), a ground layer, and an insulating layer (FIG. 9). (Insulating layer between the inner layer ground layer and the inner power supply layer), the power supply layer, and the insulating layer (the insulating layer between the inner layer power supply layer and the back surface ground layer in FIG. 9) are penetrated. Since the impedance of the signal wiring changes depending on the surrounding ground and the presence or absence of a power supply, for example, the impedance value differs at the interface between the insulating layer and the ground layer between the power supply layer and the ground layer on the surface layer. Therefore, signal reflection occurs at the interface. The same thing happens at other interfaces. The amount of such a change in impedance increases as the distance between the signal through hole and the ground layer and the power supply layer increases, the thickness of the ground layer and the power supply layer increases, and the number of interfaces increases. It is presumed that a malfunction occurred at -5, 6, 11 and 12 (schematic diagram of the signal through hole and its surrounding power supply layer, ground layer, and insulating layer and the interface where the signal is reflected (X1, X2, X3). , X4) is also shown in Fig. 39). Further, it is presumed that the reason for the malfunction of the first examples-1 and 2 is that the sum of the thicknesses of the power supply layers is small.

If the speed of the IC is further increased from the result of mounting the No. 3 IC, it is effective to have a 4-layer core with a thick conductor layer in the inner layer and α1 / α2 of 3 to 7. I understand. It is presumed that this is because power supply in a short time and prevention of signal deterioration can be achieved at the same time. Further, from the comparison between the first examples-3,4 and the first examples-7,8, it can be seen that it is electrically advantageous to dispose a thick conductor layer in the inner layer. It is presumed that this is because the inner layer has a thick conductor layer, so that the inductance becomes smaller due to the interaction between the power supply through hole and the ground layer of the inner layer and between the ground through hole and the inner layer of the power supply layer.

Regarding the multilayer printed wiring board manufactured according to the first embodiment-13 to 26, it was confirmed whether or not the mounted IC chip had a malfunction by the method as described below. As the IC chip, one of the IC chips selected from Nos. 1 to 3 below was mounted on each multilayer printed wiring board, and simultaneous switching was performed 100 times to evaluate the presence or absence of malfunction. The results are shown in Fig. 16. TH used in the figure is an abbreviation for through hole. No.1: Drive frequency: 3.06GHz, Bus clock (FSB): 533MHz No.2: Drive frequency: 3.2GHz, Bus clock (FSB): 800MHz No.3: Drive frequency: 3.46GHz, bus clock (FSB): 1066MHz

Comparing the first examples-10 and 27 with the first examples-19,20, 29 and 30, it can be seen that the IC malfunction is less likely to occur by using a through hole having no dummy land. It is presumed that this is because the mutual inductance is reduced because the through hole having the opposite potential and the conductor layer of the inner layer are close to each other because the dummy land is not provided. Alternatively, since electricity easily flows on the surface of the conductor, it is presumed that the wiring length in the flow of electricity is shortened because there is no dummy land. The printed wiring boards of the first embodiment-3, 4, 13, 14, 17, 18 and 28 were left for 100 hours in a high temperature and high humidity (85 ° C. 85%) environment. After that, the above-mentioned No. 3 IC chip was mounted on each printed wiring board, and simultaneous switching was performed to confirm the presence or absence of malfunction. No malfunction occurred except for the first embodiment-3. It is presumed that a malfunction occurred in the first example-3 because the resistance of the conductor layer increased due to the high temperature and high humidity test. Similarly, in the other examples, the resistance increases, but in contrast to the first embodiment-3, the other examples have a thick conductor layer or are through holes having no dummy land. Since the inductance is lower than that of Example-3, it is presumed that no malfunction occurred. Therefore, the thickness of the inner conductor layer is preferably 60 μm to 125 μm. From the above, it can be inferred that in the case of a multi-layer core, the conductor thickness of the inner layer and the through-hole having no dummy land influence each other.

B. Second Example The multilayer printed wiring board according to the second embodiment-1 of the present invention will be described with reference to FIGS. 18 to 25. First, the configuration of the multilayer printed wiring board 10 according to the second embodiment-1 will be described with reference to FIGS. 22 and 23. FIG. 22 shows a cross-sectional view of the multilayer printed wiring board 10, and FIG. 23 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG. 22 and mounted on the daughter board 94. As shown in FIG. 22, the multilayer printed wiring board 10 uses the multilayer core substrate 30. A signal circuit 34S, a power supply circuit 34P, and a ground circuit 34E are formed on the front and back surfaces of the multilayer core substrate 30. Further, an inner layer ground circuit 16E and a signal circuit 16S1 are formed on the inner front surface side of the multilayer core substrate 30, and a power supply circuit 16P and a signal circuit 16S2 are formed on the back surface side. The upper ground circuit 16E is formed as a plane layer for grounding, and the lower power supply circuit 16P is formed as a plane layer for power supply. The plain layer may be a single layer on only one side, or may be arranged in two or more layers. It is desirable that it is formed of 2 to 4 layers. If the number of layers exceeds four, the thickness of the core becomes thicker, and since no improvement in electrical characteristics has been confirmed, the effect is about the same as that of four layers even if more layers are used. On the contrary, it may worsen. In particular, the fact that the two layers are formed makes it difficult for warpage to occur because the elongation rates of the substrates are uniform in terms of shortening the through-hole length and matching the rigidity of the multilayer core substrate. An electrically isolated metal plate may be housed in the center of the multilayer core substrate 30. The metal plate also serves as a core material, but is not electrically connected to any through hole or via hole. It mainly improves the rigidity of the substrate against warpage. The multilayer core board 30 has an inner layer and a through hole for signal (not shown) electrically connected to the signal circuit of the IC, a ground circuit, and a power supply circuit, a through hole 36E for grounding, and a through hole 36P for power supply. The front side and the back side are connected.

On the power supply circuit 34P, the ground circuit 34E, and the signal circuit 34S on the surface of the multilayer core substrate 30, the interlayer insulating layer 50 in which the via hole 60 and the conductor circuit 58 are formed, and the via hole 160 and the conductor circuit 158 are formed. An interlayer insulating layer 150 is provided. A solder resist layer 70 is formed on the upper layer of the via hole 160 and the conductor circuit 158, and bumps 76U and 76D are formed on the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. ing.

As shown in FIG. 23, the solder bump 76U on the upper surface side of the multilayer printed wiring board 10 is connected to the land 92 of the IC chip 90. Further, a chip capacitor 98 is mounted. On the other hand, the lower external terminal 76D is connected to the land 96 of the daughter board 94. The external terminals in this case refer to PGA, BGA, solder bumps, and the like.

FIG. 25 (A) shows the X3-X3 cross section in FIG. 22, that is, the plane of the inner layer grounding plane layer 16E, and FIG. 25 (B) shows the X2-X2 cross section, that is, the inner layer for power supply. The plane of the plane layer 16P is shown. Here, the arrangements of FIGS. 22 and 25 (A) and 25 (B) do not match because FIG. 22 schematically shows the vertical structure of the multilayer printed wiring board. As shown in FIG. 25 (A), in the multilayer printed wiring board 30, when the through hole 36P for the power supply penetrates the grounding plane layer 16E of the inner layer in the multilayer core, the power supply through in the grounding plane layer 16E The hole 36P does not have a conductor circuit such as a land extending from the through hole. The power through hole 36P is arranged in the punch 35 provided in the ground plane layer 16E. As shown in FIG. 25 (B), the ground through hole 36E is the same as the ground through hole 36E that penetrates the power supply plane layer 16P, and the ground through hole 36E penetrates the inner power supply plane layer 16P. At this time, in the power supply plane layer 16P, the ground through hole 36E is arranged in the punch 35 and does not have a conductor circuit such as a land extending from the through hole. With such a core structure, between the through hole for power supply and the through hole for grounding, between the through hole for power supply and the plane for grounding in the horizontal direction of the core, and the through hole for grounding and power supply in the horizontal direction of the core. It is possible to narrow the distance between the plane layers and reduce the mutual inductance. Further, since the through hole does not have a dummy land, it is possible to increase the conductor area of the power supply plane layer and the ground plane layer. As a result, it is possible to reduce the voltage drops of the first and second times described above with reference to FIGS. 28 and 29, so that power supply shortage is less likely to occur, and even if an IC chip in a higher frequency region is mounted. Does not cause malfunctions or errors at initial startup.

In FIG. 25, the through holes of the multilayer core substrate have a structure in which the power supply through holes 36P and the ground through holes 36E are alternately arranged. This is because such an alternating arrangement reduces the mutual inductance and reduces the first and second voltage drops.

However, it is not always necessary to arrange all of them alternately, and as shown in FIGS. 31 (A) and 31 (B), some power supply through holes and ground through holes may be adjacent to each other. When the power supply through holes 36P and 36P are adjacent to each other as shown in FIG. 31 (A), they may be connected by the power supply circuit 16P1 in the ground plane layer 16E, or they may be disconnected without being connected. Through holes 36P may be formed in 35. The same applies when the grounding through holes 36E are adjacent to each other as shown in FIG. 31 (B). It is preferable to form the punch 35 because the conductor volume of the plain layer increases.

Since the signal through hole is not connected to the power supply plane layer 16P and the ground plane layer 16E, it is not necessary to provide a conductor circuit extending from the through hole in the power supply plane layer 16P and the ground plane layer 16E. However, if there is a space for forming the circuit, the circuit may be formed in any plane layer. Placing the signal circuit in the core is advantageous for finening when wiring in the build-up layer.

Further, as for the conductor thickness of the multilayer core substrate 30, it is desirable that the conductor thickness of the inner layer is equal to or larger than the conductor thickness of the surface layer. Multilayer core board 30 The surface power supply circuit 34P, ground circuit 34E, and signal circuit 34S are formed to a thickness of 10 to 60 μm, and the inner layer power supply circuit 16P, ground circuit 16E, signal circuits 16S1 and 16S2 are 10 to 250 μm thick. The conductor circuit 58 on the interlayer insulating layer 50 and the conductor circuit 158 on the interlayer insulating layer 150 are formed in 5 to 25 μm. It is more desirable that the thickness of the conductor circuit in the inner layer of the multilayer core substrate is at least twice the thickness of the conductor circuits on the front and back of the multilayer core substrate.

In the multilayer printed wiring board of the second embodiment-1, the power supply layer (conductor layer) 34P, the ground circuit 34E, the signal circuit 34S, the inner layer power supply circuit 16P, and the ground circuit 16E of the multilayer core board 30 are thickened to form multiple layers. Increases the strength of the core substrate. As a result, even if the multilayer core substrate itself is thinned, the warpage and the generated stress can be relaxed by the substrate itself.

Further, the volume of the conductor itself can be increased by thickening the signal circuit 34S, the power supply circuit 34P, the ground circuit 34E, the power supply circuit 16P, and the ground circuit 16E. By increasing the volume, the resistance in the conductor can be reduced.

Further, by using the power supply circuits 34P and 16P as the power supply layer, the power supply capacity to the IC chip 90 can be improved. Therefore, when the IC chip is mounted on the multilayer printed circuit board, the inductance from the IC chip to the substrate to the power supply can be reduced. Therefore, the third voltage drop in the initial operation becomes small, so that the power supply shortage is less likely to occur, and even if an IC chip in the high frequency region is mounted, malfunctions and errors in the initial operation will not occur. Furthermore, by using the ground circuits 34E and 16E as the ground layer, noise is not superimposed on the signal and power supply of the IC chip, and malfunctions and errors can be prevented. By mounting the capacitor, the power supply stored in the capacitor can be used as an auxiliary, so that the power supply shortage is less likely to occur. In particular, by arranging it directly under the IC chip, the effect (making it difficult to cause a power shortage) becomes remarkably good. The reason is that the wiring length of the multilayer printed wiring board can be shortened if it is directly under the IC chip.

In the second embodiment-1, the multilayer core substrate 30 has a thick power supply circuit 16P and a ground circuit 16E on the inner layer, a thin power supply circuit 34P and a ground circuit 34E on the surface, and the inner layer power supply circuit 16P and the ground circuit 16E. The power supply circuit 34P and the ground circuit 34E on the surface are used as a conductor layer for the power supply layer and a conductor layer for grounding. That is, even if the thick power supply circuit 16P and the ground circuit 16E are arranged on the inner layer side, an insulating layer covering the conductor circuit is formed. Therefore, the surface of the multilayer core substrate 30 can be made flat by canceling the unevenness due to the conductor circuit. Therefore, even if the thin power supply circuit 34P and the ground circuit 34E are arranged on the surface of the multilayer core substrate 30 so as not to cause waviness in the conductor circuits 58 and 158 of the interlayer insulation layers 50 and 150, the power supply circuit 16P of the inner layer is arranged. , The thickness added to the ground circuit 16E can secure a sufficient thickness as the conductor layer of the core. Since no waviness occurs, the impedance of the conductor layer on the interlayer insulating layer does not have a problem. By using the power supply circuits 16P and 34P as the conductor layer for the power supply layer and the ground circuits 16E and 34E as the conductor layer for grounding, it is possible to improve the electrical characteristics of the multilayer printed wiring board. Further, as shown in FIG. 34, the facing area (opposing distance) between the through hole having the opposite potential and the inner conductor layer increases, so that the electrical characteristics can be further improved.

Further, the thickness of the power supply circuit 16P and the ground circuit 16E in the inner layer of the multilayer core substrate is made thicker than the conductor circuits 58 and 158 on the interlayer insulation layers 50 and 150. As a result, even if a thin ground circuit 34E and a power supply circuit 34P are arranged on the surface of the multilayer core substrate 30, a sufficient thickness can be secured as a conductor layer of the core by adding the thick power supply circuit 16P and the ground circuit 16E in the inner layer. .. The ratio is preferably 1 &lt;(thickness of the conductor circuit in the inner layer of the core / thickness of the conductor circuit in the interlayer insulating layer) 40. It is more desirable that 1.2 (thickness of the conductor circuit in the inner layer of the core / thickness of the conductor circuit in the interlayer insulating layer) 30.

Further, a microstrip structure can be formed by arranging the signal line 16S1 between the power supply circuit 34P and the power supply circuit 16P in the multilayer core substrate. Similarly, a microstrip structure can be formed by arranging a signal line (not shown, the same layer as the power supply circuit 16P) between the ground circuit 16E and the ground circuit 34E. By forming the microstrip structure, the inductance is also reduced and impedance matching can be achieved. Therefore, the electrical characteristics can also be stabilized.

FIG. 24 shows a modified example of the second embodiment-1. In this modified example, the capacitor 98 is arranged directly under the IC chip 90. Therefore, the distance between the IC chip 90 and the capacitor 98 is short, and it is possible to prevent the voltage drop of the power supply supplied to the IC chip 90.

Subsequently, the manufacturing method of the multilayer printed wiring board 10 shown in FIG. 22 will be described with reference to FIGS. 18 to 23.

C. Manufacture of multi-layer printed wiring boards Creation of multi-layer core board (1) A copper-clad laminate 10 in which 10 to 250 μm of copper foil 16 is laminated on both sides of an insulating substrate 14 made of a glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.6 mm was used as a starting material. (Fig. 18 (A)). In the second example-1, a 30 μm copper foil was used.

(2) Next, a conductor circuit 16E having no dummy land in the punched 35 as shown in FIG. 19 (A) showing the front side of the copper foil 16 by the subtractive method, and the back side of the IC directly below the IC. As shown in 19 (B), a conductor circuit 16P having no dummy land was formed in the punch 35. For reference, FIG. 38 shows a conventional example. In the conventional example, all the punches 35 have a circuit 16DD that serves as a dummy land 16D, and a through-hole through hole 36 is formed in the circuit 16DD. A punch (opening) 35 is formed at a position where a through hole is formed. Normally, the circuit 16DD, which is a dummy land 16D, is formed with a diameter of +150 to 250 μm with respect to the through-hole diameter. The distance between the through holes, between the power supply through hole and the ground conductor (X in FIG. 34), and between the ground through hole and the power supply conductor can be narrowed. By not providing the dummy land in this way, it is possible to reduce the mutual inductance and the conductor resistance. In addition, the area where the power supply layer and the ground layer can be formed increases.

(3) After that, the substrate is made of NaOH (10 g / l), NaClO.₂ (40g / l), Na₃PO₄ Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBH₄ A reduction treatment is performed using an aqueous solution containing (6 g / l) as a reduction bath to form a roughened surface 16α on the surfaces of the lower conductor circuits 16E, 16S1, 16P, and 16S2 (Fig. 18 (C)).

(4) A 200 μm-thick prepreg 18 and an 18 μm-thick copper foil 20 were laminated in this order on both sides of the above substrate, and then heated and pressure-pressed to prepare a four-layer multilayer core substrate 30 (Fig. 18 (D)). )). The thickness of the prepreg is changed according to the thickness of the copper foil 16.

(5) The multilayer core substrate 30 is drilled and a through hole 36 is drilled (FIG. 20 (A)). After that, electroless plating and electroplating are performed, and by etching in a pattern, conductor circuits 34S, 34P, 34E and through holes 36S for signals with a diameter of 250 μm (not shown) are used for power supplies on the front and back surfaces of the multilayer core substrate. Through holes 36P and through holes 36E for grounding were formed (Fig. 20 (B)).

(6) A substrate in which conductor circuits 34S, 34P, 34E and through holes 36S, 36P, 36E are formed on the front and back surfaces of a multilayer core substrate are made of NaOH (10 g / l), NaClO.₂ (40g / l), Na₃PO₄ Blackening treatment using an aqueous solution containing (6 g / l) as a blackening bath (oxidation bath), and NaOH (10 g / l), NaBH₄ A reduction treatment is performed using an aqueous solution containing (6 g / l) as a reduction bath to form a roughened surface 34β on the surface of the upper conductor circuit and the through hole (Fig. 20 (C)).

(7) Next, the through-hole filling resin composition 40 prepared in the same manner as in the first embodiment described above was placed between the conductor circuits 34S, 34P, 34E and in the through-holes 36S, 36P, 36E using a squeegee. After filling, it was dried at 100 ° C for 20 minutes (Fig. 21 (A)). The surface of the substrate 30 is polished and flattened until the surface of the conductor circuit and the land surface of the through hole are exposed, and heated at 100 ° C for 1 hour and at 150 ° C for 1 hour to fill the through hole resin. A resin filler layer obtained by curing the composition 40 was formed into through holes 36S (not shown), 36P, and 36E (FIG. 21 (B)).

The copper thickness on the front and back surfaces of the multilayer core substrate was 7.5 to 70 μm. As described above, it is preferable that the copper thickness on the front and back surfaces of the multilayer core substrate is thinner than the copper thickness on the inner layer. In the second example-1, it was set to 25 μm. As a result, the front and back layers can form finer circuits than the inner layer, and the diameter of the through-hole land can be reduced and the gap between the conductor circuits and between the through-hole land and the conductor circuit can be reduced. Therefore, the through-hole lands and conductor circuits on the front and back layers do not interfere with narrowing the through-hole pitch.

(8) After washing the above substrate with water and acid degreasing, soft etching is performed, and then the etching solution is sprayed on both sides of the substrate by spraying the surface of the signal circuit 34S, the power supply circuit 34P, and the ground circuit 34E and the through hole 36. By etching the land surface, a roughened surface 36β was formed on the entire surface of the conductor circuit (Fig. 21 (C)). As the etching solution, an etching solution (Mech Etch Bond, manufactured by MEC) consisting of 10 parts by weight of the imidazole copper (II) complex, 7.3 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride was used. The subsequent steps are the same as those in the first embodiment described above with reference to FIGS. 5 to 7, and thus the description thereof will be omitted. However, the thickness of the conductor circuits 58 and 158 was set to 15 μm by adjusting the plating time.

[Second Example-2] In the second embodiment-1, the region where the through hole having no conductor circuit extending from the through hole exists is directly under the IC, but in the second embodiment-2, the region is changed as follows. Other parts are the same as in the second embodiment-1. FIG. 26 (A) shows a cross section of a typical ground layer of the inner layer of the four-layer core, and FIG. 26 (B) shows a cross section of a typical power supply layer of the inner layer of the four-layer core. The multilayer core of the second embodiment-2 is also a four-layer core, and when the power supply through hole 36P penetrates the ground layer 16E, the power supply through hole does not have the conductor circuit 16D extending from the through hole. , 50% of all through holes connected to the power supply circuit of the IC, and the ground through hole 36E does not have a conductor circuit extending from the through hole when penetrating the power supply layer 16P. The ground through holes are 50% of all through holes connected to the IC ground circuit. The number of through holes without dummy lands can be adjusted by changing the pattern of the exposure film when forming a circuit on the copper foil 16 in the step (2) described above with reference to FIG. 18 (B). is there.

[Second Example-3] The second embodiment-3 is the same as the second embodiment-2 except that the through hole having no conductor circuit extending from the through hole is 70% in the second embodiment-2.

[Second Example-4] The second embodiment-4 is the same as the second embodiment-2 except that the through hole having no conductor circuit extending from the through hole is 80% in the second embodiment-2.

[Second Example-5] The second embodiment-5 is the same as the second embodiment-2 except that the through hole having no conductor circuit extending from the through hole is 90% in the second embodiment-2.

[Second Example-6] In the second embodiment-6, in the second embodiment-1, the thickness of the conductor thickness of the inner power supply layer and the ground layer was changed to 45 μm. Other than that, it is the same as in the second embodiment-1.

[Second Example-7] In the second embodiment-7, in the second embodiment-1, the thickness of the conductors of the power supply layer and the ground layer of the inner layer was changed to 60 μm. Other than that, it is the same as in the second embodiment-1.

[Second Example-8] In the second embodiment-8, in the second embodiment-1, the thickness of the conductor thickness of the inner power supply layer and the ground layer was changed to 75 μm. Other than that, it is the same as in the second embodiment-1.

[Second Example-9] In the second embodiment-9, in the second embodiment-3, the thickness of the conductor thickness of the inner power supply layer and the ground layer was changed to 75 μm. Other than that, it is the same as in the second embodiment-3.

[Second Example-10] The multilayer printed wiring board according to the second embodiment-10 of the present invention will be described with reference to FIG. 27. In the multilayer printed wiring board of the second embodiment described above with reference to FIG. 22, a multilayer core board 30 in which two layers of ground circuits 16E and 16P are arranged in the inner layer is used. On the other hand, in the second embodiment-10, the multilayer core substrate 20 provided with the four-layer inner layer ground circuits 16E, 116E, 16P, and 116PP is used. The ground circuit and the power supply circuit are arranged alternately.

"Second Example-11 ~ 19" In the second embodiment-1 to 9, the thickness of the starting material and the thickness of the conductor layers on the front and back of the core substrate were changed. Specifically, the thickness of the copper-clad laminate 10 in FIG. 18 (A) was set to 0.2 mm, and the thickness of the conductor layers (34S, 34P, 34E) on the front and back of the core substrate in FIG. 20 (B) was set to 10 μm. Subsequent steps were in accordance with Second Example-1.

[Second Example-20] In the second embodiment-20, in the second embodiment-16, the number of through holes for power supply having no dummy land directly under the IC is set to 30% of the total number of through holes for power supply, and the dummy land directly under the IC is set to 30%. The number of through-holes for grounding that does not have is set to 30% of the total number of through-holes for grounding.

[Second Example-21] In the second embodiment-21, in the second embodiment-20, the thickness of the conductor thickness of the power supply layer and the ground layer of the inner layer of the multilayer core substrate was set to 60 μm.

[Second Example-22] In the second embodiment-22, in the second embodiment-20, the thickness of the conductor thickness of the power supply layer and the ground layer of the inner layer of the multilayer core substrate was set to 75 μm.

[Second Example-23] In the second embodiment-23, in the second embodiment-20, the thickness of the conductor thickness of the power supply layer and the ground layer of the inner layer of the multilayer core substrate was set to 150 μm. The thickness of the prepreg in FIG. 18 (D) was set to 275 μm.

[Second Example-24] In the second embodiment-24, in the second embodiment-20, the thickness of the conductor thickness of the power supply layer and the ground layer of the inner layer of the multilayer core substrate was set to 300 μm. The thickness of the prepreg in FIG. 18 (D) was set to 450 μm.

[Second Example-25] In the second embodiment-25, in the second embodiment-20, the number of through holes for power supply having no dummy land directly under the IC is set to 50% of the total number of through holes for power supply, and the dummy land directly under the IC is set to 50%. The number of through-holes for grounding that does not have is set to 50% of the total number of through-holes for grounding.

[Second Example-26] In the second embodiment-26, in the second embodiment-21, the number of through holes for power supply having no dummy land directly under the IC is set to 50% of the total number of through holes for power supply, and the dummy land directly under the IC is set to 50%. The number of through-holes for grounding that does not have is set to 50% of the total number of through-holes for grounding.

[Second Example-27] In the second embodiment-27, in the second embodiment-22, the number of through holes for power supply having no dummy land directly under the IC is set to 50% of the total number of through holes for power supply, and the dummy land directly under the IC is set to 50%. The number of through-holes for grounding that does not have is set to 50% of the total number of through-holes for grounding.

[Second Example-28] In the second embodiment-28, in the second embodiment-23, the number of through holes for power supply having no dummy land directly under the IC is set to 50% of the total number of through holes for power supply, and the dummy land directly under the IC is set to 50%. The number of through-holes for grounding that does not have is set to 50% of the total number of through-holes for grounding.

[Second Example-29] In the second embodiment-29, in the second embodiment-24, the number of through holes for power supply having no dummy land directly under the IC is set to 50% of the total number of through holes for power supply, and the dummy land directly under the IC is set to 50%. The number of through-holes for grounding that does not have is set to 50% of the total number of through-holes for grounding.

[Second Example-30] In the second embodiment-30, in the second embodiment-20, the number of through holes for power supply having no dummy land directly under the IC is set to 70% of the total number of through holes for power supply, and the dummy land directly under the IC is set to 70%. The number of through-holes for grounding that does not have is set to 70% of the total number of through-holes for grounding.

[Second Example-31] In the second embodiment-31, in the second embodiment-21, the number of through holes for power supply having no dummy land directly under the IC is set to 70% of the total number of through holes for power supply, and the dummy land directly under the IC is set to 70%. The number of through-holes for grounding that does not have is set to 70% of the total number of through-holes for grounding.

[Second Example-32] In the second embodiment-32, in the second embodiment-22, the number of through holes for power supply having no dummy land directly under the IC is set to 70% of the total number of through holes for power supply, and the dummy land directly under the IC is set to 70%. The number of through-holes for grounding that does not have is set to 70% of the total number of through-holes for grounding.

[Second Example-33] In the second embodiment-33, in the second embodiment-23, the number of through holes for power supply having no dummy land directly under the IC is set to 70% of the total number of through holes for power supply, and the dummy land directly under the IC is set to 70%. The number of through-holes for grounding that does not have is set to 70% of the total number of through-holes for grounding.

[Second Example-34] In the second embodiment-34, in the second embodiment-24, the number of through holes for power supply having no dummy land directly under the IC is set to 70% of the total number of through holes for power supply, and the dummy land directly under the IC is set to 70%. The number of through-holes for grounding that does not have is set to 70% of the total number of through-holes for grounding.

[Second Example-35] In the second embodiment-35, in the second embodiment-12, the thickness of the conductor thickness of the power supply layer and the ground layer of the inner layer of the multilayer core substrate was set to 60 μm.

[Second Example-36] In the second embodiment-36, in the second embodiment-25, the thickness of the conductor thickness of the power supply layer and the ground layer of the inner layer of the multilayer core substrate was set to 30 μm.

The number of through holes having no dummy land directly under the IC in the second embodiment-2 to 5, 12 to 15, 19, and 35 is a number obtained by subtracting 10 to 15% from the% shown in FIGS. 30 and 33. ..

(2nd Comparative Example-1) A multilayer core substrate was formed so as to be an inner conductor layer and a surface conductor layer having the same thickness as that of the second embodiment-1. However, the dummy lands 16 were arranged in all the through holes in the same manner as the related technology described above with reference to FIGS. 36 and 38.

(2nd Comparative Example-2) In the second comparative example-1, the conductor thickness of the multilayer core substrate is 15 μm, which is the same as that of the second comparative example-1.

(2nd Comparative Example-3) In the second comparative example-1, the thickness of the starting material was changed. Specifically, the thickness of the copper-clad laminate 10 in FIG. 18 (A) was set to 0.2 mm. Further, in FIG. 18A, the thickness of the copper foil 16 was set to 5 μm.

The amount of voltage drop when the IC chip with a frequency of 3.1 GHz is mounted on the boards of the second embodiment-1 to 9 and the second comparative example-1 and 2 to supply the same amount of power and start up. Was measured. Since the voltage of the IC chip cannot be measured directly, a circuit that can measure the voltage of the IC is formed on the printed wiring board. The value of the voltage drop amount at this time is shown. This is the value of the fluctuating voltage drop when the power supply voltage is 1.0V. In addition, the initial operations of 2nd Examples-1 to 9 and 2nd Comparative Examples-1 and 2 were confirmed. This result is shown in the chart in FIG. Furthermore, the number of through holes without dummy lands was also verified. The results are shown below. The results of (V) with the number of through holes without dummy lands on the horizontal axis and the value of the voltage drop on the vertical axis are shown in FIGS. 32 (A) and 32 (B).

From the comparison between the second embodiment-1 and the second comparative example-1, the through holes directly under the IC are made into through holes that do not have a conductor circuit extending from the through holes, so that the first and second voltage drops Is improved, and it can be seen that the malfunction of the IC no longer occurs. From the results of 2nd Example-2 to 5 and 2nd Comparative Example-1, the through holes for power supply and ground are defined as through holes having no dummy land, and the number of through holes is increased. It can be seen that the voltage drop at the second time is improved (see FIGS. 32 (A), (B), and 33). From the comparison of the second embodiment-1, 6, 7, and 8, it can be seen that the first and second voltage drops are further improved by increasing the conductor thickness of the inner layer of the multilayer core (Fig. 40). reference). When the conductor thickness of the inner layer becomes three times or more the conductor thickness of the build-up layer, the improvement effect diminishes. From the second embodiment-2 to 5 and the second comparative example-1, the voltage drops of the first and second times are improved by increasing the number of through holes having no conductor circuit extending from the through holes. You can see that. And when it becomes 70% or more, the malfunction of the IC does not occur. If the number of through holes that do not have a conductor circuit extending from the through holes is 70% or more, the improvement effect is diminished. From the second comparative example-1 and the second comparative example-2, it can be seen that the third voltage drop is improved by increasing the conductor thickness.

From the above test results, it can be seen that the degree of power supply shortage (voltage drop) that occurs at the initial startup of the IC chip is reduced by the configuration of the present invention, and even if an IC chip in the high frequency region, especially an IC chip of 3 GHz or higher is mounted. , It turned out that it can be started without any problem. Therefore, the electrical characteristics and electrical connectivity can also be improved. Further, the resistance in the circuit of the printed circuit board can be made smaller than that of the conventional printed circuit board. Therefore, even if a bias is applied and a reliability test (high temperature and high humidity bias test) is performed under high temperature and high humidity, the time for destruction is long, so that the reliability can be improved.

Next, the voltage drop of the IC chip was measured for the multilayer printed wiring board manufactured according to the second examples-11 to 36 and the second comparative example-3 by the method as described below. Simultaneous switching was performed on each multilayer printed wiring board on which the following No. 3 IC chip was mounted, and the voltage drop of the IC chip at that time was measured. Since the voltage of the IC chip cannot be measured directly, a circuit that can measure the voltage of the IC is formed on the printed wiring board. This is the value of the fluctuating voltage drop when the power supply voltage is 1.0V. In addition, regarding the multilayer printed wiring board manufactured according to the second examples-11 to 36 and the second comparative example-3, it was confirmed whether or not the mounted IC chip had a malfunction by the method as described below. As the IC chip, one of the IC chips selected from Nos. 1 to 3 below was mounted on each multilayer printed wiring board, and simultaneous switching was performed 100 times to evaluate the presence or absence of malfunction. The results are shown in FIG. No.1: Drive frequency: 3.06GHz, Bus clock (FSB): 533MHz No.2: Drive frequency: 3.2GHz, Bus clock (FSB): 800MHz No.3: Drive frequency: 3.46GHz, bus clock (FSB): 1066MHz

From the result of mounting the No. 1 IC chip, it can be seen that if a part of the through hole is a through hole that does not have a dummy land, the malfunction and voltage drop of the IC chip can be suppressed. It is presumed that this is due to the effects 2 to 4 of the second invention described in the specification. From the comparison between the second embodiment-12 and the second embodiment-36 on which the No. 2 IC chip is mounted, it can be seen that the region forming the through hole having no dummy land is preferable directly under the IC. In addition, from the comparison of the second embodiment-20 to 24 and the second embodiment-25 to 29 in which the No. 3 IC chip is mounted, there is an interaction between the conductor thickness of the inner layer and the number of through holes having no dummy land. I know there is. When the conductor thickness of the inner layer is thin, it is necessary to increase the number of through holes having no dummy land, and when the conductor thickness of the inner layer is thick, it may be small. It is inferred that this is due to the effect explained using FIG. 34. The conductor thickness of the ground layer of the inner layer is the same as the conductor thickness of the power supply layer of the inner layer, and the conductor thickness of the ground layer on the back surface of the core substrate is the same as the conductor thickness of the power supply layer on the front surface. Therefore, since the sum of the conductor thicknesses of the ground layer is as thick as that of the power supply layer, noise can be reduced and malfunctions are less likely to occur.

Comparing the second embodiment-12 and the second embodiment-36 on which the No. 2 IC chip is mounted, even if the thickness of the conductor layer of the multilayer core and the number of through holes without dummy lands are the same. It can be seen that the amount of voltage drop and malfunction differ depending on the area where the through hole without the dummy land is provided. This is because the through hole directly under the IC has a short connection wiring length to the IC, so it is presumed that the features of the present application are more effective by providing a through hole that does not have a dummy land directly under the IC. Is

<figref num="1">It is a process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example-1 of this invention.</figref><figref num="2">It is a process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example-1.</figref><figref num="3">It is a process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example-1.</figref><figref num="4">It is a process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example-1.</figref><figref num="5">It is a process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example-1.</figref><figref num="6">It is a process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example-1.</figref><figref num="7">It is a process drawing which shows the manufacturing method of the multilayer printed wiring board of 1st Example-1.</figref><figref num="8">It is sectional drawing of the multilayer printed wiring board which concerns on 1st Example-1.</figref><figref num="9">It is sectional drawing which shows the state which put the IC chip on the multilayer printed wiring board which concerns on 1st Example-1.</figref><figref num="10">It is a graph which showed the voltage change during operation of an IC chip.</figref><figref num="11">It is a graph which showed the voltage change during operation of an IC chip.</figref><figref num="12">It is a graph which showed the voltage change during operation of an IC chip.</figref><figref num="13">It is a chart which shows the test result of 1st Example and 1st Comparative Example.</figref><figref num="14">It is a chart which shows the evaluation result of the line width formation ability evaluation pattern between the minimum lines of the 1st Example.</figref><figref num="15">It is a chart which shows the test result of 1st Example and 1st Comparative Example.</figref><figref num="16">It is a chart which shows the test result of 1st Example.</figref><figref num="17">It is a graph of the amount of voltage drop with respect to α1 / α2.</figref><figref num="18">It is a process drawing which shows the manufacturing method of the multilayer printed wiring board of 2nd Example-1 of this invention.</figref><figref num="19">It is a process drawing which shows the manufacturing method of the multilayer printed wiring board of 2nd Example-1.</figref><figref num="20">It is a process drawing which shows the manufacturing method of the multilayer printed wiring board of 2nd Example-1.</figref><figref num="21">It is a process drawing which shows the manufacturing method of the multilayer printed wiring board of 2nd Example-1.</figref><figref num="22">It is sectional drawing of the multilayer printed wiring board which concerns on 2nd Example-1.</figref><figref num="23">It is sectional drawing which shows the state which put the IC chip on the multilayer printed wiring board which concerns on 2nd Example-1.</figref><figref num="24">It is sectional drawing which shows the state which put the IC chip on the multilayer printed wiring board which concerns on the modification of 2nd Example-1.</figref><figref num="25">FIG. 25 (A) is a plan view of the inner layer power supply plane layer 16P in FIG. 22, and FIG. 25 (B) is a plan view of the inner layer grounding plane layer 16E.</figref><figref num="26">FIG. 26 (A) is a plan view of the inner layer power supply plane layer 16P in FIG. 22, and FIG. 26 (B) is a plan view of the inner layer grounding plane layer 16E.</figref><figref num="27">It is sectional drawing of the multilayer printed wiring board which concerns on 2nd Example-10.</figref><figref num="28">It is a graph which showed the voltage change during operation of an IC chip.</figref><figref num="29">It is a graph which showed the voltage change during operation of an IC chip.</figref><figref num="30">It is a chart which shows the test result of 2nd Example and 2nd Comparative Example.</figref><figref num="31">FIG. 31 (A) is a plan view of another example power supply plane layer 16P in FIG. 22, and FIG. 25 (B) is a plan view of the inner layer ground plane layer 16E.</figref><figref num="32">Regarding the number of through holes having no dummy lands, the horizontal axis shows the number of through holes without dummy lands, and the vertical axis shows the value (V) of the voltage drop amount.</figref><figref num="33">It is a chart which shows the relationship between the conductor thickness of an inner layer and the voltage drop of the 1st to 3rd times.</figref><figref num="34">It is explanatory drawing which shows the relationship between a through hole and a conductor layer.</figref><figref num="35">It is sectional drawing of the multilayer printed wiring board which concerns on the related technique of this invention.</figref><figref num="36">FIG. 35 is a cross-sectional view of X4-X4 of the multilayer printed wiring board of FIG. 35, and FIG. 36 (B) is a cross-sectional view of X5-X5.</figref><figref num="37">FIG. 37 (A) is a plan view of the inner layer power supply plane layer 16P, and FIG. 37 (B) is a plan view of the inner layer grounding plane layer 16E.</figref><figref num="38">It is a cross-sectional view of the multilayer printed wiring board of the prior art.</figref><figref num="39">It is a schematic diagram of the through hole for a signal penetrating through a multilayer core.</figref><figref num="40">It is a graph which shows the voltage drop amount of the 1st time and the 2nd time.</figref>

Code description

12 Metal layer (metal plate) 14 resin layer 16 Conductor circuit 16P conductor layer 16E conductor layer 18 resin layer 30 board 32 copper foil 34 Conductor circuit 34P conductor layer 34E Conductor layer 36 through hole 40 Resin packed layer 50 Interlayer resin insulation layer 58 Conductor circuit 60 Via Hall 70 Solder resist layer 71 opening 76U, 76D Solder bump 90 IC chip 94 daughter board 98 chip capacitors