Solid state image pickup device and its manufacture method

The present invention has an overflow barrier region.<u style="single">Manufacturing method of solid-state image sensor</u>Regarding.

FIG. 8 is a schematic plan view showing the pixel arrangement portion of the solid-state image sensor.

The pixel array portion includes a plurality of photoelectric conversion elements 60, a vertical transfer channel 53, vertical transfer electrodes (first layer vertical transfer electrode 58a, second layer vertical transfer electrode 58b), and a plurality of element separation regions 57, respectively.

The photoelectric conversion elements 60 are arranged in a honeycomb, for example, in a semiconductor substrate, and generate and store signal charges according to the amount of incident light. The vertical transfer channel 53 is formed in the semiconductor substrate in the vicinity of the photoelectric conversion element 60. The signal charge generated and accumulated by the photoelectric conversion element 60 is read out to the vertical transfer channel 53 and transferred in the vertical transfer channel 53 in the vertical direction (downward in the drawing), which is the column direction (extending direction) as a whole. Will be done. A drive signal (transfer voltage) is applied to the vertical transfer electrodes (first layer vertical transfer electrode 58a, second layer vertical transfer electrode 58b) formed above the semiconductor substrate to control the potential of the vertical transfer channel 53. Transfers the signal charge read from the photoelectric conversion element 60 in the vertical direction. The vertical transfer electrode is made of polysilicon. It can also be formed of amorphous silicon.

An element separation region 57 is formed between adjacent photoelectric conversion element rows. The element separation region 57 is an region for electrically separating the photoelectric conversion element 60, the vertical transfer channel 53, and the like. In FIG. 8, the element separation region 57 is shown with diagonal lines.

9 (A) to 9 (C) are schematic cross-sectional views showing the pixel arrangement portion of the conventional example of the solid-state image sensor, respectively.

See Figure 9 (A). The n-type semiconductor substrate 50 is formed with an overflow barrier region 51 made of a p-type impurity layer in order to prevent blooming and the like. Electrons with energy exceeding the barrier height are sucked out to the n-type semiconductor substrate 50 beyond the overflow barrier region 51 to prevent blooming.

In the vicinity of the surface of the n-type semiconductor substrate 50, n⁺Mold charge storage region 55 and embedding it p⁺A mold embedding region 56 is formed. The photoelectric conversion element is configured to include, for example, these, and the signal charge generated according to the amount of incident light is accumulated in the charge storage region 55. One pixel is configured to include one photoelectric conversion element.

In the present specification and the like, a region having a higher n-type impurity concentration than the n-type region is defined as n.⁺, N in the low area^-, P-type region with higher p-type impurity concentration than p-type region⁺, P low area^-Notated as.

The signal charge accumulated in the charge storage region 55 is read out to the vertical transfer channel 53, which is an n-type region, via the read gate 54, which is a p-type region, and as described above, the entire inside of the vertical transfer channel 53 is read. Transferred vertically as.

The vertical transfer electrode 58 is formed above the vertical transfer channel 53 via an insulating film (for example, an ONO film), and the applied voltage controls the potential of the gate 54 to be vertical from the charge storage region 55. Read the signal charge to the transfer channel 53. Further, as described above, the signal charge in the vertical transfer channel 53 is transferred in the vertical direction as a whole.

A light-shielding film 59 is formed above the vertical transfer electrode 58, for example, by tungsten. The light-shielding film 59 has an opening 59a formed above the charge storage region 55.

The p-type impurity layer 52 formed directly below the vertical transfer channel 53 protects the vertical transfer channel 53 in the sense that it prevents unnecessary charges from being mixed into the vertical transfer channel 53. It also functions to reduce smear and separate pixels.

As described above, the element separation region 57 is formed between the adjacent photoelectric conversion element rows, and the photoelectric conversion element, the vertical transfer channel 53, and the like are electrically separated.

An electrode 61 is provided on the n-type semiconductor substrate 50. The voltage applied to the n-type semiconductor substrate 50 via the electrode 61 causes each pixel to perform a blooming suppression operation that sweeps out excess charge equal to or greater than the saturation amount to the substrate, and an electronic shutter that sweeps out the charge accumulated in the charge storage region 55 to the substrate. Do the action.

See Figure 9 (B). The conventional example shown in FIG. 9 (B) is different from that of FIG. 9 (A) in that the charge storage region 55 has a two-layer structure. In the example shown in FIG. 9 (A), the charge storage region 55 is n.⁺It was composed of only one type impurity layer, but in the example shown in Fig. 9 (B), n⁺A charge storage region 55 is formed by the type impurity layer and the n-type impurity layer below it.

By forming the charge storage region 55 in multiple layers, it is possible to form a pn junction at a deep position on the semiconductor substrate and widen the effective depletion layer in the n-type region. In the present specification, the effective depletion layer means a depletion layer in which the signal charge generated by photoelectric conversion is collected in the charge storage region.

See Figure 9 (C). The conventional example shown in FIG. 9 (C) is different from that in FIG. 9 (B) in that the overflow barrier region 51 has a two-layer structure. In the example shown in FIG. 9 (B), the overflow barrier region 51 was composed of only one p-type impurity layer, but in the example shown in FIG. 9 (C), the p-type impurity layer and above it. P^-An overflow barrier region 51 is formed with the type impurity layer.

By multi-layering the overflow barrier region 51 in this way, it is possible to realize a low impurity concentration in the p-type region forming the pn junction.

Generally, in a photoelectric conversion element, among the incident light, light in a long wavelength region is photoelectrically converted at a position deep from the surface of the semiconductor substrate. On the other hand, the position where the overflow barrier region 51 is formed is becoming shallower due to the recent demand for higher resolution and miniaturization of the solid-state image sensor. As a result, the light in the long wavelength region is invalidly photoelectrically converted at a position deeper than the overflow barrier region 51, and the sensitivity to the long wavelength light may not be sufficiently ensured. Further, when the overflow barrier region 51 is formed at a position deep from the surface of the semiconductor substrate in order to secure the long wavelength optical sensitivity, there is a problem that inter-pixel blooming is likely to occur. (See, for example, Patent Document 1.)

<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2000-150848</text></patcit>

<p> An object of the present invention is to be able to perform high quality imaging.<u style="single">Manufacturing method of solid-state image sensor</u>Is to provide.</p>

<p><u style="single">According to one aspect of the invention</u>(A) A step of ion-injecting a second conductive type impurity which is a reverse conductive type from the first conductive type onto the entire surface of the first conductive type semiconductor substrate to form an override barrier region, and (b) the overflobar barrier region. A step of ion-injecting the second conductive type impurity into the semiconductor substrate above the flow barrier region to form a first impurity layer for inter-pixel separation, and (c) a semiconductor layer on the semiconductor substrate. And (d) the second conductive type impurity is ion-injected into the epitaxial substrate above the first inter-pixel separation impurity layer to form an epitaxial substrate, and each charge storage region The step of forming the channel protection impurity layer so as to surround the planned formation region, and (e) ion injection of the first conductive type impurity into the epitaxial substrate above the channel protection impurity layer to make it vertical. The first step of forming the transfer channel, (f) the step of forming the vertical transfer electrode above the vertical transfer channel, and (g) the step of forming the vertical transfer electrode in the epitaxial substrate at a position surrounded by the channel protection impurity layer. 1 It has a step of injecting conductive impurities with ions to form a charge storage region, and finally the peak position of the impurity concentration in the overflo barrier region is formed at a position deeper than the surface of the epitaxial substrate by 3 μm or more. A method for manufacturing a solid-state imaging device is provided.</p><p> According to this method for manufacturing a solid-state image sensor, it is possible to manufacture a solid-state image sensor capable of high-quality imaging in which a decrease in long-wavelength light sensitivity and occurrence of inter-pixel blooming are suppressed.</p>

<p> High quality imaging is possible<u style="single">Manufacturing method of solid-state image sensor</u>Can be provided.</p>

FIG. 1 (A) is a block diagram showing a main part of a solid-state image sensor incorporating a solid-state image sensor, and FIGS. 1 (B) and 1 (C) are schematic plan views showing the configuration of the solid-state image sensor. is there.

See Figure 1 (A). The solid-state imaging device generates a signal charge according to the amount of light incident on each pixel, and supplies an image signal based on the generated signal charge. The solid-state imaging element 81 and the drive signal (transfer voltage) for driving the solid-state imaging element 81. Etc.), and the output signals of the drive signal generator 82 and the solid-state imaging element 81 that are supplied to the solid-state imaging element 81 are subjected to correlation double sampling, amplified by an externally set gain, and then converted from analog to digital. Digitally outputs image data by performing processing such as recognition processing, data compression, and network control of the image signal supplied from the analog front-stage processing device (Analog Front End, AFE) 83 and analog pre-stage processing device 83 for digital output. Timing Generator (TG) 85 that outputs timing signals to the signal processing device (Digital Signal Processor, DSP) 84, solid-state imaging element 81, drive signal generator 82, and analog pre-stage processing device 83, and controls their operation. Consists of including.

The drive signal generator 82 includes, for example, a V driver that generates a vertical CCD drive signal. The signals supplied from the drive signal generator 82 to the solid-state image sensor 81 are a horizontal CCD drive signal, a vertical CCD drive signal, an output amplifier drive signal, and a substrate bias signal.

See Figure 1 (B). The solid-state image sensor is electrically coupled to, for example, a plurality of photosensitive portions 92 arranged in a matrix, a plurality of vertical CCD portions 94 formed in close proximity to each row of the photosensitive portions 92, and a plurality of vertical CCD portions 94. The horizontal CCD section 96 and the amplifier circuit section 97 provided at the end of the horizontal CCD section 96 and amplifying the output charge signal from the horizontal CCD section 96 are included. The pixel arrangement unit 91 includes a photosensitive unit 92 and a vertical CCD unit 94. Further, this figure is a view of the semiconductor substrate on which the pixel array portion 91 and the like are formed, as viewed from the normal direction (upper side).

The photosensitive unit 92 includes a photosensitive element, for example, a photoelectric conversion element (photodiode) and a readout gate. The photoelectric conversion element generates and accumulates a signal charge according to the amount of incident light. The reading of the stored signal charge to the vertical CCD unit 94 (vertical transfer channel) is controlled by the voltage applied to the reading gate. The signal charge read by the vertical CCD unit 94 is transferred in the vertical CCD unit 94 (vertical transfer channel) as a whole in the direction toward the horizontal CCD unit 96 (vertical direction). The signal charge transferred to the end of the vertical CCD section 94 is transferred to the horizontal CCD section 96, transferred horizontally in the horizontal CCD section 96 (horizontal transfer channel), amplified by the amplifier circuit section 97, and taken out to the outside. Is done.

In addition to the case where the photosensitive portions 92 are arranged in a square (tetragonal) matrix at a constant pitch in the row direction and the column direction as shown in FIG. 1 (B), 1 is arranged in the row direction and the column direction. There is a honeycomb arrangement in which the positions are shifted by 1/2 pitch, for example, every other time. The honeycomb arrangement includes a first square-matrix-arranged photosensitive part 92 and a second square-matrix-arranged photosensitive part 92 at an interstitial position thereof.

FIG. 1C is a schematic plan view of a solid-state image sensor arranged in a honeycomb. The vertical CCD section 94 (vertical transfer channel) is formed so as to meander between the photosensitive sections 92.

FIG. 2 is a schematic cross-sectional view showing a pixel array portion of the solid-state image sensor according to the first embodiment.

Similar to the conventional example shown in FIG. 9B, but the overflow barrier region 51 is formed at a deeper position of the n-type semiconductor substrate 50, and the p-type impurity layer below the vertical transfer channel 53. A low concentration p-type (p) between 52 (impurity layer for channel protection) and the overflow barrier region 51, for example, at a depth intermediate between the two.^-Type) Impurity layer 62 (impurity layer for separation between pixels) is formed. Low concentration p type (p^-The type) impurity layer 62 is formed below the p-type impurity layer 52 and at a position facing the p-type impurity layer 52.

The peak position of the p-type impurity concentration in the overflow barrier region 51 is, for example, at a depth of 3.5 μm from the substrate surface. The overflow barrier region 51 can be formed at this position by ion-implanting p-type impurities with high acceleration energy, for example 2.5 MeV or higher.

It is desirable that the peak position of the p-type impurity concentration in the overflow barrier region 51 is formed at a position deeper than the surface of the semiconductor substrate by 3 μm or more. By forming the overflow barrier region 51 at such a position, the effective photosensitive region is expanded to the deep part of the substrate, as will be described in detail later. Therefore, it is possible to realize a solid-state image sensor capable of high-quality imaging with improved long-wavelength optical sensitivity.

The p-type impurity layer 52 is formed at a position surrounding the charge storage region 55.

By forming the p-type impurity layer 52 and the low-concentration p-type impurity layer 62 in this way, blooming between pixels can be suppressed and high-quality imaging is possible, as will be described in detail later. The element can be realized. The p-type impurity layer 52 directly below the vertical transfer channel 53 also has a function of preventing unnecessary charges from being mixed into the vertical transfer channel 53, as described above.

The low-concentration p-type impurity layer 62 has a lower p-type impurity concentration than, for example, the p-type impurity layer 52. Further, for example, the p-type impurity concentration is lower than that of the p-type impurity layer constituting the overflow barrier region 51. By adjusting the impurity concentration in this way, V_ofdWhen (overfrodo drain voltage) is increased, it is possible to suppress a decrease in long wavelength sensitivity at an early stage. (It is possible to suppress the decrease in long wavelength sensitivity during movies.) The solid-state image sensor according to the first embodiment can be manufactured, for example, as follows.

10 (A) to 10 (E) are schematic cross-sectional views showing a method of manufacturing a solid-state image sensor according to the first embodiment.

See Figure 10 (A). For example, an n-type semiconductor substrate 50, which is a silicon substrate, is prepared, and p-type impurities such as boron are ion-implanted from the surface of the entire surface with high acceleration energy, and an overflow barrier region 51, which is a p-type impurity layer, is implanted deep in the substrate. To form. Boron ion implantation, for example, dose amount 2 × 10¹¹~4×10¹¹/cm², Acceleration energy 2.5 ~ 3MeV.

Next, using the photoresist pattern as a mask, p-type impurities such as boron are added in a dose amount of 1 × 10.¹¹~2×10¹¹/cm²Ion implantation is performed with an acceleration energy of 1 to 2.5 MeV to form a low-concentration p-type impurity layer 62 above the overflow barrier region 51. Subsequently, the same p-type impurities, such as boron, are added to the dose amount of 2 × 10.¹¹~6×10¹¹/cm²Ion implantation is performed with an acceleration energy of 500 to 1000 keV to form a p-type impurity layer 52 above the low-concentration p-type impurity layer 62. The dose amount in ion implantation when forming the low-concentration p-type impurity layer 62 is smaller than, for example, the dose amount in ion implantation when forming the p-type impurity layer 52. In addition, it is smaller than the dose amount in ion implantation when the overflow barrier region 51 is formed.

See Figure 10 (B). An n-type impurity such as phosphorus or arsenic is ion-implanted above the p-type impurity layer 52 using a photoresist pattern as a mask to form a vertical transfer channel 53.

See Figure 10 (C). A p-type impurity such as boron is ion-implanted at a position adjacent to the vertical transfer channel 53 using a photoresist pattern as a mask to form a readout gate 54 and an element separation region 57.

Although not shown in FIG. 2, an insulating film 98 is formed on the surface of the n-type semiconductor substrate 50. The insulating film 98 is an ONO film composed of, for example, a silicon oxide film by thermal oxidation, a silicon nitride film by CVD (Chemical Vapor Deposition), and a silicon oxide film by thermal oxidation.

The vertical transfer electrode 58 is formed of, for example, polysilicon so as to cover the vertical transfer channel 53. The vertical transfer electrode 58 is configured to include, for example, the vertical transfer electrodes of the first layer and the second layer, is generated by a photoelectric conversion element by controlling the potential of the vertical transfer channel 53, and is read out to the vertical transfer channel 53. The signal charge is transferred in the vertical direction. The vertical transfer electrode 58 is produced by depositing polysilicon on an insulating film 98 (ONO film), for example, by CVD, and patterning the polysilicon by photolithography and etching. Although not shown in FIG. 2, the vertical transfer electrode 58 is thermally oxidized to form a silicon oxide film 99 on its surface.

See Figure 10 (D). After applying a resist on the vertical transfer electrode 58 or the insulating film 98 (ONO film) using the vertical transfer electrode 58 as a mask, exposure and development are performed to leave the resist only in a predetermined position and use the resist as a mask. , N-type impurities, such as phosphorus or arsenic, are ion-implanted to form the charge storage region 55. In addition, p-type impurities such as boron are ion-implanted to form an embedded region 56 in which a charge storage region 55 is embedded.

The photoelectric conversion element (charge storage region 55) may be formed in a square matrix or in a honeycomb array. Further, although not shown in the cross-sectional view of FIG. 2, the horizontal CCD portion 66 is formed on the n-type semiconductor substrate 50 by a step overlapping with the above step.

See Figure 10 (E). A light-shielding film 59 is formed above the silicon oxide film 99 on the surface of the vertical transfer electrode 58, for example, with tungsten. A resist is applied onto the light-shielding film 59, exposed and developed to leave the resist only at a predetermined position, and an opening 59a is formed above the charge storage region 55 by etching with the resist as a mask.

FIG. 3 is a schematic cross-sectional view showing a pixel array portion of the solid-state image sensor according to the second embodiment.

Compared with the first embodiment shown in FIG. 2, first, the overflow barrier region 51 is different in that it has a multilayer structure (two layers in the case of the illustration) along the depth direction of the substrate. In the first embodiment, the overflow barrier region 51 was composed of only one p-type impurity layer, but in the second embodiment, the p-type impurity layer and p above it.^-An overflow barrier region 51 is formed with the type impurity layer. The peak position of the p-type impurity concentration in the overflow barrier region 51 is, for example, a position at a depth of 4.4 μm from the surface of the semiconductor substrate.

The desired formation position of the peak position of the p-type impurity concentration in the overflow barrier region 51 and the effect thereof are the same as in the case of the first embodiment. Further, by forming the overflow barrier region 51 in multiple layers in this way, it is possible to realize a low impurity concentration in the p-side region of the pn junction.

Next, low concentration p type (p)^-Type) Impurity layer (impurity layer for separation between pixels) is different in that it has a multi-layer (two layers in the case of drawing) structure along the depth direction of the substrate.

The p-type impurity layer 52 (channel protection impurity layer) is formed at a position surrounding the charge storage region 55. The effect is the same as in the first embodiment. Further, by making the low-concentration p-type impurity layer multi-layered, it is possible to prevent the signal charge from moving to the adjacent pixel even if the barrier is deepened.

In the drawing, the low-concentration p-type impurity layer 62b formed on the back surface (overflo barrier region 51) side of the substrate is the low-concentration p-type impurity layer formed on the substrate surface (charge storage region 55) side. The two low-concentration p-type impurity layers 62a and 62b may be formed to have the same line width, although they project toward the lower side of the charge storage region 55 than 62a. However, if the line width of the low-concentration p-type impurity layers 62a and 62b is thick, V_ofdWhen the (overfrodo drain voltage) is increased (during the movie), the long wavelength sensitivity (depletion layer thickness) tends to decrease at an early stage, so the line widths of the low-concentration p-type impurity layers 62a and 62b are Narrower ones (eg comparable to vertical transfer channels) are preferred.

The two low-concentration p-type impurity layers 62a and 62b have a lower p-type impurity concentration than, for example, the p-type impurity layer 52. Further, for example, two layers of p-type or p that constitute the overflow barrier region 51.^-The p-type impurity concentration is lower than that of the type impurity layer. By adjusting the impurity concentration in this way, V_ofdWhen (overfrodo drain voltage) is increased, it is possible to suppress a decrease in long wavelength sensitivity at an early stage. (It is possible to suppress the decrease in long wavelength sensitivity during movies.) 4 (A) to 4 (C) are schematic cross-sectional views showing an example of a method for manufacturing a solid-state image sensor according to the second embodiment.

See Figure 4 (A). For example, an n-type semiconductor substrate 50, which is a silicon substrate, is prepared, and p-type impurities such as boron are ion-implanted from the surface of the n-type semiconductor substrate 50 to form a p-type impurity layer and p.^-An overflow barrier region 51 composed of a type impurity layer is formed. Boron ion implantation is performed twice. For example, the first dose is 2 x 10¹¹~4×10¹¹/cm², Acceleration energy 2.5 ~ 3MeV, second dose amount 1 × 10¹¹~2×10¹¹/cm², Ion implantation with acceleration energy of 1.5 ~ 2.5MeV.

Next, using the photoresist pattern as a mask, p-type impurities such as boron are added in a dose amount of 1 × 10.¹¹~2×10¹¹/cm²Ion implantation is performed with an acceleration energy of 1.5 to 2.5 MeV to form a low-concentration p-type impurity layer 62b above the overflow barrier region 51. Subsequently, a new photoresist pattern is formed to form a mask, and p-type impurities such as boron are also added to the dose amount of 1 × 10.¹¹~2×10¹¹/cm²Ion implantation is performed with an acceleration energy of 1 to 2 MeV to form a low-concentration p-type impurity layer 62a above the low-concentration p-type impurity layer 62b. It is also possible to form two low-concentration p-type impurity layers 62a and 62b using the same mask. The dose amount in ion implantation when the low-concentration p-type impurity layers 62a and 62b are formed is smaller than the dose amount in ion implantation when the overflow barrier region 51 is formed, for example.

The low-concentration p-type impurity layer 62a is formed near the surface of the n-type semiconductor substrate 50 in FIG. 4A, for example.

See Figure 4 (B). By epitaxial growth, an epi layer (semiconductor layer) 70 having the same impurity concentration as the n-type semiconductor substrate 50 is formed on the surface of the n-type semiconductor substrate 50 shown in FIG. 4 (A) to, for example, a thickness of 2 μm to form an epitaxial substrate. To do.

See Figure 4 (C). FIG. 4 (C) is the same as FIG. Using the photoresist pattern as a mask, p-type impurities such as boron are added from the surface of the epi layer 70 in a dose amount of 2 × 10.¹¹~6×10¹¹/cm²Ion implantation is performed with an acceleration energy of 500 to 1000 keV to form a p-type impurity layer 52 above the low-concentration p-type impurity layer 62a and at a position facing the low-concentration p-type impurity layer 62a. The dose amount in ion implantation when forming the p-type impurity layer 52 is larger than, for example, the dose amount in ion implantation when forming the low-concentration p-type impurity layers 62a and 62b.

The manufacturing process that follows is the same as in the case of the solid-state image sensor according to the first embodiment described with reference to FIG. In this way, the solid-state image sensor according to the second embodiment can be manufactured.

Impurities are added to the n-type semiconductor substrate 50 to form the overflow barrier region 51 or all or part of the low-concentration p-type impurity layers 62a and 62b, and then an epi layer is formed on the surface of the n-type semiconductor substrate, and then the epi layer is formed. By continuing the manufacturing process of, it becomes possible to implant ions at the time of forming the overflow barrier region 51 or the low-concentration p-type impurity layers 62a and 62b with low acceleration energy.

In manufacturing the solid-state imaging device according to the first embodiment in which the p-type impurity layer and the low-concentration p-type impurity layer 62 constituting the overflow barrier region 51 each have a single-layer structure, for example, the overflow barrier region After forming 51, a low-concentration p-type impurity layer 62 is formed near the surface of the n-type semiconductor substrate 50, and then an epi layer is formed, and the vertical transfer channel 53, the charge storage region 55, etc. are formed in the epi layer. Other components may be formed.

Further, the epi layer may be formed a plurality of times. This will be described by taking as an example the method for manufacturing a solid-state image sensor according to the second embodiment.

5 (A) to 5 (E) are schematic cross-sectional views showing another example of the method for manufacturing the solid-state image sensor according to the second embodiment.

See Figure 5 (A). For example, an n-type semiconductor substrate 50, which is a silicon substrate, is prepared, and p-type impurities such as boron are ion-implanted from the surface thereof to form a p-type impurity layer and p.^-An overflow barrier region 51 composed of a type impurity layer is formed. Boron ion implantation is performed twice. For example, the first dose is 2 x 10¹¹~4×10¹¹/cm², Acceleration energy 1.5 ~ 2.5MeV, second dose amount 1 × 10¹¹~2×10¹¹/cm², Ion implantation with acceleration energy 1-2 MeV.

Next, using the photoresist pattern as a mask, p-type impurities such as boron are added in a dose amount of 1 × 10.¹¹~2×10¹¹/cm²Ion implantation is performed with an acceleration energy of 500 to 1500 keV to form a low-concentration p-type impurity layer 62b above the overflow barrier region 51. The low-concentration p-type impurity layer 62b is formed near the surface of the semiconductor substrate 50 in FIG. 5A, for example.

See Figure 5 (B). By epitaxial growth, an epi layer 70a having the same impurity concentration as the n-type semiconductor substrate 50 is formed on the surface of the n-type semiconductor substrate 50 shown in FIG. 5 (A) to, for example, a thickness of 2 μm.

See Figure 5 (C). A photoresist pattern 65 is formed to form a mask, and p-type impurities such as boron are added from the surface of the epi layer 70a to a dose amount of 1 × 10.¹¹~2×10¹¹/cm²Ion implantation is performed with an acceleration energy of 10 to 500 keV to form a low-concentration p-type impurity layer 62a above the low-concentration p-type impurity layer 62b. The low-concentration p-type impurity layer 62a is formed near the surface of the epi layer 70a, for example.

See Figure 5 (D). FIG. 5 (D) is a diagram corresponding to FIG. 4 (B). By epitaxial growth, the epi layer 70b having the same impurity concentration as the n-type semiconductor substrate 50 (epi layer 70a) is formed on the surface of the n-type semiconductor substrate 50 (epi layer 70a surface) shown in FIG. 5 (C), for example, to a thickness of 2 μm. Form.

See Figure 5 (E). FIG. 5 (E) is the same as FIG. The manufacturing process following the formation of the epi layer 70b is the same as that described with reference to FIG. 4 (C). It is also possible to manufacture the solid-state image sensor according to the second embodiment by forming the epi layer a plurality of times in this way.

By forming the epi layer multiple times, ion implantation during the formation of the overflow barrier region 51 or the low-concentration p-type impurity layers 62a and 62b can be performed with lower acceleration energy than when the epi layer is formed only once. It can be carried out.

Hereinafter, the effects of the solid-state image sensor according to the first and second examples will be considered.

6 (A) to 6 (C) are potential diagrams along line 6A-6A of the cross section of the solid-state image sensor according to the conventional example shown in FIG. 9 (C), and solid-state imaging according to the first embodiment shown in FIG. It is a potential diagram along the 6B-6B line of the element cross section, and is a potential diagram along the 6C-6C line of the solid-state image sensor cross section according to the second embodiment shown in FIG. Each figure is a result based on a simulation.

In each figure, the horizontal axis indicates the depth from the substrate surface in the unit "μm", and the vertical axis indicates the potential in the unit "V".

In all the potential diagrams of FIGS. 6 (A) to 6 (C), the potential on the substrate surface shows -0.472V. In addition, the maximum value is about 1.75V at a depth of about 0.6 μm. This indicates that the peak position of the n-type impurity concentration in the charge storage region is at a depth of about 0.6 μm from the surface of the semiconductor substrate.

The minimum value of the potential is about 0.2V in all potential maps, but the depth at which the minimum value is given differs in each potential map. In the case of the conventional example shown in FIG. 6 (A), the minimum value is taken at a depth of about 2.5 μm. In the case of the first embodiment shown in FIG. 6 (B), the depth is minimal at a depth of about 3.5 μm, and in the case of the second embodiment shown in FIG. 6 (C), the depth is minimized at a depth of about 4.4 μm. It is taking a value. This is because the peak position of the p-type impurity concentration in the overflow barrier region is at a depth of about 2.5 μm from the surface of the semiconductor substrate in the case of the conventional example shown in FIG. 6 (A), and this is shown in FIG. 6 (B). In the case of the first embodiment shown in, it is at a depth of about 3.5 μm, and in the case of the second embodiment shown in FIG. 6 (C), it is at a depth of about 4.4 μm. There is.

The effective depletion layer of the photoelectric conversion element is formed deep in the substrate in the order of the second embodiment, the first embodiment, and the conventional example shown in FIG. 9 (C).

7 (A) to 7 (C) are equipotential bonding diagrams in the cross section of the solid-state image sensor according to the conventional example shown in FIG. 9 (C), and FIGS. 7 (A) to 7 (C) in the cross section of the solid-state image sensor according to the first embodiment shown in FIG. It is an equipotential diagram and the equipotential diagram in the cross section of the solid-state image sensor according to the second embodiment shown in FIG. Each figure is a result based on a simulation.

In each equipotential diagram, the horizontal axis indicates the position in the in-plane direction (horizontal direction in each sectional view) in each sectional view (FIGS. 9 (C), 2 and 3) and the distance from the reference point (each sectional view). In the figure, the distance to the right is indicated by the unit "μm", and the vertical axis indicates the depth from the substrate surface in the unit "μm".

The portion where the closed curves are concentrated in a ring shape in the upper center of each figure (near the surface of the substrate) is the location of the charge storage region. The blackish portion on the upper left and right sides of each figure (near the surface of the substrate) is the position where the vertical transfer channel exists.

The depth that gives the minimum potential value (the peak position of the p-type impurity region in the overflo barrier region) is about 2.5 μm from the substrate surface in FIG. 7 (A) and about 3.5 μm in FIG. 7 (B). At 7 (C), it is about 4.4 μm, and an effective depletion layer is formed above these.

In both the first and second examples, the distribution of equipotential surfaces below the charge storage region is distributed to a deep position near the overflow barrier region. From this, it can be seen that the signal charge photoelectrically converted at a deep position near the overflow barrier region is also collected in the charge storage region. Therefore, it is effective in suppressing a decrease in sensitivity to long-wavelength light.

Further, in both the first and second embodiments, it can be seen that the carrier confinement effect is generated in the lateral direction from the lower side of the charge storage region as it crosses the equipotential surface toward the left and right. Therefore, it is effective in suppressing inter-pixel blooming. This effect is more remarkable in the solid-state image sensor according to the second embodiment.

As a result of repeated simulations by the inventors of the present application, when the peak position of the p-type impurity concentration in the overflow barrier region 51 is at a position deeper than the surface of the semiconductor substrate by 3 μm or more, the sensitivity to long-wavelength light decreases and inter-pixel blooming occurs. It was found that a solid-state image sensor with sufficient effect for suppression can be obtained.

Although the present invention has been described above with reference to Examples, the present invention is not limited thereto. For example, it is possible to invert the n-type and the p-type. It will be obvious to those skilled in the art that various other changes, improvements and combinations are possible.

The above-mentioned solid-state image sensor can be used for all digital cameras, for example, devices having a digital camera function such as a mobile phone.

<figref num="1">(A) is a block diagram showing a main part of a solid-state image sensor incorporating a solid-state image sensor, and (B) and (C) are schematic plan views showing a configuration of a solid-state image sensor.</figref><figref num="2">It is a schematic cross-sectional view which shows the pixel arrangement part of the solid-state image sensor according to 1st Example.</figref><figref num="3">It is a schematic cross-sectional view which shows the pixel arrangement part of the solid-state image sensor according to 2nd Example.</figref><figref num="4">(A) to (C) are schematic cross-sectional views showing an example of a method for manufacturing a solid-state image sensor according to the second embodiment.</figref><figref num="5">(A) to (E) are schematic cross-sectional views showing another example of the method for manufacturing the solid-state image sensor according to the second embodiment.</figref><figref num="6">(A) to (C) are potential diagrams along line 6A-6A of the cross section of the solid-state image sensor according to the conventional example shown in FIG. 9 (C), and the cross section of the solid-state image sensor according to the first embodiment shown in FIG. It is a potential diagram along the 6B-6B line of No. 6B-6B, and a potential diagram along the 6C-6C line of the cross section of the solid-state image sensor according to the second embodiment shown in FIG.</figref><figref num="7">(A) to (C) are equipotential diagrams in the cross section of the solid-state image sensor according to the conventional example shown in FIG. 9 (C) and equipotential positions in the cross section of the solid-state image sensor according to the first embodiment shown in FIG. 2, respectively. It is an equipotential diagram in the cross section of the solid-state image sensor according to the second embodiment shown in the figure and FIG.</figref><figref num="8">It is a schematic plan view which shows the pixel arrangement part of a solid-state image sensor.</figref><figref num="9">(A) to (C) are schematic cross-sectional views showing the pixel arrangement portion of the conventional example of the solid-state image sensor, respectively.</figref><figref num="10">(A) to (E) are schematic cross-sectional views showing a method of manufacturing a solid-state image sensor according to the first embodiment.</figref>

Code description

50 n type semiconductor substrate 51 Overflo barrier area 52 p-type impurity layer 53 Vertical transfer channel 54 Read gate 55 Charge storage area 56 Embedded area 57 Element separation area 58 Vertical transfer electrode 58a Layer 1 Vertical Transfer Electrode 58b Layer 2 vertical transfer electrode 59 Light-shielding film 59a opening 60 Photoelectric conversion element 61 Electrodes 62, 62a, 62b Low concentration p-type impurity layer 65 photoresist pattern 70, 70a, 70b epi layer 81 Solid-state image sensor 82 Drive signal generator 83 Analog pre-processing device 84 Digital signal processor 85 Timing Generator 91 Pixel array 92 Photosensitive part 94 Vertical CCD section 96 Horizontal CCD section 97 Amplifier circuit section 98 Insulation film 99 Silicon oxide film