Integrated circuit for monitoring battery cell
5 claims: 2 independent, 3 dependent
- 1電気的に直列に接続され、それぞれ、電気的に直列に接続された複数の電池セルを有する複数の単位電池セルと、 前記複数の単位電池セルのそれぞれに対応して設けられ、対応する単位電池セルが有する複数の電池セルのそれぞれの端子に電気的に接続されて、対応する単位電池セルが有する複数の電池セルを監視する複数の集積回路と、を有し、 前記複数の集積回路は、それぞれ、 High又はLowレベルの1ビット信号を入力するための第1信号入力端子と、 High又はLowレベルの1ビット信号を出力するための第1信号出力端子と、 コマンド信号を入力するための第2信号入力端子と、 コマンド信号を出力するための第2信号出力端子と、 対応する単位電池セルが有する複数の電池セルに過充放電があるか否かを検出するための検出手段と、 前記第1信号入力端子に入力された1ビット信号に基づいて、前記第1信号出力端子から出力される1ビット信号を発生する通信回路と、を有しており、 前記複数の集積回路間には、 第1の集積回路の第1信号入力端子に入力された信号に基づいて信号が前記第1の集積回路の第1信号出力端子から出力されて第2の集積回路の第1信号入力端子に入力され、というように、前記複数の集積回路に前記1ビット信号を直列に伝送する第1信号伝送路と、 第1の集積回路の第2信号入力端子に入力された信号に基づいて信号が前記第1の集積回路の第2信号出力端子から出力されて第2の集積回路の第2信号入力端子に入力され、というように、前記複数の集積回路にコマンド信号を直列に伝送する第2信号伝送路と、が構成されている、 ことを特徴とする電池システム。
- 2請求項1に記載の電池システムにおいて、さらに、 前記複数の集積回路に対して信号を出力する制御装置と、 前記制御装置から出力された1ビット信号を受ける第1の集積回路の第1信号入力端子と前記制御装置との間に設けられた第1絶縁手段と、 前記制御装置から出力されたコマンド信号を受ける第1の集積回路の第2信号入力端子と前記制御装置との間に設けられた第2絶縁手段と、を有し、 前記第1信号伝送路は、前記第1絶縁手段によって電気的に絶縁され、前記制御装置から出力された前記1ビット信号を、前記第1絶縁手段を介して前記第1の集積回路の第1入力端子に伝送し、 前記第2信号伝送路は、前記第2絶縁手段によって電気的に絶縁され、前記制御装置から出力された前記コマンド信号を、前記第2絶縁手段を介して前記第1の集積回路の第2入力端子に伝送する、 ことを特徴とする電池システム。
- 3請求項2に記載の電池システムにおいて、 前記制御装置は、前記第1信号伝送路の状態をテストするための1ビット信号を前記第1絶縁手段を介して第1の集積回路の第1信号入力端子に出力し、前記1ビット信号が前記第1信号伝送路を介して前記制御回路に戻されることにより、前記第1信号伝送路の状態をテストする、ことを特徴とする電池システム。
- 4電気的に直列に接続された複数の電池セルを有すると共に、電気的に直列に接続された複数の単位電池セルと、 前記複数の単位電池セルのそれぞれに対応して設けられ、対応する単位電池セルが有する複数の電池セルのそれぞれの端子電圧を検出するために用いられる複数の電池セル制御用集積回路と、 前記複数の電池セル制御用集積回路と対をなし、対をなす電池セル制御用集積回路が接続される複数の電池セルに電気的に接続されて、対をなす電池セル制御用集積回路が接続される複数の電池セルを監視するために用いられる複数の電池セル監視用集積回路と、を有し、 前記複数の電池セル監視用集積回路は、それぞれ、 High又はLowレベルの1ビット信号を入力するための第1信号入力端子と、 High又はLowレベルの1ビット信号を出力するための第1信号出力端子と、 コマンド信号を入力するための第2信号入力端子と、 コマンド信号を出力するための第2信号出力端子と、 対応する単位電池セルが有する複数の電池セルに過充放電があるか否かを検出するための検出手段と、 前記第1信号入力端子に入力された1ビット信号に基づいて、前記第1信号出力端子から出力される1ビット信号を発生する通信回路と、を有しており、 前記複数の電池セル監視用集積回路間には、 第1の電池セル監視用集積回路の第1信号入力端子に入力された信号に基づいて信号が前記第1の電池セル監視用集積回路の第1信号出力端子から出力されて第2の電池セル監視用集積回路の第1信号入力端子に入力され、というように、前記複数の電池セル監視用集積回路に前記1ビット信号を直列に伝送する第1信号伝送路と、 前記第1の電池セル監視用集積回路の第2信号入力端子に入力された信号に基づいて信号が前記第1の電池セル監視用集積回路の第2信号出力端子から出力されて第2の集積回路の第2信号入力端子に入力され、というように、前記複数の電池セル監視用集積回路にコマンド信号を直列に伝送する第2信号伝送路と、が構成されている、 ことを特徴とする電池システム。
- 5請求項4に記載の電池システムにおいて、さらに、 前記複数の電池セル監視用集積回路に対して信号を出力する制御装置と、 前記制御装置から出力された1ビット信号を受ける第1の電池セル監視用集積回路の第1信号入力端子と前記制御装置との間に設けられた第1絶縁手段と、 前記制御装置から出力された通信コマンドを受ける第1の電池セル監視用集積回路の第2信号入力端子と前記制御装置との間に設けられた第2絶縁手段と、を有し、 前記第1信号伝送路は、前記第1絶縁手段によって電気的に絶縁され、前記制御装置から出力された前記1ビット信号を、前記第1絶縁手段を介して前記第1の電池セル監視用集積回路の第1入力端子に伝送し、 前記第2信号伝送路は、前記第2絶縁手段によって電気的に絶縁され、前記制御装置から出力された前記コマンド信号を、前記第2絶縁手段を介して前記第1の電池セル監視用集積回路の第2入力端子に伝送する、 ことを特徴とする電池システム。
Independent claims5
104 paragraphs, as filed
The present invention relates to a secondary battery (lithium battery) for an in-vehicle or power source, and particularly a secondary battery (lithium). Manage the status of the battery)<u style="single">battery</u>Regarding the system.
In order to improve the accuracy of voltage detection, the number of insulating means is reduced to solve the problem that the cost of the insulating means provided by each of the plurality of lower control devices is high, and the cost is reduced. Has been proposed (see, for example, Patent Document 1). This Patent Document 1 describes noise, etc. The aim is to reduce the effects of disturbances, improve reliability, and improve the accuracy of voltage detection.
<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2003-70179 (Pages 3-4, Fig. 1)</text></patcit>
<p> The conventional power storage device is provided corresponding to each of a plurality of power storage modules in which a plurality of power storage modules connected in series are further connected in series, and a plurality of power storage modules constituting the power storage module. In a power storage device having a plurality of lower control devices and a higher control device for controlling a plurality of lower control devices, the lower control device is located at the input terminal and the lowest potential of the lower control device located at the highest potential among the plurality of lower control devices. With the output terminal of the lower controller , An insulating means or potential conversion means for connecting the upper control device, and a cutoff provided between the output terminal of the lower control device and the storage battery in the storage battery on the low potential side to block the discharge current of the storage battery in the storage module. It is configured by providing an element and connecting terminals related to signal input / output between a plurality of lower control devices in an electrically non-insulated state.</p><p> This conventional power storage device is not satisfactory in terms of high reliability.</p><p> An object of the present invention is that high reliability can be obtained.<u style="single">battery</u>To provide the system.</p>
<p> The invention according to claim 1 of the present application<u style="single">Battery system</u>Is<u style="single">A plurality of unit battery cells electrically connected in series and each having a plurality of battery cells electrically connected in series, and a unit battery cell provided corresponding to each of the plurality of unit battery cells and corresponding to each other. It has a plurality of integrated circuits that are electrically connected to the respective terminals of the plurality of battery cells possessed by the battery and monitor the plurality of battery cells possessed by the corresponding unit battery cell.</u></p><p><u style="single">The plurality of integrated circuits have a first signal input terminal for inputting a high or low level 1-bit signal and a first signal output terminal for outputting a high or low level 1-bit signal, respectively. Detects whether the second signal input terminal for inputting a command signal, the second signal output terminal for outputting a command signal, and the plurality of battery cells of the corresponding unit battery cells are overcharged or discharged. It has a detection means for performing the above and a communication circuit for generating a 1-bit signal output from the 1st signal output terminal based on the 1-bit signal input to the 1st signal input terminal.</u></p><p><u style="single">Further, between the plurality of integrated circuits, a signal is output from the first signal output terminal of the first integrated circuit based on the signal input to the first signal input terminal of the first integrated circuit, and the second integrated circuit is used. It was input to the first signal input terminal of the circuit, and so on, to the first signal transmission line that transmits 1-bit signals in series to multiple integrated circuits, and to the second signal input terminal of the first integrated circuit. Based on the signal, the signal is output from the second signal output terminal of the first integrated circuit and input to the second signal input terminal of the second integrated circuit, and so on, the command signal is connected in series to multiple integrated circuits. It is characterized in that a second signal transmission line for transmission is configured.</u></p><p> Claims of the present application<u style="single">2</u>The invention described in<u style="single">In the battery system according to claim 1, further, a control device that outputs signals to a plurality of integrated circuits, and a first signal input terminal of the first integrated circuit that receives a 1-bit signal output from the control device. The first insulating means provided between the control device and the second insulating means provided between the second signal input terminal of the first integrated circuit that receives the command signal output from the control device and the control device. The first signal transmission line is electrically insulated by the first insulating means, and the 1-bit signal output from the control device is transmitted to the first integrated circuit of the first integrated circuit via the first insulating means. It is transmitted to the input terminal, the second signal transmission line is electrically insulated by the second insulating means, and the command signal output from the control device is sent to the second input of the first integrated circuit via the second insulating means. It is characterized by transmitting to a terminal.</u></p><p> Claims of the present application<u style="single">3</u>The invention described in<u style="single">In the battery system according to claim 2, the control device outputs a 1-bit signal for testing the state of the first signal transmission line to the first signal input terminal of the first integrated circuit via the first insulating means. A battery system characterized in that a 1-bit signal is returned to a control circuit via a first signal transmission line to test the state of the first signal transmission line.</u></p><p> Claims of the present application<u style="single">4</u>The invention described in<u style="single">Battery system</u>Is<u style="single">It has a plurality of battery cells electrically connected in series, and is provided corresponding to each of a plurality of unit battery cells electrically connected in series and a plurality of unit battery cells, and corresponds to the unit battery cell. A battery cell control integrated circuit that is paired with a plurality of battery cell control integrated circuits used to detect the terminal voltage of each of the plurality of battery cells possessed by the battery and a plurality of battery cell control integrated circuits. A plurality of battery cell monitoring integrated circuits used for monitoring a plurality of battery cells to which a pair of battery cell control integrated circuits are electrically connected to a plurality of battery cells to which the battery cells are connected. The plurality of battery cell monitoring integrated circuits have a first signal input terminal for inputting a High or Low level 1-bit signal and a first signal input terminal for outputting a High or Low level 1-bit signal, respectively. Overcharge / discharge occurs in one signal output terminal, a second signal input terminal for inputting a command signal, a second signal output terminal for outputting a command signal, and a plurality of battery cells of the corresponding unit battery cells. It has a detection means for detecting the presence or absence, and a communication circuit that generates a 1-bit signal output from the 1st signal output terminal based on the 1-bit signal input to the 1st signal input terminal. A signal is input between the plurality of battery cell monitoring integrated circuits based on the signal input to the first signal input terminal of the first battery cell monitoring integrated circuit. 1-bit signal is transmitted in series to a plurality of battery cell monitoring integrated circuits, such as being output from the first signal output terminal of the above and input to the first signal input terminal of the second battery cell monitoring integrated circuit. A signal is output from the second signal output terminal of the first battery cell monitoring integrated circuit based on the signal input to the first signal transmission line and the second signal input terminal of the first battery cell monitoring integrated circuit. It is input to the second signal input terminal of the second battery cell monitoring integrated circuit, and so on, and a second signal transmission line that transmits command signals in series to a plurality of battery cell monitoring integrated circuits is configured. It is characterized by being.</u></p><p> Claims of the present application<u style="single">5</u>The invention described in<u style="single">In the battery system according to claim 4, further, a control device that outputs a signal to a plurality of battery cell monitoring integrated circuits and a first battery cell monitoring integrated device that receives a 1-bit signal output from the control device. Control with the first insulating means provided between the first signal input terminal of the circuit and the control device, and the second signal input terminal of the integrated circuit for monitoring the first battery cell that receives the communication command output from the control device. It has a second insulating means provided between the device and the first signal transmission line, which is electrically insulated by the first insulating means, and the 1-bit signal output from the control device is first insulated. The command signal output from the control device is transmitted to the first input terminal of the integrated circuit for monitoring the first battery cell via the means, and the second signal transmission line is electrically insulated by the second insulating means. It is characterized in that it is transmitted to the second input terminal of the integrated circuit for monitoring the first battery cell via the second insulating means.</u></p>
<p> According to the present invention, high reliability can be obtained.</p>
The present invention is realized by collecting a large number of battery cells connected in series into a plurality of units, managing the battery status and batteries, detecting an abnormality in an IC chip circuit or a battery cell, and taking appropriate measures. ..
Hereinafter, of the present invention<u style="single">battery</u>An embodiment of the system will be described in detail.
FIG. 1 shows the present invention.<u style="single">An example of a battery system is shown,</u>The configuration of the multi-series battery control system is shown.
In FIG. 1, the battery system 1 has a pair of control ICs 3 (control IC chip 3A and cells) in a unit battery cell 2 in which four battery cells 2A, 2B, 2C, and 2D are connected in series to form one unit. A monitoring IC chip 3B) is provided accordingly. This pair of control ICs 3 consists of two ICs, one is a control IC chip 3A equipped with a control circuit, and the other is a cell monitoring IC chip 3B that monitors the unit battery cell 2. Is. The terminals of the battery cells 2A, 2B, 2C, and 2D of the unit battery cell 2 are connected to one end of the control IC chip 3A. Further, the main controller 5 is connected to the other end of the control IC chip 3A via the high-speed insulating means 4. Further, one end of the cell monitoring IC chip 3B is connected to the main controller 5 via the insulating means 6 and 7, and the other end of the cell monitoring IC chip 3B is connected to the other end. , Each terminal of the battery cell 2A, 2B, 2C, 2D of the unit battery cell 2 is connected.
This pair of control ICs 3 is provided for each unit battery cell composed of four battery cells. In FIG. 1, three pairs of control ICs are shown, but a large number of pairs of control ICs are provided between each pair of control ICs 3, and this pair of control ICs is a lithium battery. All battery cells are provided in units of four battery cells.
FIG. 2 shows the detailed circuit of the control IC chip 3A. Here, an example of one control IC chip 3A is shown, but the control IC chip 4A constituting the multi-series battery control system in the present invention, ... Control IC chip 5A (in the drawing, the control IC chip 5A) 3A, control IC chip 4A, control IC chip 5A, but N control IC chips) have the same configuration.
In FIG. 2, the (+) terminal of the battery cell 2A of the unit battery cell 2 is connected to the control means 20 via the V1 input terminal. The selection means 20 is composed of, for example, a multiplexer. The selection means 20 is provided with switches 20A, 20B, 20C, 20D, 20E. Then, one terminal of the switch 20A is connected to the V1 input terminal, and the other terminal of the switch 20A is connected to the power supply 21 and the voltage detecting means 22. Further, at the (-) terminal of the battery cell 2A of the unit battery cell 2, one terminal of the switch 20B of the selection means 20 is connected to the (+) terminal of the battery cell 2B via the V2 input terminal, and the switch 20B is connected. The other terminal of is connected to the voltage detecting means 22.
Also, at the (-) terminal of the battery cell 2B of the unit battery cell 2, the (+) terminal of the battery cell 2C , One terminal of the switch 20C of the selection means 20 is connected via the V3 input terminal, and the other terminal of the switch 20C is connected to the voltage detecting means 22. Further, at the (-) terminal of the battery cell 2C of the unit battery cell 2, one terminal of the switch 20D of the selection means 20 is connected to the (+) terminal of the battery cell 2D via the V4 input terminal, and the switch 20D is connected. The other terminal of , Connected to the voltage detecting means 22.
Then, one terminal of the switch 20E of the selection means 20 is connected to the (-) terminal of the battery cell 2D of the unit battery cell 2 via the GND (ground) terminal, and the other terminal of the switch 20E detects the voltage. It is connected to means 22.
The power supply 21 is composed of a DC / DC converter or the like, converts the power of the unit battery cell 2 into a predetermined voltage and supplies it to the outside from the VDD terminal, or supplies the drive power supply of each circuit in the control IC chip 3A. It was created by the unit battery cell 2.
Further, the voltage detecting means 22 detects the voltage between the terminals of the battery cells 2A, 2B, 2C, and 2D of the unit battery cell 2, and the detected voltage between the terminals of the battery cells 2A, 2B, 2C, and 2D is , Is output to the calculation means 23. The calculation means 23 is provided with a power management means 24, a storage means 25, and a correction means 26. The power management means 24 controls ON / OFF of the power supply 21.
Further, the storage means 25 stores the voltage between each terminal of the battery cells 2A, 2B, 2C, 2D of the unit battery cell 2 detected by the voltage detection means 22 for each battery cell 2A, 2B, 2C, 2D. It is a thing. Specifically, the storage means 25 is composed of a shift register. further The correction means 26 is for correcting the voltage between the terminals of the battery cells 2A, 2B, 2C, and 2D of the unit battery cell 2 detected by the voltage detection means 22.
A communication means 27 is connected to the calculation means 23. The communication means 27 receives a communication command (on / off signals such as 8bit, 10bit, 12bit, etc.) sent from the main controller 5 from the RX terminal via the high-speed isolation means 4. That is, the main controller 5 is a communication command that reads the voltage between each battery cell 2A, 2B, 2C, 2D, or adjusts the voltage between each battery cell 2A, 2B, 2C, 2D to a specific unit battery cell 2. Sends a command to operate the specific control IC chip 3A, such as a communication command to be executed, to the high-speed insulation means 4. .. In this high-speed insulation means 4, the communication command input from the main controller 5 is not directly transmitted, but is transmitted to the communication means 27 via insulation.
The high-speed insulating means 4 is a transformer type and is as small as an IC. Since it is a transformer type, the high-speed insulating means 4 requires a power source, and is configured to be driven by supplying power from the cell monitoring IC chip 3B.
In the communication means 27, the signal corresponding to the communication command sent from the main controller 5 and transmitted via the high-speed isolation means 4 is sent by the voltage of eight battery cells in which two unit battery cells 2 are connected in series. (On / off signals such as 10bit and 12bit) are created and output to the calculation means 23. In the uppermost unit battery cell 2, the maximum value is the added voltage for eight battery cells, and the minimum value is the added voltage for four battery cells. Therefore, the communication command transmitted from the communication means 27 can be detected by setting the threshold value to half the voltage of the added voltage of eight battery cells and the voltage of four battery cells.
However, in the unit battery cell 2 on the downstream side of the highest unit battery cell 2, the voltage of the highest unit battery cell 2 is divided (for example, 1/2), so that the maximum value is the battery cell 4. The additional voltage for one battery (because it is divided into 1/2), and the minimum value is the additional voltage for two battery cells (because it is divided into 1/2). That is, the communication command transmitted from the communication means 27 has a threshold value of half that of the added voltage of four battery cells and the added voltage of two battery cells, similar to the unit battery cell 2 having the highest threshold value. If it is set to voltage, it cannot be detected because the minimum value is the added voltage for two battery cells. Therefore, in the unit battery cell 2 on the downstream side of the uppermost unit battery cell 2, the threshold voltage for detecting the communication command is the maximum value (additional voltage for four battery cells) and the minimum value (battery cell 2). Detection is possible if the voltage is set to half the voltage (additional voltage for each battery).
About the detection method of the communication signal in each of these control IC chips 3A, 4A, ... 5A This will be described with reference to FIG.
In FIG. 10, the control IC chip 3A or less, the control IC chip 4A, ... The communication signal is determined by the chip 5A by the control IC chip 3A and the control IC chip 4A, and the control IC chip 4A and the control IC chip 5A. The control IC chip 3A in FIG. 10 is a signal in which the total voltage value obtained by adding the voltages of the battery cells 2A, 2B, 2C, and 2D of the unit battery cell 2 is set to Hi and the GND (ground) level is set to low. The VCC3 voltage level signal (the signal that becomes Hi / Low at the VCC3 voltage level) is input to the RX terminal of the control IC chip 3A. The VCC3 voltage level signal input from the RX terminal of the control IC chip 3A is output from the TX terminal of the control IC chip 3A, but this voltage is divided by a resistor and the voltage of this VCC3 is divided. A voltage level signal (a signal that becomes Hi / Low at a voltage level under voltage division of VCC3, for example, 1/2) is input to the RX terminal of the control IC chip 4A. That is, the communication signal becomes a signal that repeats Hi / Low at a voltage level under voltage division of VCC3, for example, 1/2, and is input to the RX terminal of the control IC chip 4A. Therefore, when trying to determine the signal output from the TX terminal of the control IC chip 3A with the same threshold as the control IC chip 3A based on each voltage of the unit battery cell 2 managed by the control IC chip 4A, the control IC chip 3A Since the Low level of the signal output from the TX terminal of is 1/2 of the total voltage applied to the control IC chip 4A, it cannot be determined.
That is, in FIG. 10, the voltage of the RX terminal of the control IC chip 3A changes from the voltage of VCC3 to GND3. In addition, the voltage of the RX terminal of the control IC chip 4A is divided by a resistor in half the voltage output from the TX terminal of the control IC chip 3A, so (VCC3 to G). The voltage of ND4) × R / 2R changes. The voltage of the TX terminal of the control IC chip 4A changes from VCC4 to GND4. Similarly, the voltage at the RX terminal of the control IC chip 5A is divided by a resistor in half the voltage output from the TX terminal of the control IC chip 4A. The voltage of VCC4 ~ GND5) × R / 2R changes.
Therefore, the uppermost control IC chip 3A changes the voltage of VCC and GND for both input and output (RX, TX). Therefore, the threshold value for determining Hi / Low of the input (RX) of the uppermost control IC chip 3A may be 1 / 2VCC. The output (TX) of the control IC chip (4A, ... 5A) other than this top-level control IC chip 3A recommends the voltage of VCC and 1 / 2VCC. Move. Therefore, the Hi / Low of the input (RX) of the control IC chip 4A, ... 5A If the threshold value to be judged is not 3/4 VCC, it will not work well.
Further, the (+) terminal of the battery cell 2A of the unit battery cell 2 is connected to the B1 terminal via the resistor R1. One terminal of the SW state detecting means 28A is connected to this B1 terminal, and one terminal of the SW state detecting means 28A is connected to the other terminal of the SW state detecting means 28A via the V2 terminal of the battery cell 2A of the unit battery cell 2 (-). ) The terminal is connected. A balancing switch 29A connected in series with the resistor R1 is inserted and connected between both terminals of the battery cell 2A of the unit battery cell 2.
Further, the (+) terminal of the battery cell 2B of the unit battery cell 2 is connected to the B2 terminal via the resistor R2. One terminal of the SW state detecting means 28B is connected to this B2 terminal, and one terminal of the SW state detecting means 28B is connected to the other terminal of the SW state detecting means 28B via the V3 terminal of the battery cell 2B of the unit battery cell 2 (-). ) The terminal is connected. A balancing switch 29B connected in series with the resistor R2 is inserted and connected between both terminals of the battery cell 2B of the unit battery cell 2.
Further, the (+) terminal of the battery cell 2C of the unit battery cell 2 is connected to the B3 terminal via the resistor R3. One terminal of the SW state detecting means 28C is connected to this B3 terminal, and one terminal of the SW state detecting means 28C is connected to the other terminal of the SW state detecting means 28C via the V4 terminal of the battery cell 2C of the unit battery cell 2 (-). ) The terminal is connected. A balancing switch 29C connected in series with the resistor R3 is inserted and connected between both terminals of the battery cell 2C of the unit battery cell 2.
Further, the (+) terminal of the battery cell 2D of the unit battery cell 2 is connected to the B4 terminal via the resistor R4. One terminal of the SW state detecting means 28D is connected to this B4 terminal, and the (-) terminal of the battery cell 2D of the unit battery cell 2 is connected to the other terminal of the SW state detecting means 28D. ing. A balancing switch 29D connected in series with the resistor R4 is inserted and connected between both terminals of the battery cell 2D of the unit battery cell 2.
The SW state detecting means 28A, 28B, 28C, and 28D constantly detect the voltage across the balancing switches 29A to 29D, respectively. In addition, abnormalities of balancing switches 29A, 29B, 29C, and 29D have been detected. That is, the voltage is battery cells 2A, 2B, 2C even though the balancing switches 29A, 29B, 29C, 29D are ON. It is possible to detect that the balancing switches 29A, 29B, 29C, and 29D are abnormal when the terminal voltage of 2D is output. The SW state detecting means 28A, 28B, 28C, 28D are voltage detection circuits composed of a differential amplifier or the like.
In addition, the balancing switches 29A, 29B, 29C, 29D discharge the battery cells 2A, 2B, 2C, 2D connected in series that make up the unit battery cell 2, and the four that make up the unit battery cell. It is a switch that short-circuits between battery cells via resistors R1, resistor R2, resistor R3, and resistor R4 in order to match the voltage of each battery cell 2A, 2B, 2C, and 2D. Specifically, it is composed of MOS FETs. Further, the SW state detecting means 28A detects whether or not the balancing switch 29A is operating normally, and the SW state detecting means 28B detects whether or not the balancing switch 29B is operating normally. The SW state detecting means 28C detects whether or not the balancing switch 29C is operating normally, and the SW state detecting means 28D detects whether or not the balancing switch 29D is operating normally. Is. That is, the SW state detecting means 28A to 28D constantly detect the voltage of the balancing switches 29A to 29D, respectively. , When the balancing switches 29A, 29B, 29C, 29D are turned on, the SW state detecting means 28A, 28B, 28C, 28D will detect a voltage close to 0 (zero).
The potential conversion means 30 is connected to the SW state detecting means 28A, 28B, 28C, 28D. The potential conversion means 30 sets the voltage value between each battery cell 2A, 2B, 2C, 2D detected by the SW state detection means 28A, 28B, 28C, 28D to a predetermined potential (potential that can be processed). ) And output to the comparison means 31. That is, since the potential conversion means 30 has different potential levels between the battery cells 2A, 2B, 2C, and 2D, the potential conversion means 30 converts them into potential levels that can be compared together.
Further, the drive signal of the SW drive means 33 is input to the comparison means 31, and the drive signal and each of the SW state detection means 28A, 28B, 28C, 28D detected by the SW state detection means 28A, 28B, 28C, 28D output from the potential conversion means 30. The voltage value between the balancing switches 29A to 29D is compared with the voltage converted to a predetermined potential (processable potential), and it is determined whether or not the balancing switches 29A, 29B, 29C, and 29D are abnormal.
On the other hand, from the main controller 5, the signal that drives the balancing switch 29A via the BS1 terminal, the signal that drives the balancing switch 29B via the BS2 terminal, and the signal that drives the balancing switch 29C via the BS3 terminal are output. The signals for driving the balancing switch 29D via the BS4 terminal are input to the SW drive means 33, respectively. The SW drive means 33 converts the switch signal sent from the main controller 5 into each switch drive signal and outputs the switch signal to the comparison means 31 connected to the SW drive means 33 and the potential conversion means 32. ..
The potential conversion means 32 receives the switch drive signal transmitted from the SW drive means 33 and converts it into a drive voltage signal (specifically, a gate signal) that turns the balancing switches 29A, 29B, 29C, and 29D on and off. It is supplied to each balancing switch 29A, 29B, 29C, 29D (specifically, the gate voltage is supplied).
When an abnormality of the balancing switches 29A, 29B, 29C, 29D is detected in the comparison means 31, which balancing switch 29A, 29B, 29C, 29D is identified by the switch drive signal output from the SW drive means 33. , Is output to the calculation means 23. When an abnormality is detected in the comparison means 31, the arithmetic means 23 identifies the abnormality balancing switch and sends a signal indicating the abnormality from the FFO terminal of the communication means 27 or from the TX terminal of the communication means 27. Send to controller 5.
In FIG. 2, the BS1 to BS4 terminals provided on the SW drive means 33 are used when a signal for turning on the balancing switches 19A to 19D is input from the outside, and when a signal is input from the BS1 to BS4 terminals. , The SW drive means 33 is driven, and the ON signals of the balancing switches 19A to 19D are transmitted from the SW drive means 33 to the potential conversion means 32. The potential conversion means 32 receives the switch drive signal transmitted from the SW drive means 33 and converts it into a drive voltage signal (specifically, a gate signal) that turns on the balancing switches 29A, 29B, 29C, 29D. And supplies to each balancing switch 29A, 29B, 29C, 29D (specifically, supply of gate voltage).
Further, in FIG. 2, 34 is a temperature abnormality detecting means, and this temperature abnormality detecting means 34 detects the temperature of the control IC chip 3A, and checks whether or not the preset temperature has been reached. When the temperature detected by the temperature abnormality detecting means 34 detects a temperature equal to or higher than a preset temperature, a signal is output to the SW driving means 33 and a current is sent to the balancing switches 29A to 29D which are heat generating sources in order to prevent heat generation. Do not perform discharge control by balancing switches 29A, 29B, 29C, 29D so as not to supply.
FIG. 3 shows a specific embodiment of the voltage detecting means 22 shown in FIG.
The voltage detecting means 22 in FIG. 3 is connected to the selecting means 20. The voltage detecting means 22 has a resistor 22R1 connected to the (+) terminal of the battery cells 2A, 2B, 2C, 2D which are switched and connected by the switches 20A, 20B, 20C, 20D, 20E of the selecting means 20. It is provided. One end of the resistor 22R2 and the (-) input terminal of the operational amplifier 22OP1 are connected to the other end of the resistor 22R1. An AC / DC converter 22A is connected to the other end of the resistor 22R2.
On the other hand, a resistor 22R3 connected to the (-) terminal of the battery cells 2A, 2B, 2C, 2D which is switched and connected by the switches 20A, 20B, 20C, 20D, 20E of the selection means 20 is provided. One end of the resistor 22R4 and the (+) input terminal of the operational amplifier 22OP1 are connected to the resistor 22R3. The output terminal of this operational amplifier 22OP1 is connected to the AC / DC converter 22A. The other end of the resistor 22R4 is grounded.
An adding machine 12C is connected to the output terminal of the AC / DC converter 22A via a 10-bit register 22B, and a 16-bit register rolling average 22D is connected to this adding machine 12C.
Since the double integral type is adopted in this way, the noise component of the input voltage can be filtered. Furthermore, by using the 16-bit register rolling average 22D, the resolution can be improved and the detected values can be filtered.
FIG. 4 shows an embodiment of the communication command. This communication command is sent from the main controller 5 and input from the RX terminal of the communication means 27 shown in FIG. This communication command consists of 8 bits as one unit and 5 bytes as one communication command. The first 8 bits of this communication command is a break field indicating that a signal has arrived, the second 8 bits is a synchronous field that is a signal for synchronization, and the third 8 bits is which control IC chip 3A. The 4th 8bit is the data byte indicating the communication content (control content), and the 5th 8bit is the checksum. This 5-byte communication command is a series.
Figure 5 shows the startup sequence (Wake-Up) at system startup. That is, this rise sequence (Wake-Up) is an operation processing flow for activating the control IC chip 3A and the cell monitoring IC chip 3B when the main controller 5 is started.
In FIG. 5, when the main controller 5 shown in FIG. 2 is activated (key switch is turned ON) in step 100, the main controller 5 is initialized in step 110. When the main controller 5 is initialized in this step 110, in step 120, the Wake-Up terminal of the main controller 5 is connected to the RX terminal of the cell monitoring IC chip 3B via the insulating means 6 as shown in FIG. 6 (A). Output the Up signal. The RX terminal of this cell monitoring IC chip 3B is a terminal for Wake-Up of the cell monitoring IC chip 3B, and when a Wake-Up signal is input to the RX terminal of this cell monitoring IC chip 3B. , Cell monitoring IC chip 3B starts up (Wake-Up). This cell monitoring IC When the device 3B starts up, the power VCC supplied from the battery cells 2A, 2B, 2C, and 2D as shown in FIG. 6B is output via the VDD terminal of the cell monitoring IC chip 3B.
In this step 120, when the Wake-Up signal as shown in FIG. 6A is output from the Wake-Up terminal of the main controller 5 to the RX terminal of the cell monitoring IC chip 3B via the insulating means 6, the cell monitoring IC chip 3B Then, in step 140, the power VCC as shown in FIG. 6 (B) is supplied from the VDD pin to the high-speed isolation means 4 (VDD output). This When the power VCC as shown in FIG. 6 (B) is supplied to the high-speed insulating means 40 from the VDD terminal of the cell monitoring IC chip 3B, the high-speed insulating means 4 starts up. When the high-speed insulating means 4 starts up, it becomes possible to output the Wake-Up signal output from the TX terminal of the main controller 5 to the RX terminal of the control IC chip 3A as shown in FIG. 6 (D).
In this way, the cell monitoring IC chip 3B rises when the Wake-Up signal output from the Wake-Up terminal of the main controller 5 via the insulating means 6 is received by the RX terminal in step 120 as shown in FIG. 6 (A). , From the TX terminal of the main controller 5 In step 130, a Wake-Up signal as shown in FIG. 6 (D) for starting up the control IC chip 3A is output to the RX terminal of the control IC chip 3A via the high-speed insulating means 40. In this step 130, a Wake-Up signal as shown in FIG. 6 (D) for starting up the control IC chip 3A is output from the TX terminal of the main controller 5 to the RX terminal of the control IC chip 3A via the high-speed insulation means 4. When received by the RX terminal of the control IC chip 3A, the control IC chip 3A rises (Wake-Up) in step 150.
Further, by the Wake-Up signal as shown in FIG. 6 (A) output from the Wake-Up terminal of the main controller 5 to the RX terminal of the cell monitoring IC chip 3B via the insulating means 6. When the cell monitoring IC chip 3B starts up, the cell monitoring IC chip 3B copies the Wake-Up signal as shown in FIG. 6 (A) and uses the cell monitoring IC as the Wake-Up signal as shown in FIG. 6 (C). Output from the TX terminal of chip 3B to the RX terminal of the next-stage cell monitoring IC chip 4B. This cell monitoring IC chip 4B rises by the Wake-Up signal as shown in FIG. 6 (C) output from the TX terminal of the cell monitoring IC chip 3B, and in the cell monitoring IC chip 4B, the TX of the cell monitoring IC chip 3B Copy the Wake-Up signal as shown in Fig. 6 (C) output from the terminal, and connect the TX terminal of the cell monitoring IC chip 4B to the RX terminal of the cell monitoring IC chip 5B in the final stage in Fig. 6 (E). It is output as a Wake-Up signal as shown in. A plurality of cell monitoring IC chips are provided between the cell monitoring IC chip 4B and the final stage cell monitoring IC chip 5B, but they are omitted in FIG.
On the other hand, the power supplied from the battery cells 2A, 2B, 2C, 2D is output from the VDD terminal of the cell monitoring IC chip 3B to the high-speed insulation means 4, the high-speed insulation means 4 is turned on, and the TX terminal of the main controller 5 is used. A Wake-Up signal as shown in FIG. 6 (D) is output to the RX terminal of the control IC chip 3A via the high-speed insulating means 4. When the Wake-Up signal as shown in FIG. 6 (D) is input to the RX terminal of the control IC chip 3A, the control IC chip 3A starts up. When this control IC chip 3A starts up, the control IC chip 3A copies the Wake-Up signal as shown in Fig. 6 (D) transmitted from the TX terminal of the main controller 5 to the TX terminal of the control IC chip 3A. Then, it is output as a Wake-Up signal as shown in Fig. 6 (F) to the RX terminal of the control IC chip 4A in the next stage.
This control IC chip 4A rises by the Wake-Up signal as shown in FIG. 6 (F) output from the TX terminal of the control IC chip 3A, and is output from the TX terminal of the control IC chip 3A in the control IC chip 4A. Copy the Wake-Up signal as shown in Fig. 6 (F), and transfer the Wake-Up signal from the TX terminal of the control IC chip 4A to the RX terminal of the control IC chip 5A in the final stage as shown in Fig. 6 (I). Output as a signal. A plurality of control IC chips are provided between the control IC chip 4A and the final stage control IC chip 5A, but they are omitted in FIG.
In this way, the control IC chip 3A, the control IC chip 4A, ..., the control IC chip 5A, the cell monitoring IC chip 3B, the cell monitoring IC chip 4B, ... The battery management IC that manages cells 2A to 2N starts up. In addition, each of the control IC chip 3A, control IC chip 4A to 5A, cell monitoring IC chip 3B, and cell monitoring IC chip 4B to 5B are provided with VDD terminals, and the usage of these VDD terminals should be devised. Therefore, it becomes possible to supply electric power to the outside.
After the cell monitoring IC chip 3B is started up in this way, the cell monitoring IC chips 4B and subsequent cell monitoring IC chips are started up by repeating the same operation. The cell monitoring IC chip 5B starts up by receiving the Wake-Up signal as shown in FIG. 6 (E) output from the TX terminal of the cell monitoring IC chip 4B at the RX terminal. When the cell monitoring IC chip 5B starts up by the Wake-Up signal as shown in Fig. 6 (E) output from the TX terminal of the cell monitoring IC chip 4B to the RX terminal of the cell monitoring IC chip 5B, the cell monitoring IC chip In 5B, the Wake-Up signal as shown in FIG. 6 (E) is copied, and the Wake-Up signal as shown in FIG. 6 (G) is transferred from the TX terminal of the cell monitoring IC chip 5B to the ANS terminal of the main controller 5. Output.
When the cell monitoring IC chip 5B starts up, the power VCC shown in FIG. 6 (H) is supplied from the VDD pin to the high-speed insulation means 8 (VDD output). This cell monitoring IC chip 5 When the power VCC as shown in FIG. 6 (H) is supplied to the high-speed insulating means 8 from the VDD terminal of B, the high-speed insulating means 8 starts up. When the high-speed insulating means 8 starts up, the high-speed insulating means 8 turns on, and the TX terminal of the control IC chip 5A and the RX terminal of the main controller 5 can communicate with each other. That is, when the high-speed insulating means 8 is turned on, the Wake-Up signal as shown in FIG. 6 (J) is transmitted from the TX terminal of the control IC chip 5A to the RX terminal of the main controller 5. By receiving the Wake-Up signal as shown in FIG. 6 (J) from the TX terminal of the control IC chip 5A at the RX terminal of the main controller 5, the main controller 5 has the control IC chip 3A, the control IC chip 4A, and so on. Control IC chip 5A and cell Monitoring IC chip 3B, cell monitoring IC chip 4B, ... Cell monitoring IC chip 5B stands Check that the battery management IC that manages the battery cells 2A to 2N has started up normally. Cell monitoring IC chip 3B, cell monitoring IC chip 4B, ... Cell monitoring IC chip 5 Whether or not B is up or not is determined by the fact that the cell monitoring IC chip 5B is up and the high-speed insulation means 8 is turned on, and the Wake-Up signal as shown in Fig. 6 (J) is output from the TX terminal of the control IC chip 5A. It is confirmed by being transmitted to the RX terminal of the main controller 5.
This battery management IC is provided with a high-speed insulating means 4 at the top stage and a high-speed insulating means 8 at the final stage, is insulated, and is not chassis grounded (the power supply is floated from the vehicle body). ).
Figure 7 shows the FF-TEST subroutine. That is, this FF-TEST subroutine is a processing flow for inputting a test signal from the FFI terminal of the cell monitoring IC chip 3B and detecting an abnormality in the circuit of the cell monitoring IC chips 3B to 5B.
In FIG. 7, as shown in FIG. 1, from the FF-TEST terminal of the main controller 5 to the FFI terminal of the communication means of the cell monitoring IC chip 3B shown in FIG. 1 via the insulating means 7 in step 200, High. Send a signal. When the High signal is transmitted to the FFI terminal of the communication means of the cell monitoring IC chip 3B in this step 200, in the cell monitoring IC chip 3B, in step 210, the High signal is directly transmitted from the FFO terminal to the next stage without any processing. Output to the FFI terminal of the cell monitoring IC chip 4B. Similarly, when a High signal is transmitted to the FFI terminal of the communication means of the cell monitoring IC chip 4B, the cell monitoring IC chip 4B sends the High signal as it is from the FFO terminal to the next-stage cell monitoring IC chip without any processing. Output to 5B FFI terminal. Then, when the High signal is transmitted to the FFI terminal of the communication means of the cell monitoring IC chip 5B, the cell monitoring IC chip 5B outputs the High signal from the FFO terminal to the main controller 5 as it is without any processing. When a signal is output from the FFO terminal of the communication means 27, in step 220, the level of the FF port is determined based on the signal transmitted from the FFO terminal to the main controller 5. When the FF port level is determined based on the signal output from the FFO terminal transmitted to the main controller 5 in step 220, the FF port level is high in the main controller 5 in step 230. Judge whether or not.
If the main controller 5 determines in step 230 that the level of the FF port is not High (Low), in step 240, it is determined that somewhere in the circuit is broken or the cell monitoring IC chip itself is abnormal. And end this flow.
Further, when the main controller 5 determines in step 230 that the level of the FF port is High, in step 250, the returned High signal is a signal that can be determined to be normal despite overloading and overdischarging ( You have to see if the High signal) happens to come in. That is, in step 250, a state (abnormality) detection command, which is a command for detecting another abnormality (battery cell abnormality), is transmitted to the RX terminal of the communication means 27 provided in the control IC chip 3A. When this state (abnormality) detection command is transmitted to the RX terminal of the communication means 27 of the main controller 5 and the control IC chip 3A, in step 260, the calculation means 23 of the control IC chip 3A uses data indicating the current state. A certain state (abnormal) data is transmitted from the TX terminal of the communication means 27 of the control IC chip 3A to the main controller 5. When the status (abnormal) data from the TX terminal of the communication means 27 is transmitted to the main controller 5, the main controller 5 confirms the status (abnormality) in step 270, and this communication is performed in step 280. It is determined whether or not the state (abnormal) data transmitted from the TX terminal of the means 27 is a signal with an abnormality. Similarly, the status (abnormality) of the control IC chip 4A and control IC chip 5A ) Is confirmed, and it is determined whether or not the state (abnormal) data transmitted from the TX terminal of the communication means 27 is a signal with an abnormality. If it is determined in step 280 that the state (abnormal) data transmitted from the TX terminal of the communication means 27 is a signal without abnormality, normal processing is performed in step 290, and this flow ends. Further, if it is determined in step 280 that the state (abnormal) data transmitted from the TX terminal of the communication means 27 is a signal with an abnormality, the battery abnormality processing is performed in step 300 and this flow is terminated. ..
Figure 8 shows a balancing subroutine when switching the balancing switches 29A, 29B, 29C, 29D. That is, this balancing subroutine discharges the battery cells 2A, 2B, 2C, 2D connected in series that make up the unit battery cell 2, and the four battery cells 2A, 2B, that make up the unit battery cell 2. This is a processing flow for matching the voltage of each battery cell of 2C and 2D.
In FIG. 8, in step 400, the main controller 5 transmits a voltage reading command for each battery cell, which is a command for reading the voltage data of the battery cells 2A to 2D, to the RX terminal of the communication means 27 shown in FIG. .. When each battery cell voltage read command is transmitted in this step 400, each battery cell voltage read command determines the control content in the calculation means 23 of the control IC chip 3A, and is periodically written and stored in the storage means. The voltage of each battery cell 2A, 2B, 2C, 2D is read out, and in step 410, the voltage data of each battery cell is transmitted from the TX terminal to the main controller 5 in series. When each battery cell voltage data from the control IC chip 3A is received, the main controller 5 sees the minimum value battery cell voltage among the transmitted battery cell voltage data in step 420 and of each battery cell. To calculate the discharge time, calculate the minimum cell voltage value. When the minimum cell voltage value is calculated in step 420, the ON time values of the balancing switches 29A, 29B, 29C, and 29D are calculated in step 430. The ON time of each of the balancing switches 29A, 29B, 29C, and 29D is obtained from the value obtained by subtracting the minimum cell voltage from the voltage value of each battery cell.
In this step 440, a bypass SW control (ON) command for ON-controlling the balancing switches 29A, 29B, 29C, and 29D is transmitted from the main controller 5 to the RX terminal of the communication means 27 shown in FIG. When the bypass SW control (ON) command is transmitted in step 440, the control content of this bypass SW control (ON) command is determined by the calculation means 23 of the control IC chip 3A, and the SW drive means 33 is transmitted in step 450. It drives and outputs a switch drive signal (a signal that identifies which switch is driven) from the SW drive means 33 to the potential conversion means 32, and one of the selected balancing switches 29A, 29B, 29C, and 29D. Switch is turned on (ON) .. When any of the selected balancing switches 29A, 29B, 29C, 29D is turned on, any of the battery cells 2A, 2B, 2C, 2D is discharged.
Balancing switches 29A, 29B, 29C selected in this step 450 When any of the switches 29A and 29D is turned on (ON), the main controller 5 counts the ON elapsed time of each bypass SW (balancing switch) 29A, 29B, 29C, 29D in step 460. When the ON elapsed time of each bypass SW is counted in this step 460, whether or not the ON elapsed time of each bypass SW (balancing switch) 29A, 29B, 29C, 29D is larger than the ON time in step 470. To judge. That is, in step 470, it waits for the ON time elapsed of each bypass SW (balancing switch) 29A, 29B, 29C, 29D to become larger than the ON time.
In this step 470, each bypass SW (balancing switch) 29A, 29B If it is determined that the ON time of 29C, 29D is longer than the ON time, in step 480, the balancing switches 29A, 29B, 29C, are connected to the RX terminals of the communication means 27 shown in FIG. 2 from the main controller 5. Send a bypass SW control (OFF) command to control 29D OFF. When the bypass SW control (OFF) command is transmitted in step 480, the control content of this bypass SW control (OFF) command is determined by the calculation means 23 of the control IC chip 3A, and the SW drive means 33 is transmitted in step 490. Controlled to output a switch drive signal (a signal that identifies which switch is to be driven) from the SW drive means 33 to the potential conversion means 32, and one of the selected balancing switches 29A, 29B, 29C, 29D. Switch off (OFF). When any of the selected balancing switches 29A, 29B, 29C, 29D is turned off, the discharge of any of the battery cells 2A, 2B, 2C, 2D is stopped. The same applies to the control IC chip 4A and the control IC chip 5A.
FIG. 9 shows an operation flow for testing whether the control IC chips 3A to 5A or each battery cell is abnormal.
First, in step 500, a state (abnormality) detection command is transmitted from the TX terminal of the main controller 5 to the RX terminal of the control IC chip 3A via the insulating means 4. When a status (abnormal) detection command is transmitted from the TX terminal of the main controller 5, the control IC chip 3A receives the status (abnormal) detection command.
When a status (abnormality) detection command is transmitted from the TX terminal of the main controller 5 in this step 500, the control IC chip 3A, the control IC chip 4A, ..., The control IC chip 5A sequentially receives the command in step 510. Then, it is transmitted from the cell monitoring IC chip 5B in the final stage to the main controller 5.
That is, in the control IC chip 3A that has received the state (abnormality) detection command, the state (abnormality) detection command is transmitted from the TX terminal to the RX terminal of the next control IC chip 4A. When this state (abnormal) detection command is output from the TX terminal of the control IC chip 3A, the control IC chip 4A receives the state (abnormal) detection command, and the state (abnormal) detection command is received from the TX terminal of the control IC chip 4A. (Abnormal) Sends the detection command to the TX terminal of the next control IC chip 5A. Then, when the control IC chip 5A in the final stage receives the state (abnormal) detection command transmitted from the TX terminal of the control IC chip 4A, the state (abnormal) detection command received from the TX terminal of the control IC chip 5A is received. Is transmitted to the RX terminal of the main controller 5 via the insulating means 10.
In this step 510, control IC chip 3A, control IC chip 4A, ... Control When the IC chip 5A sequentially receives and transmits from the final stage control IC chip 5A to the main controller 5, the state (abnormal) detection command is received from the control IC chip 5A at 520. Abnormal) Confirm. The state (abnormality) detection command returned to the main controller 5 indicates which control IC chip 3A, control IC chip 4A, ... Control IC chip 5A or the corresponding battery cell has an abnormality. To
When the status (abnormality) of the control IC chip 3A, control IC chip 4A, ... Control IC chip 5A is checked in this 520, which control IC chip or the corresponding battery cell has an abnormality in the 530? Is determined. When it is determined that there is no abnormality in all the control IC chips or the corresponding battery cells in this 530, this flow ends. In addition, if it is determined that there is an abnormality in any of the control IC chips of the control IC chip 4A, ... Control IC chip 5A in this 530, in the 540, the control with the abnormality from the TX terminal of the main controller 5 A status (abnormal content) detection command for specifying the address of the IC chip and identifying the abnormal content is transmitted to the RX terminal of the control IC chip 3A via the insulating means 7.
When a status (abnormal content) detection command is transmitted from the TX terminal of the main controller 5 in this step 540, it is received by the control IC chip 3A in step 550, and is in the same state on the control IC chip that does not correspond to the specified address. (Abnormal content) Send the detection command to the control IC chip in the next stage. In this reception / transmission, the control IC chip 3A receives the status (abnormal content) detection command at the RX terminal and transmits it from the TX terminal to the RX terminal of the control IC chip 4A. The state (abnormal content) detection command sent from the RX terminal of the chip 5A and received from the control IC chip 4A is sent from the TX terminal of the control IC chip 5A to the RX terminal of the main controller 5 via the insulating means 10. Send to.
When an abnormality is detected based on the state (abnormality content) detection command received from the control IC chip 4A transmitted from the TX terminal of the control IC chip 5A to the RX terminal of the main controller 5 via the insulating means 9, the abnormality is detected. A signal is output from the Relay terminal of the main controller 5 to drive the relay drive circuit and turn off the relay.
In this step 550, control IC chip 3A, control IC chip 4A, ... Control When the IC chip 5A sequentially receives and transmits from the final stage control IC chip 5A to the main controller 5, the main controller 5 that receives the status (abnormal content) detection command from the control IC chip 5A at 560 controls. IC chip 3A, control IC chip 4A, ... Confirm the abnormal part in the control IC chip 5A and confirm the content of the abnormality, and end this flow.
In the main controller 5, the TX terminal of the main controller 5 first transmits a warning signal (break field) to send a signal to the RX terminal of the control IC chip 3A, and then the signal can be taken when the signal arrives. A synchronization signal for synchronizing is transmitted, and then a signal for detecting the presence or absence of an abnormality is constantly transmitted. The signal that detects the presence or absence of this abnormality is the control IC chip 3A, control IC chip 4A, ... The control that has an abnormality in either the control IC chip 5A or the battery cell is the control that has an abnormality. The address of the IC chip is specified and sent. Upon receiving this abnormality signal, the main controller 5 transmits a signal for identifying the content of the abnormality based on the abnormality signal. The signal for identifying the content of this abnormality is what kind of information should be transmitted to what number control IC chip, and the content of the abnormality includes the address and data type (overcharge, battery cell voltage, etc.). Has been identified. In this way, in the main controller 5, cell voltage and cell balancing are performed at startup. That is, in the main controller 5, the individual voltage of the battery cell is taken in at the time of startup to perform cell balance control, and then a signal for detecting the presence or absence of an abnormality in each control IC chip is transmitted, and when the abnormality is detected, an abnormality is detected. Send a signal to identify the contents of.
In this main controller 5, the total voltage of the battery cell is periodically detected by the voltage detecting means, and is taken in by the VALL terminal of the main controller 5 via the insulating means. .. Further, the total current of the battery cell is detected by the current detecting means, and is taken in by the CUR terminal of the main controller 5. Further, in the main controller 5, the consistency diagnosis is performed by periodically adding all the cell voltages and comparing the total voltage to see if the difference voltage is within a certain range. Then, if it is checked whether this difference voltage is within a certain range, then the balance is adjusted by checking the voltage of each battery cell and turning the balancing switch ON / OFF.
FIG. 11 shows an example in which this embodiment is used in combination with a commercial power source.
In the figure, 1201 is a commercial power supply, 1202 is a photovoltaic power generation device, 1203 is a load device, 1204 is a control converter, and 1205 is a switch.
A plurality of battery cells 101 are connected in series, a battery management IC is connected to each of the battery cells 101, and the output of the battery management IC is connected to the main controller 5 via an insulating coupler. Further, the control converter 1204 is connected to both ends of the battery cell 101 row, and the main controller 5 and the MCU in the control converter 1204 are also connected to each other.
Further, the photovoltaic power generation device 1202, the load device 1203, and the control converter 1204 are connected to the common commercial power supply 1201 via the switch 1205, respectively. At the same time, the photovoltaic power generation device 1202, the load device 1203, the control converter 1204, the switch 1205, and the main controller 5 are connected in both directions.
The photovoltaic power generation device 1202 is a device that converts sunlight into DC power by a solar cell and outputs AC power by an inverter device.
The load device 1203 is a home appliance such as an air conditioner, a refrigerator, a microwave oven, and a lighting, and an electric device such as a motor, a computer, and a medical device. The control converter 1204 is a charger / discharger that converts AC power into DC power or converts DC power into AC power. Also It also serves as a controller for controlling these charges and discharges and for controlling devices such as the above-mentioned photovoltaic power generation device 1202 and load device 1203.
According to this configuration, when the power required by the load device 1203 cannot be covered by the commercial power source 1201 or the photovoltaic power generation device 1202, the power is supplied from the battery cell 101 via the control converter 1204. Then, when the power supply from the commercial power source 1201 or the photovoltaic power generation device 1202 is excessive, the battery cell 101 is charged with electricity via the control converter 1204.
During these operations, when the voltage between the terminals of the battery cell 101 reaches the discharge stop or charge stop level, the main controller 5 sends the signal to the control converter 1204, and the control converter 1204 controls charging / discharging and the like. ..
With these configurations, it is possible to reduce the contract power and power consumption of the commercial power source 1201 and the power generation rating of the photovoltaic power generation device 1202, and the equipment cost and running cost are reduced.
In addition, when the power consumption is concentrated in a certain time zone, the battery cell 101 supplies power to the commercial power supply 1201, and when the power consumption is low, the power is stored in the power storage device to alleviate the concentration of power consumption. Power consumption is leveled.
Further, since the control converter 1204 monitors the power consumption of the load device 1203 and controls the load device 1203, energy saving and effective use of power can be achieved.
FIG. 12 shows an example in which this embodiment is applied to a motor generator for automobiles.
In the figure, 1101 is a motor generator, 1004 is a control converter, 1005 is a voltage regulator, and 1102 is a DC load device (for example, power steering, electric brake, intake / exhaust valve timing device, etc.).
A plurality of battery cells 101 are connected in series, a battery management IC is connected to each of the battery cells 101, and the output of the battery management IC is connected to the main controller 5 via an insulating coupler. In addition, the main controller 5 and the MCU in the control converter 1004 are also connected to each other.
The motor generator 1101 is a generator that converts the generated AC power into DC power and outputs it.
According to this configuration, an automobile is driven by an engine, and power is generated by a motor generator 1101 which is directly driven by the traveling of the automobile via a drive belt or by engaging an electromagnetic clutch. The electric power generated by the motor generator 1101 is supplied to the battery cell 101 via the control converter 1004 to charge the battery cell 101. The charge / discharge transition of the battery cell 101 is controlled by the motor generator 1101 from the battery management IC via the main controller 5. Also, when discharging, power is supplied from the battery management IC to the motor to drive the tires to rotate. The MCUs in the control transducer 1004 are also interconnected.
The main controller 5 is grounded (chassis ground), but both terminals of the battery cells 2A, 2B, 2C, and 2D of the unit battery cell 2 are floating from the ground. In addition, the control converter 1004 is not grounded, and is floating from the ground. That is, the power system circuit is in a state of floating from the ground.
Even if the main controller 5 runs out of control and is judged to be normal, if it is actually abnormal, the main controller 5 is out of control and the relay cannot be turned off. Output to drive the relay drive circuit and turn off the relay.
According to this embodiment, the number of parts constituting the multi-series battery control system can be reduced.
Further, according to the present embodiment, it is possible to reduce the cost for configuring the multi-series battery control system.
Further, according to this embodiment, high reliability of the multi-series battery control system can be obtained.
Furthermore, according to this embodiment, the usability of the multi-series battery control system can be improved.
Furthermore, according to this embodiment, it is possible to generalize the multi-series battery control system.
Further, according to the present embodiment, it is possible to increase the speed of communication in the multi-series battery control system.
Further, according to the present embodiment, the multi-series battery control system can be easily configured, and the multi-series battery control system can be simplified.
<figref num="1">It is a figure which shows the Example of the multi-series battery control system of this invention.</figref><figref num="2">FIG. 1 is a detailed circuit diagram of the control IC chip shown in the figure.</figref><figref num="3">FIG. 2 is a circuit configuration diagram showing a specific embodiment of the illustrated voltage detecting means.</figref><figref num="4">It is a figure which shows the Example of a communication command.</figref><figref num="5">It is a figure which shows the start-up sequence (Wake-Up) at the time of system start-up.</figref><figref num="6">FIG. 5 is a diagram showing transmission / reception signals of the Wake-Up signals shown in each control IC.</figref><figref num="7">It is a figure which shows the FF-TEST subroutine.</figref><figref num="8">It is a figure which shows the balancing subroutine when switching a balancing switch.</figref><figref num="9">It is a figure which shows the operation flowchart for testing the abnormality of the battery cell or the IC chip.</figref><figref num="10">It is a figure for demonstrating the detection method of the communication signal in each control IC.</figref><figref num="11">It is a figure which shows the example when it is used together with a commercial power source.</figref><figref num="12">It is a figure which shows the example when it is applied to a motor generator.</figref>
Code description
1................................................. Battery system 2................................................. Unit battery cell 2A ~ 2D ........................ Battery cell 3................................................. Control IC 3A ~ 5A .................................. Control IC chip 3B ~ 5B .................................. Cell monitoring IC chip 4,8 ........................ High-speed insulation means 5 .................................. Main controller 6,7,9,10 ............... Insulation means 20 ................................. Selection method 22 ................................. Voltage detection means 23 ................................. Computational means 28A ~ 28D .................. SW state detection means 29A ~ 29D .................. Balancing switch 30 ................................. Potential conversion means 31 ................................. Comparison means 33 ................................. SW drive means
12 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12
Every citation, both ways
| Document | Relation | Office |
|---|---|---|
| JP2008141954A | Cites | Japan |
| JP2004023949A | Cites | Japan |
| JP05048623A | Cites | Japan |
21 members in 2 offices
Priority claims1
| Document | Office | Kind | Date |
|---|---|---|---|
| 2004135022 | Japan | A |
Members21
| Document | Office | Kind | |
|---|---|---|---|
| US2005242667A1 | United States of America | A1 | |
| JP2005318750A | Japan | A | |
| JP4092580B2 | Japan | B2 | |
| JP2008141953A | Japan | A | |
| JP2008141954A | Japan | A | |
| US7511457B2 | United States of America | B2 | |
| US2009224769A1 | United States of America | A1 | |
| JP2011055702A | Japan | A | |
| JP4656152B2This record | Japan | B2 | |
| JP4656153B2 | Japan | B2 | |
| US8339099B2 | United States of America | B2 | |
| JP5177196B2 | Japan | B2 | |
| US2013113428A1 | United States of America | A1 | |
| US2013119936A1 | United States of America | A1 | |
| US2013207609A1 | United States of America | A1 | |
| US2013214740A1 | United States of America | A1 | |
| US8786256B2 | United States of America | B2 | |
| US8791668B2 | United States of America | B2 | |
| US8884584B2 | United States of America | B2 | |
| US2014340042A9 | United States of America | A9 | |
| US8912756B2 | United States of America | B2 |
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Numbers
- Publication
- 4656152
- Application
- 5175
Titles2
- Japanese
- 電池システム
- English
- Battery system
Classification
- CPC, 29
- B60L3/0046
- B60L3/0069
- B60L2210/40
- B60L2240/545
- B60L2240/547
- B60L2240/549
- B60L2240/80
- H02J3/32
- Y02T90/14
- Y02T90/16
- Y02T10/70
- B60L53/14
- B60L50/16
- B60L58/19
- B60L58/22
- B60L50/64
- B60L53/51
- B60L58/15
- B60L58/18
- B60L58/14
- B60L58/24
- Y02T10/7072
- Y02T10/72
- Y02T90/12
- H02J7/54
- H02J7/82
- G01R31/3835
- Y04S10/126
- Y02E60/00
- IPC, 8
- H02J7 00
- H02J7 02
- H01M10 48
- H01M10 44
- B60L1 00
- B60L11 18
- B60L50 16
- H02J3 32
