Bidirectional semiconductor device and method of manufacturing the same

[0001] [Technical field to which the invention belongs] The present invention has a high withstand voltage and a large current capacity applicable to MOSFETs (insulated gate type field effect transistors), IGBTs (insulated gate bipolar transistors), bipolar transistors, etc., and is capable of passing current in both directions. Bipolar bidirectional superjunction semiconductor device and its manufacturing method. [0002] Here, the superjunction semiconductor device is a semiconductor device having a drift region composed of a parallel pn structure in which a current flows in the on state and is depleted in the off state. The parallel pn structure is a structure in which a first conductive type (for example, n type) drift region and a second conductive type (for example, p type) partition region are alternately and repeatedly joined. [0003] [Conventional technology] Conventionally, as a semiconductor device capable of controlling both direct current and alternating current with a low on-voltage, a vertical bidirectional MOS semiconductor device having the structure shown in FIG. 27 is known (Japanese Patent Laid-Open No. 7-307469). Disclosure). In this bidirectional semiconductor device, the first n-channel IGBT is n⁺ Emitter layer 102, p-type base layer 103, n^- It is composed of a substrate 101 and a p-anode layer 104. Also, the second n-channel IGBT is n⁺ Emitter layer 105, p-type base layer 104, n^- It is composed of a substrate 101 and a p-anode layer 103, and its operation is an inverted operation of a first n-channel IGBT. When the current flows from the first terminal 106 to the second terminal 107, the first n-channel IGBT flows, and when the current flows from the second terminal 107 to the first terminal 106, the second The n-channel IGBT carries current. [0004] By the way, in general, in a MOSFET, there is a trade-off relationship between the on-resistance and the withstand voltage, such that the withstand voltage decreases when the on-resistance is small and the on-resistance increases when the withstand voltage is high. It is known that such a trade-off relationship is similarly established in semiconductor elements such as IGBTs, bipolar transistors, and diodes. The same applies to both vertical semiconductor devices in which the direction of the drift current flowing when the current is on and the direction in which the depletion layer extends when the depletion layer is off, and horizontal semiconductor devices in which the direction in which the drift current flows and the direction in which the depletion layer extends are different. Trade-off relationship is established. [0005] As a solution to this trade-off problem, the present inventors composed a drift layer composed of parallel pn layers in which n-type regions and p-type regions with increased impurity concentrations were alternately arranged, and when in the off state. Has previously applied for an invention relating to a superjunction semiconductor device having a structure that is depleted to bear the withstand voltage (Japanese Patent Application No. 10-209267). In a semiconductor device having such a parallel pn structure, even if the impurity concentration of the parallel pn structure is high, the depletion layer expands from each pn junction of the parallel pn structure in the off state, and the entire drift region is depleted. The pressure resistance can be increased. [0006] [Problems to be Solved by the Invention] However, regarding the above-mentioned superjunction semiconductor element, for example, in the case of a MOSFET, the current flowing from the drain to the source can be controlled, but the current flowing from the source to the drain cannot be controlled. Only proposed for devices. That is, the above-mentioned trade-off relationship also holds for bidirectional semiconductor devices, but a solution to this trade-off problem has not yet been presented for bidirectional semiconductor devices. Further, regarding the withstand voltage, the withstand voltage is maintained when the drain is applied to a positive voltage with respect to the source, but the withstand voltage cannot be maintained when the drain is a negative voltage. [0007] The present invention has been made in view of the above problems, and is a bidirectional superjunction semiconductor device capable of passing a current in both directions, having a low on-resistance in any direction, and having a high withstand voltage. It is an object of the present invention to provide a manufacturing method capable of manufacturing the product easily and with good mass productivity. [0008] [Means for solving problems] In order to achieve the above object, the bidirectional superjunction semiconductor device according to the present invention has a first conductive drift region and a second conductive partition region between the first element region and the second element region. A semiconductor region forming a parallel pn structure arranged alternately is provided, and a second conductive type partition region, a second conductive type first region in the first element region, and a second in the second element region are provided. The second conductive type region is separated from each other by the first conductive type semiconductor including at least the first conductive type drift region. [0009] According to the present invention, the second conductive type partition region, the first region in the first element region, and the second region in the second element region are separated from each other by the first conductive type semiconductor. Therefore, withstand voltage can be obtained in both directions. [0010] In the present invention, the third region of the first conductive type in the first element region and the fourth region of the first conductive type in the second element region are connected by the first conductive type drift region. You may. In this way, a current can flow in both directions between the first element region and the second element region, and low on-resistance can be easily reduced. [0011] Further, in the bidirectional superjunction semiconductor device according to the present invention, the first conductive type drift region and the second conductive type partition region are alternately arranged in parallel between the first element region and the second element region. Two semiconductor regions forming a pn structure are provided, and the second conductive type partition region of the first parallel pn structure and the second conductive type partition region of the second parallel pn structure are separated by the first conductive type region. It is something that I tried to do. [0012] According to the present invention, the second conductive type partition region is separated into two by the first conductive type region between the first element region and the second element region. Therefore, the second conductive type partition region of the first parallel pn structure is connected to the first region of the second conductive type in the first element region, and the second conductive type of the second parallel pn structure is connected. Even if the partition region is connected to the second region of the second conductive type in the second element region, the first region and the second region are separated from each other, so that a withstand voltage is obtained in both directions. be able to. [0013] In the present invention, the first conductive drift region of the first parallel pn structure and the first conductive drift region of the second parallel pn structure may be connected by a first conductive type semiconductor. In this way, a current path can be created by the first conductive drift region of the first parallel pn structure, the first conductive drift region of the second parallel pn structure, and the first conductive type semiconductor. A current can flow in both directions between the element region and the second element region, and low on-resistance can be easily reduced. [0014] Further, in the method for manufacturing a bidirectional superjunction semiconductor device according to the present invention, a pair of semiconductor devices having an element region and a semiconductor region forming a parallel pn structure are manufactured, the back surface of the semiconductor element is polished, and then the semiconductor element is manufactured. Are attached to each other on the back surface to integrate them. According to the present invention, since the parallel pn structure can be easily manufactured, the manufacturing process can be simplified and the manufacturing cost can be reduced. [0015] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the bidirectional superjunction semiconductor device and the method for manufacturing the same according to the present invention will be described in detail with reference to the drawings. [0016] (Embodiment 1) FIG. 1 is a vertical cross-sectional perspective view showing a main part of the vertical bidirectional superjunction MOSFET according to the first embodiment of the present invention. This bidirectional superjunction MOSFET has a first n-channel MOSFET, which is a first element region, and a second n-channel, which is a second element region, on the first main surface side and the second main surface side, respectively. MOSFETs are formed, and a semiconductor region forming a parallel pn structure is provided between the first and second MOSFETs. [0017] The first n-channel MOSFET has a p-type base region 4, n, which is the first region.⁺ It has a mold source region 6, a gate insulating film 7, a gate electrode 9, and a source electrode 10. Within the base region 4, a p-type high impurity concentration contact region 5 and a source region 6 are provided. The source region 6 is separated from the n-type high resistance region 3 which is the third region by the base region 4. The gate electrode 9 is provided on the surface of the base region 4 between the source region 6 and the high resistance region 3 via the gate insulating film 7. The source electrode 10 is provided over the surfaces of the interlayer insulating film 8 and the contact region 5 for insulating from the gate electrode 9. The high resistance region 3 has a region having a relatively high impurity concentration from the surface side of the device to the vicinity of the depth of the base region 4. [0018] The second n-channel MOSFET has the same configuration as the first n-channel MOSFET described above, that is, the p-type base region 14, n, which is the second region.⁺ It has a mold source region 16, a gate insulating film 17, a gate electrode 19, and a source electrode 20. Within the base region 14, a p-type high impurity concentration contact region 15 and a source region 16 are provided. The source region 16 is separated from the n-type high resistance region 13 which is the fourth region by the base region 14. The gate electrode 19 is provided on the surface of the base region 14 between the source region 16 and the high resistance region 13 via the gate insulating film 17. The source electrode 20 is provided over the surfaces of the interlayer insulating film 18 and the contact region 15 for insulating from the gate electrode 19. The high resistance region 13 has a region having a relatively high impurity concentration from the surface side of the device to the vicinity of the depth of the base region 14. [0019] The parallel pn structure has a structure in which an n-type drift region 1 and a p-type partition region 2 are alternately arranged in a stripe shape between two high resistance regions 3 and 13. Drift region 1 is connected to two high resistance regions 3, 13. The partition region 2 is separated from the base regions 4 and 14 of each MOSFET by the high resistance regions 3 and 13. Due to such a configuration, the parallel pn structure conducts current in the on state and depletions in the off state. [0020] Here, the electric field strength at the pn junction formed by the base region 4 and the high resistance region 3 of the first element region is the critical electric field strength at the voltage required for the parallel pn structure to be completely depleted. It is necessary to set the impurity concentration and thickness of the high resistance regions 3 and 13 so that the depletion layer extending from the parallel pn structure does not punch through the base region 14 of the second element region. Then, it becomes easy to increase the pressure resistance. On the other hand, in the on state, the drift current flows in the region where the impurity concentration of the parallel pn structure is high, so that the on resistance is reduced. [0021] [0021] Further, it is preferable that the amount of impurities in the net of the drift region 1 and the partition region 2 is almost the same. The reason is that the planar arrangement of one or both of the drift region 1 and the partition region 2 is not limited to the stripe shape, and may be, for example, a grid point shape of a three-way grid, a square grid, or a hexagonal grid, but the drift region. This is because if the amount of impurities in the nets of 1 and the partition region 2 is almost the same, the withstand voltage can be easily increased regardless of the arrangement shape of each of the regions 1 and 2. When the amount of impurities in the drift region 1 and the partition region 2 is out of balance, it becomes difficult to obtain a high withstand voltage because a region that does not deplete is created in the parallel pn structure. [0022] When the bidirectional superjunction MOSFET with the above configuration is applied to, for example, a 500V class, the values such as the dimensions and impurity concentration of each part are as follows, for example. The thickness of the drift region is 30.0 μm. For the n-type drift region 1 and the p-type partition region 2, their widths are both 8.0 μm, and their impurity concentrations are both 2.0 × 10.¹⁵cm^-3Is. For the base regions 4 and 14, the diffusion depth is 3.5 μm, and the surface impurity concentration is 2.0 × 10.¹⁷cm^-3Is. For each of the contact regions 5 and 15, the diffusion depth is 1.0 μm and the surface impurity concentration is 4.0 × 10.¹⁹cm^-3Is. For each of the source regions 6 and 16, the diffusion depth is 0.5 μm and the surface impurity concentration is 3.0 × 10.²⁰cm^-3Is. The thickness of each of the high resistance regions 3 and 13 is 19.0 μm, and the impurity concentration is 3.0 × 10.¹⁴cm^-3Is. However, in each of the high resistance regions 3 and 13, the diffusion depth of the portion having a high surface impurity concentration is 3.0 μm, and the surface impurity concentration is 1.0 × 10.¹⁶cm^-3Is. [0023] Next, the manufacturing method of the bidirectional superjunction MOSFET shown in FIG. 1 will be described with reference to FIGS. 2 to 6. First, an n-type high resistance layer 202 is epitaxially grown on an n-type substrate 201, a photoresist mask 203 is formed on the n-type high resistance layer 202, and boron ions are injected into a position to be a partition region 2 (see FIG. 2). Then, after removing the resist, a photoresist mask 204 is formed, and phosphorus ions are injected into the position of the drift region 1 (see FIG. 3). After removing the resist, the n-type high resistance layer is epitaxially grown and boron ions or phosphorus ions are repeatedly injected to obtain a predetermined thickness, and then the high resistance region 3 is epitaxially grown on the surface. After that, impurities are diffused and activated by heat treatment to form a drift region 1 and a partition region 2 (see FIG. 4). [0024] Then, the base region 4, the contact region 5, and the source region 6 are formed on the surface layer of the high resistance region 3 according to a normal manufacturing process of the double diffusion MOSFET. Subsequently, a gate oxide film (gate insulating film) 7 and a gate electrode 9 such as polysilicon are formed, and an interlayer insulating film 8 is deposited on the surface thereof. Then, a contact hole is opened and a metal (0045) such as Al-Si is sputtered to form a source electrode 10 (see FIG. 5). [0025] Then, the semiconductor region consisting of the substrate 201 and the parallel pn structure is mechanically and chemically polished from the back surface of the substrate to finish the semiconductor region consisting of the parallel pn structure to a predetermined thickness (see FIG. 6). The element thus obtained is directly bonded to another element produced in the same manner and their back surfaces, and integrated by heat treatment at about 400 ° C. under pressure, and is shown in FIG. The semiconductor element is completed. At that time, the natural oxide film on the bonded surface is sufficiently removed with an HF aqueous solution. [0026] Next, the operation of the bidirectional superjunction MOSFET shown in FIG. 1 will be described. In the off state, the gate terminal (hereinafter referred to as gate 1) of the first MOSFET is shorted to the source terminal (hereinafter referred to as source 1) with reference to the source of the first MOSFET, and the second MOSFET is used. A positive voltage is applied to the source 2 and the gate 2 with the source terminal (hereinafter referred to as the source 2) and the gate terminal (hereinafter referred to as the gate 2) short-circuited. When this applied voltage is increased, the depletion layer extends from the pn junction between the base region 4 and the high resistance region 3 on the first MOSFET side into the high resistance region 3 and reaches the parallel pn structure. [0027] Then, since the base region 4 on the first MOSFET side and the partition region 2 are electrically connected, the depletion layer extends to the high resistance region 13 on the second MOSFET side and also in the pn junction direction of the parallel pn structure. It also begins to spread. When the applied voltages of the source 2 and the gate 2 are further increased, the parallel pn structure is completely depleted, and the depletion layer expands the high resistance region 13 on the second MOSFET side toward the base region 14. Then, the high withstand voltage is maintained until the holes injected from the base region 14 cause a sudden snow landslide multiplication in the depletion region. On the other hand, when a negative voltage is applied to the source 2 and the gate 2 in a state where the source 2 and the gate 2 are short-circuited, the operation becomes an inverted operation with respect to the above-described operation. [0028] Another operation in the off state will be described. With reference to source 1, gate 1 is shorted to source 1, and a positive voltage is applied to source 2 and gate 2 while holding gate 2 at a voltage that forms an n-type channel with respect to source 2. To do. In this case, the extension of the depletion layer is the same as in the first case where the n-type channel is not formed as described above, but there is almost no hole injection from the base region 14 on the second MOSFET side. Since the source 2, the high resistance region 13 on the second MOSFET side, and the drift region 1 are electrically connected, it is easier to increase the withstand voltage than in the first case described above. [0029] This is because a channel is formed when the configuration consisting of the base region 4 on the first MOSFET side, the high resistance regions 3, 13 and the drift region 1, and the base region 14 on the second MOSFET side is regarded as a pnp bipolar transistor. The state in which it is not open corresponds to the collector-emitter breakdown voltage BVceo with the base open, and the state in which the channel is formed corresponds to the collector-base breakdown voltage BVcbo with the emitter open. When a negative voltage is applied to the source 2 and the gate 2, the operation becomes an inverted operation as opposed to the above-mentioned operation. [0030] To change from the off state to the on state, the gate 1 may be applied to the positive voltage for the source 1 and the gate 2 may be applied to the positive voltage for the source 2. When a positive voltage sufficient to form a channel is applied to the source 2 and the gate 2 with respect to the source 1, an n-type channel is formed on each surface layer of the base regions 4 and 14. , Source 1 through n-type channel in base region 4, high resistance region 3 on the first MOSFET side, drift region 1, high resistance region 13 on the second MOSFET side, n-type channel in base region 14, source 2 Electrons will flow toward. Further, when a negative voltage is applied to the source 2 and the gate 2 with respect to the source 1, the electron flow is opposite to the above-mentioned direction. [0031] Further, when changing from the off state in which the positive voltage is applied to the source 2 and the gate 2 to the source 1 to the on state, it is sufficient to simply change the gate 1 to the positive voltage with respect to the source 1. In this case, the electrons that have passed from the source 1 through the n-type channel formed on the surface layer of the base region 4 and reached the high resistance region 13 on the second MOSFET side have high resistance with the base region 14 on the second MOSFET side. The pn junction consisting of region 13 is forward biased and holes are injected from the base region 14. By injecting holes, the parallel pn structure and each of the high resistance regions 3 and 13 are conductivity-modulated, resulting in a low on-voltage. This is the so-called IGBT operation. [0032] On the contrary, when changing from the off state in which the negative voltage is applied to the source 2 and the gate 2 to the source 1 to the on state, a positive voltage may be applied to the source 2 to the gate 2. In this case, the operation is the same except that the direction of the current is reversed. In such an IGBT operation, since a small number of carriers are accumulated in the drift region 1, the switching speed is slower than that of the MOSFET operation described above, but there is an advantage that a low on-voltage can be obtained in a large current region. [0033] According to the first embodiment, a current can flow in both directions between the first MOSFET and the second MOSFET, and the on-resistance in either direction can be lowered. Moreover, the withstand voltage can be ensured in both directions. Further, by forming the MIS type semiconductor element in the element region, it is possible to obtain the effect that the power consumption of the drive circuit can be reduced and simplified. Furthermore, since the element on which the first MOSFET and the parallel pn structure are manufactured and the element on which the second MOSFET and the parallel pn structure are manufactured are bonded to each other on the back surfaces, the aspect ratios of the drift region 1 and the partition region 2 are increased. Even if it is large, the parallel pn structure can be easily manufactured, so that the manufacturing process can be simplified and the manufacturing cost can be reduced. [0034] (Embodiment 2) FIG. 7 is a vertical cross-sectional perspective view showing a main part of the vertical bidirectional superjunction MOSFET according to the second embodiment of the present invention. The second embodiment differs from the first embodiment in the following three points. First, the parallel pn structure consists of a first parallel pn structure half formed closer to the first MOSFET and a second parallel pn structure half formed closer to the second MOSFET. is there. Second, the stripe directions of these two parallel pn structure halves are approximately intersecting each other with respect to the other. Third, the direction in which the base region 14 of the second MOSFET extends and the direction in which the stripes in the second parallel pn structure half are extended are perpendicular to each other. Other configurations are the same as those in the first embodiment. The same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. [0035] The drift region 1 of the first parallel pn structure half and the drift region 1 of the second parallel pn structure half are connected to each other by a part thereof. Similarly, the partition area 2 of the first parallel pn structure half and the partition area 2 of the second parallel pn structure half are connected to each other by a part thereof. [0036] In the method of manufacturing the bidirectional superjunction MOSFET shown in FIG. 7, the first MOSFET and the element having the parallel pn structure are formed in the same manner as in the first embodiment, and the second MOSFET and the element having the parallel pn structure are formed. , Each is the same as in Example 1 except that the back surfaces are polished and then bonded so that the directions of the stripes of the respective parallel pn structures are overlapped. Since the operation of the bidirectional superjunction MOSFET shown in FIG. 7 is the same as that of the first embodiment, the description thereof will be omitted. [0037] According to the second embodiment, as in the first embodiment, a MIS type semiconductor capable of allowing current to flow in both directions, achieving low on-resistance in both directions, and ensuring withstand voltage in both directions. In addition to the effect that the power consumption of the drive circuit can be reduced and simplified by forming the element, the parallel pn structures are precisely aligned with each other so that their stripes match accurately at the time of bonding. Since it is not necessary, the bidirectional superjunction MOSFET can be easily manufactured. [0038] (Embodiment 3) FIG. 8 is a vertical cross-sectional perspective view showing a main part of the vertical bidirectional superjunction MOSFET according to the third embodiment of the present invention. The third embodiment differs from the first embodiment in the following four points. First, the parallel pn structure consists of a first parallel pn structure formed closer to the first MOSFET and a second parallel pn structure formed closer to the second MOSFET. The first parallel pn structure consists of a drift region 11 and a partition region 12. The second parallel pn structure consists of a drift region 21 and a partition region 22. [0039] Second, the first parallel pn structure and the second parallel pn structure are separated by an n-type separation region 33. Third, there are no n-type high resistance regions 3, 13 in the first and second element regions. Fourth, the first parallel pn structure and the second parallel pn structure are connected to the base region 4 of the first MOSFET and the base region 14 of the second MOSFET, respectively. Other configurations are the same as those in the first embodiment. The same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. [0040] In the third embodiment, the withstand voltage is maintained in both directions by the partition regions 12 and 22 and the separation region 33 of the first and second parallel pn structures, and the impurity concentration and the thickness of the separation region 33 are appropriately selected. High withstand voltage can be obtained. The electric field strength at the pn junction formed by the partition region 12 and the separation region 33 of the first parallel pn structure is less than or equal to the critical electric field strength at the voltage at which the parallel pn structure is completely depleted, and the second It is necessary to set the impurity concentration and thickness of the separation region 33 so as not to punch through the parallel pn structure of. Further, since a part of the n-type substrate is used as the separation region 33, it is necessary to adjust the impurity concentration of the substrate to a predetermined concentration. [0041] The method for manufacturing the bidirectional superjunction MOSFET shown in FIG. 8 applies to the element in which the first MOSFET and the parallel pn structure are formed, and the element in which the second MOSFET and the parallel pn structure are formed in the same manner as in the first embodiment. In order to obtain a separation region 33 having a predetermined thickness, the same as in Example 1 except that the back surface of the substrate is polished so that a part of the n-type substrate 201 remains as shown in FIG. Since the operation of the bidirectional superjunction MOSFET shown in FIG. 8 is the same as that of the first embodiment, the description thereof will be omitted. [0042] According to the third embodiment, as in the first embodiment, a MIS type semiconductor capable of allowing current to flow in both directions, achieving low on-resistance in both directions, and ensuring withstand voltage in both directions. By forming the element, it is possible to obtain the effect that the power consumption of the drive circuit can be reduced and simplified. [0043] (Embodiment 4) FIG. 10 is a vertical cross-sectional view showing a main part of the vertical bidirectional superjunction MOSFET according to the fourth embodiment of the present invention. The fourth embodiment is a modification of the third embodiment, and the fourth embodiment differs from the third embodiment in the following four points. First, n⁺ It is formed on the low resistance layer 34 of the mold. Second, the first MOSFET and the second MOSFET are formed on the same main surface. Thirdly, the first parallel pn structure and the second parallel pn structure are provided so as to face each other in the lateral direction. Fourth, the separation region 33 that separates the first parallel pn structure and the second parallel pn structure is n.^- It consists of a type high resistance region 33a and an n type region 33b. [0044] Separation area 33 n^- The high resistance region 33a of the mold is sandwiched between the first parallel pn structure and the second parallel pn structure. The n-type region 33b of the separation region 33 is provided between the semiconductor substrate 34 and the first and second parallel pn structures and the n-type high resistance region 33a of the separation region 33 in contact with each other. There is. Other configurations are the same as those in the third embodiment. The same components as those in the third embodiment are designated by the same reference numerals, and the description thereof will be omitted. [0045] Next, a method for manufacturing the bidirectional superjunction MOSFET shown in FIG. 10 will be described. First, on the low resistance layer 34, n-type regions 33b and n of the separation region 33^- The n-type layer and the n-type high resistance layer that form the mold high resistance region 33a are sequentially epitaxially grown. A resist mask is formed on the resist, and boron ions are injected into the partition regions 12 and 22 to remove the resist. Subsequently, a resist mask is formed, phosphorus ions are injected into the position of the drift region 1, and then the resist is removed. [0046] The n-type high resistance layer having the same thickness as the first n-type high resistance layer is epitaxially grown again, and boron ions or phosphorus ions are injected, and this is repeated to obtain a predetermined thickness. After that, epitaxial growth is performed, which is the outermost surface portion, and impurities are diffused and activated by heat treatment to form drift regions 11,21 and partition regions 12, 22. The mask pattern may be adjusted so that boron ions and phosphorus ions are not injected into the portion corresponding to the separation region 33. [0047] Then, the base region 4,14, the contact region 5,15 and the source region 6,16 are formed according to the usual manufacturing process of the double diffusion MOSFET. Subsequently, a gate oxide film 7,17 and a gate electrode 9,19 such as polysilicon are formed, and an interlayer insulating film 8 is deposited on the surface thereof. In addition, the insulating film 35 is also deposited on the exposed surface of the separation region 33. Then, a contact hole is opened and a metal such as Al-Si is sputtered to form source electrodes 10 and 20. [0048] Next, the operation of the bidirectional superjunction MOSFET shown in FIG. 10 will be described. In the off state, a positive voltage is applied to the source 2 and the gate 2 with the gate 1 shorted to the source 1 and the gate 2 shorted to the source 2. As this applied voltage is increased, the first parallel pn structure becomes depleted, and the partition region 12 in contact with the division region 33 in the first parallel pn structure, and the high resistance regions 33a and n-type of the separation region 33. The depletion layer extends from the pn junction with the n-type region consisting of the region 33b to the high resistance region 33a. The withstand voltage is positively injected until the depletion layer reaches the partition region 22 in contact with the partition region 33 in the second parallel pn structure, or from the partition region 2 in contact with the partition region 33 in the second parallel pn structure. The holes are retained until a sudden landslide multiplication occurs in the previous depletion region. When a negative voltage is applied to the source 2 and the gate 2 with respect to the source 1, the above-described operation is inverted. [0049] When changing from the off state to the on state, the gate 1 may be applied to the positive voltage for the source 1 and the gate 2 should be applied to the positive voltage for the source 2 to form an n-type channel. .. When the source 2 is positively applied to the source 1, the electrons flow from the source 1 through the n-type channel in the vertical direction through the drift region 11 of the first parallel pn structure. Then, the current reaching the n-type region 33b on the back surface side flows laterally through the n-type region 33b toward the second parallel pn structure, and the drift regions 21 and n-type of the second parallel pn structure It flows to source 2 via the channel. When the source 2 has a negative voltage with respect to the source 1, the current flows in the path opposite to the above-mentioned current path. [0050] According to the fourth embodiment, as in the third embodiment, a MIS type semiconductor capable of allowing current to flow in both directions, achieving low on-resistance in both directions, and ensuring withstand voltage in both directions. By forming the element, it is possible to obtain the effect that the power consumption of the drive circuit can be reduced and simplified. [0051] (Embodiment 5) 11 is a plan view showing a main part of the horizontal bidirectional superjunction MOSFET according to the fifth embodiment of the present invention, and FIGS. 12 and 13 are vertical cross-sectional views taken along the cutting lines AA and BB of FIG. 11, respectively. Is. This bidirectional superjunction MOSFET uses an SOI substrate in which an insulating film 46 is laminated on an n-type or p-type semiconductor substrate 44, and the first MOSFET and the first MOSFET, which are the first element regions, are on the SOI substrate. It has a structure in which a second MOSFET, which is the element region of 2, is formed so as to sandwich a parallel pn structure. [0052] The parallel pn structure has a structure in which a short fence-shaped n-shaped drift region 1 and a short fence-shaped p-shaped partition region 2 are alternately arranged along the surface of the insulating film 46. The parallel pn structure is in contact with the n-type high resistance region 3 on the first MOSFET side and the n-type high resistance region 13 on the second MOSFET side. Although there is a difference between the horizontal type and the vertical type in the fifth embodiment, the configuration and operation thereof are basically the same as those in the first embodiment. Therefore, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted, and the description of the operation will also be omitted. [0053] In the fifth embodiment, since the p-type base regions 4, 14 are sandwiched between the n-type high resistance regions 3, 13 and the SOI substrate, withstand voltage can be obtained in both directions. Further, since the drift region 1 and the partition region 2 are formed with substantially the same width, the amount of impurities in each region 1 and 2 may be substantially the same. When the widths of the drift region 1 and the partition region 2 are different, it is necessary to control the amount of impurities introduced so that the amount of impurities in each region 1 and 2 becomes the same. Since the current flows through the drift region 1 having a high impurity concentration, it is possible to reduce the on-resistance. [0054] When the bidirectional superjunction MOSFET with the above configuration is applied to, for example, a 500V class, the values such as the dimensions and impurity concentration of each part are as follows, for example. The thickness of the drift region is 30.0 μm. For the n-type drift region 1 and the p-type partition region 2, their widths are both 8.0 μm, and their impurity concentrations are both 2.0 × 10.¹⁵cm^-3And their depth is both 2.0 μm. For each of the high resistance regions 3 and 13, the length is 16.0 μm and the impurity concentration is 3.0 × 10.¹⁴cm^-3Is. For the base regions 4 and 14, the diffusion depth is 2.0 μm and the surface impurity concentration is 2.0 × 10.¹⁷cm^-3Is. For each of the contact regions 5 and 15, the diffusion depth is 0.5 μm and the surface impurity concentration is 4.0 × 10.¹⁹cm^-3Is. For each of the source regions 6 and 16, the diffusion depth is 0.5 μm and the surface impurity concentration is 3.0 × 10.²⁰cm^-3Is. [0055] Next, a method for manufacturing the bidirectional superjunction MOSFET shown in FIGS. 11 to 13 will be described. First, a resist mask is formed on the n-type high resistance layer of the SOI substrate, and boron ions are injected into the position of the partition region 2 to remove the resist. Subsequently, a resist mask is formed, phosphorus ions are injected into the position of the drift region 1, and then the resist is removed. A mask is used to prevent boron ions and phosphorus ions from being injected into the portions corresponding to the high resistance regions 3 and 13. After that, impurities are diffused and activated by heat treatment to form a drift region 1 and a partition region 2. [0056] Then, the base region 4,14, the contact region 5,15 and the source region 6,16 are formed according to the usual manufacturing process of the double diffusion MOSFET. Subsequently, the gate oxide films 7 and 17 and the interlayer insulating film 45 are formed, and further, the gate electrodes 9 and 19 such as polysilicon are formed. Then, a contact hole is opened and a metal such as Al-Si is sputtered to form a source electrode (not shown). [0057] According to the fifth embodiment, as in the first embodiment, the horizontal element can also flow a current in both directions, can reduce on-resistance in both directions, and can secure a withstand voltage in both directions. By forming the MIS type semiconductor element, it is possible to reduce the power consumption and simplify the drive circuit, and it is possible to obtain the effect of facilitating the manufacturing method. [0058] [0058] In the parallel pn structure, instead of the structure in which the short fence-shaped drift region 1 and the short fence-shaped partition region 2 are arranged alternately in a plane, the layered drift region and the layered partition region are alternately arranged. It may have a laminated structure. Further, the gate structure may be a planer structure or a U-groove structure. [0059] (Embodiment 6) FIG. 14 is a plan view showing a main part of the horizontal bidirectional superjunction MOSFET according to the sixth embodiment of the present invention, and FIGS. 15 and 16 are vertical cross-sectional views taken along the cutting lines AA and BB of FIG. 14, respectively. is there. The sixth embodiment is a modification of the fifth embodiment, and the difference between the sixth embodiment and the fifth embodiment is that instead of the SOI substrate, p.^- N on a mold high resistance semiconductor substrate 54^- A semiconductor substrate in which a high-resistance semiconductor layer 57 of the mold is laminated is used. Other configurations are the same as in the fifth embodiment. [0060] In the off state, the depletion layer extends to the semiconductor layer 57 in addition to the direction in which the current flows. Therefore, p-type base regions 4, 14, n^- The base-open collector-emitter breakdown voltage BVceo is a transverse MOSFET when the configuration consisting of the type high resistance regions 3, 13 and the n-type semiconductor layer 57 and the p-type semiconductor substrate 54 is regarded as a pnp bipolar transistor. It is necessary to set the thickness of the semiconductor layer 57 and the impurity concentration so as to exceed the withstand voltage of. The same components as those in the fifth embodiment are designated by the same reference numerals, and the description thereof will be omitted. Further, the description of the operation will be omitted as in the fifth embodiment. [0061] Next, a method of manufacturing the bidirectional superjunction MOSFET shown in FIGS. 14 to 16 will be described. First, p^- N on the semiconductor substrate 54 of the mold^- The high resistance semiconductor layer 57 of the mold is epitaxially grown. A resist mask is formed on the resist mask to form high resistance regions 3 and 13. Then, a resist mask is formed, and boron ions are injected into the position of the partition region 2 to remove the resist. Subsequently, a resist mask is formed, phosphorus ions are injected into the position of the drift region 1, and then the resist is removed. After that, impurities are diffused and activated by heat treatment to form a drift region 1 and a partition region 2. From this point onward, the MOSFET is manufactured in the same manner as in the fifth embodiment. [0062] According to the sixth embodiment, as in the fifth embodiment, a MIS type semiconductor capable of allowing current to flow in both directions, achieving low on-resistance in both directions, and ensuring withstand voltage in both directions. By forming the element, it is possible to obtain the effect that the power consumption of the drive circuit can be reduced and simplified. [0063] (Embodiment 7) FIG. 17 is a plan view showing a main part of the horizontal bidirectional superjunction MOSFET according to the seventh embodiment of the present invention, and FIGS. 18 and 19 are vertical cross-sectional views taken along the cutting lines AA and BB of FIG. 17, respectively. is there. The seventh embodiment is a modification of the sixth embodiment, and the seventh embodiment differs from the sixth embodiment in the following four points. First, the parallel pn structure consists of a first parallel pn structure formed closer to the first MOSFET and a second parallel pn structure formed closer to the second MOSFET. The first parallel pn structure consists of a drift region 11 and a partition region 12. The second parallel pn structure consists of a drift region 21 and a partition region 22. [0064] Second, the first parallel pn structure and the second parallel pn structure are separated by an n-type separation region 33. This separation region 33 is p^- N laminated on the high resistance semiconductor substrate 54 of the mold^- It is part of the high resistance semiconductor layer 57 of the mold. Third, n in the first and second element regions^- There are no high resistance regions 3, 13 of the mold. [0065] Fourth, the first parallel pn structure and the second parallel pn structure are connected to the base region 4 of the first MOSFET and the base region 14 of the second MOSFET, respectively. Other configurations are the same as in the fifth embodiment. That is, the seventh embodiment corresponds to the vertical element of the third embodiment having a horizontal structure. The same components as those in the fifth embodiment are designated by the same reference numerals, and the description thereof will be omitted. Further, since the operation is basically the same as that of the vertical element, the description thereof will be omitted. [0066] Next, a method for manufacturing the bidirectional superjunction MOSFET shown in FIGS. 17 to 19 will be described. First, p^- N on the semiconductor substrate 54 of the mold^- The high resistance semiconductor layer 57 of the mold is epitaxially grown. A resist mask is formed on the resist, and boron ions are injected into the partition regions 12 and 22 to remove the resist. Subsequently, a resist mask is formed, phosphorus ions are injected into the positions of the drift regions 11 and 21, and then the resist is removed. A mask is used to prevent boron ions and phosphorus ions from being injected into the portion corresponding to the separation region 33. After that, impurities are diffused and activated by heat treatment to form drift regions 11,21 and partition regions 21, 22. From this point onward, the MOSFET is manufactured in the same manner as in the fifth embodiment. [0067] According to the seventh embodiment, as in the fifth embodiment, a MIS type semiconductor capable of allowing current to flow in both directions, achieving low on-resistance in both directions, and ensuring withstand voltage in both directions. By forming the element, it is possible to obtain the effect that the power consumption of the drive circuit can be reduced and simplified. [0068] [0068] (Embodiment 8) FIG. 20 is a plan view showing a main part of the horizontal bidirectional superjunction MOSFET according to the eighth embodiment of the present invention, and FIG. 21 is a vertical cross-sectional view taken along the cutting line AA of FIG. The eighth embodiment is a modification of the fifth embodiment, and the difference between the eighth embodiment and the fifth embodiment is that the parallel pn structure alternately stacks the layered drift region 1 and the layered partition region 2. It has a structure like this. Other configurations are the same as in the fifth embodiment. The same components as those in the fifth embodiment are designated by the same reference numerals, and the description thereof will be omitted. Further, the description of the operation will be omitted as in the fifth embodiment. [0069] Next, a method for manufacturing the bidirectional superjunction MOSFET shown in FIGS. 20 and 21 will be described. First, a resist mask is formed on the n-type high resistance layer of the SOI substrate, and boron ions are injected into the position of the partition region 2 to remove the resist. Subsequently, a resist mask is formed, phosphorus ions are injected into the position of the drift region 1, and then the resist is removed. A mask is used to prevent boron ions and phosphorus ions from being injected into the portions corresponding to the high resistance regions 3 and 13. [0070] Subsequently, epitaxial growth of an n-type high resistance layer and injection of boron ions or phosphorus ions are repeated to obtain a predetermined thickness. After that, impurities are diffused and activated by heat treatment to form a drift region 1 and a partition region 2. The outermost epitaxial growth layer of the parallel pn structure is preferably a p-type region. [0071] Then, the base region 4,14, the contact region 5,15, and the source region 6,16 are formed on the surfaces of the high resistance regions 3,13 on both sides of the parallel pn structure according to the normal manufacturing process of the double diffusion MOSFET. .. Subsequently, the gate oxide films 7 and 17 and the interlayer insulating film 45 are formed, and further, the gate electrodes 9 and 19 such as polysilicon are formed. Then, a contact hole is opened and a metal such as Al-Si is sputtered to form a source electrode (not shown). [0072] According to the eighth embodiment, as in the fifth embodiment, a MIS type semiconductor capable of allowing current to flow in both directions, achieving low on-resistance in both directions, and ensuring withstand voltage in both directions. By forming the element, it is possible to obtain the effect that the power consumption of the drive circuit can be reduced and simplified. [0073] (Embodiment 9) FIG. 22 is a plan view showing a main part of the horizontal bidirectional superjunction MOSFET according to the ninth embodiment of the present invention, and FIG. 23 is a vertical sectional view taken along the cutting line AA of FIG. 22. The ninth embodiment is a modification of the eighth embodiment, and the difference between the ninth embodiment and the eighth embodiment is that instead of the SOI substrate, p^- N on a mold high resistance semiconductor substrate 54^- A semiconductor substrate in which a high-resistance semiconductor layer 57 of the mold is laminated is used. Other configurations are the same as in the eighth embodiment. The same components as those in the eighth embodiment are designated by the same reference numerals, and the description thereof will be omitted. Further, as in the case of the eighth embodiment, the description of the operation will be omitted. [0074] Next, a method of manufacturing the bidirectional superjunction MOSFET shown in FIGS. 22 and 23 will be described. First, p^- N on the semiconductor substrate 54 of the mold^- The high resistance semiconductor layer 57 of the mold is epitaxially grown. A resist mask is formed on the resist mask to form high resistance regions 3 and 13. Then, a resist mask is formed, and boron ions are injected into the position of the partition region 2 to remove the resist. Subsequently, a resist mask is formed, phosphorus ions are injected into the position of the drift region 1, and then the resist is removed. [0075] Subsequently, epitaxial growth of an n-type high resistance layer and injection of boron ions or phosphorus ions are repeated to obtain a predetermined thickness. After that, impurities are diffused and activated by heat treatment to form a drift region 1 and a partition region 2. The outermost epitaxial growth layer of the parallel pn structure is preferably a p-type region. From this point onward, the MOSFET is manufactured in the same manner as in the eighth embodiment. [0076] According to the ninth embodiment, as in the eighth embodiment, a MIS type semiconductor capable of allowing current to flow in both directions, achieving low on-resistance in both directions, and ensuring withstand voltage in both directions. By forming the element, it is possible to obtain the effect that the power consumption of the drive circuit can be reduced and simplified. [0077] (Embodiment 10) FIG. 24 is a plan view showing a main part of the horizontal bidirectional superjunction MOSFET according to the tenth embodiment of the present invention, and FIGS. 25 and 26 are vertical cross-sectional views at the cutting lines AA and BB of FIG. 24, respectively. Is. The tenth embodiment is a modification of the eighth embodiment, and the difference between the tenth embodiment and the eighth embodiment is that a trench type MOSFET is formed instead of the planar type MOSFET. In this case, the gate insulating films 7 and 17 are provided on one side surface of the groove which is etched in the high resistance regions 3 and 13, respectively, and are in contact with the base regions 4 and 14, respectively. The source regions 6 and 16 are formed so as to be in contact with the gate insulating films 7 and 17 in the base regions 4 and 14, respectively, and are separated from the high resistance regions 3 and 13 by the base regions 4 and 14. [0078] The gate electrodes 9 and 19 are in contact with the gate insulating films 7 and 17, respectively, and are arranged on the opposite sides of the gate insulating films 7 and 17 from the source regions 6 and 16. Other configurations are the same as in the eighth embodiment. The same components as those in the eighth embodiment are designated by the same reference numerals, and the description thereof will be omitted. Further, as in the case of the eighth embodiment, the description of the operation will be omitted. [0079] Next, a method of manufacturing the bidirectional superjunction MOSFET shown in FIGS. 24 to 26 will be described. First, n of the SOI board^- A resist mask is formed on the high resistance of the mold, and boron ions are injected into the position of the partition region 2 to remove the resist. Subsequently, a resist mask is formed, phosphorus ions are injected into the position of the drift region 1, and then the resist is removed. It should be noted that a mask is used to prevent boron ions and phosphorus ions from being injected into the portions corresponding to the high resistance regions 3 and 13. [0080] [0080] Next, n^- Epitaxy growth of the high resistance layer of the mold and injection of boron ion or phosphorus ion are repeated to obtain a predetermined thickness. After that, impurities are diffused and activated by heat treatment to form a drift region 1 and a partition region 2. The outermost epitaxial growth layer of the parallel pn structure is preferably a p-type region. [0081] Then, trench grooves are dug by etching in the regions where the base regions 4, 14 and the high resistance regions 3, 13 are formed, respectively. Then, after forming the gate insulating films 7 and 17 inside each groove, the groove is filled with polysilicon to form the respective gate electrodes 9 and 19. Subsequently, the source regions 6 and 16 are formed so as to be in contact with the side surfaces of the respective grooves in the base regions 4 and 14, and the interlayer insulating film 45 is deposited on the surface thereof. Then, after opening the contact hole, a metal such as Al-Si is sputtered to form a source electrode (not shown). [0082] According to the tenth embodiment, as in the eighth embodiment, a MIS type semiconductor capable of allowing current to flow in both directions, achieving low on-resistance in both directions, and ensuring withstand voltage in both directions. By forming the element, it is possible to obtain the effect that the power consumption of the drive circuit can be reduced and simplified. [0083] In the above, in the present invention, the element manufactured in the element region is not limited to the MOSFET, and may be a MIS type semiconductor element having other configurations, a bipolar transistor, or the like. In the above description, the metal wiring is actually provided on the source electrode via an interlayer insulating film, and a passivation film or the like is deposited on the metal wiring. However, for convenience, in the above description and the attached drawings, the metal wiring is deposited. I omitted them. [0084] [Effect of the invention] According to the present invention, a current can flow in both directions between the first element region and the second element region, and the on-resistance in either direction can be lowered. Moreover, the withstand voltage can be ensured in both directions. Moreover, since the parallel pn structure can be easily manufactured, the manufacturing process can be simplified and the manufacturing cost can be reduced. [Simple explanation of drawings] FIG. 1 is a vertical cross-sectional perspective view showing a main part of a vertical bidirectional superjunction MOSFET according to a first embodiment of the present invention. FIG. 2 is a vertical cross-sectional perspective view showing a main part in the manufacturing stage of the bidirectional superjunction MOSFET shown in FIG. FIG. 3 is a vertical cross-sectional perspective view showing a main part in the manufacturing stage of the bidirectional superjunction MOSFET shown in FIG. FIG. 4 is a vertical cross-sectional perspective view showing a main part in the manufacturing stage of the bidirectional superjunction MOSFET shown in FIG. 5 is a vertical cross-sectional perspective view showing a main part in the manufacturing stage of the bidirectional superjunction MOSFET shown in FIG. 1. FIG. FIG. 6 is a vertical cross-sectional perspective view showing a main part in the manufacturing stage of the bidirectional superjunction MOSFET shown in FIG. FIG. 7 is a vertical cross-sectional perspective view showing a main part of a vertical bidirectional superjunction MOSFET according to a second embodiment of the present invention. FIG. 8 is a vertical cross-sectional perspective view showing a main part of a vertical bidirectional superjunction MOSFET according to a third embodiment of the present invention. 9 is a vertical cross-sectional perspective view showing a main part in the manufacturing stage of the bidirectional superjunction MOSFET shown in FIG. 8. FIG. FIG. 10 is a vertical cross-sectional view showing a main part of a vertical bidirectional superjunction MOSFET according to a fourth embodiment of the present invention. FIG. 11 is a plan view showing a main part of a horizontal bidirectional superjunction MOSFET according to a fifth embodiment of the present invention. 12 is a vertical cross-sectional view taken along the cutting line AA of FIG. 11. FIG. 13 is a vertical cross-sectional view taken along the cutting line BB of FIG. 11. FIG. FIG. 14 is a plan view showing a main part of a horizontal bidirectional superjunction MOSFET according to a sixth embodiment of the present invention. 15 is a vertical cross-sectional view taken along the cutting line AA of FIG. 14. FIG. 16 is a vertical cross-sectional view taken along the cutting line BB of FIG. 14. FIG. FIG. 17 is a plan view showing a main part of a horizontal bidirectional superjunction MOSFET according to a seventh embodiment of the present invention. FIG. 18 is a vertical cross-sectional view taken along the cutting line AA of FIG. 19 is a vertical cross-sectional view taken along the cutting line BB of FIG. FIG. 20 is a plan view showing a main part of a horizontal bidirectional superjunction MOSFET according to a eighth embodiment of the present invention. 21 is a vertical cross-sectional view taken along the cutting line AA of FIG. 20. FIG. FIG. 22 is a plan view showing a main part of a horizontal bidirectional superjunction MOSFET according to a ninth embodiment of the present invention. FIG. 23 is a vertical cross-sectional view taken along the cutting line AA of FIG. FIG. 24 is a plan view showing a main part of a horizontal bidirectional superjunction MOSFET according to a tenth embodiment of the present invention. 25 is a vertical cross-sectional view taken along the cutting line AA of FIG. 24. FIG. 26 is a vertical cross-sectional view taken along the cutting line BB of FIG. 24. FIG. FIG. 27 is a cross-sectional view of a main part showing a configuration of a conventional vertical bidirectional MOSFET. [Explanation of symbols] 1,11,21 (1st conductive type) Drift region 2,12,22 (2nd conductive type) Partition area 3 Third region (high resistance region) 3 ~ 6 1st element region (1st n-channel MOSFET) 3,13 1st conductive type area 4 First area (base area) 6 First source area 7 First insulating film (gate insulating film (gate oxide film)) 9 First gate electrode 13 Fourth region (high resistance region) 13 ~ 16 2nd element region (2nd n-channel MOSFET) 14 Second area (base area) 16 Second source area 17 Second insulating film (gate insulating film) 19 Second gate electrode 33 First conductive type region (separation region) 46 Insulator (insulating film)