Device for separating signal component, filter device, receiver, communications equipment and communicating method
22 claims: 16 independent, 6 dependent
- 1マルチキャリア変調された信号群(シンボル群)からある信号群を分離する信号成分分離装置であって、 入力信号群をN/2 (m+1) シンボル遅延するシンボル遅延手段と、 入力信号群を0Hzを基準として、-π(k/2 m )ラジアン位相シフトする位相オフセット調整手段と、 上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して当該信号成分分離装置に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と、 上記シンボル遅延手段の出力信号から上記位相オフセット調整手段の出力信号を減算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する他方のシンボル列を算出する減算手段と からなる二分岐回路が二分岐方式で段階的かつ階層的に接続されている、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 信号成分分離装置。
- 2複数チャネルのサブキャリアが周期的に配置されているマルチキャリア変調による多重通信に用いる受信装置であって、 信号群を受信する受信手段と、 信号成分分離装置であって、 入力した信号群を N/2 (m+1) シンボル遅延するシンボル遅延手段と、入力した信号群を 、-π(k/2 m ) ラジアン位相シフトする位相オフセット調整手段と、上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と、上記シンボル遅延手段の出力信号から上記位相オフセット調整手段の出力信号を減算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する他方のシンボル列を算出する減算手段と、からなる二分岐回路が二分岐方式で段階的かつ階層的に接続されている、信号成分分離装置と、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 上記信号成分分離装置で分離した信号群について直交変換を行う直交変換手段と、 上記直交変換した情報を復号する復号手段と、 を具備する、 受信装置。
- 3複数チャネルのサブキャリアが周期的に配置されているマルチキャリア変調による多重通信に用いる、送信装置と受信装置とを有する通信装置であって、 上記送信装置は、 複数チャネルの情報を独立に符号化する符号化手段と、 上記符号化した情報をそれぞれ所定の変調方式に基づいて変調して信号点配置を行う信号点配置手段と、 上記複数の信号点配置した信号を時間周期的に多重化する信号多重化手段と、 上記多重化した信号を逆直交変換する逆直交変換手段と、 上記直交変換した情報を送出する送信手段と、 を有し、 上記受信装置は、 上記送信手段とは異なる送信手段から 送出された信号群を受信する受信手段と、 上記受信した信号群を選択分離する信号成分分離手段と、 上記選択分離された信号を直交変換する直交変換手段と、 上記直交変換した情報を復号する復号手段と を有し、 上記信号成分分離手段は、 入力信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、 入力信号群を 、-π(k/2 m ) ラジアン位相シフトする位相オフセット調整手段と、 上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と、 上記シンボル遅延手段の出力信号から上記位相オフセット調整手段の出力信号を減算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する他方のシンボル列を算出する減算手段と からなる二分岐回路が二分岐方式で段階的かつ階層的に接続されて構成されている、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 通信装置。
- 4上記送信装置における上記信号多重化手段は、上記複数の信号点配置した信号を所定のサブキャリア 間隔で 、チャネルごと に 、周波数をずらして多重化する、 請求項3記載の通信装置。
- 5上記送信装置における上記信号点配置手段における変調方式は直交周波数多重化方式(OFDM方式)を用いる変調方式である、 請求項3記載の通信装置。
- 6上記送信装置における上記逆直交変換処理手段は逆フーリエ変換処理を行い、 上記受信機における上記直交変換処理手段はフーリエ変換処理を行う、 請求項3記載の通信装置。
- 7複数チャネルのサブキャリアが周期的に配置されているマルチキャリア変調による多重通信に用いる受信装置であって、 信号群を受信する受信手段と、 信号成分分離装置であって、 入力信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、入力信号群を 、-π(k/2 m ) ラジアン位相シフトする位相オフセット調整手段と、上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と、上記シンボル遅延手段の出力信号から上記位相オフセット調整手段の出力信号を減算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する他方のシンボル列を算出する減算手段と、からなる二分岐回路が二分岐方式で段階的かつ階層的に接続されている信号成分分離装置と、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 上記信号成分分離装置で分離したシンボル列のうち、所定のサブキャリアのシンボル群を1系列または複数系列選択して出力する信号選択手段と、 上記信号選択手段で選択出力した1系列または複数系列のシンボル群について周波数オフセット補償する周波数オフセット補償手段と、 上記周波数オフセット補償手段のそれぞれの出力信号について直交変換を行う2つの直交変換手段と、 上記直交変換した信号を復号する復号手段と、 を具備する、 受信装置。
- 8上記周波数オフセット補償手段は、 上記周波数オフセット補償のために複素正弦波信号を出力する周波数オフセット補償信号発生手段と、 上記信号群と、上記周波数オフセット補償信号発生手段から出力される複素正弦波信号とを乗算する乗算手段と、 該乗算手段における乗算結果のシンボルを周波数軸に沿って並べ替えるシンボル並べ替え手段と を有する、 請求項7記載の受信装置。
- 9複数チャネルのサブキャリアが周期的に配置されているマルチキャリア変調による多重通信に用いる、送信装置と受信装置とを有する通信装置であって、 上記送信装置は、 複数チャネルの情報を独立に符号化する符号化手段と、 上記符号化した情報をそれぞれ所定の変調方式に基づいて変調して信号点配置を行う信号点配置手段と、 上記複数の信号点配置した信号を時間周期的に多重化する信号多重化手段と、 上記多重化した信号を逆直交変換する逆直交変換手段と、 上記直交変換した信号群を送出する送信手段と、 を有し、 上記受信装置は、 上記送信手段とは異なる送信手段から 送出された信号群を受信する受信手段と、 上記受信した信号群を分離する信号成分分離装置であって、 入力信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、 入力信号群を 、-π(k/2 m ) ラジアン位相シフトする位相オフセット調整手段と、 上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と、 上記シンボル遅延手段の出力信号から上記位相オフセット調整手段の出力信号を減算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する他方のシンボル列を算出する減算手段と、 からなる二分岐回路が二分岐方式で段階的かつ階層的に接続されている信号成分分離装置と、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 上記信号成分分離装置で分離したシンボル列のうち、所定のサブキャリアのシンボル群を1系列または複数系列選択して出力する信号選択手段と、 上記信号選択手段で選択出力した1系列または複数系列のシンボル群について周波数オフセット補償する周波数オフセット補償手段と、 上記周波数オフセット補償手段のそれぞれの出力信号について直交変換を行う2つの直交変換手段と、 上記直交変換した信号を復号する復号手段と、 を具備する、 通信装置。
- 10上記周波数オフセット補償手段は、 上記周波数オフセット補償のために複素正弦波信号を出力する周波数オフセット補償信号発生手段と、 上記信号群と、上記周波数オフセット補償信号発生手段から出力される複素正弦波信号とを乗算する乗算手段と、 該乗算手段における乗算結果のシンボルを周波数軸に沿って並べ替えるシンボル並べ替え手段と を有する、 請求項9記載の通信装置。
- 11複数チャネルのサブキャリアが周期的に配置されているマルチキャリア変調による多重通信に用いる受信装置であって、 信号群を受信する受信手段と、 信号成分分離装置であって、 入力信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、入力信号群を 、-π(k/2 m ) ラジアン位相シフトする位相オフセット調整手段と、上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と、上記シンボル遅延手段の出力信号から上記位相オフセット調整手段の出力信号を減算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する他方のシンボル列を算出する減算手段と、からなる二分岐回路が二分岐方式で段階的かつ階層的に接続されている信号成分分離装置と、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 上記信号成分分離手段で分離した1系列または複数系列のシンボル群について周波数オフセット補償する周波数オフセット補償手段と、 上記周波数オフセット補償手段のそれぞれの出力信号について直交変換を行う2つの直交変換手段と、 上記直交変換した信号を復号する復号手段と、 を具備する、 受信装置。
- 12上記周波数オフセット補償手段は、 上記周波数オフセット補償のために複素正弦波信号を出力する周波数オフセット補償信号発生手段と、 上記信号群と、上記周波数オフセット補償信号発生手段から出力される複素正弦波信号とを乗算する乗算手段と、 該乗算手段における乗算結果のシンボルを周波数軸に沿って並べ替えるシンボル並べ替え手段と を有する、 請求項11記載の受信装置。
- 13複数チャネルのサブキャリアが周期的に配置されているマルチキャリア変調による多重通信に用いる、送信装置と受信装置とを有する通信装置であって、 上記送信装置は、 複数チャネルの情報を独立に符号化する符号化手段と、 上記符号化した情報をそれぞれ所定の変調方式に基づいて変調して信号点配置を行う信号点配置手段と、 上記複数の信号点配置した信号を時間周期的に多重化する信号多重化手段と、 上記多重化した信号を逆直交変換する逆直交変換手段と、 上記直交変換した信号群を送出する送信手段と、 を有し、 上記受信装置は、 上記送信手段とは異なる送信手段から 送出された信号群を受信する受信手段と、 上記受信した信号群を分離する信号成分分離装置であって、 入力信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、 入力信号群を 、-π(k/2 m ) ラジアン位相シフトする位相オフセット調整手段と、 上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と、 上記シンボル遅延手段の出力信号から上記位相オフセット調整手段の出力信号を減算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する他方のシンボル列を算出する減算手段と、 からなる二分岐回路が二分岐方式で段階的かつ階層的に接続されている信号成分分離装置と、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 上記信号成分分離装置で分離した1系列または複数系列のシンボル群について周波数オフセット補償する周波数オフセット補償手段と、 上記周波数オフセット補償手段のそれぞれの出力信号について直交変換を行う2つの直交変換手段と、 上記直交変換した信号を復号する復号手段と、 を具備する、 通信装置。
- 14マルチキャリア変調された信号群から特定の信号を抽出するフィルタ装置であって、 信号成分分離装置であって、 入力信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、入力信号群を 、-π(k/2 m ) ラジアン位相シフトする位相オフセット調整手段と、上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と、上記シンボル遅延手段の出力信号から上記位相オフセット調整手段の出力信号を減算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する他方のシンボル列を算出する減算手段と、からなる二分岐回路が二分岐方式で段階的かつ階層的に接続されている信号成分分離装置と、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 上記信号成分分離装置で分離したシンボル列のうち、特定のサブキャリアのシンボル群を選択して出力する信号選択手段と、 上記信号選択手段で選択出力したシンボル群について周波数オフセット補償する周波数オフセット補償手段と、 を具備する、 フィルタ装置。
- 15複数チャネルのサブキャリアが周期的に配置されているマルチキャリア変調による多重通信に用いる受信装置であって、 マルチキャリア変調された信号群を受信する受信手段と、 上記受信手段で受信したマルチキャリア変調された信号群から特定の信号を抽出するフィルタ装置と、 該フィルタ装置で抽出した信号について直交変換を行う直交変換手段と、 上記直交変換した信号を復号する復号手段と を具備し、 上記フィルタ装置は、 信号成分分離装置であって、 入力信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、入力信号群を 、-π(k/2 m ) ラジアン位相シフトする位相オフセット調整手段と、上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と、上記シンボル遅延手段の出力信号から上記位相オフセット調整手段の出力信号を減算して 当該信号成分分離装置 に入力された多重化信号のうち周波数軸上交互に位置する他方のシンボル列を算出する減算手段と、からなる二分岐回路が二分岐方式で段階的かつ階層的に接続されている信号成分分離装置と、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 上記信号成分分離装置で分離したシンボル列のうち、特定のサブキャリアのシンボル群を選択して出力する信号選択手段と、 上記信号選択手段で選択出力したシンボル群について周波数オフセット補償する周波数オフセット補償手段と、 を具備する、 受信装置。
- 16マルチキャリア変調された信号群から特定の信号を抽出するフィルタ装置であって、 サブキャリアを選択するサブキャリア選択手段と、 上記選択されたサブキャリアに応じて、入力された信号群から特定の信号群を選択して出力する、少なくとも1段の信号選択手段と、 上記信号選択手段で選択した信号について周波数オフセット補償する周波数オフセット補償手段と を具備し、 上記信号選択手段は、 上記選択されたサブキャリアに応じて、入力された信号群を位相シフトする位相オフセット調整手段と、 入力された信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、 上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して 当該フィルタ装置 に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と を有する、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 フィルタ装置。
- 17複数チャネルのサブキャリアが周期的に配置されているマルチキャリア変調による多重通信に用いる受信装置であって、 マルチキャリア変調された信号群を受信する受信手段と、 上記受信手段で受信したマルチキャリア変調された信号群から特定の信号を抽出するフィルタ装置と、 該フィルタ装置で抽出した信号について直交変換を行う直交変換手段と、 上記直交変換した信号を復号する復号手段と を具備し、 上記フィルタ装置は、 サブキャリアを選択するサブキャリア選択手段と、 上記選択されたサブキャリアに応じて、入力された信号群から特定の信号群を選択して出力する、少なくとも1段の信号選択手段と、 上記信号選択手段で選択した信号について周波数オフセット補償する周波数オフセット補償手段と を具備し、 上記信号選択手段は、 上記選択されたサブキャリアに応じて、入力された信号群を位相シフトする位相オフセット調整手段と、 入力された信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、 上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して上記信号選択出力手段に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と を有する、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 受信装置。
- 18マルチキャリア変調された信号群から特定の信号を抽出するフィルタ装置であって、 選択すべきチャネルに応じた複素正弦波信号を出力する通過サブキャリア選択信号出力手段と、 上記通過サブキャリア選択出力手段から出力された複素正弦波信号と、入力信号群との乗算を行う乗算手段と、 上記乗算手段における乗算結果のうち、特定の信号群を選択する少なくとも1段の信号成分分離手段と、 上記信号成分分離装置の出力を周波数軸上に並べ替えるシンボル並べ替え手段と を具備し、 上記信号成分分離手段は、 入力信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、 上記シンボル遅延手段の出力信号と上記入力信号群とを加算して周波数軸上交互に位置する一方のシンボル列を算出する加算手段と からなる回路が二分岐方式で段階的かつ階層的に接続されている、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 フィルタ装置。
- 19複数チャネルのサブキャリアが周期的に配置されているマルチキャリア変調による多重通信に用いる受信装置であって、 マルチキャリア変調された信号群を受信する受信手段と、 上記受信手段で受信したマルチキャリア変調された信号群から特定の信号を抽出するフィルタ装置と、 該フィルタ装置で抽出した信号について直交変換を行う直交変換手段と、 上記直交変換した信号を復号する復号手段と を具備し、 上記フィルタ装置は、 選択すべきチャネルに応じた複素正弦波信号を出力する通過サブキャリア選択信号出力手段と、 上記通過サブキャリア選択出力手段から出力された複素正弦波信号と、入力信号群との乗算を行う乗算手段と、 上記乗算手段における乗算結果のうち、特定の信号群を選択する少なくとも1段の信号成分分離手段と、 上記信号成分分離装置の出力を周波数軸上に並べ替えるシンボル並べ替え手段と を有し、 上記信号成分分離手段は、 入力信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、 上記シンボル遅延手段の出力信号と上記入力信号群とを加算して周波数軸上交互に位置する一方のシンボル列を算出する加算手段と からなる回路が二分岐方式で段階的かつ階層的に接続されている、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 受信装置。
- 20複数チャネルのサブキャリアが周期的に配置されているマルチキャリア変調による多重通信に用いる受信装置であって、 マルチキャリア変調された信号群を受信する受信手段と、 入力信号群をスイッチングするスイッチング手段と、 上記受信手段で受信したマルチキャリア変調された信号群を保持するバッファ手段と、 上記スイッチング手段の後段に接続され、入力された信号群のうち特定の信号群を選択出力するフィルタ装置と、 上記フィルタ装置で抽出した信号について直交変換を行う直交変換手段と、 上記直交変換した信号を復号する復号手段と を具備し、 上記スイッチング手段は1シンボル分の信号群を上記フィルタ装置に出力し、上記バッファ手段はその間、入力された1シンボル分の信号群を保持し、上記フィルタ装置への信号送出終了後、上記バッファ手段に保持した信号群を上記スイッチング手段を介して上記フィルタ装置に送出し、 上記フィルタ装置は、上記スイッチング手段を介して入力された信号群のうち指定されたサブキャリアのみ選択出力し、 上記フィルタ装置は、 入力信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、入力信号群を、 -π(k/2 m ) ラジアン位相シフトする位相オフセット調整手段と、上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して 当該フィルタ装置 に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と、上記シンボル遅延手段の出力信号から上記位相オフセット調整手段の出力信号を減算して 当該フィルタ装置 に入力された多重化信号のうち周波数軸上交互に位置する他方のシンボル列を算出する減算手段と、からなる二分岐回路が二分岐方式で段階的かつ階層的に接続されている信号成分分離装置と、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 上記信号成分分離装置で分離したシンボル列のうち、特定のサブキャリアのシンボル群を選択して出力する信号選択手段と、 上記信号選択手段で選択出力したシンボル群について周波数オフセット補償する周波数オフセット補償手段と、 を具備する、 受信装置。
- 21複数チャネルのサブキャリアが周期的に配置されているマルチキャリア変調による多重通信に用いる受信装置であって、 マルチキャリア変調された信号群を受信する受信手段と、 上記受信手段で受信したマルチキャリア変調された信号群のうち偶数キャリアの信号群を選択して出力する第1のフィルタ装置と、 上記受信手段で受信したマルチキャリア変調された信号群のうち奇数キャリアの信号群を選択して出力する第2のフィルタ装置と、 上記第2のフィルタ装置の出力信号群を保持するバッファ手段と、 上記第1のフィルタ装置の出力信号群をスイッチングするスイッチング手段と、 上記スイッチング手段の後段に接続され、スイッチングされた出力信号について直交変換を行う直交変換手段と、 上記直交変換した信号を復号する復号手段と を具備し、 上記スイッチング手段は上記第1のフィルタ装置の出力信号を上記直交変換手段に送出し、上記直交変換手段への信号送出終了後、上記バッファ手段に保持した信号群を上記スイッチング手段を介して上記直交変換手段に送出し、 上記第1および第2のフィルタ装置はそれぞれ、 入力信号群を N/2 (m+1) シンボル 遅延するシンボル遅延手段と、入力信号群を 、-π(k/2 m ) ラジアン位相シフトする位相オフセット調整手段と、上記シンボル遅延手段の出力信号と上記位相オフセット調整手段の出力信号を加算して 当該フィルタ装置 に入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出する加算手段と、上記シンボル遅延手段の出力信号から上記位相オフセット調整手段の出力信号を減算して 当該フィルタ装置 に入力された多重化信号のうち周波数軸上交互に位置する他方のシンボル列を算出する減算手段と、からなる二分岐回路が二分岐方式で段階的かつ階層的に接続されている信号成分分離装置と、 ただし、mは二分岐回路の段数の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 上記信号成分分離装置で分離したシンボル列のうち、特定のサブキャリアのシンボル群を選択して出力する信号選択手段と、 上記信号選択手段で選択出力したシンボル群について周波数オフセット補償する周波数オフセット補償手段と を具備する、 受信装置。
- 22送信手段において、 複数チャネルの情報を独立に符号化し、上記符号化した情報をそれぞれ所定の変調方式に基づいて変調して信号点配置を行い、上記複数の信号点配置した信号を時間周期的に多重化し、上記多重化した信号を逆直交変換し、 当該送信手段が 上記直交変換した情報を送出する符号化送信工程と、 受信手段において、上記送信手段とは異なる送信手段から 送出された信号を受信し、上記受信した直交変換処理後の多重化信号のうち、希望するチャネルの信号のみ選択出力し、上記選択出力された信号を直交変換し、上記直交変換した情報を復号する受信復号工程と を有する通信方法であって、 上記受信工程における信号選択処理は、 入力信号群をN/2 (m+1) シンボル遅延し、 入力信号群を0Hzを基準として、-π(k/2 m ) ラジアンだけ位相シフトし、 上記シンボル遅延した信号と上記位相シフトした信号を加算して 上記受信手段に 入力された多重化信号のうち周波数軸上交互に位置する一方のシンボル列を算出するか、上記シンボル遅延した信号から上記位相シフトした信号を減算して上記 上記受信手段に 入力された多重化信号のうち周波数軸上交互に位置する他方のシンボル列を算出する、 方法を二分岐的かつ段階的に行う、 ただし、mは二分岐処理の段の位置を示すパラメータであり、 Nは1変調時間内に存在するシンボルの数であり、 kは0(Hz)を基準としてサブキャリアの周波数オフセット を持つ信号群が入力されていることを示すパラメータである、 通信方法。
Independent claims22
1 paragraph, as filed
[0001] [Technical field to which the invention belongs] The present invention relates to a communication device (communication system), a transmitter and a receiver, and a communication method, and in particular, a wireless transmitter used in a digital communication device (system) and a digital communication device (system) that perform multicarrier modulation. (Wireless transmitter) The present invention relates to a wireless receiver (wireless receiver) and its communication method. More specifically, the present invention is a signal component separator that separates a multicarrier signal multiplexed by the Orthogonal Frequency Division Multiplexing (OFDM) method into a symbol sequence, a specific symbol from a multicarrier signal. The present invention relates to a filter device for extracting, and a signal receiving device having these signal component separators, filter devices, and the like. [0002] [Conventional technology] A DAB (Digital Audio Broadcasting) system is illustrated as an example of a modulated signal by the OFDM method. The DAB system is known as a high-quality digital audio terrestrial broadcasting system that can receive mobile data developed by the EUREKA147 project. Digital satellite audio broadcasting, which applies the DAB system to satellite broadcasting, is also being put into practical use. [0003] As a modulation method used in such a digital communication system (device), an OFDM method having a feature of being resistant to multipath fading, ghost, etc. has been proposed. The OFDM method is usually a multicarrier modulation method using tens to hundreds of quadrature carriers, and each carrier is modulated by a modulation method such as QAM or PSK. In DAB systems and the like, multi-carrier communication is applied to transmit multiple-channel digital audio signals. [0004] 21 (A) and 21 (B) are diagrams showing a configuration example of a digital wireless communication system using an OFDM system applied to a DAB system or the like as a multi-carrier modulation system. Figures 21 (A) and 21 (B) simplify and illustrate a part of the DAB system. In the following explanation, the DAB system will be illustrated and the explanation will be focused on the part related to multiplexing. [0005] The wireless transmitter 10 of the OFDM wireless communication system illustrated in FIG. 21 (A) includes a coding circuit 11, a symbol mapping circuit 12, a multiplexer (signal multiplexing processing circuit) 13, a frequency interleaving circuit 14, and a frequency interleaving circuit 14. It has an inverse fast Fourier transform (IFFT) circuit 15, a radio transmission circuit 16, and an antenna 17. [0006] Each bit of the information bit stream is mapped to a transmission symbol in the symbol mapping circuit 12 after processing such as coding and interleaving is performed in the coding circuit 11. This work is performed separately for each channel, and in the example shown in FIG. 21 (A), for example, a symbol of 64 ksps (symbols / second) per second is generated per channel. [0007] These symbol streams are multiplexed symbol streams by simply connecting them in series in the multiplexer 13. For example, if 18 channels of 64ksps are multiplexed, the transmission rate of the multiplexed symbol stream will be 1152ksps (= 18x64ksps). The multiplexed symbol stream is rearranged by the frequency interleaving process in the frequency interleaving circuit 14. By this work, the symbols of each channel will be arranged separately. [0008] After that, in the symbol stream, the symbols arranged separately by IFFT processing in the inverse fast Fourier transform (IFFT) circuit 15 are arranged on the frequency axis, and the symbol representations on these frequency axes are converted into symbols on the time axis and transmitted. It is sent from the circuit 16 to the air via the antenna 17. [0009] FIG. 22 illustrates an example of a symbol string that is multi-carriered into 6 carriers output from the transmitter 10. [0010] So far, it has not been performed to extract only a specific symbol of a plurality of multi-carrier-ized symbols (symbol series) described above. Therefore, in a wireless signal receiver, it is assumed that a method of extracting a desired symbol or carrier component from the symbol sequence illustrated in FIG. 22 is performed using an existing technique. [0011] FIG. 23 is a diagram showing a first method of separating multicarrier signals. In this method, a plurality of band filters having the frequency band characteristics of the corresponding carriers are provided, and the corresponding symbols are extracted by the respective band pass filters. As such a filter, for example, a comb-shaped filter can be used. [0012] However, such a method is not suitable for separating symbols of a modulation method such as OFDM in which carriers are closely spaced. That is, in the modulation method by the OFDM method, since a large number of carriers are packed in a certain frequency band, the isolation of adjacent signal components cannot be sufficiently obtained. Therefore, in order to identify the carrier signals of adjacent frequencies, each band passing filter is used. Must have steep frequency characteristics. [0013] For example, it is difficult to prepare various highly accurate filters having such steep frequency characteristics with a comb-type filter, and it is difficult to realize because the price is considerably high. [0014] FIG. 24 is a diagram showing a second method of separating the multicarrier signal. In FIG. 24, the signal received by the receiving circuit 22 is subjected to a fast Fourier transform by the fast Fourier transform (FFT) circuit 23 to generate a received symbol sequence arranged on the frequency axis, and the symbol sequence is generated by the demultiplexer (signal separator) 29. Is separated into separate symbols so that only specific symbols can be selected. However, in this method, even when a specific symbol is extracted, a high-speed Fourier transform is performed on all the symbols, so that a complicated FFT circuit 23 must be provided, which complicates the device configuration. [0015] FIG. 25 is a schematic configuration diagram in the case of extracting only the carrier signal components at regular intervals. In FIG. 25, a plurality of band-passing filters having a plurality of different pass-band characteristics are provided, and signals band-limited by the filters are added by the addition circuits 28A and 28B to obtain a desired signal. Also in this case, for example, a comb filter is used as the band filter. However, since this method is also a multi-carrier method like the method of FIG. 23, it is possible to prepare a highly accurate filter having a steep frequency characteristic and the carriers are clogged and the signal component cannot be sufficiently isolated. We encounter the problem of difficulty in terms of price and so on. [0016] FIG. 21 (B) is a schematic configuration diagram of a radio signal receiver in the DAB system illustrated in FIG. 21 (A). The wireless receiver 20 of the OFDM wireless communication system 1 shown in FIG. 21 (B) includes an antenna 21, a receiving circuit 22, a fast Fourier transform (FFT) circuit 23, a symbol selection circuit 24, and a bit extraction circuit 25. , With a decoding circuit 26. [0017] A baseband signal is obtained by frequency-converting a signal in a desired frequency band received by the antenna 21 in the receiving circuit 22 and extracting only a baseband signal component. Since the baseband signal obtained in this way is represented on the time axis of the signal whose information is arranged on the frequency axis, the FFT circuit 23 performs FFT processing and arranges the information on the frequency axis. Extract subcarriers. At this time, the symbols output by the FFT processing are subcarrier groups of the entire received signal band (for example, information for 1152 ksps is included in this example). [0018] The symbol selection circuit 24 extracts a symbol from the subcarrier group from the presence position of the symbol of the desired channel arranged by the frequency interleaving performed on the transmitting side illustrated in FIG. 21 (A). As a result, 64 kbps, which is the information of the desired channel, is extracted. [0019] By extracting the received bit stream from the symbol stream of the desired channel thus obtained in the bit extraction circuit 25 to obtain a coded bit stream, and then decoding this in the decoding circuit 26, the desired channel can be obtained. You are getting an information bitstream. [0020] [Problems to be Solved by the Invention] In this way, in the OFDM system, multiplexing is performed by assigning symbols of different channels to each subcarrier, but the wireless receiver 20 transmits all the multiplexed signals for all the transmitted channels. After receiving and extracting the symbols for all channels by the FFT circuit 23, the channel is selected in the symbol selection circuit 24, which exceeds the amount of calculation required for the information for one channel that was originally required. The calculation is FFT processing performed in the FFT circuit 23. That is, the FFT signal processing is performed in the FFT circuit 23 including the channels that the wireless receiving device 20 does not want, and there is a problem that the circuit scale of the FFT circuit 23 becomes large. [0021] [0021] As a method for solving the above-mentioned problems, the inventor of the present application proposes, for example, the invention described in Japanese Patent Application No. 11-140442, which was filed on May 20, 1999. In the invention described in Japanese Patent Application No. 11-140442, a circuit for separating a symbol string for each alternating subcarrier from a symbol sequence is provided in a multi-stage hierarchical manner by a two-branch method. [0022] An object of the present invention is to solve the above problem by a method different from the invention described in Japanese Patent Application No. 11-140442, and to efficiently extract only one symbol. [0023] An object of the present invention is to provide a signal component separator capable of efficiently bifurcating a symbol sequence. [0024] Another object of the present invention is to provide a filter device capable of efficiently extracting a specific symbol from a symbol sequence. [0025] Yet another object of the present invention is to provide a receiving device having the signal component separating device and / or a filter circuit. [0026] Still another object of the present invention is to provide a communication system having the receiving device and the transmitting device. [0027] Another object of the present invention is to provide a communication method for performing the reception process and the transmission process. [0028] [Means for solving problems] According to the first aspect of the present invention, it is a signal component separator that separates a certain signal group from a multicarrier-modulated signal group (symbol group). Input signal group N / 2<sup>(m + 1)</sup> Symbol delay means and symbol delay means Input signal group is -π (k / 2) with reference to 0Hz<sup>m</sup> ) Radian phase shift phase offset adjusting means, An adding means that adds the output signal of the symbol delay means and the output signal of the phase offset adjusting means to calculate one of the multiplexed signals input to the signal selection output means that is alternately located on the frequency axis. When, Subtraction means for subtracting the output signal of the phase offset adjusting means from the output signal of the symbol delay means and calculating the other symbol string alternately located on the frequency axis among the multiplexed signals input to the signal selection output means. When Provided is a signal component separator in which a two-branch circuit consisting of two branches is connected stepwise and hierarchically in a two-branch system. However, m is a parameter that indicates the position of the number of stages in the two-branch circuit. N is the number of symbols present in one modulation time, k is the frequency offset of the subcarrier with respect to 0 (Hz) It is a parameter indicating that a signal group having is input. [0029] According to the second aspect of the present invention, there is provided a receiving device to which the signal component separating device is applied and used for multiplex communication by multicarrier modulation in which subcarriers of a plurality of channels are periodically arranged. The receiving device is The receiving means for receiving the signal group and Input signal group N / 2<sup>(m + 1)</sup> The symbol delay means for symbol delay and the input signal group are -π (k / 2).<sup>m</sup> ) Radian phase shift adjusting means, the output signal of the symbol delay means and the output signal of the phase offset adjusting means are added, and the multiplexed signals input to the signal selection output means alternate on the frequency axis. Of the multiplexing signals input to the signal selection output means by subtracting the output signal of the phase offset adjusting means from the output signal of the symbol delay means and the addition means for calculating one of the positioned symbol strings, on the frequency axis. A subtraction means that calculates the other symbol strings that are alternately located, and a signal component separator in which a two-branch circuit consisting of two-branch circuits is connected stepwise and hierarchically in a two-branch method. Orthogonal conversion means for performing orthogonal conversion on the signal group separated by the signal component separator, and With a decoding means for decoding the orthogonally converted information To be equipped. [0030] According to the third aspect of the present invention, a communication having a transmitting device and a receiving device used for multiplex communication by multi-carrier modulation in which subcarriers of a plurality of channels are periodically arranged to which the receiving device is applied. Equipment is provided. The transmission device of the communication device includes a coding means that independently encodes information of a plurality of channels and a signal point arrangement means that modulates the encoded information based on a predetermined modulation method and arranges signal points. A signal multiplexing means that multiplexes the signals arranged at the plurality of signal points in a time-periodic manner, an inverse orthogonal conversion means that performs inverse orthogonal conversion of the multiplexed signals, and a transmission means that transmits the orthogonally converted information. And have. The receiving device of the communication device is a component of the receiving device, that is, a receiving means for receiving the transmitted signal group, a signal component separating means for selectively separating the received signal group, and the selective separation. It has an orthogonal conversion means for orthogonally converting the signal, and a decoding means for decoding the orthogonally converted information. The signal component separating means has the above-described configuration. [0031] Preferably, the signal multiplexing means in the transmitting device multiplexes the signals arranged at the plurality of signal points by shifting the frequency for each channel with a predetermined subcarrier. [0032] Further, preferably, the modulation method in the signal point arrangement means in the transmission device is a modulation method using an orthogonal frequency multiplexing method (OFDM method). [0033] Further, preferably, the inverse orthogonal transform processing means in the transmitter performs an inverse Fourier transform process, and the orthogonal transform process means in the receiver performs a Fourier transform process. [0034] According to the fourth aspect of the present invention, it is a receiving device used for multiplex communication by multicarrier modulation in which subcarriers of a plurality of channels are periodically arranged. The receiving means for receiving the signal group and Input signal group N / 2<sup>(m + 1)</sup> The symbol delay means to be delayed and the input signal group are -π (k / 2).<sup>m</sup> ) Radian phase shift adjusting means, the output signal of the symbol delay means and the output signal of the phase offset adjusting means are added, and the multiplexed signals input to the signal selection output means alternate on the frequency axis. Of the multiplexing signals input to the signal selection output means by subtracting the output signal of the phase offset adjusting means from the output signal of the symbol delay means and the addition means for calculating one of the positioned symbol strings, on the frequency axis. A subtraction means for calculating the other symbol strings located alternately, a signal component separator in which a two-branch circuit composed of two-branch circuits is connected stepwise and hierarchically in a two-branch method. A signal selection means for selecting and outputting one or more series of symbols of a predetermined subcarrier from the symbol strings separated by the signal component separator. Frequency offset compensating means for frequency offset compensating for one or more series of symbols selected and output by the above signal selecting means, and Two orthogonal conversion means that perform orthogonal conversion for each output signal of the frequency offset compensation means, and With a decoding means for decoding the orthogonally converted signal A receiving device comprising the above is provided. [0035] Preferably, the frequency offset compensating means is a frequency offset compensating signal generating means that outputs a complex sine wave signal for the frequency offset compensating, the signal group, and the complex sine that is output from the frequency offset compensating signal generating means. It has a multiplication means for multiplying the wave signal and a symbol rearrangement means for rearranging the symbols of the multiplication result in the multiplication means along the frequency axis. [0036] According to the fifth aspect of the present invention, the transmitting device and the receiving device used for multiplex communication by multicarrier modulation in which subcarriers of a plurality of channels are periodically arranged using the receiving device of the fourth aspect. A communication device having the above is provided. [0037] According to the sixth aspect of the present invention, it is a receiving device used for multiplex communication by multicarrier modulation in which subcarriers of a plurality of channels are periodically arranged. The receiving means for receiving the signal group and Input signal group N / 2<sup>(m + 1)</sup> The symbol delay means to be delayed and the input signal group are -π (k / 2).<sup>m</sup> ) Radian phase shift adjusting means, the output signal of the symbol delay means and the output signal of the phase offset adjusting means are added, and the multiplexed signals input to the signal selection output means alternate on the frequency axis. Of the multiplexing signals input to the signal selection output means by subtracting the output signal of the phase offset adjusting means from the output signal of the symbol delay means and the addition means for calculating one of the positioned symbol strings, on the frequency axis. A subtraction means for calculating the other symbol strings located alternately, a signal component separator in which a two-branch circuit composed of two-branch circuits is connected stepwise and hierarchically in a two-branch method. Frequency offset compensating means for frequency offset compensating for one or more series of symbols separated by the above signal component separating means, and Two orthogonal conversion means that perform orthogonal conversion for each output signal of the frequency offset compensation means, and With a decoding means for decoding the orthogonally converted signal A receiving device comprising the above is provided. [0038] According to the seventh aspect of the present invention, a communication device having a transmitting device and a receiving device used for multiplex communication by multi-carrier modulation in which subcarriers of a plurality of channels are periodically arranged to which the receiving device is applied. Is provided. [0039] According to the eighth aspect of the present invention, it is a filter device that extracts a specific signal from a multicarrier-modulated signal group. Input signal group N / 2<sup>(m + 1)</sup> The symbol delay means to be delayed and the input signal group are -π (k / 2).<sup>m</sup> ) Radian phase shift adjusting means, the output signal of the symbol delay means and the output signal of the phase offset adjusting means are added, and the multiplexed signals input to the signal selection output means alternate on the frequency axis. Of the multiplexing signals input to the signal selection output means by subtracting the output signal of the phase offset adjusting means from the output signal of the symbol delay means and the addition means for calculating one of the positioned symbol strings, on the frequency axis. A subtraction means for calculating the other symbol strings located alternately, a signal component separator in which a two-branch circuit composed of two-branch circuits is connected stepwise and hierarchically in a two-branch method. A signal selection means for selecting and outputting a symbol group of a specific subcarrier from the symbol strings separated by the signal component separator, and With the frequency offset compensating means for frequency offset compensating for the symbol group selected and output by the above signal selecting means A filter device comprising the above is provided. [0040] According to the ninth aspect of the present invention, it is a receiving device to which the above-mentioned filter device is applied and used for multiplex communication by multicarrier modulation in which subcarriers of a plurality of channels are periodically arranged. A receiving means for receiving a multicarrier-modulated signal group, and A filter device that extracts a specific signal from the multicarrier-modulated signal group received by the receiving means, and Orthogonal conversion means for performing orthogonal conversion on the signal extracted by the filter device, and With a decoding means for decoding the orthogonally converted signal A receiving device comprising the above is provided. [0041] According to the tenth aspect of the present invention, it is a filter device that extracts a specific signal from a multicarrier-modulated signal group. Subcarrier selection means for selecting subcarriers, At least one stage of signal selection means that selects and outputs a specific signal group from the input signal group according to the selected subcarrier, and With a frequency offset compensating means that compensates for the frequency offset of the signal selected by the above signal selecting means A filter device comprising the above is provided. [0042] According to the eleventh aspect of the present invention, it is a receiving device to which the above-mentioned filter device is applied and used for multiplex communication by multicarrier modulation in which subcarriers of a plurality of channels are periodically arranged. A receiving means for receiving a multicarrier-modulated signal group, and A filter device that extracts a specific signal from the multicarrier-modulated signal group received by the receiving means, and Orthogonal conversion means for performing orthogonal conversion on the signal extracted by the filter device, and With a decoding means for decoding the orthogonally converted signal A receiving device comprising the above is provided. [0043] According to the twelfth aspect of the present invention, it is a filter device that extracts a specific signal from a multicarrier-modulated signal group. Passing subcarrier selection signal output means that outputs a complex sine wave signal according to the channel to be selected, A multiplication means for multiplying the complex sine wave signal output from the passing subcarrier selection output means and the input signal group, and Of the multiplication results in the above multiplication means, at least one stage of signal component separation means for selecting a specific signal group, and With a symbol rearranging means for rearranging the output of the signal component separator on the frequency axis A filter device comprising the above is provided. [0044] According to the thirteenth aspect of the present invention, it is a receiving device to which the above-mentioned filter device is applied and used for multiplex communication by multicarrier modulation in which subcarriers of a plurality of channels are periodically arranged. A receiving means for receiving a multicarrier-modulated signal group, and A filter device that extracts a specific signal from the multicarrier-modulated signal group received by the receiving means, and Orthogonal conversion means for performing orthogonal conversion on the signal extracted by the filter device, and With a decoding means for decoding the orthogonally converted signal A receiving device comprising the above is provided. [0045] According to the fourteenth aspect of the present invention, it is a receiving device used for multiplex communication by multicarrier modulation in which subcarriers of a plurality of channels are periodically arranged. A receiving means for receiving a multicarrier-modulated signal group, and A switching means for switching the input signal group and A buffer means for holding the multicarrier-modulated signal group received by the receiving means, and a buffer means. A filter device connected to the subsequent stage of the switching means and selectively outputting a specific signal group from the input signal groups, Orthogonal conversion means that performs orthogonal conversion on the signal extracted by the above filter device, and With a decoding means for decoding the orthogonally converted signal Equipped with The switching means outputs a signal group for one symbol to the filter device, and the buffer means holds the input signal group for one symbol during that time, and after the signal transmission to the filter device is completed, the buffer means. The signal group held in the above is sent to the filter device via the switching means. The filter device selectively outputs only a designated subcarrier from the signal group input via the switching means. A receiving device is provided. [0046] The above-mentioned various filter devices can be applied to the above-mentioned filter device. [0047] According to the fifteenth aspect of the present invention, it is a receiving device used for multiplex communication by multicarrier modulation in which subcarriers of a plurality of channels are periodically arranged. A receiving means for receiving a multicarrier-modulated signal group, and A first filter device that selects and outputs an even-numbered carrier signal group from the multicarrier-modulated signal group received by the receiving means, and a first filter device. A second filter device that selects and outputs an odd-numbered carrier signal group from the multicarrier-modulated signal group received by the receiving means, and a second filter device. A buffer means for holding the output signal group of the second filter device and A switching means for switching the output signal group of the first filter device and An orthogonal conversion means connected to the subsequent stage of the switching means and performing orthogonal conversion on the switched output signal, With a decoding means for decoding the orthogonally converted signal Equipped with The switching means sends the output signal of the first filter device to the orthogonal conversion means, and after the signal transmission to the orthogonal conversion means is completed, the signal group held in the buffer means is transmitted to the orthogonal conversion means via the switching means. Send to conversion means, A receiving device is provided. [0049] According to the 16th aspect of the present invention, it is a communication method. Independently encodes information from multiple channels Each of the above encoded information is modulated based on a predetermined modulation method to arrange signal points, and then the signal points are arranged. The signals arranged at the above-mentioned multiple signal points are multiplexed in a time-periodic manner. Inverse orthogonal conversion of the above multiplexed signal is performed. Send the above orthogonally converted information Coded transmission process and Upon receiving the above transmitted signal, Of the received multiplexed signals after orthogonal conversion processing, only the signals of the desired channel are selected and output. The above selected output signal is orthogonally converted and Decrypt the above orthogonally converted information With the reception decoding process Is a communication method that has The signal selection process in the reception process is N / 2<sup>(m + 1)</sup> Symbol delay, π (k / 2<sup>m</sup> ) Phase shift only in radians, The symbol-delayed signal and the phase-shifted signal are added to calculate one of the input multiplexed signals that is alternately located on the frequency axis, or the phase-shifted signal is phase-shifted from the symbol-delayed signal. The signal is subtracted to calculate the other symbol string that is alternately located on the frequency axis among the above-input multiplexed signals. The method is bifurcated and stepwise A communication method is provided. [0050] BEST MODE FOR CARRYING OUT THE INVENTION A preferred embodiment of the communication device (communication system), the transmitter (transmitter), the receiver (receiver), and the communication method of the present invention will be described with reference to the accompanying drawings. [0051] In the following embodiments, a wireless communication system will be exemplified as a communication system, but the present invention is not limited to the wireless communication system and can be applied to a wired communication system. However, in the following embodiments, a wireless communication system, eg, an orthogonal frequency division multiplexing (OFDM) system similar to a DAB system, is used to illustrate the communication system. [0052]<u style="single">First Embodiment of Communication Equipment</u>The communication system, transmitter, receiver, and communication method of the present invention with reference to FIGS. 1 (A), (B), 2 (A), (B), (C), and FIG. 1 The embodiment is described. [0053] 1 (A) and 1 (B) are configuration diagrams of the communication system, the transmitting device and the receiving device of the present invention, and a digital wireless communication system using the OFDM method as the multicarrier modulation method as one embodiment of the communication method. FIG. 1A is a configuration diagram of a transmitter 30 of an OFDM wireless communication system, and FIG. 1B is a configuration diagram of a receiver 40 of an OFDM wireless communication system. [0054] The transmitting device 30 and the receiving device 40 form an OFDM wireless communication system. [0055]<u style="single">Transmitter (transmitter) 30</u>The transmitter (transmitter) 30 will be described. The transmitter 30 of the OFDM type wireless communication system illustrated in FIG. 1 (A) is a coding circuit 31 for the first channel.<sub>1</sub> And 1st channel symbol mapping circuit 32<sub>1</sub> , 2nd channel coding circuit 31<sub>2</sub> And symbol mapping circuit for 2nd channel 32<sub>2</sub> , ~, Coded circuit for M channel 31<sub>M</sub> And symbol mapping circuit for M channel 32<sub>M</sub> Have. This example shows an example of encoding an information bitstream of M channel. The transmission device 30 further includes a multiplexer (signal multiplexing processing circuit) 34, a scramble processing / IFFT / guard time addition / window processing circuit 36, a transmission circuit 38, and an antenna 39. [0056] The transmitter 30 thus has a plurality of coding circuits 31.<sub>1</sub> ~31<sub>M</sub> And multiple symbol mapping circuits 32<sub>1</sub> ~32<sub>M</sub> On the other hand, it has one multiplexer 34, scramble processing / IFFT / guard time addition / window processing circuit 36, and transmission circuit 38. The coding circuit 31 and the symbol mapping circuit 32 are provided for the number of channels. [0057] Coding circuit 31 for independent information bitstreams of channels 1 to M<sub>1</sub> ~31<sub>M</sub> In each case, processing such as coding and interleaving is performed independently. [0058] [0058] Coding circuit 31<sub>1</sub> ~31<sub>M</sub> A specific example of the coding process in the above will be described. When an OFDM wireless communication system is applied to the transmission of an audio signal such as a DAB system, since the bit signal of the information bit stream is an audio signal, the coding circuit 31<sub>1</sub> ~31<sub>M</sub> Performs coding processing on each audio signal. Coding circuit 31<sub>1</sub> ~31<sub>M</sub> Also performs interleaving processing as needed. [0059] Coding circuit 31<sub>1</sub> ~31<sub>M</sub> The coded bit signal of each channel generated in is the symbol mapping circuit 32.<sub>1</sub> ~32<sub>M</sub> Is mapped to the transmit symbol and a symbol stream is generated. [0060] Symbol mapping circuit 32<sub>1</sub> ~32<sub>M</sub> In, various modulation methods applied to the OFDM method can be applied. As such a modulation method, various modulation methods such as multi-level QAM and PSK can be applied. In this way, the symbol mapping circuit 32<sub>1</sub> ~32<sub>M</sub> In, as illustrated in FIG. 2 (A), an independent symbol stream is generated in each channel. [0061] The symbol stream for each of multiple channels is multiplexed in the multiplexer 34 and generated as a multiple symbol stream. The multiplexer 34 has the switch circuit illustrated in FIG. 2 (B), and as a result of the multiplexing process of the multiplexer 34, the symbols of the multiple channels illustrated in FIG. 2 (A) are illustrated in FIG. 2 (C). It becomes a multiplexed symbol stream in which symbols of a plurality of channels are arranged on the frequency axis. [0062] The multiplexed symbol stream multiplexed in the multiplexer 34 is subjected to random phase shift processing (RPS: Randam Phase Shift) and random orthogonal conversion processing (ROT: Randam Orthogonal) in the scramble processing, IFFT, guard time addition, and window processing circuit 36. It is scrambled by Transform) etc. [0063] In the scramble processing, IFFT, guard time addition, and window processing circuit 36, the frequency domain multiplexed symbol stream is converted to the time domain multiplexed symbol stream by the inverse Fourier transform processing (IFFT processing). Further, in the scramble processing, IFFT, guard time addition, and window processing circuit 36, guard time is added and window processing (window processing) is performed. [0064] The scramble processing / IFFT / guard time addition / window processing circuit 36 is a general term for scramble processing, inverse fast Fourier transform (IFFT) processing, guard time processing, window processing (window processing), etc., which will be described later. These processes are shown as one means, and these processes may be separated into individual circuits or individual means. [0065] The scramble processing, IFFT, guard time addition, and windowing processing in the scramble processing, IFFT, guard time addition, and windowing processing circuit 36 are not essential for the present invention. However, when scrambling is performed, the confidentiality (confidentiality) of communication is increased. [0066] Although IFFT has been illustrated as a typical example of the orthogonal transform, instead of the IFFT in the scramble processing, IFFT, guard time addition, and window processing circuit 36, another orthogonal transform processing, for example, the inverse discrete cosine transform (IDCT) Cosine Transform) processing can also be performed. [0067] From the above, the scramble processing / IFFT / guard time addition / windowing processing circuit 36 is basically a circuit or means for performing orthogonal transform processing. [0068] [0068] The output symbol of the scramble processing, IFFT, guard time addition, and window processing circuit 36 is convoluted with the high frequency signal in the transmission circuit 38 and frequency-converted to a desired frequency band, and then transmitted in the air via the antenna 39. .. [0069] The internal configuration of the multiplexer 34 and the arrangement of symbols of each channel generated by this multiplexing method will be described with reference to FIGS. 2 (A) to 2 (C). 2 (A) to 2 (C) are diagrams showing the basic concept of multiplex transmission in the multiplexer 34 illustrated in FIG. The multiplexer 34 illustrated in FIG. 1 (A) is basically configured as the switching circuit illustrated in FIG. 2 (B). [0070] FIG. 2 (A) shows the symbol stream of each channel multiplexed in the multiplexer 34. Here, four channels from channel 1 (CH1) to channel 4 (CH4) are illustrated. The symbol stream for each channel is individually inserted into the multiplexer 34. [0071] FIG. 2B shows the concept of processing in the multiplexer 34. The input symbol stream of each channel is cyclically switched, and the symbols are arranged so that the symbols of each channel appear periodically. The multiplexed symbol stream is shown in Fig. 2 (C). [0072] In this example, the occurrence cycle of the symbol of each channel is 4, because the case of multiplexing up to 4 channels is taken as an example, but the maximum number of channel multiplexing is not limited to this, and any integer n About 2<sup>n</sup> It can be set to (n = 1, 2, 3, 4, ...). In that case, the appearance cycle of the symbols of each channel is the same as the maximum number of multiplex 2<sup>n</sup> Will be. [0073] Multiplexing in multiplexer 34 2<sup>2</sup> When processing channels, if the number of channels actually used for communication is smaller than the maximum number of multiplexes, a null symbol with an amplitude of "0 (zero)" is used as a symbol for unused channels. Insert and perform periodic multiplexing processing in the multiplexer 34. [0074] FIG. 3 is a diagram showing the arrangement of subcarriers of a plurality of channels. In the example illustrated in FIG. 3, the case where the number of channels is 4 and the OFDM processing of 4 kHz is performed for each channel having a subcarrier interval adjacent to each other, that is, the case where one symbol modulation time is 250 μs = 1/4 kHz is illustrated. ing. The subcarrier interval of multiple signals is 4kHz, but since channels 1 to 4 appear periodically on the frequency axis in units of 1 subcarrier, the subcarriers of each channel appear every 16kHz = 4 × 4kHz. ing. Symbol f in Figure 3<sub>c</sub> Indicates the carrier frequency (center frequency of the band signal). [0075] In the embodiment of the present invention, subcarriers of a plurality of channels are periodically arranged when performing multiplex communication by multicarrier modulation. The reason is to facilitate the modulation of a large number of symbols, and further to facilitate the channel separation in the channel selection circuit 43 in the receiving device 40, which will be described later. [0076]<u style="single">First Embodiment of the receiving device</u>The receiver 40 of the OFDM type wireless communication system illustrated in FIG. 1 (B) will be described. In this embodiment, as in the transmission device 30, a case where the OFDM processing with the number of multiple channels of 4 and the subcarrier interval of 4 kHz is performed, that is, the case where the 1-symbol modulation time is 250 μs = 1/4 kHz is illustrated. Further, for convenience of explanation, a case where the signal band of the multiplex signal is 1024 kHz and there are 256 subcarriers will be illustrated. This corresponds to the case where the number of subcarriers per channel is 64 (= 256/4). [0077] The receiving device 40 includes a receiving antenna 41, a high frequency receiving circuit 42, a signal component separator (demultiplexer or channel selection circuit) 43, an FFT / descramble processing means 44, a bit extraction circuit 45, and a decoding circuit. Has 46 and. [0078] The signal transmitted from the transmitter 30 of the OFDM wireless communication system is received by the receiving antenna 41 and down-converted to the baseband band in the high frequency receiving circuit 42. Further, it is converted into a digital signal by an A / D converter (not illustrated) and input to the signal component separator 43 from the connection line 202. [0079] The signal in which the signals of channels 1 to 4 are arranged on the frequency axis is input to the signal component separator 43 in terms of the time axis. The signal component separator 43 separates (demultiplexes) the signal for each of a plurality of channels, contrary to the processing of the multiplexer 34 in the transmitter 30. The detailed circuit configuration and processing method of the signal component separator 43 will be described later with reference to FIGS. 4 to 7. [0080] [0080] The number of symbols input from the high-frequency receiver circuit 42 to the signal component separator 43 is 256 per modulation time (for simplicity, oversampling is not considered here), but the number of subcarriers of the desired channel is that. Since it is 1/4, the channel selection circuit 43 performs decimation on the frequency axis and outputs 64 (= 256/4) symbols. As a result, the number of symbols for FFT processing in the FFT / descramble processing means 44 is reduced to 1/4. [0081] The output symbol of the signal component separator 43 is input to the FFT / descramble processing means 44 via the signal line 204. In the FFT / descramble processing means 44, a fast Fourier transform (FFT) process opposite to the IFFT (inverse fast Fourier transform) performed in the transmission device 30, scramble processing, IFFT, guard time addition, and window processing circuit 36 is performed. Then, the symbol strings arranged on the frequency axis are extracted. [0082] Since the symbol of the desired channel is selected and extracted by the signal component separator 43 and applied to the FFT / descramble processing means 44, the symbol extracted by the FFT processing is of a channel other than the desired channel. Symbols are not included. That is, the processing in the processing means 44 is sufficient as the FFT processing having the minimum number of points necessary for receiving the desired channel. As a result, the FFT processing circuit in the FFT / descramble processing means 44 becomes small. [0083] The symbol stream of the desired channel extracted in this way is subjected to processing corresponding to processing such as scrambling processing, IFFT, guard time addition, random phase shift processing in the window processing circuit 36, random orthogonal transform processing, and the like. After the scramble performed in the transmission device 30, it is input to the bit extraction circuit 45 via the signal line 206. [0084] In the bit extraction circuit 45, bits are extracted according to the modulation method in which the symbol is modulated, and a coded bit stream is applied to the decoding circuit 46. As such a modulation method, various modulation methods such as QPSK, 8PSK, and 16QAM applied in the OFDM method can be applied. [0085] The decoding circuit 46 is a multi-channel coding circuit 31 in the transmitter 30.<sub>1</sub> ~31<sub>M</sub> The information bitstream is extracted by performing deinterleaving and decoding processing, which is the opposite of the coding and interleaving performed in. [0086] By providing the signal component separator 43 in the receiving device 40 that has received the signals of the symbol strings of a large number of subcarriers, the sample rates in the FFT / descramble processing means 44, the bit extraction circuit 45, and the decoding circuit 46 can be set for the desired channel. It is possible to reduce (decimate) to, and then significantly reduce the processing amount of circuits 45 to 46 after the FFT / descramble processing means 44, for example (1/multiple number). It will be possible. [0087] In particular, since the signal component separating device 43 is provided in front of the FFT / descramble processing means 44 to reduce the number of FFT processing data in the FFT / descramble processing means 44, the memory capacity for FFT processing is reduced. , Contributes greatly to the miniaturization of the receiving device 40. In addition, the FFT processing time in the FFT / descramble processing means 44 can be shortened. [0088] Since the subcarriers of each channel are arranged over the entire frequency band of the system, when this embodiment is applied to a wireless communication system in which a large number of channels are multiplexed, such as a DAB system, a large frequency is used. Diversity effect can be expected. This makes it possible to suppress deterioration of communication quality due to fading. [0089]<u style="single">Signal component separator 43</u>An embodiment of the signal component separator 43 shown in FIG. 1 (B) will be described with reference to FIGS. 4 to 7. FIG. 4 is a configuration diagram of the signal component separating device 43. FIG. 5 is a circuit diagram of a two-branch circuit constituting the signal component separator 43 illustrated in FIG. FIG. 6 is a diagram showing an embodiment of the symbol delay circuit 43a illustrated in FIG. FIG. 7 is a diagram showing an embodiment of the phase offset adjustment circuit 43b illustrated in FIG. In this embodiment, there are two subcarriers.<sup>3</sup> The case of channel = 8 channels C0 to C7 will be described. [0090] The signal component separator 43 illustrated in FIG. 4 includes one first-stage bifurcated circuit 431 and two second-stage bifurcated circuits 432.<sub>1</sub> 、432<sub>2</sub> And four third-stage two-branch circuits 433<sub>1</sub> ~433<sub>4</sub> Have. This circuit configuration of the signal component separator 43 is a bifurcated circuit 431: 432 that sequentially bifurcates the symbols.<sub>1</sub> 、432<sub>2</sub> :433<sub>1</sub>~433<sub>4</sub> Is configured to diffuse in the form of a power of 2 (or hierarchically like a pyramid in the form of a power of 2). [0091] The meaning of the two-branch circuit is that when a symbol string is input, the symbol string branched into two systems alternately for each subcarrier is extracted. [0092] As illustrated in FIG. 4, the signal component separator 43 is a separate bifurcated circuit 431, 432.<sub>1</sub> 、432<sub>2</sub> , And 433<sub>1</sub> ~433<sub>4</sub> Can be combined, or these two-branch circuits can be configured with one DSP (digital signal processor). Hereinafter, a case where two branch circuits are individually provided and combined with each other will be described. [0093] The meanings of the symbols in FIG. 4 will be explained. The symbol N indicates the number of sample points per modulation time of the symbol series output from the high-frequency receiving circuit 42 and received by the signal component separator 43. The symbol K (uppercase) indicates the number of separated symbols separated in the bifurcated circuit of each stage inside the signal component separator 43. The first-stage bi-branch circuit 431 is separated into two series of symbol strings, so K = 2, and the second-stage two-branch circuit 432<sub>1</sub> 、432<sub>2</sub> Since it is separated into 4 series of symbol strings, K = 4, and the 4 bifurcated circuits in the 3rd stage 433<sub>1</sub> ~433<sub>4</sub> Since it is separated into 8 series of symbol strings, K = 8. The symbol m indicates the position of the stage of the bifurcated circuit. Let m = 0 in the first stage. The symbol k (lowercase) is a parameter indicating that a signal group having a frequency offset of several subcarriers is input to the bifurcated circuit with reference to 0 (Hz). [0094] Each bi-branch circuit can be represented using parameters (m, k). The specific meaning will be described with reference to Fig. 5. [0095] The signal component separator 43 separates the baseband band multicarrier digital signal (multicarrier multiplex signal) output from the high frequency receiving circuit 42 into subcarrier units. Since the symbol strings received by the high-frequency receiving circuit 42 are arranged periodically, the signal component separator 43 receives 2 received signals.<sup>C</sup> 2 for every carrier<sup>c</sup> Separate into pieces. c is any integer, 2<sup>c</sup> = 2,4,8,16, ... [0096] FIG. 5 shows the general circuit configuration of the two-branch circuit illustrated in FIG. The two-branch circuit is composed of a symbol delay circuit 43a, a phase offset adjustment circuit 43b, an addition circuit 43c, and a subtraction circuit 43d. [0097] The m-stage symbol delay circuit 43a has a memory capacity of the number of symbols input to the symbol delay circuit 43a, and the input symbol sequence is the number of symbols N / (2).<sup>(m + 1)</sup> ) Is delayed. The number of stages m is the number of stages m = 0 of the first stage. The symbol delay circuit 43a is essentially for N symbols within one modulation time (2).<sup>(m + 1)</sup> ) Delay the symbol. The symbol delay circuit 43a can be configured by, for example, a FIFO (First-In First-Out) memory, a normal random access memory, or the like. [0098] FIG. 6 illustrates the delay amount of the symbol delay circuit 43a for m = 0 to m = 3. [0099] When the symbol sequence of 8 channels C0 to C7 is input from the high frequency receiving circuit 42 to the first stage bifurcated circuit 431 illustrated in FIG. 5, m = 0, 2<sup>(m + 1)</sup> Since = 2, the symbol delay circuit 43a of the first-stage bifurcated circuit 431 is delayed by half the number of symbols N. [0100] Similarly, the second stage two-branch circuit 432<sub>1</sub> ,432<sub>2</sub> The symbol delay circuit 43a in the above has half the memory capacity of the symbol delay circuit 43a of the first-stage two-branch circuit 431, and is delayed by the number of symbols N / 4. Third stage two-branch circuit 432<sub>1</sub> ~432<sub>4</sub> The symbol delay circuit 43a in the above has a memory capacity of 1/4 that of the symbol delay circuit 43a of the first-stage bifurcated circuit 431, and is delayed by the number of symbols N / 8. [0101] In the two-branch circuit of each stage, the number of output symbols is half of the number of input symbols, which is equivalent to decimation, and the number of symbols input to the two-branch circuit in the subsequent stage. Is half the number of symbols input to the two-branch circuit in the previous stage, and the memory capacity of the symbol delay circuit 43a is also halved as it goes to the latter stage. [0102] The m-stage phase offset adjustment circuit 43b has -π (k / (2).<sup>m</sup> ) (Radian) to shift (phase offset) the phase of the input symbol. As illustrated in FIG. 3, since there is a frequency offset with reference to 0 (Hz) depending on the subcarrier group, the phase offset adjustment circuit 43b performs a phase shift for adjusting the rotation of the phase generated by this offset. The phase shift amount is the angle of the amount corresponding to k (lowercase) indicating the frequency offset for the subcarrier and the number of stages m with respect to 0 (Hz), -π (k / 2).<sup>m</sup> ) (Radian). [0103] FIG. 7 illustrates the phase shift state of the phase offset adjustment circuit 43b for various parameters m and k. [0104] The phase offset adjustment circuit 43b in the first-stage two-branch circuit 431 does not rotate the phase because the parameters are m = 0 and k (lowercase) = 0. [0105] Second stage two-branch circuit 432<sub>1</sub> Since the parameters of the phase offset adjustment circuit 43b of the above are m = 1 and k = 0, the phase offset adjustment circuit 43b does not perform phase rotation like the phase offset adjustment circuit 43b of the first-stage two-branch circuit 431. However, the second stage two-branch circuit 432<sub>2</sub> Since the parameters of the phase offset adjustment circuit 43b of are m = 1, k (lowercase) = 1, the phase is rotated by -π / 2 (radians). This phase rotation means that the I-axis and the Q-axis are exchanged and the polarities are reversed as shown in the illustration. To rotate the phase of the symbol, when it is a multiple of π / 2, it is only necessary to reverse the polarity of the signal or switch the I-axis and the Q-axis. [0106] Third stage two-branch circuit 433<sub>1</sub> ~433<sub>4</sub> Each phase offset adjustment circuit 43b of the above performs a phase shift for the parameters m = 2, k (lowercase letters) = 1 to 3 as shown in the illustration. When k = 0, no phase shift is performed. [0107] As described above, the phase shift by the phase offset adjusting circuit 43b in the bifurcated circuit can be realized by inversion of polarity, addition / subtraction, and coefficient multiplication. [0108] The operation of the two-branch circuit illustrated in Fig. 5 will be described. The two-branch circuit is a circuit that alternately separates the input signal and decimates the symbol string on the frequency axis. [0109] As shown in Fig. 5, when the signal sequence (subcarrier group) of 8-channel subcarriers C0, C1, C2, C3 to C7 is input to the first-stage bifurcated circuit 431, the symbol is symbolized in the symbol delay circuit 43a. When the symbol delayed by the number (N / 2) and the symbol string in the phase offset adjustment circuit 43b where k = 0 and the phase is not shifted are added by the addition circuit 43c, the subcarriers C0, C2, C4, C6 Only the symbol series of is separated and extracted. [0110] In the subtraction circuit 43d, when the symbol sequence that is not phase-shifted in the phase offset adjustment circuit 43b is subtracted from the symbol that is delayed by the number of symbols N / 2 in the symbol delay circuit 43a, only the symbol series of the subcarriers C1, C3, C5, and C7 is displayed. Separated and extracted. In this way, the first-stage bifurcated circuit 431 separates the symbol sequence for each of the input alternating subcarriers. [0111] The resolution on the frequency axis of each of the separated symbol series is halved, and the number of symbols output is N / 2 symbols for both outputs. [0112] Second stage two-branch circuit 432<sub>1</sub> When the subcarriers C0, C2, C4, and C6 are input to, the symbol delayed by the number of symbols N / 4 in the symbol delay circuit 43a and the symbol in the phase offset adjustment circuit 43b where k = 0 and the phase is not rotated. When the columns are added by the addition circuit 43c, the symbol series of the subcarriers C0 and C4 is extracted. Two-branch circuit 432<sub>1</sub> In the subtraction circuit 43d of the above, the symbol sequence of the subcarriers C2 and C6 is extracted by subtracting the symbol sequence not phase-rotated in the phase offset adjustment circuit 43b from the symbol delayed by N / 4 in the symbol delay circuit 43a. [0113] In this way, the second-stage two-branch circuit 431<sub>1</sub> Also in, the input subcarriers are alternately separated and the symbol series is output. Each separated symbol sequence has half the resolution on the frequency axis and is decimation. [0114] The second stage two-branch circuit 431<sub>1</sub> The memory capacity of the symbol delay circuit 43a in the first stage is half the memory capacity of the symbol delay circuit 43a in the first stage bifurcated circuit 431. [0115] Second stage two-branch circuit 432<sub>2</sub> When the subcarriers C1, C3, C5, and C7 are input to, the symbol delayed by N / 4 (sampling time) in the symbol delay circuit 43a and k = 1, m = 1 in the phase offset adjustment circuit 43b. , -The symbol sequence of subcarriers C1 and C5 is extracted by adding the phase-shifted symbol sequence by -π / 2 (radians) with the adder circuit 43c. [0116] Two-branch circuit 432<sub>1</sub> In the subtraction circuit 43d of, the symbol sequence of the subcarriers C3 and C7 is obtained by subtracting the symbol sequence phase-shifted by -π / 2 (radians) in the phase offset adjustment circuit 43b from the symbol delayed by N / 4 in the symbol delay circuit 43a. Is extracted. [0117] In this way, the second-stage two-branch circuit 431<sub>2</sub> As for the odor, the symbol series in which the input subcarriers are alternately separated is extracted. Each of the separated symbol sequences has half the resolution on the frequency axis and is decimation. [0118] The second stage two-branch circuit 431<sub>2</sub> The memory capacity of the symbol delay circuit 43a in the first stage is half the memory capacity of the symbol delay circuit 43a in the first stage bifurcated circuit 431. [0119] Third stage two-branch circuit 433<sub>1</sub> ~433<sub>4</sub> Also, the same symbol separation and decimation as described above are performed. As a result, finally, the third stage two-branch circuit 433<sub>1</sub> ~433<sub>4</sub> The symbols of channels C0, C4, C2, C6, C1, C5, C3, and C7 are separated and output from each output line of. [0120] The symbols separated into the symbols for each subcarrier are, for example, after the frequency offset is corrected through the frequency offset compensation circuit (frequency offset compensation / removal means) described later with reference to FIG. 8, FIG. 1 (B). It is applied to the FFT / descramble processing means 44 illustrated in 1. The operation after the FFT / descramble processing means 44 is described above. Since a signal having a reduced resolution on the frequency axis is applied to the FFT / descramble processing means 44, the circuit configuration of the FFT / descramble processing means 44 becomes simple. [0121] According to the signal component separator 43 configured by hierarchically combining the two-branch circuits in this way, the symbols are alternately separated for each subcarrier input in each stage, and the resolution of the signal component on the frequency axis is determined. It can be sequentially reduced (decimated) by 1/2. [0122] The two-branch circuits that make up each part of the signal component separator 43 basically have the same circuit configuration, and the memory capacity of the symbol delay circuit 43a goes from the first stage to the second stage and the third stage. The circuit configuration is basically the same except that is gradually halved and the amount of phase shift in the phase offset adjustment circuit 43b is different. Therefore, the configuration of the signal component separator 43 configured by combining the two-branch circuits having a simple configuration is also simple. Further, since the decimation is performed in units of 1 / (power of 2), the circuit configuration becomes simple even in a multi-carrier in which a large number of subcarriers are modulated. [0123] Although the above embodiment has been illustrated for an 8-symbol string, the separation of the 8-symbol string, the 16-symbol string, the 32-symbol string, and the like can be realized by the same method as described above. Needless to say, it is possible to separate into a 2-symbol string and a 4-symbol string. [0124]<u style="single">Second Embodiment of the receiving device</u>FIG. 8 is a configuration diagram of the receiving device 40A as the second embodiment of the present invention. The receiving device 40A illustrated in FIG. 8 receives the multicarrier signal transmitted from the transmitting device 30 illustrated in FIG. 1 (A), similarly to the receiving device 40 illustrated in FIG. 1 (B). [0125] The receiving device 40A includes a signal component separating device 43, a signal selection circuit 47, and two frequency offset compensation circuits 48A and 48B. In this embodiment, an example in which two frequency offset compensation circuits 48A and 48B are provided is illustrated, but a plurality of frequency offset compensation circuits can be provided in parallel. [0126] In the subsequent stages of the frequency offset compensation circuits 48A and 48B, the FFT / descramble processing means 44, the bit extraction circuit 45, the decoding circuit 46, etc. illustrated in FIG. 1 (B) are systemized according to the number of frequency offset compensation circuits. , In this embodiment, two systems are provided. [0127] The signal component separation device 43 can have a configuration in which two branch circuits similar to those illustrated in FIG. 4 are layered. Therefore, from the signal component separator 43, the signal component is output in units of subcarriers, 2<sup>C</sup> As you can see (where C is any integer), you get the separated signal components. [0128] The signal selection circuit 47 selects and outputs a symbol of a desired subcarrier from the signal components separated by the signal component separator 43. As is clear from the illustration in FIG. 4, since the output of the two-branch circuit in the final stage of the signal component separator 43 is uniquely determined which subcarrier group corresponds to, the symbol selection in the signal selection circuit 47 is selected. It's easy. In this example, the signal selection circuit 47 selectively outputs two symbols, but the number of selection symbols in the signal selection circuit 47 can be one or any plurality. [0129] The frequency offset compensation circuits 48A and 48B compensate for the frequency offset of the signals of the subcarrier group selected by the signal selection circuit 47 as illustrated in FIG. [0130] FIG. 9 is a diagram showing a circuit configuration example of the frequency offset compensation circuits 48A and 48B. The frequency offset compensation circuits 48A and 48B each have a multiplier 481, a gyrator (oscillator) 482, and a symbol rearrangement circuit 483, respectively. [0131] The signal input to the multiplier 481 has different frequency offsets in the positive direction shown below with reference to 0 (Hz). [0132] [Number 1] exp (j2π (k / N) i + πk) [0133] In order to remove this offset, the gyrator 482 outputs a complex sine wave signal of the above offset and conjugate shown below to the multiplier 481. As described above, the gyrator 482 is a signal generator that generates the following complex component signals. [0134] [Number 2] exp (-j2π (k / N) i + πk) [0135] The multiplier 481 multiplies the symbol selected by the signal selection circuit 47 with the above-mentioned complex sinusoidal signal from the gyrator 482, and performs frequency conversion to remove the offset component. [0136] The symbol rearrangement circuit 483 swaps the first half and the second half of the frequency conversion results and outputs the result. [0137] In the present embodiment, before the FFT processing in the FFT / descramble processing means 44 of FIG. 1 (B), the number of symbols to be processed is reduced by a plurality of symbols and two in the present embodiment. The FFT circuit configuration is simplified and the processing speed is improved. [0138] That is, according to the present embodiment, the number of symbols handled by the FFT / descramble processing means is half that of FIG. 1 (B) described above. When the number of symbols is represented by N, the number of gates constituting the FFT circuit is the number of gates proportional to (logN). Therefore, when the number of symbols input to the FFT circuit decreases, the number of gates of the FFT circuit decreases extremely. Comparing the sum of the number of gates of the FFT in the FFT / descramble processing means 44 of FIG. 1 (B) and the number of gates of the two FFT circuits of the FFT / descramble processing means in the receiving device illustrated in FIG. The sum of the number of gates of the two FFT circuits of the FFT / descramble processing means in the form of is smaller. This means that providing two FFT / descramble processing means simplifies the circuit configuration as compared with the one FFT / descramble processing means 44 illustrated in FIG. 1 (B). In addition, a simple FFT circuit can increase the operating speed. Therefore, using the receiving device 40A of FIG. 8 has an advantage that the entire circuit configuration is simplified and the operating speed is also improved. [0139] The selection of the subcarrier group in the signal selection circuit 47 is not limited to two, and only one subcarrier group may be selected, or a plurality of two or more subcarrier groups may be selected. [0140]<u style="single">Third Embodiment of the receiving device</u>FIG. 10 is a configuration diagram of the receiving device 40B as the third embodiment of the present invention. The receiving device 40B illustrated in FIG. 10 is the same as the receiving device 40 illustrated in FIG. 1 (B), or is transmitted from the transmitting device 30 illustrated in FIG. 1 (A) in the same manner as the receiving device 40A illustrated in FIG. Receives the multi-carrier signal. [0141] The receiving device 40B includes a high frequency receiving circuit 42, a signal component separating device 43, and two series of frequency offset compensation circuits 48A and 48B. In this embodiment, an example in which two frequency offset compensation circuits 48A and 48B are provided is illustrated, but a plurality of frequency offset compensation circuits can be provided in parallel. [0142] In the subsequent stages of the frequency offset compensation circuits 48A and 48B, the FFT / descramble processing means 44, the bit extraction circuit 45, the decoding circuit 46, etc. illustrated in FIG. 1 (B) are systemized according to the number of frequency offset compensation circuits. , In this embodiment, two systems are provided. [0143] The signal component separator 43 includes, for example, a first-stage bifurcated circuit 431 illustrated in FIG. 4 and a second-stage bifurcated circuit 432.<sub>1</sub> And the third stage two-branch circuit 433<sub>1</sub> 、433<sub>2</sub> Is provided. As a result, the subcarrier group of C0, C4, C2, and C6 and the subcarrier group of C1, C5, C3, and C7 are separated from the signal component separator 43. [0144] The frequency offset compensation circuits 48A and 48B compensate for the frequency offset of the signals of the subcarrier group separated by the signal component separator 43 as illustrated in FIG. The frequency offset compensation circuits 48A and 48B have been described in the second embodiment. That is, a circuit configuration example of the frequency offset compensation circuits 48A and 48B is illustrated in FIG. 9, and the operation thereof has been described above, and thus the description thereof will be omitted. [0145] The FFT / descramble processing means 44A and 44B are for the subcarrier group of C0, C4, C2, C6 and the subcarrier group of C1, C5, C3, C7, which are frequency offset compensated by the frequency offset compensation circuits 48A and 48B, respectively. Perform FFT processing, etc. [0146] The number of symbols handled by the FFT / descramble processing means 44A and 44B is half that of FIG. 1 (B) described above. When the number of symbols is represented by N, the number of gates constituting the FFT circuit is the number of gates proportional to (logN). Therefore, when the number of symbols input to the FFT circuit decreases, the number of gates of the FFT circuit decreases extremely. Comparing the number of gates of the FFT in the FFT / descramble processing means 44 of FIG. 1 (B) with the number of gates of the two FFT circuits of the FFT / descramble processing means 44A and 44B illustrated in FIG. The sum of the number of gates of the two FFT circuits of the descramble processing means 44A and 44B is smaller. This means that the circuit configuration is simpler when the two FFT / descramble processing means 44A and 44B are provided than in the one FFT / descramble processing means 44 illustrated in FIG. 1 (B). In addition, a simple FFT circuit can increase the operating speed. Therefore, using the receiving device 40B of FIG. 10 has an advantage that the entire circuit configuration is simplified and the operating speed is also improved. [0147] In the above example, the case where the frequency offset compensation circuit and the FFT / descramble processing means 44A and 44B are provided in two systems has been described, but these can be provided in parallel by the number of powers of 2. [0148]<u style="single">Fourth Embodiment of the receiving device</u>FIG. 11 is a schematic configuration diagram of the receiving device 40C according to the fourth embodiment of the present invention. Similarly to the receiving devices 40, 40A, and 40B of the first to third embodiments described above, the receiving device 40C also separates and decodes the multicarrier signal transmitted from the transmitting device 30 of FIG. 1 (A). [0149] The receiving device 40C includes a receiving antenna 41, a high frequency receiving circuit 42, a filter device 49, and an FFT / descramble processing means 44. The circuit after the FFT / descramble processing means 44 is the same as in FIG. 1 (B). [0150] To describe the difference between the receiving device 40C illustrated in FIG. 11 and the receiving devices 40, 40A, 40B described above, the receiving device 40C uses a signal component separating device 43 like the receiving devices 40, 40A, 40B, and has a plurality of symbols. Instead of extracting the sequence, only the signal component of one desired subcarrier group is extracted by the filter device 49, and the result is processed by the circuit of the FFT / descramble processing means 44 or later. [0151] As described above, the high-frequency receiving circuit 42 performs frequency conversion of the high-frequency signal received by the receiving antenna 41 antenna into the baseband band, and converts the analog signal frequency-converted into the baseband band into a digital signal (9 symbol strings). [0152] The filter device 49 inputs a digital symbol string from the high frequency receiving circuit 42, filters it in subcarrier units, and extracts only a desired subcarrier group. The filter device 49 outputs only the minimum number of samples required to represent the output subcarrier group. As a result, a large decimation on the frequency axis is realized. [0153] The difference between the signal component separator (two-branch circuit) and the filter device will be described. The signal component separator inputs one signal group and outputs two signal groups separated from one signal group. On the other hand, the filter device inputs one signal group, selects and outputs one signal group in a specific frequency band. [0154] The circuits after the FFT / descramble processing means 44 perform the same processing as described with reference to the circuits such as the receiving device 40 in FIG. 1 (B). [0155]<u style="single">First Embodiment of the filter device</u>FIG. 12 is a circuit example of the first embodiment of the filter device shown in FIG. The filter device 49 illustrated in FIG. 12 includes a signal component separator (demultiplexer) 491, a symbol group selection circuit 492, and a frequency offset compensation circuit (frequency offset compensation / removal circuit) 493. [0156] The configuration of the filter device 49 is similar to the circuit configuration of FIG. 8, that is, the signal component separator 43, the signal selection circuit 47, the frequency offset compensation / removal circuits 48A, 48B, and the filter device 49 is substantially the same as that of FIG. Performs the same processing as these circuits 43, 47, 48A, and 48B. [0157] Similar to the signal component separator 43 of FIG. 8, the signal component separator 491 has a circuit configuration of a combination of the two-branch circuits illustrated in FIG. The symbol group selection circuit 492 is similar to the signal selection circuit 47 in FIG. The frequency offset compensation / removal circuit 493 has the same circuit configuration as the frequency offset compensation / removal circuits 48A and 48B illustrated in FIG. [0158] The signal component separator 491 separates the symbols of the symbol string output from the high frequency receiving circuit 42 at desired subcarrier intervals. The frequency offset compensation / removal circuit (frequency offset compensation circuit) 493 has the circuit configuration illustrated in Fig. 9, and performs frequency conversion to the subcarrier group with the input symbol (signal) as the reference at 0 (Hz). , Perform frequency offset removal. [0159] Since the FFT / Discrete rumble processing means 44 of FIG. 11 performs FFT processing only on the selected symbol, the number of DFT points can be kept small, and the circuit configuration of the FFT / Discrete rumble processing means 44 becomes simple. [0160]<u style="single">Second Embodiment of the filter device</u>FIG. 13 is a circuit example of the second embodiment of the filter device of FIG. The filter device of the second embodiment is a filter device that branches the received subcarrier group into an odd number of carriers and an even number of carriers. The filter device 49A of the second embodiment includes a subcarrier selection circuit 494, a filter decimation circuit 495, and a frequency offset compensation / removal circuit 493. [0161] FIG. 14 is a diagram showing a circuit configuration example of the filter decimation circuit 495 illustrated in FIG. The filter decimation circuit 495 includes a symbol delay circuit 495a, a phase offset adjustment circuit 495b, and an adder circuit 495c. [0162] The circuit configuration of the filter decimation circuit 495 is similar to the one-unit bifurcated circuit of the signal component separator 43 illustrated in FIG. That is, the symbol delay circuit 495a corresponds to the symbol delay circuit 43a, the phase offset adjustment circuit 495b corresponds to the phase offset adjustment circuit 43b, and the adder circuit 495c corresponds to the adder circuit 43c. However, the filter decimation circuit 495 is not provided with the subtraction circuit 43d. The reason is that the filter decimation circuit 495 does not require both even-numbered subcarriers and odd-numbered subcarriers as in the two-branch circuit illustrated in FIG. 5, and only one of them needs to be output. [0163] The symbol delay circuit 495a sets the input subcarriers C0 to C7 by the points defined by the parameters N and m, that is, N / (2).<sup>m + 1</sup> ) Only delay in advance. In the present embodiment, m = 0, and the delay of the symbol delay circuit 495a is N / 2. [0164] The subcarrier selection circuit 494 selects the desired subcarrier. The phase offset adjustment circuit 495b performs a phase shift on the input subcarriers C0 to C7 according to the passing subcarrier group selected by the subcarrier selection circuit 494. [0165] The value of the rotational phase (phase shift amount) performed by the phase offset adjustment circuit 495b is-(α / 2).<sup>m</sup> ) Π (radian). The parameter α is a value determined by the subcarrier group to be passed and the parameter m, and has the regularity shown in Table 1 below. In the table below, C0 to C7 mean subcarriers arranged from 0 Hz. [0166] [table 1]<img file="JP4622115B2_D0001.tif" />[0167] By making the filter decimation circuit 495 multi-stage, it is possible to configure a filter device such as K (uppercase letter) = 8,16,32. In that case, the values of the rotational phase performed by the phase offset adjustment circuit 495b of each stage are the values shown in Table 2 below. However, Table 2 exemplifies up to K = 8. [0168] [Table 2]<img file="JP4622115B2_D0002.tif" />[0169] In the present embodiment, the value of the rotational phase performed by the phase offset adjustment circuit 495b is 0 (rad) when passing even-numbered carriers and π (rad) when passing through odd-numbered carriers. Which rotation phase is applied is appropriately indicated by the subcarrier selection circuit 404. [0170] The addition circuit 495c adds the rotational phase-processed subcarriers performed by the phase offset adjustment circuit 495b and the subcarriers delayed by the symbol delay circuit 495a. As a result, for example, when subcarriers C0 to C7 are input to the filter decimation circuit 495, one of the subcarrier series symbols specified by the subcarrier selection circuit 494 is displayed from the filter decimation circuit 495. It is output. [0171] The frequency offset compensation / removal circuit 493 in the filter device 49A of FIG. 13 has the same circuit configuration as illustrated in FIG. 9, similar to the frequency offset compensation / removal circuit 493 of FIG. The frequency offset compensation / removal circuit 493 operates in the same manner as the frequency offset compensation / removal circuits 48A and 48B of FIG. 8 or the frequency offset compensation / removal circuit 493 of FIG. 12 described above. [0172] In the filter device 49A illustrated in FIG. 13, decimation is performed on the frequency axis by the filter decimation circuit 495, and the number of output symbols is halved. Therefore, the subsequent signal processing becomes simple and quick. [0173]<u style="single">Third Embodiment of the filter device</u>FIG. 15 is a circuit diagram of a third embodiment of the filter device illustrated in FIG. The filter device 49B illustrated in FIG. 15 includes a subcarrier selection circuit 494, a first filter decimation circuit 495A, a second filter decimation circuit 495B, and a frequency offset compensation / removal circuit 493. The filter device 49B is a circuit in which the filter decimation circuit 495 of the filter device 49A illustrated in FIG. 13 is replaced with two-stage filter decimation circuits 495A and 495B provided in series. Both the filter decimation circuits 495A and 495B have the circuit configuration illustrated in FIG. 14, the first stage filter decimation circuit 495A has m = 0, and the second stage filter decimation circuit 495B has m = 1. Yes, when this parameter m is applied, the amount of delay in each of the filter decimation circuits 495A and 495B is specified, as illustrated in FIG. [0174] The frequency offset compensation / removal circuit 493 can have the same circuit configuration as the circuit illustrated in FIG. [0175] The value of the rotational phase (phase shift amount) performed by the phase offset adjustment circuit 495b is-(α / 2).<sup>m</sup> ) Π (radian). The parameter α is a value determined by the subcarrier group to be passed and the parameter m, and has the regularity shown in Table 1. [0176] By making the filter decimation circuit 495 multi-stage, it is possible to configure a filter device such as K (uppercase letter) = 8,16,32. In that case, the values of the rotational phase performed by the phase offset adjustment circuit 495b of each stage are the values shown in Table 2. In the present embodiment, the value of the rotational phase performed by the phase offset adjustment circuit 495b is 0 (rad) when passing even-numbered carriers and π (rad) when passing through odd-numbered carriers. Which rotation phase is applied is appropriately indicated by the subcarrier selection circuit 404. [0177] The addition circuit 495c adds the rotational phase-processed subcarriers performed by the phase offset adjustment circuit 495b and the subcarriers delayed by the symbol delay circuit 495a. As a result, for example, when subcarriers C0 to C7 are input to the filter decimation circuit 495, one of the subcarrier series symbols specified by the subcarrier selection circuit 494 is displayed from the filter decimation circuit 495. It is output. [0178] Since the filter device 49B illustrated in FIG. 15 is provided with the two-stage filter decimation circuits 495A and 495B, it is a filter device that outputs any of the four subcarrier groups. That is, it is a circuit that outputs a signal with 1/4 decimation on the frequency axis. In the present embodiment, the case where two filter decimation circuits 495A and 495B are connected in series in two stages is illustrated, but further connected in three stages and four stages in multiple stages (m), 2<sup>3</sup> 、2<sup>4</sup> 、2<sup>m</sup> It is possible to separate into subcarrier groups of the above and pass through one of the subcarrier groups. In that case, the regularity of the parameter m of each filter decimation circuit is the same as in FIG. The value of the phase to be rotated is determined by the regularity shown in Tables 1 and 2. [0179]<u style="single">Fourth Embodiment of the filter device</u>FIG. 16 is a circuit example of the fourth embodiment of the filter device illustrated in FIG. The filter device 49C includes a multiplier 496, a passing subcarrier selection signal output circuit 497, a filter decimation circuit 499, and a symbol reordering circuit 498. [0180] The frequency offset of the symbol string input to the multiplier 496 is the same as the frequency offset of the symbol string input to the multiplier 481 of FIG. [0181] In order to eliminate the frequency offset, the passing subcarrier selection signal output circuit 497 outputs a complex sinusoidal signal corresponding to the channel to be selected to the multiplier 496, similar to the gyrator (oscillator) 482 illustrated in FIG. [0182] The multiplier 496 multiplies the symbol sequence from the high frequency receiving circuit 42 with the complex sinusoidal signal output from the passing subcarrier selection signal output circuit 497. This calculation is for giving a frequency offset so that the symbol (subcarrier component) selected by the filter device 49C among the symbol series input to the filter device 49C includes 0 (Hz). Therefore, the passing subcarrier selection signal output circuit 497 outputs the signal and conjugate of the frequency of the subcarrier closest to the subcarrier in the positive frequency direction from 0 (Hz) among the subcarriers selected, and the multiplier 496 outputs the conjugate signal. Is multiplied by the input symbol to remove the frequency offset. [0183] The filter decimation circuit 499 will be described with reference to FIG. FIG. 17 is a circuit example of the filter decimation circuit 499 illustrated in FIG. The filter decimation circuit 499 includes a symbol delay circuit 495a and an adder circuit 495c. The circuit configuration of the filter decimation circuit 499 is a circuit configuration in which the phase offset adjustment circuit 43b and the subtraction circuit 43d are deleted from the two-branch circuit illustrated in FIG. 5, and from the circuit configuration of the filter decimation circuit 495 illustrated in FIG. This is a circuit configuration in which the phase offset adjustment circuit 495b is deleted. The filter decimation circuit 499 is a circuit that selectively outputs only the symbol series of the even-numbered subcarrier channels with reference to 0 (Hz) among the input subcarriers. The number of symbols output by the filter decimation circuit 499 is also halved, which means that decimation is performed on the frequency axis. [0184] The symbol rearrangement circuit 498 exchanges the order of the symbol group (subcarrier group) output from the filter decimation circuit 499 between the first half part and the second half part, and outputs only the symbol of the second half part as a valid symbol. [0185]<u style="single">Fifth Embodiment of the filter device</u>FIG. 18 is a circuit example of the fifth embodiment of the filter device illustrated in FIG. The filter device 49D includes a multiplier 496, a channel selection signal output circuit 497, first and second filter decimation circuits 499A and 499B, and a symbol reordering circuit 498. The first and second filter decimation circuits 499A and 499B have the same circuit configurations as the filter decimation circuit 499 described with reference to FIG. 17, respectively. [0186] The filter device 49D is obtained by adding a second filter decimation circuit 499B to the filter device 49C illustrated in FIG. With the addition of the filter decimation circuit 499B, the passing carriers are further limited to 1/2 from the filter device 49C illustrated in FIG. 16, similar to the circuit configurations of the two-stage filter decimation circuits 495A and 495B illustrated in FIG. be able to. Others are the same as the filter device 49C illustrated in FIG. [0187] By connecting the filter decimation circuit 499 in series in multiple stages, for example, by connecting in series in m stages, the passing carrier is halved.<sup>m</sup> Can be limited to. [0188]<u style="single">Fifth Embodiment of the receiving device</u>FIG. 19 is a configuration diagram of a receiving device according to a fifth embodiment of the present invention. The receiving device 40D includes a receiving antenna 41, a high-frequency receiving circuit 42, a switch circuit 50, a buffer circuit 52, a filter device 49, an FFT / descramble processing means 44, and bit extraction of the illustration in FIG. 1 (B) without illustration. It has a circuit 45 and a decoding circuit 46. [0189] The high frequency receiving circuit 42 operates in the same manner as described above. [0190] In the initial state, the switch circuit 50 outputs the signal of the high frequency receiving circuit 42 to the filter device 49. Meanwhile, the buffer circuit 52 continues to accumulate the signal of the high frequency receiving circuit 42 until all the signals for one symbol are transferred to the filter device 49. [0191] The filter device 49 is a filter device 49 shown as various embodiments described above, and is used only for a specified part of the signals input from the high frequency receiving circuit 42 through the switch circuit 50, for example. , The signal of only even carriers is extracted, decimation is performed on the frequency axis, and the selection signal is output to the FFT / descramble processing means 44. [0192] The FFT / descramble processing means 44 is configured as a circuit that performs FFT processing on a number of subcarriers smaller than the number of subcarriers received by the high frequency receiving circuit 42. That is, the FFT / descramble processing means 44 is configured to be compact and capable of high-speed operation. After performing FFT processing or the like with the FFT / descramble processing means 44, processing is performed by the bit extraction circuit 45, decoding circuit 46, etc. illustrated in FIG. 1 (A). [0193] The buffer circuit 52 starts sending signals to the filter device 49 via the switch circuit 50 after all the signals for one symbol from the high frequency receiving circuit 42 are transferred to the filter device 49. When the signal of the high frequency receiving circuit 42 is completely transferred to the filter device 49, the switch circuit 50 switches so as to apply the signal from the buffer circuit 52 to the filter device 49. The filter device 49 extracts a signal that has passed a signal component required for this communication from the signal components that have not passed earlier, for example, an odd-numbered carrier, and applies it to the FFT / descramble processing means 44. The FFT / descramble processing means 44 performs FFT processing on the re-input signal to extract a received symbol, and causes the circuits after the bit extraction circuit 45 to be processed. [0194] By adopting the circuit configuration illustrated in FIG. 19, the received symbol can be extracted by a circuit smaller than the FFT circuit originally required for FFT processing of the symbol received in the high frequency receiving circuit 42. That is, if the circuit configuration shown in FIG. 19 is adopted, the circuit scale of the FFT / descramble processing means 44 can be reduced. [0195] The circuit configuration of the receiving device illustrated in FIG. 19 illustrates the case where the receiving symbol is halved, but it can be divided into 4 or 8 by further reducing the passing carrier in the filter device 49. As a result, the circuit scale of the FFT / descramble processing means 44 becomes smaller. [0196]<u style="single">6th Embodiment of the receiving device</u>FIG. 20 is a configuration diagram of a receiving device according to a sixth embodiment of the present invention. In the receiving device 40E, the receiving antenna 41, the high frequency receiving circuit 42, the first filter device 49A, the second filter device 49B, the switch circuit 50, the buffer circuit 52, the FFT / descramble processing means 44, and the illustration are omitted. FIG. 1B has an illustrated bit extraction circuit 45 and a decoding circuit 46. [0197] The high frequency receiving circuit 42 operates in the same manner as described above. [0198] The filter devices 49A and 49B can have the circuit configurations of the various filter devices 49 described above, the first filter device 49A extracts signals of even carriers, for example, and the second filter device 49B has a second filter device 49B. For example, the signals of odd-numbered carriers are extracted. That is, in the present embodiment, the filter devices 49A and 49B decimate the symbols by 1/2, respectively. [0199] In the initial state, the switch circuit 50 outputs the even-numbered carrier signal output from the filter device 49A to the FFT / descramble processing means 44. During that time, the odd-numbered carrier signals selected by the filter device 49B are accumulated in the buffer circuit 52. [0200] The buffer circuit 52 continues to accumulate the signals from the filter device 49B until all the signals applied to the FFT / descramble processing means 44 extracted by the filter device 49A are transferred to the FFT / descramble processing means 44. [0201] The FFT / descramble processing means 44 is configured as a circuit that performs FFT processing on the number of subcarriers smaller than the number of subcarriers received by the high frequency receiving circuit 42 output from the filter device 49A. That is, the FFT / descramble processing means 44 is configured to be compact and capable of high-speed operation. After performing FFT processing or the like with the FFT / descramble processing means 44, processing is performed by the bit extraction circuit 45, decoding circuit 46, etc. illustrated in FIG. 1 (A). [0202] The buffer circuit 52 transfers the signals of the even carriers from the filter device 49A to the FFT / descramble processing means 44, and then transfers the signals accumulated in the FFT / descramble processing means 44 via the switch circuit 50 to the FFT / descramble processing means 44. Transfer to descramble processing means 44. [0203] When the signal transfer from the filter device 49A to the FFT / descramble processing means 44 is completed, the switch circuit 50 switches so as to apply the signal from the buffer circuit 52 to the FFT / descramble processing means 44. [0204] The filter device 49B and the buffer circuit 52 generate a signal that has passed a signal component required for this communication among the signal components that have not passed earlier, for example, an odd number carrier, and apply the signal component to the FFT / descramble processing means 44. To do. [0205] The FFT / descramble processing means 44 performs FFT processing on the re-input signal to extract a received symbol, and causes the circuits after the bit extraction circuit 45 to be processed. [0206] By adopting the circuit configuration of the receiving device illustrated in FIG. 20, it is possible to extract the received symbol with a circuit smaller than the FFT circuit originally required for FFT processing of the symbol received by the high frequency receiving circuit 42. That is, if the circuit configuration shown in FIG. 20 is adopted, the circuit scale of the FFT / descramble processing means 44 can be reduced. [0207] The circuit configuration illustrated in FIG. 20 exemplifies the case where the received symbol is decimmed in half, but it can be divided into 4 or 8 by further reducing the passing carriers in the filter devices 49A and 49B. As a result, the circuit scale of the FFT / descramble processing means 44 becomes smaller. [0208] The communication system, the transmitter (transmitter) 30, the receiver (receiver) 40, and the signal component separator and the filter device that form a part of the receiver (receiver) 40 of the present invention are limited to the above-described configurations. However, various modifications or the above-described embodiments can be combined as appropriate. [0209] Although the wireless communication system has been illustrated as the embodiment of the present invention, the present invention can be applied not only to the wireless communication system but also to the wired communication system and the like. [0210] [Effect of the invention] According to the present invention, it is possible to provide a signal component separator capable of appropriately separating a multicarrier modulated signal. [0211] According to the present invention, from a 1-input multicarrier modulated signal group to 2<sup>c</sup> A signal component separator that separates signals into a signal group of (c is an arbitrary integer) could be provided. [0212] According to the present invention, it is possible to provide a filter device that selects a specific 1-output signal group from a 1-input multicarrier modulated signal group. [0213] According to the present invention, it is possible to provide an appropriate receiving device having the above signal component separating device. In the receiving device of the present invention, the circuit scale of the FFT can be reduced, and the FFT processing is high speed. [0214] According to the present invention, an appropriate receiving device having the above-mentioned filter device can be provided. In the receiving device of the present invention, the circuit scale of the FFT is miniaturized, and the FFT processing is high speed. [0215] According to the present invention, it is possible to provide a communication system in which a transmitting device that performs multicarrier modulation and the receiving device cooperate with each other. [0216] According to the present invention, it is possible to provide a communication method for performing multicarrier modulation and its demodulation. [Simple explanation of drawings] 1A and 1B show, for example, the communication system, the transmitting device and the receiving device of the present invention, and the OFDM method as the multicarrier modulation method as one embodiment of the communication method, for example. , A configuration diagram of a digital wireless communication system applied to a DAB system, FIG. 1 (A) is a configuration diagram of a transmitter of an OFDM system wireless communication system, and FIG. 1 (B) is a configuration diagram of an OFDM system wireless communication system. It is a block diagram of a receiving device. 2 (A) to 2 (C) are graphs showing the processing of the transmitter illustrated in FIG. 1 (A), and FIG. 2 (A) shows independent symbol streams for each channel. 2 (B) is a schematic configuration diagram of the multiplexer illustrated in FIG. 1 (A), and FIG. 2 (C) is a graph showing a multicarrier modulated signal. FIG. 3 is a graph showing a sequence of multi-channel subcarriers modulated by the transmitter of FIG. 1 (A). FIG. 4 is a configuration diagram of a signal component separator illustrated in FIG. 1 (B). FIG. 5 is a configuration diagram of a two-branch circuit constituting the signal component separator illustrated in FIG. FIG. 6 is a diagram showing an embodiment of the symbol delay circuit illustrated in FIG. FIG. 7 is a diagram showing an embodiment of the phase offset adjustment circuit illustrated in FIG. FIG. 8 is a configuration diagram of a receiving device as a second embodiment of the present invention. FIG. 9 is a configuration diagram of a frequency offset compensation / removal circuit illustrated in FIG. FIG. 10 is a configuration diagram of a receiving device as a third embodiment of the present invention. FIG. 11 is a schematic configuration diagram of a receiving device according to a fourth embodiment of the present invention. FIG. 12 is a configuration diagram of a first embodiment of the filter device shown in FIG. FIG. 13 is a configuration diagram of a second embodiment of the filter device of FIG. FIG. 14 is a block diagram of the filter decimation circuit illustrated in FIG. FIG. 15 is a configuration diagram of a third embodiment of the filter device illustrated in FIG. FIG. 16 is a configuration diagram of a fourth embodiment of the filter device illustrated in FIG. FIG. 17 is a configuration diagram of a filter decimation circuit illustrated in FIG. FIG. 18 is a configuration diagram of a fifth embodiment of the filter device illustrated in FIG. FIG. 19 is a configuration diagram of a receiving device according to a fifth embodiment of the present invention. FIG. 20 is a configuration diagram of a receiving device according to a sixth embodiment of the present invention. 21 (A) and 21 (B) are diagrams showing a configuration example of a digital wireless communication system using an OFDM system applied to a DAB system or the like as a multi-carrier modulation system. FIG. 21 (FIG. 21). A) and a configuration diagram of the transmitting device, and FIG. 21 (B) is a configuration diagram of the receiving device. FIG. 22 is a graph showing an example of a multi-carrier symbol string output from the transmitter of FIG. 21 (A). FIG. 23 is a graph showing a conventional first method of separating multicarrier signals. FIG. 24 is a configuration diagram of a receiving device showing a conventional second method of separating multicarrier signals. FIG. 25 is a graph showing the extraction of conventional carriers having a fixed cycle. [Explanation of symbols] 10 ... Wireless transmitter 11 ... Coding circuit 12 ... Symbol mapping circuit 13 ... Multiplexer (signal multiplexing processing circuit) 14 ... Frequency interleaving circuit 15 ... Inverse Fast Fourier Transform (IFFT) 16 ... Wireless transmission circuit 17 ... Antenna 20 ... Wireless receiver 21 ... Antenna 22 ... Reception circuit 23 ... Fast Fourier Transform (FFT) 24 ... Symbol selection circuit 25 ... Bit extraction circuit 26 ... Decoding circuit 30 ... Transmitter (transmitter) 31 ... Coding circuit 32 ... Symbol mapping circuit 34 ... Multiplexer (signal multiplexing processing circuit) 36 Scramble processing IFFT Guard time added Window processing circuit 38 ... Transmission circuit 39 ... Antenna 40 ... Receiver (receiver) 41 ... Receiving antenna 42 ... High frequency receiver circuit 43 ... Signal component separator 43a ... Symbol delay circuit 43b ... Phase offset adjustment circuit 43c ... Addition circuit 43d ... Subtraction circuit 44 ... FFT / descramble processing means 45 ... Bit extraction circuit 46 ... Decoding circuit 47 ... Signal selection circuit 48A, 48B ... Frequency offset compensation circuit 481 ... Multiplier 482 ... Gyrator (oscillator) 483 ... Symbol sorting circuit 49 ... Filter device 491 ... Signal component separator (demultiplexer) 492 ... Symbol group selection circuit 493 ... Frequency offset compensation / removal circuit 494 ... Subcarrier selection circuit 495 ... Filter decimation circuit 495a ... Symbol delay circuit 495b ... Phase offset adjustment circuit 495c ... Addition circuit 496 ... Multiplier 497 ... Passing subcarrier selection signal output circuit 498 ... Symbol sorting circuit 499 ... Filter decimation circuit 50 ... Switch circuit 52 ... Buffer circuit
27 sheets
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Every citation, both ways
| Document | Relation | Office |
|---|---|---|
| WO00003508A1 | Cites | World Intellectual Property Organization (WIPO) |
| JP11041197A | Cites | Japan |
| JP2000332722A | Cites | Japan |
| JP2001223668A | Cites | Japan |
14 members in 2 offices
Priority claims7
| Document | Office | Kind | Date |
|---|---|---|---|
| 2000046820 | Japan | A | |
| 2000046820 | Japan | A | |
| 2000046820 | Japan | – | |
| 2001036727 | Japan | A | |
| 2000200046820 | – | – | – |
| JP20000046820 | – | – | – |
| JP20010036727 | – | – | – |
Members14
| Document | Office | Kind | |
|---|---|---|---|
| JP2001308818A | Japan | A | |
| US2001040928A1 | United States of America | A1 | |
| US6816555B2 | United States of America | B2 | |
| US2005025253A1 | United States of America | A1 | |
| US7133458B2 | United States of America | B2 | |
| US2007053457A1 | United States of America | A1 | |
| US7545872B2 | United States of America | B2 | |
| US2010002780A1 | United States of America | A1 | |
| US7660361B2 | United States of America | B2 | |
| US2010135440A1 | United States of America | A1 | |
| US2010135441A1 | United States of America | A1 | |
| JP4622115B2This record | Japan | B2 | |
| US7965781B2 | United States of America | B2 | |
| US8325834B2 | United States of America | B2 |
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Numbers
- Publication
- 4622115
- Publication, DOCDB
- 4622115
- Publication, EPODOC
- JP4622115B
- Application
- 36727
- Application, DOCDB
- 2001036727
- Application, EPODOC
- JP20010036727
Titles2
- Japanese
- 信号成分分離装置、フィルタ装置、受信装置、通信装置、および、通信方法
- English
- Signal component separator, filter device, receiver, communication device, and communication method
Classification
- IPC, 1
- H04J11 00
