Method and apparatus for logic synchronization

[Technical field to which the invention belongs] The present invention relates to a semiconductor device. More specifically, the present invention relates to the synchronization of logic circuits within a semiconductor device. [0001] [Conventional technology] Clocking in digital logic circuits Purpose of the clock A clock is a periodic signal used for timing and synchronization purposes in synchronous digital logic circuits. The clock determines the time during which a logical operation is performed by the circuit. A logical operation involves propagating a state through a series of logic gates. [0002] In a synchronous circuit, the propagation of the logical state is initiated by the Source Clock Edge. After propagating through the path of the logic gate, the resulting logical state is sampled by the Destination Clock Edge. The destination clock edge is generated from the clock event that follows the clock event that generated the source clock edge. [0003] Since it takes time to propagate the state through the gate path, the logical path is in the new state (valid for this cycle) and the old state (invalid for this cycle) for some time after the source clock edge. Will include. Generally, at the end of a given time (which is often defined as a clock cycle), the valid state has propagated through the entire path or set of paths and is invalid in the circuit. There is nothing in that state anymore. The subsequent clock edge starts a new process. [0004] Logical operations performed in electronic circuits propagate through the paths of both branching and converging logic gates. When a logical path converges or is combined with another path, it must do so at similar points in time, at which point the various convergent paths all have valid data. This point in time is determined by the arrival time of the latest arrival data. In general, there are other faster paths that are converging at this point, and valid data must be retained until they are successfully combined with later arriving data. In most digital circuits, one or more clocks provide this synchronization capability. Therefore, the clock can be thought of as performing an adjustment or adjustment function, slowing or holding a faster path until a slower path becomes effective. [0005] Generally speaking, logic circuits are required to work as quickly as possible. Therefore, it is highly desirable that the clock perform their tuning function with as little loss as possible on the operating speed of the circuit. [0006] Clock Skew Clock skew is a component of timing error that can interfere with the clock adjustment function and reduce the maximum operating speed of the circuit. The definition of clock skew is "difference in arrival time between clock edges derived from the same clock event but associated with physically separate clock nodes". [0007] For example, the master clock is generally distributed to many propagation destinations by some means. The distribution means may be as simple as a network of wires or may include multiple levels of active buffers. Figure 1 shows a clock system with a single clock source (usually a phase-locked loop, PLL, or digital delay loop, DLL) followed by several generators. .. The generator transforms a single clock source into multiple clocks. Deformations that occur within the generator can be a direct delay in the source clock, an inversion of the source clock, or a change in the shape of the clock waveform (eg, a change in duty cycle, a change in slew rate, etc.). Alternatively, it can be any combination of the aforementioned variants. In either case, the propagation time of the clock edge through this distribution path requires a certain non-zero time. The propagation time to each propagation destination can be adjusted smaller or larger depending on the design, depending on the design needs. However, in practice, analyzing or simulating a clock distribution circuit to predict the actual clock skew with full accuracy is costly (in terms of design effort). [0008] In fact, even with complete design knowledge, it is not possible to control skew with perfect accuracy due to normal manufacturing variations throughout the circuit. For example, certain clock dividers may become more resistant in parts of the circuit to some extent due to localized variations in connection thickness or width. This can lead to an always longer delay to the clock propagation destination at the end of this line relative to other clock propagation destinations on a particular die. [0009] It can be seen that the clock skew has both predictable and unpredictable components. Although somewhat difficult, the designer can adjust or control the clock skew within certain limits. In practice, this control is also limited by design time limits as well as normal manufacturing and environmental variations. Due to the consequences of the difficulty of fully controlling the clock skew and the harmful effects of the clock skew, the design is tolerant of any instability of the clock skew between various clock propagation destinations. It is important to be. [0010] Clock Jitter Clock jitter, like clock skew, is a component of timing error, which can adversely affect the clock adjustment function and the operating speed of the circuit. Clock jitter is defined as "error or variation in the arrival time of clock events on a single clock node." This error or variation is relative to the ideal or intended arrival time (usually specified for the previous clock event). That is, clock skew indicates the arrival time of the same event at physically separated locations, while clock jitter indicates the arrival time of different events at the same physical location. Clock jitter can be somewhat different for each clock node. [0011] Clock jitter is rarely introduced intentionally into a clock network (with one exception being the intentional frequency modulation of the clock). Jitter can be caused by several factors. Jitter may be present on the input clock of the circuit. It is generally passed through a distribution network. It may also be introduced by a part of a clock generation logic circuit such as a PLL. For example, FIG. 4 illustrates the introduction of jitter by a clock generation logic circuit and shows a feedback system control system (typical PLL) connected to the transfer function of Z (clock generator). The PLL contains a stable phase error that affects the edge placement. Noise sent into the system at various points will cause a temporary reaction within the system. Noise can be generated by either the reference signal θ (t), the phase comparator, the loop filter, the voltage controlled oscillator (VCO), the clock generator (Z) or the wiring connecting these components. For these components, the main source of noise is the voltage source (power supply and ground), and for the wiring, the concatenated noise. [0012] Clock jitter can also be caused by power supply noise and inductive signal coupling or capacitive signal coupling. The effect of jitter is to shorten or lengthen the clock period recognized by a particular part of the circuit. For example, if a particular clock edge is delayed from the arrival time predicted by the previous edge, the end clock period is lengthened, but the subsequent clock period is shortened. [0013] Clock jitter that varies between various clock propagation destinations can also increase clock skew. For example, local power supply noise can cause clock edges to arrive early at one location, but the same clock edge can arrive at another location on time. [0014] Clock jitter can be short-term and cause cycle-to-cycle variation in clock cycles, or it can be long-term and affect a series of continuous cycles in a similar manner. Jitter can also change the duty cycle of a clock from its intended value. Usually both short-term and long-term components are present in the clock. [0015] Setup Hazard and Hold Hazard Setup hazards and retention time hazards can exist in the absence of clock skew or jitter, but skew (especially unpredictable skew) and jitter generally reduce the potential and severity of these hazards. Increase. Setup hazards occur when the clock edge is sampling data that arrives very late compared to the clock. If the data is too late or the sampling clock is too early for the intended arrival time, invalid data will be sampled and the circuit will malfunction. These hazards are also called slow path hazards or critical path hazards because they are associated with paths designed with the longest propagation delay. [0016] Since the logical path starts at the source clock and ends by sampling at the destination clock, the setup hazard is affected by the delay between the source clock and the destination clock as well as the logical path delay. Setup hazards can be less severe or even eliminated by slowing down the clock frequency. Therefore, setup hazards limit the high frequency performance of digital circuits, but do not prevent them from operating properly at lower frequencies. [0017] In contrast, retention hazards occur when you mistakenly sample data that was valid but invalid again before the sampling cycle is complete. Retention time issues are also called fast path problems. [0018] As mentioned above, the destination clock edge is usually generated from the clock event that follows the clock event that generated the source clock edge. Fluctuations in retention time occur when data is sampled by a destination clock edge that is actually derived from the same clock edge that generated the source clock. This is when the data propagates too fast from the source to the destination, or when the destination clock edge occurs too late compared to the source edge generated from the same root clock event. Can occur. It is important to note that retention hazards are not mitigated by changing the clock frequency, as retention hazards are related to timing between clock edges derived from the same event. Violations of retention time prevent the circuit from operating at any frequency. For this reason, retention time violations are more serious than setup time issues. Retention time issues can be fixed by inserting additional delays into the fast data path, delaying the source clock, accelerating the arrival time of the destination clock, or a combination of these methods. [0019] The cost of synchronization in static logic circuits The part of the cycle associated with logic circuit synchronization is called synchronization overhead and represents the time spent without computational work. Obviously, for high performance designs, it would be desirable to maximize the amount of work that can be achieved in a given amount of time. Spending time on synchronization overhead deviates from this goal by reducing the computational efficiency of the design. [0020] Figure 2 shows a simple logical path that contains two logical paths. One pass begins with flip-flop 1 and ends with flip-flop 2. The other pass begins with flip-flop 2 and returns to flip-flop 1. If there is no unpredictable skew or jitter in the clock, the cycle time determined by the round trip delay through these two paths can be calculated by: [0021] [0021] T (O₁+ D + S₂+ O₂+ D'+ S₁) / 2 (Equation 1) here, O_i= Output delay of flip-flop i O₁And O₂= Output delays for flip-flops 1 and 2, respectively S₁And S₂= Setup time for flip-flops 1 and 2, respectively S_i= Flip-flop i setup time, and D and D'are delays in the logical path. [0022] Figure 3 shows a typical clock signal with a 50% duty cycle. The clock period T is measured from the midpoint of the rising edge of the clock signal to the midpoint of the rising edge of the clock signal. The skew is represented by shades around the rising and falling edges of the clock. Note that the first rising edge is taken as a reference point and has no skew. Although this figure illustrates this situation, it is also important to note that in practice it describes skew between unique points in the clock network. In relation to FIGS. 2 and 3, the first rising edge of the clock (Figure 3) is measured at the clock input of flip-flop 1 (Figure 2), while the next rising edge of the clock is the flip-flop. Measured with 2 clock inputs. [0023] Predictable clock skew is fairly easy to deal with, and in some cases can even be utilized. For example, if flip-flop 2 is known to employ a slightly slower version of the clock than flip-flop 1, the designer can actually get the data a little later. In this case, the flip-flop 1 reaches the rising edge earlier than the flip-flop 2, so that the time to pass through the logic gate is short in the next cycle. Flip-flop 1 has no skew to itself, so the data must go through the entire loop path in two cycles. If all skews are predictable, then equation (1) will show the minimum cycle time, in which case the two path delays will be averaged. [0024] Unpredictable clock skew poses a different problem. If the designer does not know what the skew looks like between flip-flop 1 and flip-flop 2, the designer must assume the worst. That is, in the first cycle, the flip-flop 2 is assumed to be faster than the flip-flop 1, and in the second cycle, the opposite is true. In this way, the data arrives on time, no matter which case is true. Unfortunately, this means that for this part of the skew, the designer cannot take advantage of the delayed clock as described above. Equation (2) expresses this two-cycle path as follows. [0025] T (O₁+ D + S₂+ O₂+ D'+ S₁+ 2K_u) / 2 (Equation 2) Where K_u= Unclear part of clock skew. [0026] If the effect of clock jitter is also added to this delay equation, then: [0027] T (O₁+ D + S₂+ O₂+ D'+ S₁+ 2K_u+ 2J) / 2 (Equation 3) Where J = clock jitter. [0028] The cause of unpredictable clock skew is independent of clock frequency. This is a flip-flop delay (O)₁, S₁), And generally the clock jitter. This poses a major problem with high frequency design, as the proportion of clocks dedicated to synchronization overhead increases when designing for higher frequencies with a given technology. At some point, this overhead becomes prominent, and the benefits of higher frequency designs are outweighed by the reduced computational efficiency of logic circuits. Obviously, for very high frequency designs, designers need to consider ways to minimize synchronization overhead. [0029] One design method that minimizes synchronization overhead is to separate the two latches that form the flip-flop and provide a logic circuit between the two latches. The designer then adjusts the timing of the logic circuit so that the latch is transparent when the evaluation edge (of the clock signal) of the slowest logic path arrives at the input of the latch. Here, the clock skew leads to the clock edge controlling the latch so that it operates almost on time, so the slowest path is unaffected (assuming the clock skew is not too large). This is a skew resistant design. The clock skew in this type of design can be as large as the time between the ideal clock edge time and the time the evaluation edge of the slowest path arrives at the latch input. If the designer adjusts the timing of the evaluation edge so that the evaluation edge arrives in the middle of the positive clock pulse for each latch (time when the clock is high), the design is full of 1/4 cycle of skew. Can withstand. Another advantage of this scheme is that the evaluation edge can be slightly removed from this point without loss (assuming the skew is less than 1/4 cycle). Therefore, the skew-resistant design eliminates skew loss and output and setup delays through the latch from the cycle time. However, this design adds a propagation delay through the latch, which modifies the cycle time equation as follows: [0030] T (D₁+ D + D₂+ D'+ 2J) / 2 (Equation 4) Where D₁And D₂= Delay through latches 1 and 2, respectively D and D'= delay through logical path J = clock jitter [0031] The above design format does not eliminate the effects of long-term clock jitter, which reduces clock cycle time. Although there is a delay loss in latch propagation time, this loss is generally less than the loss incurred in flip-flops. [0032] Synchronization in clock precharge logic circuit Clock synchronous precharge logic circuit (CP logic circuit / crocked precharge) logic) is a design format that often has speed advantages over static CMOS logic circuits and can provide additional advantages in overcoming synchronization losses. Unlike static gates, CP gates have unique synchronization characteristics. The CP gate has two main operating phases: precharge and evaluation. Since this can be switched only once during the evaluation phase, it can be considered that the value is retained until the start of the precharge phase. More importantly, CP gates cannot be switched until the beginning of their evaluation phase (unlike static CMOS gates, which can switch whenever the input changes). [0033] The CP gates are connected and clocked in such a way that the first gate evaluates sequentially, the next gate evaluates, and so on until all the gates in the path have evaluated. When the clock to these gates (this is called the clock PH1) switches to its precharged state, these gates precharge and lose that state. Therefore, it is necessary to memorize the result of the calculation before precharging the gate. This is typically done by stringing the output value of the final gate at the end of the evaluation period before the precharge begins (ie, with a clock similar to the PH1 clock of the CP gate). Here, this structure is similar to the arrangement of static logic gates in the design form of the latch system. This latch or set of latches provides input to another set of CP gates that are typically clocked by a clock that is the opposite of the clock of the CP gates of the first set (this is called clock PH2). To do. In this way, the first set is evaluating and the second set of CP gates is precharged while the latch between the two sets of CP gates is transparent. When the gates of the first set are precharged (when PH1 is Low), the latch retains its state and the gates of the second set detect the latch output and begin evaluation. As with the first set of CP gates, the results obtained from the second set of CP gates must be latched (when PH2 is High) during their evaluation phase. The output of the second type latch (PH2 latch) can then drive more first type CP gates (PH1 CP gates). This logic circuit and synchronous form are known as CP logic circuits without skew resistance because they are susceptible to clock edge skew and jitter. Figure 5 shows this type of logic circuit. [0034] The cost of synchronization in CP logic circuits without skew resistance CP logic circuits without skew resistance suffer the clock loss described above. The CP gate can only be evaluated when the clock is High, but the evaluation must be completed by the time the clock switches from High to Low so that the results can be stored in the latch at the end of the phase. This format is affected by the unpredictable skew of both edges of the clock, as the results must be set up on the latch in time for sampling. Incorrect results are sampled if the data is slow or the latch clock is fast. Therefore, referring again to FIG. 5, the following equation shows the cycle time. [0035] TD₀+ D + D₁+ D'+ 2K_u+ 2J (Equation 5) Where the delay through Di = Latch I K_u= Unclear part of clock skew J = clock jitter [0036] This synchronization scheme suffers from problems very similar to those encountered in flip-flop static logic circuit design. [0037] Logic circuit synchronization is the process of controlling all timings of logic signals in a system. The present invention is a method and apparatus for describing a synchronization mechanism that withstands skew and jitter as much as possible in order to reduce the minimum operating cycle time for logic circuit devices. However, the synchronization mechanism is best understood in the context of logic circuits, and the logic circuits used to describe the present invention are "Method and MFP for a N-Nary logic circuit using 1 of 4". N-ary logic circuits as described in U.S. Patent Application No. 09/019355, a co-pending application filed May 2, 1998, now U.S. Pat. No. 6069665 under the name "Encoding". Is. Briefly, this group of logic gates can be thought of as a non-inverting clock prechurch circuit that precharges when the clock input signal is low and evaluates when the clock input signal is high. Figure 10A shows a 1-4 logic circuit typical of an N-nary logic family. [0038] An efficient processor design operates a logic gate at its maximum speed, where the gate speed is the sum of its logic propagation time and its node regeneration time. A static logic gate "regenerates" when the gate encounters a new input value. Dynamic gates, on the other hand, require an explicit precharge operation to prepare for the next set of inputs. The logic gate operates at its duty cycle limit when there is no time when the output has not transitioned to the evaluation level or the precharge level. Figures 9A and 9B illustrate this concept, where t_eIs the evaluation time, t_pIs the precharge time, t_soRepresents a stable output. [0039] A given dynamic gate has one or more significant inputs and one output. When in the evaluation phase, the output of the dynamic gate responds to the input. When in the precharge phase, the dynamic gate output returns to the regenerated level. Note that Figures 9A and 9B show the gates (outputs) that transition during each evaluation phase. This is not the case for traditional dynamic gates, which only transition when the gate evaluates to "true." However, the N-ary logic circuit includes multiple wires, and only one wire transitions in each evaluation. In some cases, there may be no wiring to evaluate, so the output may not transition. Therefore, from the point of view of the signal in the N-ary logic, FIGS. 9A and 9B represent the N-ary output signal, which is the logical sum of the output wiring as shown in FIG. 10B. Is the equivalent of. [0040] FIG. 9B shows the desired mode of operation of the dynamic gate. Once the output signal is read (when the transition is complete), the gate begins to regenerate, so there is little or no time for the output signal to be stable. Then, once the reproduction is finished, the gate starts the transition again. Under these conditions, a logic gate is known to distribute as many logic operations as the gate can distribute at a given time. [0041] However, Figure 9A shows a more realistic application of dynamic gates, as is typical in prior art systems. As can be seen from the figure, a considerable amount of additional time is required both after the logic gate evaluation and after the logic gate precharge phase. Prior art has many technologies that make trade-offs by focusing on the evaluation and precharge cycle. Unfortunately, there is no prior art that directly focuses on gate efficiency. By focusing on improving gate efficiency, the present invention produces a better set of guidelines for producing processors with maximum performance, as well as alternatives that derive directly from the essence of the technology. Develop a new clocking method. [0042] Some logic gates are faster than others. The slowest gate is usually the designer's concern, while the designer can often ignore the faster gate. Gate speed is a greater issue for dynamic logic circuits, as the clocking required of a dynamic gate limits the position within the clock cycle in which the gate can perform its desired function. On the other hand, static logic circuits always perform their functions. Whenever an input arrives, the static gate switches accordingly. Nevertheless, efficient clocking methods should allow dynamic logic gates to perform their function over as long a time as possible. [0043] US Pat. No. 5,517,136 granted to Harris et al. (Name "Opportunistic Time-Borrowing Domino") Logic ") is an attempt at an efficient clocking method. A feature of this patent is that it provides some time borrowing between specific clock domains. The purpose of the Harris patent is to eliminate the need for a latch to store the output at the end of each half of the clock cycle, which is essentially some time stealing, or what this patent calls it. Allows "opportunistic time borrowing". However, the clock timing or synchronization asymmetry in the Harris patent limits the location within the clock cycle in which time borrowing can actually occur. In fact, the performance of the clocking method must be affected by clock instability, as borrowing cannot occur at any point in any path. [0044] Harris is a tracking document for patents, Harris, D., and Horowitz, M., Skew-Tolerant Domino Circuits, IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, pp. In 1702-1711 (November 1997), the above clocking scheme was extended to a more generalized approach for polyphase clock systems. In addition to extending the Harris patent to a more generalized approach for multiphase clock systems, the Harris document attempts to include tolerances for clock skew within clocking schemes. .. Unfortunately, this document was unable to distinguish between predictable and unpredictable clock errors. Also, this document does not understand the effect of clock jitter on the clocking scheme in addition to skew, and has not developed a method of measuring gate efficiency to guide a practical design. It argues against clocking methods similar to those disclosed in the disclosure document. [0045] US Pat. No. 5,434,520 (named "Clocking Systems and Methods for Pipelined Self-Timed Dynamic Logic") granted to Yetter, another prior art patent. Circuits ") is another attempt to optimize system clocking by focusing on improving evaluation and precharge cycles. This patent, like the Harris patent and Harris document above, implements an awkward and inefficient clocking system, which only improves inefficiencies in traditional dynamic logic circuits. is there. [0046] Overlapping Clocks Using Clocks Figure 6 shows one technique for achieving logic circuit synchronization, which is due to "stretching" the clock cycle. As mentioned above, there are numerous examples of stretch clocks in the prior art, including Harris patents, Yetter patents and Harris documents. It can be seen that the latch has a period when both clocks are high, and therefore the latch is transparent, and the CP gate on one side is in evaluation mode. This means that within the overlapping window, the evaluation edge can pass through the latch and immediately continue through the gate on the other side. Assuming that the latch is provided when both clocks are clearly high (ie, not within the skewed range shown in the drawing), skew is not an issue, as in the transparent latch design style. .. Equation 6 shows the relationship to the cycle time when using the clock stretched in this way. [0047] T (D₀+ D + D₁+ D'+ J) (Equation 6) Where the delay through Di = Latch I J = clock jitter [0048] Another advantage that designers can get with the stretch clock is the latch delay. The reason the latch was in the path was to hold the result of the phase of the logic circuit during the transition from one phase to the next. With overlapping clocks, it is possible to have logic feeding from a gate in one phase to a gate in the next phase while both of them are in evaluation mode. .. This means that there is an excess of latches. The only requirement is that the earlier gate does not precharge before its value propagates through the later gate. Figure 7 shows the paths implemented in this scheme, and equation 7 shows the clock cycle time as follows: [0049] T (D + D'+ J) (Equation 7) Where J = clock jitter [0050] Stretched Clocks problem However, there are some problems with this synchronization scheme. Duty cycles greater than 50% on the clock present many of the same physical obstacles not described in this disclosure document. Also, the hold time problem is exacerbated. Systems with a stretch clock are fast without considering skew or jitter. path) will cause retention time issues. Retention time issues require additional design work to adjust the fast path. In a typical design, there are several critical paths that require careful adjustment (potential setup time issues), but potentially many fast paths. The work done when adjusting the clock has the advantage of improving the performance of the logic chip when adjusting these paths. There is also a fast path (potential retention time issue) that the designer must adjust here. Adjusting these paths generally means inserting a delay (increasing the range) or "crafting" with a clock (misleading and requiring a great deal of analysis). In order to have a functional chip (at any frequency), it is necessary to solve the retention time problem, but there is no performance benefit to doing so. [0051] There are various ways to synchronize logic circuits within a pipeline on an integrated circuit. For example, Figure 16 shows a typical 4-clock system used in the Harris and Yetter patents. This type of clocking system typically has a master clock CLK.₁And vice versa clock CLK₃Is involved. The other two clocks, CLK₂And CLK₄Is a clock with a stretch clock cycle that may match the master clock or vice versa. For example, CLK₂The leading edge of is CLK₁Matches the leading edge of CLK₄The leading edge of is CLK₃Matches the leading edge of. Each complete cycle of the clock signal is two parts, even half cycle t_xAnd odd half cycle t_yAlso includes. Each half cycle of the clock k signal has a precharge period t_pAnd evaluation period t_eincluding. A common feature of this type of clocking system is its evaluation window 220, which has several overlapping phases, but is due only to clocks with a stretch clock cycle. [0052] Figure 13 shows a typical dynamic logic circuit described in the Yetter patent, which in this patent refers to the mousetrap logic. It is called circuit). This circuit includes a logic circuit 24 that performs some sort of logic evaluation on the two input signals 26 and 28 to generate the output signal 32. An output buffer device is connected to this logic circuit, which is the inverter 30 here. Further, a precharge device 22 using a clock signal CK is connected to the logic tree circuit in order to determine a period for recharging the dynamic node of the logic circuit. One drawback of this type of dynamic logic circuit is the difficulty of using this type of circuit for pipelines. Another drawback is the inability to stop the clock without losing information. The clocking synchronization of the present invention overcomes these drawbacks by using multiple clock domains with overlapping phases. [0053] 14A and 14B show the output buffering device in the Harris patent (US Pat. No. 5,517,136). FIG. 14A shows FIG. 1 of the Harris patent and FIG. 14B shows FIG. 2 of the Harris patent. The circuit of FIG. 14A uses an output buffer similar to the half-signal retainer of the present invention. When the output of the inverter is low, this transistor keeps the input high and stabilizes the gate. However, when the output is low, the input node can float if the input to the gate is removed. The circuit of FIG. 14B uses an output buffer similar to the complete signal retainer of the present invention, including N-channel transistors, especially for the purpose of keeping the output low when no input occurs. [0054] FIG. 14A is composed of logic circuit 41, which further consists of input signals A and B. This input signal A is connected to NFET44, and the input signal B is connected to NFET42. The NFET40 is an evaluation device for this circuit and the PFET46 is a precharge device. Both the evaluation device and the precharge device connect to the clock signal CLK. The circuit also includes an output buffering device consisting of an inverter 50 and a PFET 48. The output of the logic circuit 41 is connected to the inverter 54, which Harris calls a high skew device. Output 56 is connected to, for example, the next logic circuit, which could be the next circuit in the pipeline. Harris calls this type of logic circuit with an output buffer device a D1 type gate. [0055] FIG. 14B is composed of logic circuits 61, which further consist of input signals A and B. This input signal A is connected to NFET64, and the input signal B is connected to NFET62. The NFET60 is an evaluation device for this circuit and the PFET66 is a precharge device. Both the evaluation device and the precharge device connect to the clock signal CLK. This circuit also includes an output buffering device consisting of inverter 68 and inverter 70. The output of the logic circuit 61 is connected to the inverter 72, which Harris calls a high skew device. Output 76 is connected to, for example, the next logic circuit, which could be the next circuit in the pipeline. Harris calls this type of logic circuit with an output buffer device a D1K type gate. [0056] [Problems to be Solved by the Invention] Optimal clocking implementations are due to gate speed differences between simple gates and complex gates, gates with low output loads and gates with large output loads, and speeds due to manufacturing variations. Allow sufficient time borrowing from one dynamic gate to the next to deal with the difference between, and do so at every point in every path. In order to overcome the above problems of the prior art, the present invention provides an extremely flexible logic synchronization method and apparatus using a polyphase clock having overlapping phases. [0057] [Means for solving problems] The present invention is a method and apparatus for synchronizing logic in an integrated circuit (IC). The present invention includes a plurality of clock signals, each of which has a duty cycle of about 50% and overlapping phases. phase). The phases of these plurality of clocks overlap with the phase of the previous clock signal by the amount that the phase of each clock signal overlaps with the phase of the next clock signal by approximately equal to the amount of overlap. Further, the present invention includes a plurality of clocked precharge logic gates. Such CP logic gates are connected in series and do not require the intervention of latches, buffers or registers. The CP logic gate includes a logic evaluation circuits, an evaluate device and one or more signal keeper devices. Each CP logic gate is connected to an individual clock signal through its evaluation device. For data flows through individual CP logic gates, the logic gate takes its data input to the earlier CP logic gate in the series array (previous CP logic gate / earlier CP logic). It is received from the gate) and passed to the next logic gate (next CP logic gate) of the series array. Here, the above-mentioned "previous CP logic gate" is connected to the clock signal of the previous phase, and the "next CP logic gate" is connected to the clock signal of the next phase. Furthermore, the present invention also includes embodiments having 3, 4, 5, and 6 clock signals. Further, in the present invention, the logic gate is another logic circuit in a feed forward loop or a feedback loop, and is only a logic circuit using a clock signal of the next phase. It can be transmitted to. [0058] [0058] The present invention is also a method and apparatus for generating a clock signal for synchronizing logic in an integrated circuit (IC). And the present invention includes a master global clock. This master global clock is a low-skew method across the associated clock domain area. Dispersed by manner). In addition, a plurality of clocks are locally generated by buffering and delaying the rising edge or falling edge of the master global clock. Then, in the present invention, these locally generated clocks are associated with the master global clock. By locally adjusting the delayed master global clock, the plurality of locally generated clocks are adjusted, resulting in skew and jitter tolerance in the logic design. Further, the present invention includes embodiments having 3, 4, 5, and 6 locally generated clocks. [0059] The present invention also provides a method and apparatus for testing the logic state of a logic gate when the clock of the logic gate is stopped or started. The present invention includes a plurality of clock signals including overlapping phases and a plurality of CP logic gates connected in series. Each of the plurality of CP logic gates is individually connected to an individual clock signal. Further, the present invention includes one or more signal keeper devices. This signal retainer is connected to a predetermined individual CP logic gate in the critical path of the logic state. The signal retainer allows the logic state of the plurality of CP logic gates to be tested when stopping or starting individual clock signals for each of the plurality of CP logic gates. The present invention is suitable for a variety of testing techniques including IDDQ testing, scan testing and hardware emulation testing. [0060] BEST MODE FOR CARRYING OUT THE INVENTION The present invention relates to methods and devices for synchronizing logic circuits in integrated circuits (ICs). Other embodiments of the present invention include three-phase clocks, four-phase clocks, five-phase clocks and six-phase or more clocks. This disclosure describes a large number of specific details, including specific structures, circuits and logical functions, in order to provide a complete understanding of the present invention. Those skilled in the art will appreciate that the present invention can be practiced without these particular detailed description. It should be noted that this disclosure does not describe in detail well-known structures such as transistors so as not to obscure the present invention. [0061] Wave-clocked Skew Tolerant CP Logic Designers of high-performance systems can use multi-phase clocks with stretched clock cycles and overlapped clocks. We want to keep the advantages of clocks), but eliminate the disadvantages. The advantage is primarily due to the fact that both adjacent phase gates are in evaluation mode for a period of time (called the phase transition time). The biggest drawback is related to the fact that all gates are in evaluation mode at the same time. [0062] A duty cycle clock of 50% (or close to 50%) is desirable. One reason for this is the source clock, which has good cycle-time jitter characteristics. By dividing the clock) in half, the duty cycle skew can be controlled. But what happens to the system if you use three 50% duty cycle clocks that are 120 degrees out of phase? The duty cycle of the clock is especially important. The 50% duty cycle provides an amount of time for the gate output to rise for the gate output to rise. However, if the clock duty cycle deviates significantly from 50%, the time of the precharge phase or the evaluate phase in the operation processing is reduced. Therefore, a precharge transistor or evaluation can be completed within the allotted time. It is necessary to form a larger transistor). This is an inefficient use of the transistor area. Also, the larger the precharge transistor, the faster the precharge time of the CP gate, but in reality, a larger load is applied to the evaluation transistor, which slows down the evaluation time slightly. The reverse is also true. That is, if the evaluation transistor is made larger to speed up the evaluation time of the gate, the precharge transistor must also be made larger so that a larger capacitance can be precharged at the same time. [0063] FIG. 8 shows an embodiment of the invention showing a 3-clock signal or domain with a 50% duty cycle and an overlapping clock phase that is 120 degrees out of phase. Systems with overlapping clocks can easily transition from one phase to the next. If all clocks have a duty cycle of about 50%, there is no time when all three clocks are high. That is, the overlapping characteristic in the present invention means that any two consecutive clock signals overlap in their evaluation phase. And the 50% duty cycle clock not only makes it easy to generate, but also allows the CP gate to be precharged in half the cycle. Not all three clocks go high, so having every path have at least one gate for each clock phase frees you from holding time issues. (Note that there is no way to propagate the signal through and catch up with the preceding group of signals.) And you can transition outside the skew range (shaded in Figure 8). if Ru, the slowest signal The propagation time (and thus the cycle time) will be unaffected by the clock skew. Equation 8 shows the relationship with respect to cycle time. [0064] T (D₀+ D₁+ D₂+ J) (Equation 8) Where J = clock period jitter, D_iIs the propagation delay of gate i. [0065] The importance of this practical aspect of the invention cannot be overestimated. Prior art solutions can provide efficient design, but require substantial skill and time on the part of the designer, making the design process inefficient. The purpose of efficient high-performance design requires both design efficiency and design process efficiency. [0066] It will be described back to the three-phase clock in the above example. Focusing on the amount of clock phase overlap and its meaning, it can be seen that there is an overlap time of T / 2 to T / 3 or T / 6. This means that there is a 1/6 window of one cycle to transition from one phase to the next. Note that this is the overlap time for the ideal clock. This overlap time is reduced by skew and jitter. In general, if there are N clock phases, the resulting transition window time (W)_t) Is calculated by the following equation 9. [0067] W_t= T / 2-T / n- (J + K_u+ K_c) (Equation 9) Where J = clock jitter, K_u= Unclear part of clock skew, K_c= Controlled portion of clock skew, T = ideal cycle time, n = number of phases, and W_t= Transition window time. [0068] Aside from the effects of jitter and skew, the overlap between a phase and its previous phase is the same as the overlap between that phase and the next phase. Figures 18A, 18B, 18C and 18D show overlapping phases for 3, 4, 5 and 6 clock domain systems, respectively. [0069] The designer's goal is to pass the evaluation edge through the center of this transition window, which is skew. Tolerance) is maximized. Looking at equation 9, we can see that as the number of phases increases, so does the size of the transition window. The size of the window is not so important if the delays of many logic gates are all about the same, but if there is a significant difference in delay between different logic gates (usually this is the case), the evaluation edge It becomes difficult to pass through the center of the transition window. In this regard, if the designer makes a big mistake, the system may run into skew problems and need to slow down the clock to increase the size of the transition window. This provides the rationale for maximizing the number of phases in the clock. The number of phases is determined by the number of gates in the longest path. Therefore, when setting the number of clock phases, a given critical path (critical) It is desirable that there is a delay of exactly one gate for each phase in relation to path). And all other paths are required to have the same number of clock phases (although paths shorter than the longest path above have an additional buffer to deal with the extra phase. Will be). That is, in the logic circuit synchronization method according to the present invention, in a device including a group of CP gates, almost all signal paths need to pass the same number of clock phases. [0070] Clocking efficiency With reference to FIG. 9A, it can be seen that a single gate clock cycle has four regions. That is, first the precharge period t_pDuring this period, the gate is precharged to a known logical value. Following this precharge period, there is a period during which the clock switches from Low to High (although the input to the gate is not valid during this period). This period is the skew-tolerance period t_stCan be thought of. The reason is that the path is specially designed so that the input is not valid until the gate is known to be in evaluate mode (for example, the evaluation edge is at some point after the clock arrives). arrive). Then, the evaluation period t_eHere, the gate input is valid and the gate actually evaluates. This period can be thought of as the time it takes for the evaluation edge to pass through the logic gate. Finally, the output-hold-time period t_soIn this period, the output is kept constant until it is found that the next gate has captured the output value of the previous gate. And from here, the process is restarted by precharging the gate. [0071] It is desirable to use logic gates as efficiently as possible. In other words, it is desirable to optimally arrange four phases with different operations for the gate. You can calculate the amount of time required for "precharge," "skew tolerance," "evaluation," and "hold time" for a particular logic function and then generate the correct clock for those times. .. One of the important points to consider in this synchronization scheme is an attempt to reduce the difference in evaluation time required by the logic circuit for each phase. This reduces the size of the transition window and improves cycle time. One way to reduce this "evaluation time difference" is to ensure that the logic functions performed for each phase contain exactly the same number of gates. Any number of gates can be used as long as there is little difference in speed between the different gates. It should also be noted that the larger the amount of phase overlap, the larger the size of the transition window, which indicates that the number of clock phases increases (as a result, the gate for each phase). The number decreases). Therefore, a preferred embodiment of the present invention has one gate for each clock phase. FIG. 9B shows the clocking mode of the present invention when using the above design principles. [0072] Clock generation There are basically two ways to generate different clock phases in a polyphase clocking system. First, it is possible to generate multiple clocks by delaying a single clock. Alternatively, a phase detector can be used to generate a large number of appropriately out-of-phase clocks from a single clock. If you want to route with only a single clock, you have to build different phases from multiple clocks that are delayed by that single clock. [0073] In a preferred embodiment of the invention, a single global master clock is distributed in a low skew manner throughout the relevant clock domain area. The individual phases are generated for multiple local regions by buffering and delaying such a master clock. This approach has two main advantages. First, since the skew is a single electrical node, the skew is well controlled throughout the master clock. Second, multiple local phase clocks can be deliberately skewed with fine-grained control. This is because the plurality of local phase clocks are supplied to a fixed number of gates. The local phase clock that rises in the first half of the cycle defined by the master clock is derived from the rising edge of the master clock. Also, the rising phase in the second half of the master clock cycle is derived from the falling edge of the master clock. Thus, when the clock is stopped, at least one phase clock is precharged. This prevents race-through. [0074] Tuning the Transition Window The advantage of using multiple clocks locally generated from a single global clock source is that each local phase clock for a particular context can be tuned. Such clock delay adjustability allows some degree of non-uniformity in gate delay. For example, suppose there are multiple gates with a relatively long propagation time, followed by one gate with a relatively short propagation time. If one local phase clock regulates one gate with such a short propagation time, the clock arrival time of that gate can be adjusted to delay it more than usual. This allows the evaluation edge of this gate to be more centered within the period that its clock is high. As a result, higher skew and jitter tolerance is achieved than otherwise. The earliest and latest arrival times of gate inputs are easily determined by a static timing analysis tool or a dynamic analysis tool. Thus, this design method adjusts the clock phase delay to match the evaluation time of the gate within the cycle. It is also important to note that the clock adjustment method is not iterative. A single static or dynamic timing analysis (assuming the clock does not interfere with critical path timing) can be used to properly tune the clock. This is important from the standpoint of efficiency in the design process. [0075] There is a limit to the degree of non-uniform gate delay that can be included in the design as efficiency begins to decline. Even with a slow-paced gate, clock adjustments allow some of the evaluation time of its adjacent gates to be used, but the "slow-paced gate" must still be precharged. It doesn't become. Gates that perform "evaluation" at a slow pace also tend to "precharge" at a slow pace. Therefore, design efficiency cannot be optimized by cycle stealing with only "evaluation time". In practice, some gates "precharge" faster than they do during "evaluation" (generally complex functions and light output loads), but such are not common. Therefore, the overlap of evaluation periods in efficient design is primarily intended to tolerate clock instability. [0076] Why is the gate clock regulated? As mentioned above, clocks are needed to prevent fast signals from going too fast. That is, the clock is there to slow down the event. Therefore, when designing a clock, the fast paths should have the required impact and the slow paths should have as little impact as possible. And the biggest advantage of clocked-precharged logic is that the transistors used for synchronization are closer to the evaluation path of the logic. That is, there is no advantage in propagating logic processing through devices that exist only for synchronization purposes. As an alternative, synchronous devices are designed to create virtual power nodes and ground nodes that turn gates on and off. [0077] Why the gate needs to hold its output The gate must hold the output long enough for the subsequent gate to initiate the "evaluation" process. We know that two clock phases alone cannot form a critical design due to unpredictable causes of skew. This is because there is no overlap between the evaluation period of one clock phase and the evaluation period of the next clock phase. (Note that the Harris paper teaches a configuration that uses two clocks. This is a simple design, but it is not feasible due to the difficulty of adjusting both fast and slow paths. However, the three clock phases provide a 1/6 cycle overlap between one clock phase and the next clock phase, as shown in Figure 18A. Figure 18B shows four clock phases. Figure 18C shows five clock phases and Figure 18D shows six clock phases. As shown in Table 1, there is a direct relationship between the number of phases and the amount of overlap in the evaluation period. [0078] [table 1]<img file="JP4599485B2_D0001.tif" />[0079] All of the clock waveforms illustrated in relation to different clocking methods are well balanced, resulting in maximum unpredictable error tolerance and as much as possible. Time borrowing is realized. The method chosen should only be determined by the sum of the amount of error present and the desired amount of time borrowed. [0080] [0080] In a typical 0.18u process, the dynamic gate can be evaluated at 100ps to 200ps and precharged at 150ps, which allows the gate to cycle from 300ps to 350ps. Clock jitter (unpredictable error) can be controlled within 50ps. Therefore, if a 200ps gate rents 25ps on each side and is tolerant of 50ps jitter at each clock edge, then 50ps overlap between each clock domain must be guaranteed. is there. In the three-phase system, the maximum clock period would be 450ps (75ps at 1/6) for a peak clock rate of 2.222GHz. A four-phase scheme operating with similar constraints would require 300ps to satisfy the overlap, but four gates require at least 600ps, so this method sacrifices the clock rate. It provides jitter and time-borrowing tolerance that exceeds what is needed. Therefore, three-phase clocks (having overlapping phases) provide a good solution for synchronizing logic in most cases. Note that the three phases are the minimum numbers that eliminate the need to adjust fast paths. One of the differences between the Harris patent and other prior arts and the present invention is the construction of functional logic circuits. The logic circuit according to the present invention includes a signal keeper device as a part of such a functional logic circuit. Prior art usually separates logic circuits from a device that acts as an output buffer (or a device that acts as a type of signal holding function). However, in the present invention, such a signal holding circuit and an output buffer are regarded as a part of a logic circuit. As a result, in the present invention, it becomes possible to have a well-controlled evaluation node, and all the capacitances in the circuit are completely grasped. Further, by including the signal holding device as a part of the logic circuit, the present invention does not require a dedicated keeper inverter. For example, FIGS. 17A and 17B illustrate the need for additional inverters (additional inverters) in the present invention and correspond to FIGS. 14A and 14B. In FIG. 17A, output 222 represents an output from a circuit utilizing the teachings of the present invention. This output in a preferred embodiment is directly connected to the input of the next logic gate connected in series. Note that in the prior art, the output signal 56 (which leads to the next logic gate) must first travel through the additional inverter 54 (additional inverter). Similarly, in FIG. 17B, output 224 represents an output from a circuit utilizing the teachings of the present invention. This output in a preferred embodiment is directly connected to the input of the next logic gate connected in series. And it should be noted that in the prior art, the output signal 76 must first be transmitted through the additional inverter 72 (additional inverter). In addition, in FIG. 17B, the additional inverter 68 of FIG. 14B is redrawn so as to be similar to the all signal holder as described in the present invention. [0081] Static interface No design can be completely dynamic. In any case, the dynamic gate will have to communicate with existing hardware, but almost all of them use static logic. Converting a signal from static to dynamic requires a time reference point. This is because the dynamic signal conveys both "state information" and "whether the state information is valid". Static signals, on the other hand, are designed to carry only "state information" and must rely on an external time reference to indicate when the state information is valid. Therefore, in order to generate an appropriate dynamic signal, it is necessary to add "validation information" from the clock to the "state information" from the static signal. [0082] When the dynamic gate is in the evaluation phase, its input must arrive before the end of the evaluation phase. In addition, the input must transition from the asserted state to the precharged state during this cycle. In other words, when the gate is evaluating, its input transitions from i) asserted, ii) unasserted, or iii) unasserted to asserted. Must be, and must not transition from an asserted state to an unasserted state. [0083] Static signals can be switched many times during a cycle before reaching their final and valid values. The static signal also uses its voltage level to encode information (generally, a high voltage "High" indicates logic 1 and a low voltage "Low" indicates logic zero). These two characteristics of static logic circuit cause problems when the static logic circuit works with the CP logic circuit. [0084] The fact that both issues are related is that CP logic gates cannot recover their precharged state during the evaluation phase. Therefore, suppose that the static input to the CP gate temporarily goes high during the evaluation phase of the CP gate before it finally goes low. In such a case, the CP gate will erroneously switch in response to a temporary and invalid High static signal. [0085] In order to avoid such a situation, the static signal must be controlled to prevent accidental transition to High during the evaluation phase of the CP gate. Such control can be performed by latching the static signal prior to the CP gate in such a way that the CP gate input is stable during the evaluation phase. [0086] Since the CP gate does not provide an inverting function (inverter function), it is generally necessary to provide not only a latched static signal but also a latched and inverted signal. [0087] Clocking device As mentioned above, dynamic gates may include a signal retainer. The designer wants the input to the dynamic gate to disappear before the end of the dynamic gate's evaluation period, so the gate's evaluation stack is the path to the ground for the internal evaluation node for some time. May not be provided. When this happens, the evaluation node is completely disconnected from the power supply and ground and drifts from its desired voltage level. For gates evaluated as "true" (gates that discharge the evaluation node), the voltage may drift to High. In addition, the input may not be "true" when the gate is in the evaluation phase, which means that the evaluation node will not discharge. In this case, there is no path to ground to discharge such node, but no path to power to keep the node high (the node is not precharged). Therefore, the node will drift low. [0088] Some dynamic logic circuits, as described in the Harris patent, allow the input to be present throughout the evaluation period, but the Harris patent calls this dynamic logic circuit scheme a "domino" logic circuit. I'm out. Domino is an array of dynamic gates in series, with all gates precharged at once, followed by all gates being evaluated at once. When these gates are in the evaluation phase, the input is fed directly to the first gate of the array, and the evaluation node begins to "fall" like a series of upright dominoes. In this configuration, the inputs to each dynamic gate are valid throughout their evaluation phase. (Note that the word "domino" is misused in the art and often means any dynamic gate. In fact, "domino" is the first popularization of dynamic gates. Means one of the clocking methods used). When the input is valid (Low, High, or Low to High transition), no N-channel signal retainer is needed. An N-channel retainer appears to be needed only to keep the input low after the previously "true" input is gone. Therefore, there was a transition from High to Low. [0089] The clocking method described in the present invention is different from the clocking method of a domino logic circuit. Instead of erecting all dominoes and then defeating the first of a series of dominoes, the present invention restores each domino immediately after defeating the next domino. Looking at dominoes moving in this way, it seems more appropriate to call them wave clocking rather than domino clocking, as those collapsing patterns appear to propagate as "waves". is there. Using this clocking method, all signals propagate through a single gate corresponding to each clock phase. For each combination of adjacent gates, the evaluation periods overlap sufficiently that the inaccuracy of the clock itself due to jitter is acceptable. These overlaps represent the "waves" that the signal must pass through to propagate, the corridor of time. If the signal arrives at the gate early, the signal is only delayed in starting through the gate until its evaluation clock period. [0090] Some of the elements of the preferred embodiments of the present invention can be summarized as follows. That is, since the gate of each clock phase must receive its input only from the gate of the previous clock phase, all paths must pass through the same number of logic circuits. Also, with very few exceptions, all signals are dynamic to avoid synchronization loss incurred on dynamic static interfaces. The present invention avoids the use of latches, registers and flip-flops, which further reduces synchronization loss. Also, the feedback and feedforward paths must skip as many gates (integer multiples) as the number of clock phases in this clocking method. [0091] An important difference between the present invention and the Domino logic circuit is that the input to one dynamic gate in the present invention disappears before the next dynamic gate in the series completes its evaluation period. Therefore, it is possible to obtain a transition from High to Low by inputting to the gate to be evaluated. This is acceptable because the signal is correct if it is "High" and processing at the dynamic gate is simply done by propagating the information to the next gate. In this case, the gate needs to start precharging in earnest and prepare for the next evaluation phase. However, since the gate can transition from High to Low, it is possible to encounter a state where the evaluation node is discharged, but it is not something that keeps it discharged during low frequency operation or when the clock is stopped. Absent. Therefore, a signal holder is needed. This is because the present invention requires a signal retainer as part of a logic circuit as shown in FIGS. 10A, 11A and 11B. Without the signal holder, the dynamic nodes of the CP logic device, which are floating during low frequency operation or when the clock is stopped, will drift to an unknown voltage level. Figure 20 illustrates a five-phase clock system as shown in Figure 18C, showing the problems encountered in low frequency operation (operating at 1/10 clock speed). The reference numerals 2010-2020 indicate when CLK0 is in the evaluation period. Reference numeral 2030 indicates the descending edge of CLK5. CLK5 is in precharge 2040 until CLK1 exits "evaluation" in 2020 and enters "precharge". Due to the length of time that CLK1 has been in the "evaluated" state, its dynamic node will drift to an unknown voltage level. [0092] 18A, 18B, 18C and 18D show the clocking system of the present invention. In the drawing, t_eIs the "evaluation" phase of the clock cycle, t_pIs the "precharge" phase of the clock cycle. Also, each clock has a duty cycle of 50%. The different clocks are as follows. That is, the phase of each clock signal overlaps with the phase of the earlier clock signal by the amount equal to the amount of overlap with the phase of the next clock signal. And the clock phase overlap occurs so that two or more clock signals overlap in their evaluation phase at any time. Figure 18A shows a three-phase clocking system with clocks CLK1, CLK2, and CLK3. Reference numeral 250 indicates the propagation of "waves" in different clock evaluation cycles. Figure 18B shows a four-phase clocking system with clocks CLK1, CLK2, CLK3 and CLK4. Reference numeral 252 indicates the propagation of "waves" in different clock evaluation cycles. Figure 18C shows a five-phase clocking system with clocks CLK1, CLK2, CLK3, CLK4, and CLK5. Reference numeral 254 indicates the propagation of "waves" in different clock evaluation cycles. Figure 18D also shows a six-phase clocking system with clocks CLK1, CLK2, CLK3, CLK4, CLK5 and CLK6. Reference numeral 256 indicates the propagation of "waves" in different clock evaluation cycles. [0093] The design using the preferred embodiment of the present invention is designed to operate at a sufficiently high clock speed so that the evaluation node does not have time to drift. For example, at 2GHz, the evaluation node must first be kept low, so the time the evaluation node is not kept high is only 250ps, and the time it is not kept low is even shorter. The signal retainer helps to avoid noise to some extent, which is especially important if the evaluation node has serious noise problems. As discussed in the Harris patent, it is suggested that the evaluation node can be a long wire because the evaluation node itself is used as the output. When this happens, there may be large coupling components that increase the need for cage transistors in the gate. However, the present invention requires that the evaluation node be kept entirely within the logic gate. This reduces the coupling effect to the extent that no additional signal retainer on the signal is required, as in the Harris patent and other prior art. [0094] Figures 19A, 19B, 19C and 19D show a pipeline design in an integrated circuit using a system for synchronizing logic circuits of the present invention. A preferred embodiment of the present invention defines that each logic circuit receives its input from an earlier logic circuit in the series array and passes it to the next logic circuit in the series array. The faster logic circuit is connected to the faster phase clock signal, and the next logic circuit in the series array is connected to the next phase clock signal. Also, preferred embodiments of the present invention stipulate that a logic circuit may supply only to another logic circuit in a feedback loop or feedforward loop (the circuit uses the next phase clock signal). There is. [0095] FIG. 19A shows pipeline 110 in an integrated circuit using a three-phase clocking system (shown in FIG. 18A) with clocks CLK1, CLK2 and CLK3. The pipeline 110 includes a data path 128, an input signal 112 and an output signal 114. Data path 128 includes one or more wires to propagate the signal through the pipeline. For example, data path 128 may contain one or more N-ary signals. Further, the input signal 112 and the output signal 114 may include a signal using N-ary coding. Pipeline 110 includes logic circuits 116,118, 120, 122, 124 and 126 connected in series with data path 128. These logic circuits may include N-ary logic circuits. Also, each logic circuit may further include one or more additional logic circuits. [0096] FIG. 19B shows pipeline 130 in an integrated circuit using a four-phase clocking system (shown in FIG. 18B) with clocks CLK1, CLK2, CLK3 and CLK4. Pipeline 130 includes a data path 136, an input signal 132 and an output signal 134. Data path 136 includes one or more wires to propagate the signal through the pipeline. For example, data path 130 may contain one or more N-ary signals. Further, the input signal 132 and the output signal 134 may include a signal using N-ary coding. Pipeline 130 includes logic circuits 138, 140, 142, 144, 146, 148, 150 and 152 connected in series with data path 136. These logic circuits may include N-ary logic circuits. Also, each logic circuit may further include one or more additional logic circuits. [0097] FIG. 19C shows pipeline 300 in an integrated circuit using a five-phase clocking system (shown in FIG. 18C) with clocks CLK1, CLK2, CLK3, CLK4 and CLK5. Pipeline 300 includes a data path 304, an input signal 302 and an output signal 326. The data path 304 includes one or more wires to propagate the signal through the pipeline. For example, data path 304 may contain one or more N-ary signals. Further, the input signal 302 and the output signal 326 may include a signal using N-ary coding. Pipeline 300 includes logic circuits 306, 308, 310, 312, 314, 316, 318, 320, 322 and 324 connected in series with data path 304. Logic circuits may include N-ary logic circuits. Also, each logic circuit may further include one or more additional logic circuits. [0098] FIG. 19D shows pipeline 160 in an integrated circuit using a six-phase clocking system (shown in FIG. 18D) with clocks CLK1, CLK2, CLK3, CLK4, CLK5 and CLK6. Pipeline 160 includes a data path 166, an input signal 162 and an output signal 164. Data path 166 includes one or more wires to propagate the signal through the pipeline. For example, data path 166 may contain one or more N-ary signals. Further, the input signal 162 and the output signal 264 may include a signal using N-ary coding. Pipeline 166 includes logic circuits 168, 170, 172, 174, 176, 178, 180, 182, 184, 186, 188 and 190 connected in series with data path 166. Logic circuits may include N-ary logic circuits. Also, each logic circuit may further include one or more additional logic circuits. [0099] FIG. 19E shows a feedback loop and a feedforward loop with pipeline 110 of FIG. 19A. The logic circuit 122 connected to the CLK1 signal can communicate only with the logic gate connected to the CLK2 signal. The "logic gate leading to CLK2" in this case is either the logic gate 118 via the feedback loop 800 or the logic gate 124 (connected in series in the pipeline 110). Further, the logic circuit 118 connected to the CLK2 signal can communicate only with the logic gate connected to the CLK3 signal. The "logic gate leading to the CLK3 signal" in this case is either the logic gate 126 via the feedforward loop 802 or the logic gate 120 (connected in series in the pipeline 110). [0100] Clock stop The final aspect of the present invention relates to the effect of stopping the clock on logic circuits. When stopping the clock, it must be stopped in either the "High" state or the "Low" state. When the clock is stopped, some gates in the dynamic gate sequence are stopped in the "precharge" state, while others are stopped in the "evaluation" state. Here, when a certain gate is stopped in the evaluation state, if the previous gate is stopped in the precharge state, the input of the gate (the former gate) may not exist. Therefore, this gate requires an N-channel keeper. Also, when stopped, the gate's input can be a logical zero output (when the N stack is off), so this gate requires a P-channel keeper. Will be. As shown in FIGS. 11A and 11B, there are two types of cages of the present invention: full-keepers and half-keepers. Therefore, if it is necessary to see the output of the evaluated gate when stopping the clock, the integrated circuit must include the full cage in the critical path of the set of logic circuits. [0101] During the manufacturing test process, the clock is stopped in both the High and Low states to test the circuit for low levels of current leakage. This type of test, commonly known as IDDQ testing, is used to test for potential defects and improve the output characteristics and reliability of circuit products. According to simple measurements, every gate is shut down in the evaluation state, so every gate requires a full cage. However, not all gates in a series of logic gates need to include all cages. In a serial array, if the first gate to perform the evaluation process has all cages, the gates in the evaluation phase will be shut down and the remaining evaluation gates will be similar to the domino clocking strategy. In addition, the input will be kept "true". It should be noted that this is greatly simplified by the form for synchronizing the logic circuits of the present invention, where each clock phase must supply only to the next clock phase. [0102] Hardware emulation testing and scan testing are other features that benefit significantly from the ability to stop the clock and keep the circuit in its state. In both applications, "the ability to stop the clock" and "the ability to inspect and / or correct valid circuit conditions" are desirable and even necessary. The present invention makes it possible to do this, and further allows the clock to be restarted without interfering with the operation of the circuit. [0103] Explaining the clock stop, a 6-phase design can be considered. In this case, three clocks are generated according to the global clock signal, and three clocks are generated according to the inversion of the global clock signal. A series array of logic gates will have a precharge (P) or evaluation (E) logic gate in one of the six phases below, depending on where the measurement is made in the cycle. [0104] [Table 2]<img file="JP4599485B2_D0002.tif" />[0105] Since phases 0-2 are derived from the "positive" clock signal and phases 3-5 are derived from the "inverted" clock signal, these clocks can stop in any of these states. it can. [0106] [Table 3]<img file="JP4599485B2_D0003.tif" />[0107] The other four states shown in Table 2 are temporary and do not survive when the clock is stopped. Therefore, at a minimum, logic gates in phase 0 and phase 3 clocks may require full retainers, and logic gates in other phases may use semi-retainers. [0108] The present invention is a method and apparatus for synchronizing logic in an integrated circuit (IC). The present invention includes multiple clock signals having overlapping phases and a duty cycle of about 50%. The phases of the plurality of clocks overlap with the phase of the previous clock signal by an amount equal to the amount of overlap with the phase of the next clock signal. Further, the present invention includes a plurality of clock synchronous precharge logic gates (CP logic gates / Clocked Precharge Logic Gates) connected in series. CP logic gates are logic evaluation circuits, evaluate devices, and one or more signal keeper. device) is included. Each CP logic gate is connected to an individual clock signal through the evaluation device of the CP logic gate. For data flows through individual CP logic gates, the logic gate receives its data input from the previous CP logic gate in the series array and passes it to the next CP logic gate in the series array. hand off. The above-mentioned "previous CP logic gate" is connected to the clock signal of the previous phase, and the "next CP logic gate" is connected to the clock signal of the next phase. According to the present invention, the arrangement of CP logic gates and overlapping clocks (duty cycle: 50%) can avoid the synchronous overhead costs inherent in registers and latches in conventional logic circuits. it can. Further, the present invention includes embodiments including 3, 4, 5, and 6 or more clock signals. Also, in the present invention, the logic gate is a feedback loop or a feed forward loop. It is another logic circuit in loop) and can be transmitted only to a logic circuit that uses a clock signal of the next phase. [0109] The present invention is also a method and apparatus for generating a clock signal for synchronizing logic in an integrated circuit (IC). And the present invention includes a master global clock. This master global clock is distributed in a low-skew manner across the associated clock domain area. In addition, a plurality of clocks are locally generated by buffering and delaying the rising edge or falling edge of the master global clock. Then, in the present invention, these locally generated clocks are associated with the master global clock. By locally adjusting the delayed master global clock, the plurality of locally generated clocks are adjusted, resulting in skew and jitter tolerance in the logic design. Further, the present invention includes embodiments having 3, 4, 5, and 6 locally generated clocks. [0110] The present invention also provides a method and apparatus for testing the logic state of a logic gate when the clock of the logic gate is stopped or started. The present invention includes a plurality of clock signals having overwrapped phases and a plurality of CP logic gates connected in series. Each of the plurality of CP logic gates is individually connected to an individual clock signal. Further, the present invention relates to one or more signal keeper. device) is included. This signal retainer is connected to a predetermined individual CP logic gate in the critical path of the logic state. The signal retainer allows the logic state of the plurality of CP logic gates to be tested when stopping or starting the individual clock signals for each of the plurality of logic gates. The present invention is suitable for a variety of testing techniques, including IDDQ testing, scan testing and hardware emulation testing. [0111] Other embodiments of the present invention will become apparent to those skilled in the art upon examination of this specification or implementation of the disclosed invention. It should be noted that this specification and the above examples are only representative and the scope of the invention is set forth in the claims. [Simple explanation of drawings] FIG. 1 shows a clock generation system. FIG. 2 shows a simple logical path that begins and ends with a flip-flop. FIG. 3 is an example of a clock signal. [Fig. 4] Shows the clock generator. FIG. 5 shows a logic circuit without skew resistance. FIG. 6 shows a logic circuit whose clock is adjusted by a two-phase clock. FIG. 7 shows a logic circuit whose clock is adjusted by a two-phase clock. FIG. 8 shows an embodiment of the present invention including a three-phase clock. FIG. 9A shows a desired mode of operation of a dynamic gate, and FIG. 9B shows a typical mode of operation of a dynamic gate. FIG. 10 (A) shows one of the four logic circuits used in the present invention, and (B) shows one of the four logic circuits used in the present invention. .. FIG. 11 (A) shows another signal holder device of the present invention, and FIG. 11 (B) shows another signal holder device of the present invention. FIG. 12 is an example of a pipeline in an integrated circuit. FIG. 13 shows an example of a logic circuit of the prior art. FIG. 14 (A) shows an example of a logic circuit of the prior art, and FIG. 14 (B) shows an example of a logic circuit of the prior art. [Fig. 15] (A) shows the clock conditioning for the dynamic logic gate, (B) shows the clock conditioning for the dynamic logic gate, and (C) shows the clock conditioning for the dynamic logic gate. Is shown. FIG. 16 shows a prior art 4-phase clock system. FIG. 17 (A) shows the difference in logic gate configuration between the prior art and the present invention, and FIG. 17 (B) shows the difference in logic gate configuration between the prior art and the present invention. Shown. FIG. 18 (A) shows the clocking system of the present invention, (B) shows the clocking system of the present invention, and (C) shows the clocking system of the present invention. (D) shows the clocking system of the present invention. FIG. 19 (A) shows the pipelined logic circuit according to the present invention, (B) shows the pipelined logic circuit according to the present invention, and (C) shows the pipelined logic circuit according to the present invention. , The pipeline of the logic circuit provided with the present invention is shown, and (D) shows the pipeline of the logic circuit provided with the present invention. [Fig. 20] A 5-phase clock system of Figure 18C operating at low frequencies is shown.