Nitrogen treatment of polished halogen-doped silicon glass

[0001] [Technical field to which the invention belongs] The present invention relates to the manufacture of an integrated circuit. More specifically, the present invention provides a method and an apparatus for manufacturing an element having an improved dielectric layer. [0002] [Conventional technology] Integrated circuits continue to evolve and are generally becoming more complex. This ever-increasing complexity stems from the desire to have greater capacity, or higher degree of integration, for the semiconductor chips from which integrated circuits are manufactured. For example, efforts have been made to make the circuit components (transistors, capacitors, etc.) of the integrated elements smaller, bring the components closer together, and increase the number of components per unit chip area. [0003] As the size of the element features in an integrated circuit becomes smaller, new concerns arise regarding the performance of the integrated circuit. These things may need to be addressed differently in the new generation of devices. For example, operating speed and power consumption can be affected by the sensitivity of the integrated circuit to the dielectric constant of the material used to electrically insulate conductive structures such as metal wiring. Various shapes of silicon oxide or silicon oxide-based glass are often used as insulating materials in the manufacture of integrated circuits. Silicon oxide has an acceptablely low dielectric constant for some applications, but even lower dielectric constants are desirable for many types of circuits. [0004] The addition of fluorine to silicon oxide to produce so-called fluorine-doped silicon glass (FSG) makes it possible to reduce the permittivity of the insulating material. However, the addition of fluorine to silicon oxide, which is commonly performed during chemical vapor deposition (CVD) processes such as plasma accelerated CVD (PECVD) processes, poses new problems in the manufacturing process. For example, "free" (unbound) fluorine may combine with water, including water vapor in the atmosphere, to form hydrofluoric acid. This hydrofluoric acid can then corrode or chemically erode some of the materials used in the manufacture of integrated circuits, such as aluminum metal wiring. In addition, the water absorbed by the FSG thin film generally increases the permittivity of the thin film that fluorine was primarily trying to lower. [0005] Various methods have been developed to address the problems posed by free fluorine and hydrofluoric acid. One of these techniques is undoped silicon glass (USG) to seal this FSG from the atmosphere until the FSG-USG layer is coated with another thin film and the integrated circuit can be further processed. It was to form a "cap" of "). Other techniques have been developed to stabilize the FSG thin film, such as surface heating or baking the wafer. [0006] However, the application of new integrated circuit manufacturing methods limits the usefulness of traditional FSG stabilization techniques in some manufacturing processes. For example, chemical mechanical polishing (CMP) techniques are now being incorporated into the manufacturing processes of various integrated circuit manufacturers. CMP generally removes a selected amount of material from an integrated circuit wafer to smooth the surface of that wafer. For example, if a layer of insulating material is deposited on top of a patterned layer of conductive material such as traces (wiring), at least part of the topology (shape) of the patterned layer is of the deposited layer. Often remains on the surface. A wide variety of smoothing methods have been developed. However, since the CMP process produces a flat and smooth surface, this process is the most suitable smoothing technique for some applications. In general, CMP uses a polishing pad and a special polishing agent to remove a high part of the surface of the wafer and polish the surface to a flat flat surface. The flat surface created by CMP is desirable for several other reasons, especially when subsequent layers are deposited and patterned, especially when very small features are defined within the subsequent layers. is there. However, CMP generally removes the top of the surface of the layer, which can interfere with the stabilization techniques used for FSG thin films when they are polished. [0007] Therefore, an FSG stabilization method suitable for CMP processing is desired. It is further desired that such FSG stabilization techniques be compatible with standard integrated circuit materials and be feasible in integrated circuit manufacturing environments. [0008] [Means for solving problems] The present invention allows integrated circuit devices on a substrate (eg, a silicon wafer) that allow the FSG layers to be smoothed by a CMP processing step and still maintain the stability of these FSG layers during subsequent processing steps. Provides a process and equipment for manufacturing. [0009] In one embodiment, an FSG thin film is deposited on the substrate and then chemically and mechanically polished. The polished surface is subsequently nitrided by exposing the polished surface of this FSG thin film to nitrogen. For example, the substrate is mainly nitrogen gas (N₂The substrate is heated to facilitate the diffusion of nitrogen into the FSG thin film while being exposed to the plasma formed from). In yet another embodiment, the substrate uses plasma containing a biased high frequency component to reduce the source plasma power required to achieve the desired surface temperature, thereby reducing particulate contamination of the surface of the substrate. Heated using. In such a nitriding treatment, it is preferable to mix nitrogen into the FSG thin film to a depth of at least 5000 Å, or at least a via depth, as described below. [0010] To further understand the object and advantages of the present invention, the following detailed description, which is described with the accompanying drawings, should be referred to. [0011] BEST MODE FOR CARRYING OUT THE INVENTION I. Preface The present invention stabilizes a polished FSG thin film by nitriding the surface of the FSG thin film after the CMP treatment step. The CMP treatment is generally a wet treatment that hydrates the FSG thin film. When the surface of a chemically and mechanically polished FSG thin film is exposed to nitrogen plasma under selected conditions, nitrogen is mixed into the FSG thin film. It is believed that the nitrogen in the FSG thin film acts as a scavenger / getter (impurity remover) for both hydrogen and free fluorine, thus suppressing the formation of hydrofluoric acid. [0012] In addition, nitrogen stabilizes the thin film by reducing the possibility of subsequent moisture absorption from the environment, but in this embodiment the subsequent layer is on the polished nitrided FSG surface without opening the vacuum after nitrogen plasma treatment. It is not important in the deposited embodiment. In certain embodiments, biased plasma high frequency power is used along with source plasma high frequency power to heat the surface of a substrate coated with a chemically mechanically polished FSG thin film to a temperature of about 400 ° C. Under these conditions, the FSG thin film is nitrided to approximately "via depth" within a reasonable amount of time (with the chemically and mechanically polished surface of the FSG layer and the conductive layer beneath the surface of this FSG layer. The distance between them determines the depth at which the vias are subsequently opened and filled to make an electrical connection with the conductive layer. This is the "via depth".) Nitrogen at least in the FSG thin film. When added to the via depth, the formation of HF in this via region is suppressed. Otherwise, such HF formation can cause problems such as corrosion, delamination or adhesion with respect to the via filler material and other structures. [0013] II. Illustrative substrate processing system Figure 1A shows a high density plasma chemical vapor deposition (HDP-CVD) system in which a halogen-doped dielectric layer according to the invention is deposited, then chemically mechanically polished and then subjected to a nitriding process. An embodiment of 10 is shown. System 10 includes chamber 13, vacuum system 70, source plasma system 80A, bias plasma system 80B, gas supply system 33, and remote plasma cleaning system 50. [0014] The upper part of the chamber 13 has a dome 14 made of a ceramic dielectric material such as aluminum oxide or aluminum nitride. The dome 14 defines the upper boundary of the plasma processing region 16. The plasma processing region 16 is bounded at the bottom by the upper surface of the substrate 17 and the substrate support member 18. [0015] The heater plate 23 and the cold plate 24 are placed on the dome 14 and thermally connected to the dome 14. The heater plate 23 and cold plate 24 allow the dome temperature to be controlled within ± about 10 ° C over a range of about 100 ° C to 200 ° C. This makes it possible to optimize the dome temperature for various processes . For example, in cleaning and etching processes, it is desirable to keep the dome at a higher temperature than in the deposition process. Precise control of the dome temperature also reduces the number of flakes and particles in the chamber and improves the adhesion between the deposited layer and the substrate. [0016] The lower part of the chamber 13 has a body member 22 that connects the chamber to the vacuum system. The base portion 21 of the substrate support member 18 is attached to the main body member 22 and forms an internal surface continuous with the base portion 21. The substrate is carried in and out of chamber 13 by a robot blade (not shown) through an insertion / discharge port (not shown) on the side surface of chamber 13. The lift pin (not shown) rises and then descends under the control of an electric motor (also not shown) to move the board from the robot blade at top loading position 57 to the processing position 56 below. The substrate is placed on the substrate receiving portion 19 of the substrate supporting member 18. The substrate receiving portion 19 has an electrostatic chuck 20 capable of selectively fixing the substrate to the substrate support member 18 during substrate processing, if desired. In a preferred embodiment, the substrate support member 18 is made of aluminum oxide or an aluminum ceramic material. [0017] The vacuum system 70 includes a throttle valve body 25 that houses a twin-blade (two-blade) throttle valve (throttle valve) 26 and is attached to a gate valve 27, and a turbo molecular pump 28. The throttle valve body 25 is included here for reference, as described in US Patent Application No. 08 / 574,839, filed December 12, 1995, under simultaneous pending simultaneous transfer. It should be noted that it minimizes obstacles to the pump and allows symmetrical pumping operation. The gate valve 27 can isolate the pump 28 from the throttle valve body 25 and can also control the chamber pressure by limiting the exhaust flow rate when the throttle valve 26 is fully open. The arrangement of the throttle valve, gate valve and turbo molecular pump enables precise and stable control of the chamber pressure between about 1 mTorr and about 2 Torr. [0018] The source plasma system 80A has an upper coil 29 and a side coil 30 attached to the dome 14. A symmetrical ground shield (not shown) reduces the electrical coupling between these coils. The upper coil 29 is urged by the upper source high frequency (SRF) generator 31A, whereas the side coil 30 is urged by the side SRF generator 31B, with independent power levels and operating frequencies for each coil. And is possible. This dual coil system allows control of the radiation ion density within the chamber 13, thereby improving plasma uniformity. The side coil 30 and top coil 29 are generally inductively driven, which does not require an auxiliary electrode. In certain embodiments, the top source high frequency generator 31A provides high frequency power up to 2,500 watts at nominal 2 MHz and the side source high frequency generator 31B provides high frequency power up to 5,000 watts at nominal 2 MHz. The operating frequencies of the top and side high frequency generators can be deviated from the nominal operating frequencies (eg, 1.7 to 1.9 MHz and 1.9 to 2.1 MHz, respectively) to improve plasma generation efficiency. [0019] The bias plasma system 80B has a bias radio frequency (BRF) generator 31C and a bias matching network 32C. In this bias plasma system 80B, the substrate portion 17 is capacitively coupled to the main body member 22 that acts as an auxiliary electrode. The bias plasma system 80B serves to improve the transport of plasma species (eg, ions) generated by the source plasma system 80A to the substrate surface. In certain embodiments, the biased high frequency generator provides high frequency power up to 5,000 watts at 13.56 MHz. [0020] The high frequency generators 31A and 31B have a digitally controlled synthesizer and operate over a frequency range of approximately 1.8MHz to 2.1MHz. Each generator has a high frequency control circuit (not shown) that measures the power reflected from the chamber and coil back to the generator so that the reflected power is minimized, as understood by peers. Adjust the operating frequency. High frequency generators are generally designed to operate under loads with a characteristic impedance of 50 ohms. High frequency power can be reflected from loads with different characteristic impedances than from generators. This reduces the power transferred to the load. In addition, the power reflected from the load to the generator and back to the generator can overload and damage the generator. Since the impedance of the plasma ranges from less than 5 ohms to more than 900 ohms, depending on the plasma ion density, and because the reflected power is a function of frequency, the frequency of the generator according to the reflected power. By adjusting the frequency, the power transmitted from the high frequency generator to the plasma is increased, and the generator is also protected. Another way to reduce reflected power and improve efficiency is through a matched network. [0021] [0021] The matching networks 32A and 32B match the output impedances of the generators 31A and 31B having the coils 29 and 30, respectively. The high frequency control circuit tunes (tunes) both matching networks by changing the value of the capacitors in the matching network to match the generator to the load as the load changes. The high frequency control circuit can tune the matching network when the power reflected from the load and returned to the generator exceeds a certain limit. One way to give constant matching and effectively inactivate the high frequency control circuit from the tuning of the matching network is to set the reflected power limit above any expected value of reflected power. This helps stabilize the plasma under some conditions by keeping the matched network constant under the newest conditions. [0022] Other measurements may also help stabilize the plasma. For example, a high frequency control circuit can be used to determine the power delivered to the load (plasma) and increase or decrease the generator output power to keep the power delivered substantially constant during the deposition of a layer. You can also do it. [0023] The gas supply system 33 supplies gas from several gas sources 34A-34F via the gas supply line 38 (only a part of which is shown) to the chamber processing the substrate. As understood by peers, the actual gas source used for gas sources 34A-34F and the actual connection of the gas supply line 38 to chamber 13 is the deposition process and cleaning performed within chamber 13. It depends on the process. The gas is introduced into the chamber 13 via the gas ring 37 and / or the upper nozzle 45. FIG. 1B is a simplified partial cross-sectional view of chamber 13 showing more details of the gas ring 37. [0024] In one embodiment, the first and second gas sources 34A, 34B and the first and second gas flow controllers 35A', 35B' are routed through the gas supply line 38 (only part of which is shown). Gas is supplied to the ring plenum (ring space) 36 in the gas ring 37. The gas ring 37 has a plurality of source gas nozzles 39 (only one of which is shown for illustration) that supplies a uniform gas flow on the substrate. Nozzle length and nozzle angle can be varied to allow adaptation of the uniformity profile and efficient gas utilization for specific processes within individual chambers. In one preferred embodiment, the gas ring 37 has twelve source gas nozzles made of aluminum oxide ceramic. [0025] The gas ring 37 also has a plurality of oxidant gas nozzles 40 (only one of which is shown), which, in a preferred embodiment, is coplanar with the source gas nozzle and shorter. In one embodiment, the gas is received from the main body plenum 41. In some embodiments, it is desirable not to mix the source gas and the oxidant gas before injecting them into the chamber 13. In another embodiment, the oxidant gas and the source gas are provided with a window (not shown) between the main body plenum 41 and the gas ring plenum 36 before injecting these gases into the chamber 13. Can be mixed. In one embodiment, the third and fourth gas sources 34C, 34D and the third and fourth gas flow controllers 35C', 35D' supply gas to the main body plenum via the gas supply line 38. Nitrogen source 34F is a nitrogen gas (N) to the oxidizer nozzle of the gas ring for processing processes that utilize nitrogen plasma.₂) Is supplied to the chamber. As an alternative, nitrogen gas can also be supplied to the chamber via other or additional inlets such as the upper nozzle. Additional valves, such as the 43B (other valves not shown), can shut off gas from the gas flow controller to the chamber. [0026] In embodiments where flammable, toxic or corrosive gases are used, it is desirable to remove the gas remaining in the gas supply line after deposition. This can be achieved using a 3-way valve, such as valve 43B, to isolate the chamber 13 from the supply line 38A and, for example, to communicate the supply line 38A with the vacuum foreline 44. Other similar valves such as 43A, 43C can also be incorporated into other gas supply lines, as shown in Figure 1A. Such a 3-way valve can be placed as close to the chamber 13 as possible so as to minimize the volume of the gas supply line without a communication port (between the 3-way valve and the chamber). In addition, a 2-way (on / off) valve (not shown) may be placed between the mass flow controller (MFC) and the chamber, or between the gas source and the MFC. [0027] Referring again to FIG. 1A, chamber 13 also has an upper nozzle 45 and an upper vent 46. The upper nozzle 45 and the upper vent 46 allow independent control of the upper gas flow and the lateral gas flow, which improves thin film uniformity and fine-tunes thin film deposition and doping parameters. It is possible. The upper vent 46 is an annular opening around the upper nozzle 45. In one embodiment, the first gas source 34A supplies the source gas to the source gas nozzle 39 and the upper nozzle 45. The source nozzle MFC35A'controls the amount of gas supplied to the source gas nozzle 39, and the upper nozzle MFC35A controls the amount of gas supplied to the upper nozzle 45. Similarly, the two MFCs 35B, 35B'can be used to control the flow of oxygen from a single oxygen source, such as the gas source 34B, to both the upper vent 46 and the oxidant gas nozzle 40. The gases supplied to the upper nozzle 45 and the upper vents 46 may be separated before flowing into the chamber 13, or these gases are mixed in the upper plenum 48 before flowing into the chamber 13. You may. Separate sources of the same gas may be used to supply different parts of the chamber. [0028] A remote microwave-generating plasma cleaning system 50 is provided to periodically clean and remove sediment from the chamber components. This cleaning system has a remote microwave generator 51 that generates plasma from a cleaning gas source 34E (eg, molecular fluorine, nitrogen trifluoride, other fluorinated hydrocarbons or equivalents) within the reactor cavity 53. There is. The reaction species generated from this plasma are carried to the chamber 13 through the cleaning gas supply port 54 through the applicator tube (supply pipe) 55. The material used to house the wash plasma (eg cavity 53, supply tube 55) must withstand the attack from the plasma. The distance between the reactor cavity 53 and the supply port 54 should be as short as possible as the concentration of the desired plasma species decreases with distance from the reactor cavity 53. By generating the wash plasma in a remote cavity, efficient microwave generator use is possible, and the chamber components are the temperature, radiation and bombardment of glow discharges that can be present in the plasma formed in the insitu. Will not receive. As a result, even relatively sensitive components such as the electrostatic chuck 20 do not need to be covered with a dummy wafer or protected as required by the original plasma cleaning process. [0029] The system controller 60 controls the operation of the system 10. In a preferred embodiment, the controller 60 has a memory 62 such as a hard disk drive, a floppy disk drive (not shown), a card rack (not shown) connected to the processor 61. The card rack includes a single board computer (SBC) (not shown), an analog digital I / O board (not shown), an interface board (not shown), and a pulse motor controller board (not shown). be able to. The system controller complies with the Versa Modular European (VME) standard, which defines the dimensions and types of boards, card cages and connectors. The VME standard also defines a bus structure that has a 16-bit data bus and a 24-bit address bus. The system controller 31 operates under the control of a computer program stored on a hard disk drive or via another computer program, such as a program stored on a removable disk. This computer program specifies, for example, the timing of a particular process, gas mixing, high frequency power levels, and other parameters. The interface between the user and the system controller is via a monitor such as a cathode ray tube (CRT) 65 and a light pen 66 as shown in FIG. 1C. [0030] FIG. 1C is an explanatory view of a portion of an exemplary system user interface used in conjunction with the exemplary CVD process chamber of FIG. 1A. The system controller 60 has a processor 61 connected to a computer-readable memory 62. The memory 62 is preferably a hard disk drive 62, but may be another type of memory such as ROM, PROM, or the like. [0031] The system controller 60 operates under the control of a computer program 63 stored in a memory 62 in a computer-readable format. This computer program dictates the timing, temperature, gas flow, high frequency power levels, and other parameters of a particular process. The interface between the user and the system controller is via a CRT monitor 65 and a light pen 66 as shown in FIG. 1C. In a preferred embodiment, two monitors 65, 65A and two light pens 66, 66A are used, one mounted on the wall (65) of the clean room for the operator and the other for the service technician. It is mounted behind the wall (65A). Both monitors display the same information at the same time, but only one light pen (eg 66) can be used. To select a particular screen or function, the operator touches an area of the display screen and presses a pen button (not shown). The touched area confirms its selection by the light pen, for example by changing its color or displaying a new menu. [0032] The code for the computer program may be written in any traditional computer-readable programming language such as 68000 Assembly Language, C, C ++, or Pascal. Appropriate program code is put into a single file or multiple files using a regular text editor and stored or incorporated into a computer-usable medium such as the computer's memory system. If the code text entered is written in a higher language, the code will be compiled and the resulting compiler code will be linked to the object code of the precompiled Windows Library routine. To execute the linked compiled object code, the system user calls the object code and causes the computer system to load the code in memory. The CPU reads the code from memory and executes the code to perform the task identified by the program. [0033] FIG. 1D shows an exemplary block diagram of the hierarchical control structure of computer program 100. The user enters the process set number and process chamber number in the process selector subroutine 102 in response to a menu or screen displayed on the CRT monitor by using the light pen interface. A process set is a predetermined set of process parameters required to execute a specified process, and is identified by a predetermined set number. The process selector subroutine 102 identifies (i) the desired process chamber in a multichamber system and (ii) the desired set of process parameters required to operate the process chamber to perform the desired process. .. Process parameters for performing a particular process are related to conditions such as process gas composition and plasma conditions such as flow rate, temperature and pressure and high frequency power levels and chamber dome temperature, etc., and recipes (prescriptions). ) Is provided to the user. The parameters specified by this recipe are entered using the light pen / CRT monitor interface. [0034] The signal for monitoring the process is given by the analog digital input board of the system controller 60, and the signal for controlling the process is output on the analog digital output board of the system controller 60. [0035] The process sequencer subroutine 104 accepts the identified process chamber and set of process parameters from the process selector subroutine 102 and has program code for controlling the operation of various process chambers. A large number of users can enter a process set number and a process chamber number, or a single user can enter a large number of process set numbers and a process chamber number, and sequencer subroutine 104 is selected. The processes can be scheduled in the desired order. Sequencer subroutine 104 (i) monitors the operation of the process chamber to determine if the chamber is in use, and (ii) determines what process is running in the chamber in use. It contains program code to perform the process and (iii) the process of performing the desired process based on the availability of the process chamber of the process to be performed and the type of process. Traditional methods of monitoring the process chamber, such as polling, can be used. When scheduling which process to run, the sequencer subroutine 104 schedules the "age" of each particular user input request, the current conditions of the process chamber in use compared to the desired process conditions for the selected process, and so on. It can be designed to take into account any other related factors that the system programmer wants to include in order to prioritize. [0036] After the sequencer subroutine 104 determines which process chamber and process set combination to execute next, the sequencer subroutine 104 passes specific process set parameters from chamber manager subroutine 106A to C for that process set. It initiates execution, which controls a number of processing tasks with chamber 13 and / or other chambers (not shown) according to the process set sent by sequencer subroutine 104. [0037] Examples of the chamber component subroutine include the substrate positioning subroutine 110, the process gas control subroutine 112, the pressure control subroutine 114, and the plasma control subroutine 116. It will be appreciated by peers that other chamber control subroutines can be included, depending on which process was chosen to run within chamber 13. During operation, chamber manager subroutine 106A selectively schedules or calls process component subroutines according to a particular process chamber in progress. The chamber manager subroutine 106A schedules the process component subroutine in the same way that the sequencer subroutine 104 schedules the process chamber and process set to be executed. In general, the chamber manager subroutine 106A determines the steps of monitoring various chamber components, determining which components need to be operated based on the process parameters for the process set to be executed, and these monitoring steps. It includes a process of executing a chamber component subroutine according to the process. [0038] Now, the operation of a specific chamber component subroutine will be described with reference to FIGS. 1A and 1D. The board positioning subroutine 110 contains program code for controlling the chamber components used to load the board onto the board support member 18. The board positioning subroutine 110 can also control the movement of the board from, for example, the CMP chamber, or other chamber of a multichamber system into chamber 13 after other processes have been completed. [0039] The process gas control subroutine 112 has a program code for controlling the composition and flow rate of the process gas. Subroutine 112 controls the opening and closing positions of the safety shut-off valve and raises and lowers the mass flow controller to obtain the desired gas flow rate. All chamber component subroutines, including process gas control subroutine 112, are called by chamber manager subroutine 106A. Subroutine 112 receives process parameters from chamber manager subroutine 106A with respect to the desired gas flow rate. [0040] In general, process gas control subroutine 112 opens the gas supply line, (i) reads the required mass flow controller, (ii) compares the reading with the desired flow rate received from chamber manager subroutine 106A, and (iii) requires. The operation of adjusting the flow rate of the gas supply line is repeated accordingly. Further, the process gas control subroutine 112 may include a step of monitoring the gas flow rate with respect to the dangerous flow rate and a step of operating the safety shut-off valve when a dangerous state is detected. [0041] In some processes, an inert gas, such as argon, is flowed into the chamber 13 to stabilize the pressure in the chamber before introducing the reactive process gas. For these processes, the process gas control subroutine 112 is programmed to include the step of pouring the inert gas into the chamber 13 for the time required to stabilize the pressure in the chamber 13. In this way, the above-mentioned steps can be performed. [0042] The process gas control subroutine 112 can also control the flow of a thermally conductive gas such as helium (He) through passages inside and outside the wafer chuck by an independent helium control (IHC) subroutine (not shown). The gas stream thermally connects the substrate to the chuck. In a typical process, the wafer is heated by a plasma and a chemical reaction that forms a layer, and He cools the substrate through a water-cooled chuck. This keeps the substrate at a temperature lower than the temperature at which it can damage the features pre-existing on the substrate. [0043] The pressure control subroutine 114 contains a program code for controlling the pressure in the chamber 13 by adjusting the size of the opening of the throttle valve 26 in the exhaust portion of the chamber. There are at least two basic methods of controlling a chamber with a throttle valve. The first method relies on characterizing the chamber pressure, as the chamber pressure is particularly related to the total process gas flow rate, process chamber size and pumping capacity. In this first method, the throttle valve 26 is set in a fixed position. Setting the throttle valve 26 in place can eventually result in steady-state pressure. [0044] As an alternative, the chamber pressure can also be measured, for example with a manometer, and the position of the throttle valve 26 is the pressure, assuming that the control point is within the boundary set by the gas flow and exhaust capacity. It can also be adjusted according to the control subroutine 114. In the former method, the measured values, the comparative values and the calculated values related to the latter method are not called, and as a result, the chamber pressure can be changed more quickly. The former method may be desirable when precise control of chamber pressure is not required, but the latter method is desirable when accurate, reproducible and stable pressure is desired, such as during layer deposition. [0045] When the pressure control subroutine 114 is called, the desired or target pressure level is received as a parameter from the chamber manager subroutine 106A. The pressure control subroutine 114 reads one or more normal pressure manometers connected to the chamber, measures the pressure in the chamber 13, compares the measured value with the target pressure, and uses the stored pressure table to measure this target pressure. The proportional, integral, and differential (PID) values corresponding to are obtained, and the throttle valve 26 is adjusted according to the PID values obtained from this pressure table. Alternatively, the pressure control subroutine 114 can open or close the throttle valve 26 to a specific opening size to adjust the pressure in the chamber 13 to the desired pressure or pressure range. [0046] The plasma control subroutine 116 contains program code for controlling the frequency output and power output settings of the high frequency generators 31A and 31B, and for adjusting the matching networks 32A and 32B. The plasma control subroutine 116 is called by the chamber manager subroutine 106A in the same manner as the chamber component subroutine described above. [0047] Examples of systems that can incorporate some or all of the above subsystems and routines are ULTIMA® from APPLIED MATERIALS, INC., Santa Clara, CA, configured to implement the present invention. It will be a system. Details of such a system are listed as co-inventors by Fred C. Redeker, Farhad Moghadam, Hirogi Hanawa, Tetsuya Ishikawa, Dan Maydan, Shijian Li, Brian Lue, Robert Steger, Yaxin Wang, Manus Wong and Ashok Sinha. US Patent Application No. 08 / 679,927, filed July 15, 1996, entitled "Symmetric Tunable Inductively-Coupled HDP-CVD Reactor". It is disclosed in, and this disclosure is incorporated here for reference. The system described here is for illustrative purposes only. It would be a matter of ordinary skill for a person familiar with the present technology to select a suitable conventional substrate processing system and computer control system to realize the method of the present invention. [0048] FIG. 1E is a simplified cross-sectional view of an exemplary CMP chamber 80 in which the halogen-doped silicon oxide layer can be polished and smoothed in some embodiments of the present invention. The CMP chamber 80 has a rotary table 82 having a polishing pad 84 arranged on its upper surface. The rotating substrate holder 86 holds a substrate 88, such as a semiconductor wafer, while the substrate is polished by the pads 84. During polishing, an appropriate slurry is supplied between the substrate 88 and the pad 84, and a predetermined pressure is applied to the substrate by the pad. [0049] Chambers 13 and 80 may also be part of a cluster tool system provided by the robot with a large number of substrates placed around the central robot. An example of such a cluster tool system 120 is shown in FIG. 1F. As an alternative, chamber 13 may be part of the cluster tool system 120 and CMP chamber 80 may be part of a separate CMP tool with multiple polishing stations or chambers. The board may be manually transferred between the system 120 and the separate CMP chamber 80, or automatically using a conveyor belt and / or a suitable robotic system as known to those in the industry. You may. An example of such a multi-station CMP device and its related methods is "CONTINUOUS PROCESSING SYSTEM FOR CHEMICAL MECHANICAL POLISHING" by Tolles et al., Which was commonly transferred to Applied Materials, Inc. It is disclosed in US Pat. No. 5,738,574 entitled "System)" and is incorporated herein by reference for all purposes. A commercially available multi-station CMP device, a separable cluster tool that can be used to smooth halogen-doped layers for the present invention, is the mirra® CMP system from Applied Materials, Inc. is there. [0050] In FIG. 1F, the cluster tool system 120 has vacuum cargo fixing chambers 125 and 130. The load fixing chambers 125, 130 keep the inside of the inner chamber 135 in a vacuum state while the substrate enters and exits the system 120. The robot 140 supplies the substrate from the load fixing chambers 125 and 130 to / to the substrate processing chamber 145 and the heating chamber 150. The processing chamber 145 can be equipped to perform a number of substrate processing operations such as CVD, etching, and the like. The heating chamber 150 can be used in a heat treatment step such as an annealing step. [0051] The pass-through chamber 155 is used to maintain an ultra-high vacuum within the internal chamber 160 while allowing the substrate to be transshipped from robot 135 to robot 165. The robot 165 supplies the substrate from the pass-through chamber 155 to the substrate processing chambers 170 to 185. Like the processing chambers 145, the processing chambers 170-185 can be equipped to perform various substrate processing operations. In some cases, processing chamber 170 is equipped to perform CMP operation, processing chamber 175 is equipped to perform nitriding according to the present invention, and processing chamber 180 performs FSG deposition. [0052] During operation, the substrate is transported to the vacuum load fixation chamber by a conveyor belt or robotic system (not shown) operating under the control of a computer program executed by the system controller 60. Robots 140, 165 also operate under the control of a computer program running on the system controller 60 to move the board between the various processing chambers of the cluster tool 120. [0053] III. Illustrative process flow FIG. 2 is a simplified flow diagram showing an example of the process 200 according to the present invention. In FIG. 2, an FSG layer is deposited on the substrate (step 202). The FSG layer is then chemically and mechanically polished to smooth the thin film (step 204), after which the surface of the FSG layer is nitrided as described later in this application (step 206). Those in the industry will admit that additional processing steps, such as post-CMP cleaning, may be performed. The substrate may then be further processed to complete the manufacture of integrated circuits on this substrate (not shown). [0054] In one particular exemplary application of the invention, the deposited FSG layer has a fluorine concentration of about 7 atomic percent (atomic%) and a deposit thickness of about 16,000 Å. An example of the FSG deposition sequence is "SEQUENCING THE RECIPE STEPS FORTHE OPTIMAL LOW-DIELECTRIC CONSTANT HDP-CVD PROCESSING" by Orezyk et al., Filed on June 3, 1997. It can be found in US Patent Application No. 08 / 868,286 entitled "Process Ordering)". This application No. 08 / 868,286 has been assigned to Applied Materials, Inc., the assignee of this application, and is incorporated herein by reference for all purposes. The deposition sequence described in US Patent Application No. 08 / 868,286 describes an sequence that involves depositing the USG liner layer before depositing the FSG layer. Prior to depositing any thin film, the wafer is heated by a high frequency bias-free (ie, using only source high frequency power) plasma applied to the plasma. This heating sequence avoids sputter etching of fine patterns such as the corners of the metal wiring where the dielectric layer is subsequently deposited. Later in this sequence, conditions are maintained to avoid sputter etching or fluorine etching of fine features, including a thin liner layer that covers the corners of the metal wiring. Those in the industry will understand that other processes can be used to deposit the FSG layer. For example, it is possible to heat a wafer using both high frequency source power and bias power before depositing the first material. Also, some applications may include a USG liner layer. This method heats the wafer more quickly than using only the source high frequency power, which is preferable in some cases because it increases the amount of processing. [0055] In this exemplary application, the FSG layer is chemically and mechanically ground to a thickness of approximately 9,000 to 10,000 Å using the Mirra® CMP system from Applied Materials, Inc. Those in the industry will understand that this thickness and doping concentration are shown merely as an example, and that other thicknesses and doping concentrations of FSG thin films can also be used. Examples and more details of the process for nitriding the surface of the FSG layer are described below in Section V. [0056] IV. Illustrative device structure FIG. 3A shows a simplified cross-sectional view of the integrated circuit 300 incorporating the features of the present invention. The integrated circuit 300 can be manufactured on a semiconductor wafer such as a silicon wafer, a gallium arsenic wafer, or another wafer. As shown in FIG. 3A, the integrated circuit 300 includes an IMS transistor 303 and a MOSFET transistor 306 that are separated from each other by a field oxide region 307 and are electrically isolated. Each of the transistors 303 and 306 has a source region 308, a gate region 309, and a drain region 310. [0057] The premetal dielectric layer 311 separates the transistors 303 and 306 from the metal layer M1 by a connection between the metal layer M1 formed by the contacts 312 and each transistor. The metal layer M1 is one of the four metal layers M1 to M4 included in the integrated circuit 300. The respective metal layers M1 to M4 are separated from the adjacent metal layers by the respective intermetal dielectric (IMD) layers 313A to C. Adjacent metal layers are connected by a via 314 at the selected opening. The planar passivation layer 315 covers the metal layer M4. [0058] [0058] Although embodiments of the present invention are particularly useful for IMD layers, applications can also be found for each of the dielectric layers shown in the integrated circuit 300. It should be understood that this integrated circuit 300 is for illustration purposes only. Those in the industry will be able to implement this method for the manufacture of other integrated circuits such as microprocessors, application-specific integrated circuits, memory devices, and the like. The methods of the invention can be used to make integrated circuits using other technologies such as BiCMOS, MIMO, bipolar and others. Further, the method of the present invention can be used by the damascene (metal inlay) and double damascene process methods commonly used to manufacture devices with feature sizes of 0.25 μm or less. [0059] FIG. 3B is a simplified cross section of a portion of an electronic device 320 showing a nitrided FSG layer and its associated structure according to an embodiment of the present invention. The metal layer 322 is formed and patterned on the dielectric layer 324, and the dielectric layer is supported by the substrate 326 and may or may not have an intervening layer or material (not shown). is there. The first dielectric layer may be a layer of silicon glass or doped silicon glass, a layer of nitride or other dielectric material, or a combination of layers and / or materials. The FSG layer 328 is formed on the patterned metal layer 322 and the dielectric layer 324 (FIG. 2, step 202). Chemical mechanical polishing (Figure 2, Step 204) creates a relatively flat and smooth surface 330 of the FSG layer 328, on which an optional undoped silicon glass with a thickness of approximately 2,000 Å ("" USG ") Layer 332 is deposited. The silicon glass layer 332 is also relatively flat and smooth as it generally adapts to the underlying layer, which is desirable when manufacturing subsequent layers. [0060] Prior to depositing the undoped silicon glass layer, the chemically and mechanically polished surface of the FSG layer is nitrogen at a time and temperature sufficient to allow nitrogen to enter the FSG layer to a selected depth. Nitriding was performed by exposing the surface of the FSG layer to the contained plasma (Fig. 2, step 206). In this case, the selected depth is approximately a via depth of 334 through the FSG layer, typically between about 5,000 and 9,000 Å. This via can be formed using conventional lithography and etching techniques, and is generally practically titanium / to electrically connect the patterned metal layer to a subsequent metal layer (not shown). Titanium Titanium Filled with conductive materials such as aluminum, tungsten, and / or copper. This filling material may be the same as or different from the subsequent metal layer. [0061] Nitriding treatment forms a chipped FSG region 336 in the FSG layer. If you are a trader, you will generally see about 0.40 atomic% on the surface of the nitrided region and about 0.01 atomic% at the interface between the nitrided and non-nitrided regions (FSG as deposited) over the entire nitrided region. It will be acknowledged that the nitrogen concentration can change as it decreases to: and that the location of this interface is primarily a matter of defining the desired nitrogen concentration limit. V. Nitriding process sequence The nitriding process of the chemically and mechanically polished surface of the FSG layer according to the present invention can be achieved using a variety of process conditions. This allows the user to select the most suitable process conditions for the material (board) and device design. For example, in general, due to the large investment in manufacturing equipment, the competitive pricing of products, and the high processing volume required by both, any process in the manufacture of semiconductor devices will achieve process results in the shortest possible time. Is desired. Therefore, in some situations higher process temperatures and shorter process times are chosen. Those familiar with the technique will understand that the final result is achieved according to several process variables, among others, time, temperature, plasma nitrogen concentration. The peers also say that time, power levels and other parameters described below are related to a particular substrate processing system and that these process parameters perform the following processes or other similar processes. You will understand that it can be modified to adapt to other processing systems. [0062] However, in general, when the present invention is used to add nitrogen to a chemically and mechanically polished FSG layer that should form 5,000 to 9,000 Å vias, the nitriding step takes this for about 40 to 70 seconds. The layer will be exposed to nitrogen plasma. The wafer will be heated to about 380 to 400 ° C during this time. Such process conditions can be used to introduce nitrogen into the FSG layer all the way down to the via depth. The amount of nitrogen mixed into the thin film to the selected depth (eg via depth) is at least 1x10.¹⁹Atom / cm³Is preferable, and at least 5x10¹⁹Atom / cm³And 1x10²⁰Atom / cm³It is more preferable to be between. [0063] In order to further explain the nitriding process of the present invention, the following process is shown as a mere example. In this example, the substrate to be nitrided is placed in the ULTIMA® system chamber described in Section II after forming a chemically and mechanically polished FSG layer on the substrate. During loading operation, the throttle valve is fully open while the turbo pump exhausts the chamber, argon flows into the chamber at a flow rate of 126 sccm, and flows out at 16 sccm through the upper nozzle. After loading is complete, by closing the throttle valve and waiting for less than 10 seconds for the chamber pressure to rise above 50 mTorr, the appropriate pressure to generate the plasma is achieved and that waiting time. Later, 1000W of source high frequency power is applied to the upper coil for 1 second to generate plasma in the chamber. Next, while the throttle valve is open to a fixed position in 100 steps, 1000 W of source power is applied to the side coil, which takes about 1 second. This establishes a stable plasma with sufficient source power before the nitrogen source is flushed into the chamber. [0064] Nitrogen gas (N₂) Is applied to the plasma for 3 seconds at an initial flow rate of 30 sccm while the throttle valve is open to the 400 step position. As shown below, minimal heating of the substrate takes place during this 5 seconds when the substrate is exposed to plasma receiving these levels of source power. After the nitrogen flowed for 3 seconds, the argon flow was stopped and the nitrogen flow was increased to 80 sccm, during which a high frequency bias power of 350 W was applied in addition to the high frequency source power of 2,000 W, and the throttle valve was operated for 50 seconds. It will be fully opened. Some high frequency bias power may be applied according to the desired temperature that the substrate should achieve. [0065] Similar to the above step, during this nitriding process step, the electronic chuck is turned off and the helium cooling gas on the back surface does not flow. Plasma heats the substrate to just below about 400 ° C. It is desirable to keep the FSG layer below the temperature at which it was deposited, in this case to prevent delamination at the FSG interface with adjacent materials and to avoid other unwanted changes within the FSG layer. It is desirable to be between about 410 ° C and 420 ° C. Lower temperature limits may be appropriate if there are temperature sensitive structures on the substrate that need to be maintained at lower temperatures. On the other hand, if the FSG thin film is deposited at a high temperature above 420 ° C, the higher temperature and therefore the shorter process time, unless the result is unacceptable in terms of device yield or reliability. Can be adopted. Similarly, different times and temperatures may be employed, depending on the desired depth of the nitrided FSG. [0066] In this example, the nitriding process is performed without back helium cooling in order to quickly heat the substrate and reduce throughput time. Therefore, the temperature-time relationship of the substrate is characterized and verified using test wafers. In this case, the substrate is an 8 "silicon wafer with a bulk resistivity of 1.5 ohm-cm. The heating rate of the silicon wafer depends on the bulk resistivity of the wafer. Generally, low bulk resistivity (high electrical conductivity). ) Has higher thermal conductivity, and it takes a longer time to heat the surface region with plasma. [0067] FIG. 4 shows the relationship between the wafer temperature and the bulk resistivity at the end of the nitrogen treatment process of a silicon wafer exposed to nitrogen plasma under the same time and conditions. Figure 4 shows that the wafer temperature rises by about 60 ° C as the resistivity changes from about 0.01 ohm-cm to 1.00 ohm-cm. [0068] Dissipating heat from the back of the wafer by chucking the wafer to the wafer support would dissipate heat from the wafer and further delay the heating process at a given power level. Flowing a coolant, such as helium gas, between the back of the wafer and the wafer support will improve heat transfer from the wafer and slow down the heating process, however, when lower process temperatures are desired. And / or when process throughput is not important, or when you want a standard nitriding process for a series of wafers with varying resistances, and / or when a temperature controlled feedback system is used, etc. Under circumstances, it may be appropriate to chuck the wafer and allow the coolant to flow. [0069] As a result of the above nitriding treatment, a wafer surface temperature of about 390 ° C and a chamber pressure of about 3 mTorr are obtained. The obtained nitrided FSG region has a nitrogen concentration of about 0.40 atomic% near the surface of the FSG layer and diffuses up to about 8,000 Å in the FSG layer. Approximately 0.40 atomic% is believed to be the limit of nitrogen solubility in this type of material at this temperature. A similar process for similar wafers produces a nitriding depth between about 5,000 and 9,000 Å. For those familiar with the technology, solubility limits can be affected by many variables, including the composition, structure, and temperature of the FSG layer, and the extent of nitrogen diffusion into the FSG layer is at least near the surface of the FSG layer. We will recognize that it is a function of the concentration and the time-temperature product when the FSG layer is exposed to nitrogen. [0070] As mentioned above, it is highly desirable to choose process conditions that include temperature, pressure, gas flow rate and time, among many variables, so that nitrogen diffuses to at least the via depth. Nitriding suppresses the formation of HF in the via region and improves the stability of the thin film to that depth. In other embodiments, it is preferred that nitrogen penetrate at least a certain distance or a percentage distance deeper than the via depth to ensure a higher nitrogen concentration at the via depth. We have determined that nitrogen does not adversely affect the conductive features beneath the FSG layer when the penetration is below the via depth. [0071] The nitrided FSG has a permittivity of about 3.5, which is comparable to the permittivity of FSG. Nitriding also increases the compressive stress of FSG thin films by a factor of two. For example, the compressive stress is about 6.0x10 in the FSG thin film before nitriding.⁸Dyne / cm²Approximately 1.2x10 after nitriding⁹Dyne / cm²Increased to. This increased compressive stress is useful in that it generally has tensile stress and reduces cracking of the patterned metal layer that is surrounded or partially enclosed by the nitrided FSG. The increased compressive stress is particularly desirable for the "higher" metal layers of multi-metal layer electronic devices (elements) having a shape structure of less than about 0.25 microns. [0072] After nitriding a chemically and mechanically polished FSG thin film, a cap layer, barrier layer, adhesive layer, or other layer may be formed on the nitrided FSG, if desired, or the substrate may be Other treatments may be applied. The cap layer is, for example, a relatively thin layer (eg, 2,000 Å thick) of undoped silicon glass. [0073] VI. test results FIG. 5 is a chart showing the number of particles for 1,000 wafers manufactured according to one embodiment of the invention in the ULTIMA® Chamber HDP previously described in Section V. The average particle density is about 11 for particles larger than 0.2 micron. The alternative nitrogen plasma treatment was evaluated. In particular, nitrogen plasmas that do not have high frequency bias power, that is, urged only by high frequency source power, were evaluated. In the high frequency source power only (no high frequency bias power) process, 2,500 W of power was delivered to the top coil, while 3,500 W of power was delivered to the side coil. Within the chamber seasoned with a layer of silicon oxide, the number of particles above 0.2 microns added by nitriding with high frequency source power only spreads from 25 to 7,000, with an average number of particles added of about 3,500. It was. Throughout the experiment, the number of particles added during the source power-only nitriding process is the thickness of the seasoning layer, the composition of the seasoning layer (eg FSG vs. USG), or the number of wafers processed after seasoning the chamber. It was determined that it was not very sensitive to many parameters including such as. However, the number of particles added was determined to be sensitive to the high frequency source power applied to the plasma. [0074] Figure 6A is a graph showing the wafer temperature vs. time relationship for a substrate exposed to nitrogen-containing plasma urged by high frequency source power between 2,500 W supplied to the top coil and 3,500 W supplied to the side coil. is there. Figure 6B shows similar conditions exposed to nitrogen-containing plasma urged by a high frequency source power of 1,000 W supplied to the upper coil and 1,000 W supplied to the side coil and a high frequency bias power of 400 W. It is a graph which shows the relationship between the wafer temperature and time with respect to the lower substrate. The heating curves were similar and nitriding of chemically and mechanically polished FSG thin films was achieved by both processes. Therefore, it was determined that using high frequency bias power along with high frequency source power to heat the wafer is an efficient method of wafer heating and does not cause excessive particle contamination. [0075] Heating without high frequency bias power is a simpler process, so a process with only source power is preferred if possible. However, the plasma, which is urged by a source power high enough to heat the substrate to a temperature of about 400 ° C, covers the interior of the processing chamber to minimize contamination of the substrate (in this case, the seasoning coating). (Given a layer of silicon oxide) tends to be sputtered. As an alternative to using high frequency bias power to heat the substrate, other heating sources, such as heaters in the wafer pedestal, can be used to achieve essentially the same temperature, or lower temperatures ( Intermediate source power can be used if lower nitrogen concentrations are acceptable (for longer periods of time). Similarly, intermediate high frequency power (between 100 and 400 W) can be used with appropriate adjustment of the high frequency source power to achieve the selected substrate temperature. [0076] FIG. 7A is a SIMS spectrum of the as-deposited FSG layer deposited within the Ultima HDP chamber. This graph shows that the background concentration level of nitrogen in the FSG layer is about 1x10.¹⁸Atom / cm³It shows that it can be. In comparison, FIG. 7B is the SIMS spectrum of the FSG layer after nitriding in a nitrogen-based plasma for 60 seconds with a high frequency source power of 2,500 W for the top coil and 3,500 W for the side coil. This data shows that FSG is mixing nitrogen to a depth of about 0.9 microns before the nitrogen concentration drops rapidly to background levels. Figure 7C shows the SIMS spectrum of the FSG layer after nitriding for 60 seconds in a nitrogen-based plasma with a high frequency source power of 1,000 W applied to the top coil and 1,000 W applied to the side coil, without high frequency bias power. Is. It should be noted that the scales on the horizontal axis are different and that nitrogen is only mixed into the FSG layer to a depth of about 0.1 micron from the surface. Figure 7D shows the SIMS spectrum of the FSG layer after 120 seconds nitriding in a nitrogen-based plasma with a high frequency source power of 1,000 W applied to the top coil and 1,000 W applied to the side coil, without high frequency bias power. is there. At this exposure time, FSG mixed nitrogen to a depth of about 0.15 microns from the surface. Figure 7E shows the FSG layer after nitriding for 60 seconds in a nitrogen-based plasma with 1,000 W applied to the top coil, 1,000 W high frequency source power applied to the side coils, and 400 W high frequency bias power. SIMS spectrum. Comparing FIGS. 7E and 7B, it can be seen that biased high frequency power is an efficient way to increase the wafer temperature and the diffusion of nitrogen into the FSG layer. [0077] The method of the present invention is not intended to be limited by the particular parameters described above. Those in the industry will understand that different process conditions and different reactor sources can be used without departing from the spirit of the invention. For example, plasma is N₂It could be generated from O, ammonia and other nitrogen sources, and in addition to the nitrogen source other elements such as helium and hydrogen could be added to the plasma. Those in the industry will understand that such additives can alter the heating and sputtering properties of the plasma according to acceptable process parameters. The present application also primarily discussed nitriding of the FSG layer after CMP treatment, which can also be used to nitrid other halogen-doped silicon glass after CMP. [0078] Further, the above-described embodiment is Ultima. Although using an HDP-CVD system, other plasma systems such as parallel plate plasma systems, ECR plasma systems, or remote plasma systems can also be used to impart nitrogen species to the halogenated silicon glass surface. It is possible. Similarly, other heating methods such as heating the wafer with an infrared lamp or a resistance heating table can be used to heat the wafer to a desired temperature. The heating method may include an active temperature control function. Other equivalent or alternative methods of nitriding the halogenated chemically mechanically polished surface according to the invention, such as injecting nitrogen into the polished surface, will be apparent to peers. These equivalent or alternative methods are intended to be included within the scope of the present invention. Other variants will also be apparent to peers. Therefore, it is not intended to limit the invention except as set forth in the accompanying claims. [Simple explanation of drawings] FIG. 1A is a simplified schematic of an exemplary high density chemical vapor deposition (CVD) system that can be used to carry out the methods of the invention. FIG. 1B is a simplified cross-sectional view of a gas ring used with the exemplary CVD process chamber of FIG. 1A. FIG. 1C is a simplified schematic of a monitor and light pen used with the exemplary CVD process chamber of FIG. 1A. FIG. 1D is a flow diagram of an exemplary process control computer program product used to control the exemplary CVD process chamber of FIG. 1A. FIG. 1E is a simplified schematic of an exemplary chemical mechanical polishing chamber that can be used to smooth a halogen-doped layer in some embodiments of the present invention. FIG. 1F is a simplified schematic of an exemplary cluster tool substrate processing system that can be used to carry out the methods of the invention. FIG. 2 is a simplified flow diagram illustrating a process for manufacturing an integrated circuit device according to an embodiment of the present invention. FIG. 3A is a simplified cross-sectional view of a portion of an integrated circuit manufactured according to an embodiment of the present invention. FIG. 3B is a simplified cross-sectional view of a portion of the integrated circuit shown in FIG. 3A. FIG. 4 is a diagram showing the relationship between the wafer temperature and the bulk resistivity of a silicon wafer exposed to a standard plasma state for about 1 minute at the end of the nitrogen treatment step according to the embodiment of the present invention. FIG. 5 is a diagram showing the number of particles for 1000 wafers manufactured according to an embodiment of the method of the present invention. FIG. 6A is a diagram showing the relationship between wafer temperature and time for a wafer placed in a plasma urged by a relatively high source high frequency power. FIG. 6B is a diagram showing the relationship between wafer temperature and time for a wafer placed in a plasma urged by relatively high source high frequency power and bias high frequency power. FIG. 7A: Approximate concentrations vs. surface of selected separated atomic elements of deposited FSG thin films after being treated in a nitrogen plasma urged by a selected high frequency source power that is relatively low without high frequency bias power. It is a diagram which shows the relationship of the depth from. FIG. 7B is a diagram showing the relationship between nitrogen concentration and depth from the surface of an FSG thin film after being treated for 1 minute in a nitrogen plasma urged by a relatively high frequency source power without high frequency bias power. is there. FIG. 7C is a diagram showing the relationship between nitrogen concentration and depth from the surface of an FSG thin film after being treated for 1 minute in a nitrogen plasma urged by a relatively low high frequency source power without high frequency bias power. is there. FIG. 7D is a diagram showing the relationship between nitrogen concentration and depth from the surface of an FSG thin film after being treated for 2 minutes in a nitrogen plasma urged by a relatively low high frequency source power without high frequency bias power. is there. FIG. 7E is a diagram showing the relationship between the nitrogen concentration and the depth from the surface of the FSG thin film after being treated for 1 minute in a nitrogen plasma urged by a relatively low high-frequency source power and high-frequency bias power. is there.