Method of generating simulation model

The present invention relates to a simulation model generation method, and more particularly to a simulation model generation method for verifying the timing of an electronic circuit.

Semiconductor integrated circuits provided by various manufacturers, such as when a vendor and a customer try to collaborate to create a product by enabling simulation based on circuit information in a format commonly used in the past. Although it is possible to simulate the operation of an electronic circuit using the above, the circuit information in the above format is described according to certain published rules, so the side receiving the circuit information etc. By decoding, you can easily grasp the types of elements used in semiconductor integrated circuits, the connection relationships of each element, delay information of signals transmitted through signals, that is, design information such as circuit design know-how and development trends. It was possible to do.

In order for the customer to be able to perform the simulation, the vendor needs to provide the customer with circuit information for the functional block. The customer designs an electronic circuit using the functional block and performs a simulation based on the circuit information of the functional block. However, if circuit information is provided to the customer, there is a problem that information that the customer does not want to know, such as know-how on circuit design, is known to the customer.

In Patent Document 1 below, in order to solve the above problem, measures such as concealing design information such as circuit design know-how and development tendency by encrypting circuit information are taken.

<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2004-171367</text></patcit>

<p> However, since the circuit information remains even after encryption, the original circuit information can be restored by decrypting the encryption. With the recent improvement in computer processing power and network technology, it is becoming relatively easy to decrypt the circuit information by unlocking the encryption key.</p><p> In addition, with the progress of integrated circuit technology in recent years, the scale has increased, and IP (Intellectual Property) has come to be distributed, and concealment is essential to protect the circuit information of IP in the same semiconductor circuit. The part that becomes and the part that does not necessarily have to be kept secret have become clear.</p><p> An object of the present invention is to provide a simulation model capable of concealing circuit information of a functional block (IP) while enabling gate simulation.</p>

<p> According to one aspect of the invention<u style="single">By netlist generation means</u>Steps to generate a netlist containing circuit information of electronic circuits using functional blocks,<u style="single">By the gate simulation model generation means</u>Based on the netlist<u style="single">, Obtaining the logical information between the input and output of the functional block,</u>Delete the circuit information,<u style="single">Add the delay information of the functional block,</u>Logical information between the input and output of the functional block and<u style="single">Of functional blocks</u>Timing verification including delay information<u style="single">of</u>Has a step to generate a gate simulation model for<u style="single">However, the functional block includes the first and second logic circuits, and in the netlist, the first signal is input to the first logic circuit, the second signal is input to the second logic circuit, and the first signal is input. And the second signal are signals branched from the same signal, and in the gate simulation model, the first signal is input to the first and second logic circuits, and the delay information between the first and second signals is Distributed to the input or output buffer of the second logic circuit</u>A method for generating a simulation model is provided.</p>

<p> Since the vendor only needs to provide the customer with a gate simulation model that is a black box and does not have to provide a netlist, it is possible to conceal the circuit information and design know-how of the functional block (IP). Also, unlike the netlist, the gate simulation model does not have circuit information, so the speed of gate simulation can be improved. Further, since the gate simulation model only needs to include the delay information between the input and output, its size can be reduced, and the required file size and memory size can be significantly reduced.</p>

FIG. 1 is a flowchart showing a flow of a processing example in which a vendor and a customer cooperate to create a semiconductor integrated circuit (electronic circuit) according to an embodiment of the present invention.

In step S101, the vendor generates a logical simulation model of a functional block (IP). The functional block is, for example, a CPU or the like. The logical simulation model is a black box that does not include the circuit information of the functional block, and is a DSM (Design Simulation Model) that includes the logical information between the input and output of the functional block and performs logical verification. Then, in step S102, the vendor provides the customer with its logic simulation model. This logic simulation model is, for example, binary code compiled from a simulation language of HDL (Hardware Description Language).

Then, in step S103, the customer receives the logical simulation model from the vendor. Next, in step S104, the customer designs a semiconductor integrated circuit using the functional block corresponding to the logic simulation model. However, since the functional block remains a black box, the customer cannot know the circuit information, and the know-how of the circuit information can be kept secret. Next, in step S105, the customer performs a logic simulation of the semiconductor integrated circuit using the logic simulation model of the functional block. The logic simulation is an RTL-based pre-layout logic simulation for logic verification to confirm the logic operation of a semiconductor integrated circuit. After the logic verification by the logic simulation, in step S106, the customer passes the design data of the semiconductor integrated circuit to the vendor.

Next, in step S107, the vendor receives the design data of the semiconductor integrated circuit from the customer. Next, in step S108, the vendor designs the layout of the semiconductor integrated circuit and generates a netlist. The netlist contains circuit information for the above semiconductor integrated circuits. The layout of the above functional block black box is designed at this stage.

Next, in step S109, the vendor generates the gate simulation model of the semiconductor integrated circuit based on the netlist. The gate simulation model is a black box in which circuit information is deleted based on the above netlist, and is a DSM (Design Simulation Model) for performing timing verification including logical information and delay information between the input and output of the above functional blocks. Is. Specifically, the gate simulation model is generated by adding delay information to the above logic simulation model. Then, in step S110, the vendor provides the gate simulation model to the customer. This logic simulation model is, for example, a binary code compiled from what is written in HDL, and its delay information is annotated with SDF (Standard Delay Format).

Then, in step S111, the customer receives the gate simulation from the vendor. Here, since the above functional block remains a black box, the customer cannot know the circuit information, and the know-how of the circuit information can be kept secret. Next, in step S112, the customer performs a gate simulation of the above-mentioned semiconductor integrated circuit using the gate simulation model. The gate simulation is a post-layout (actual wiring level) simulation (validation) for verifying the timing of the setup time and hold time of the semiconductor integrated circuit. After timing verification by gate simulation, in step S113, the customer orders the semiconductor integrated circuit from the vendor.

Next, in step S114, the vendor receives an order for the semiconductor integrated circuit from the customer. Next, in step S115, the vendor manufactures the semiconductor integrated circuit based on the netlist of the above-mentioned semiconductor integrated circuits. Next, in step S116, the vendor delivers the semiconductor integrated circuit to the customer.

FIG. 2 is a diagram showing a configuration example of the logic simulation model 202 generated in step S101 of FIG. The following shows an example of ARM's CPU core (IP). The ARM7 family and ARM9 family processors developed by ARM Limited in the United Kingdom are very popular in the embedded industry. In particular, as the core of ASIC, it is integrated into a single chip together with user logic, and is widely used in consumer products such as mobile phones and digital still cameras.

Layer 201 is instantiated in the semiconductor chip. Layer 201 is, for example, A926 layer (A926_I8D8_I16D16_M). For example, a configuration example of instruction cache = 8KB, data cache = 8KB, instruction TCM (Tightly Coupled Memory) = 16KB, data TCM = 16KB, and ETM (Embedded Trace Macrocell) = medium is shown. Further, the layer 202 is instantiated as a logical simulation model under the layer 201. The layer 202 is, for example, the ARM926EJ-S layer, which is a logical simulation model of DSM. The logic simulation model 202 includes a logic simulation model 203 of functional blocks. The functional block 203 is, for example, a clock synchronization processor model (PLI-Object), and has D-type flip flops 211 to 214 and a logic circuit LG.

Layer 201 inputs the external clock signal CLK. The logic simulation model 202 includes the input signal I_i, I_jAnd the external clock signal CLK is input, and the output signal O_iAnd O_jIs output. The flip-flops 211 to 214 have a clock terminal, an input terminal D, and an output terminal Q. The clock signal CLK is input to the clock terminals of the flip-flops 211 and 212.

Input signal I_iIs input to the input terminal D of the flip-flop 211 via the logic circuit LG. The flip-flop 211 holds the signal of the input terminal D in synchronization with the clock signal CLK and outputs it from the output terminal Q. The output signal is the output signal O via the flip-flop 213 and the logic circuit LG._iIs output as.

Input signal I_jIs input to the input terminal D of the flip-flop 212 via the logic circuit LG. The flip-flop 212 holds the signal of the input terminal D in synchronization with the clock signal CLK and outputs the signal from the output terminal Q. The output signal is the output signal O via the flip-flop 214 and the logic circuit LG._jIs output as.

The logic simulation model 202 is a black box that does not include the circuit information of the functional block 203, includes only the logical information between the inputs and outputs of the functional block 203, and is described in HDL. This logic simulation model 202 enables logic simulation.

FIG. 3 is a diagram showing a configuration example of the gate simulation model 310 generated in step S109 of FIG. The gate simulation model 310 of the above functional block is the logic simulation model 203 of FIG. 2 covered with the timing wrapper 311 of the delay information of the SDF. The timing wrapper 311 has input / output buffers 301 to 305, and distributes the delay information of the functional block 203 to the input / output buffers 301 to 305.

The input buffer 301 is the input signal I_iIs delayed and supplied to the logic circuit LG in the logic simulation model 203. Input buffer 302 is input signal I_jIs delayed and supplied to the logic circuit LG in the logic simulation model 203. The input buffer 303 delays the clock signal CLK and supplies it to the clock terminals of the flip-flops 211 and 212 in the logic simulation model 203. The output buffer 304 delays the output signal of the logic circuit LG in the logic simulation model 203 and outputs the output signal O._iOutput as. The output buffer 305 delays the output signal of the logic circuit LG in the logic simulation model 203 and outputs the output signal O._jOutput as.

The gate simulation model 310 is a black box that does not include the circuit information of the functional block 203, includes logical information and delay information between the inputs and outputs of the functional block 203, and is described in HDL. The gate simulation model 310 enables gate simulation.

In the logic simulation model 202 of FIG. 2, no timing wrapper is required and the delay may be 0 or delta delay. On the other hand, in the gate simulation model 310 of FIG. 3, the delay information extracted from the layout information is annotated to the timing wrapper 311 to perform the gate simulation at the actual wiring level.

FIG. 4 is a diagram showing a configuration example of the netlist generated in step S108 of FIG. Layer 401 corresponds to layer 201 in FIG. 2, and layer 402 corresponds to layer 202 in FIG.

The points that the circuit of FIG. 4 differs from the circuit of FIG. 2 in terms of design will be described. The clock signal CLK is the clock signal CLK outside the layer 401 via the root buffer 411._iAnd CLK_jBranch to. This is because the clock tree synthesis at the customer design stage in step S104 of FIG. 1 increases the number of external clock terminals in layer 402. Clock tree synthesis is performed, for example, to adjust the delay so that the timings of the clock signals input to the flip-flops 211 and 212 are the same.

Further, in the netlist, unlike the logic simulation model, a terminal for the test input signal SCAN-IN and a terminal for the test output signal SCAN-OUT are provided in the layer 402. The terminals of the test signals SCAN-IN and SCAN-OUT are connected to the internal circuit of the functional block of layer 402 to test the internal circuit. This is because the input / output test terminals such as Scan or BIST (Boundary Scan Test) are increased by the DFT (Design For Test) process in the layout design stage of the vendor in step S108 of FIG.

The netlist contains circuit information for the entire electronic circuit using the functional blocks of layer 402. That is, it includes all circuit information and delay information in the functional block of layer 402. At the clock terminal of the flip-flop 211, the output clock signal of the root buffer 411 has a delay time α._i1Buffer, delay time α_i2Buffer and delay time α_i3Is input through the buffer of. At the clock terminal of the flip-flop 212, the output clock signal of the root buffer 411 has a delay time α._j1Buffer, delay time α_j2Buffer and delay time α_j3Is input through the buffer of.

Input signal I_iIs the delay time β_iIt is input to the logic circuit LG via the buffer of. Input signal I_jIs the delay time β_jIt is input to the logic circuit LG via the buffer of. Output signal O_iIs the output signal of the logic circuit LG with a delay time γ_iIt is a signal output through the buffer of. Output signal O_jIs the output signal of the logic circuit LG with a delay time γ_jIt is a signal output through the buffer of.

Delay time α_i1And α_j1The buffer of represents the delay time between the output of the root buffer 411 and the input of the layer 401. Delay time α_i2And α_j2The buffer of represents the delay time between the input of layer 401 and the input of layer 402. Delay time α_i3, Α_j3, Β_iAnd β_jThe buffer of represents the delay time between the input of layer 402 and the input of the first stage circuit of layer 402. Delay time γ_iAnd γ_jThe buffer in represents the delay time between the final stage circuit output of layer 402 and the output of layer 402.

As described above, the boundaries outside the functional blocks of the netlist often change as compared with the logic simulation model 202 of FIG. In particular, since the clock tree changes every time the layout is designed, it is difficult to provide a predetermined logic simulation model as a DSM. If you only want to increase the number of terminals, you only need to modify the timing wrapper 311 in Fig. 3, but in the actual layout, the clock signal CLK is different._iAnd CLK_jWhere the delay from is to be defined, the logic simulation model 202 in Figure 2 has only one clock terminal, and all input / output timing information is corrected for timing information related to its degeneracy (reducing the number of clock terminals). Need to be done with respect to.

As described above, the netlist differs in design from the logic simulation model in two points. First, the netlist of Figure 4, this clock tree is spanned by an arbitrary hierarchy is the. The second is that DFT processing is performed. Therefore, the clock signal CLK is used as the layer 402._i, CLK_jClock terminal and test signal SCAN-IN and SCAN-OUT test terminals increase. The clock tree may be stretched inside layer 401, but even if it is stretched outside it, it does not lose its generality, so that case is shown in Fig. 4. In any case, the clock tree is stretched within a certain hierarchy, and the root buffer 411 is instantiated in any hierarchy.

In the case of FIG. 4, the arbitrary clock input signal in the layer 402 is CLK._i, ..., CLK_jAnd. For the flip-flops 211 and 212 that they drive, the flip-flops 213 and 214 that have outputs in the layer 402 are taken, and the output signal of each output terminal Q is O._iAnd O_jAnd. Output signal O_iAnd O_jOutput delay time of γ_iAnd γ_jAnd. Similarly, the input signals for the flip-flops 211 and 212 having inputs in the layer 402 are I._iAnd I_jAnd. Input signal I_iAnd I_jInput delay time of β_iAnd β_jAnd.

Output signal O_iOutput delay time γ_iIs the clock signal CLK_iDepends on the output signal O_jOutput delay time γ_jIs the clock signal CLK_jDepends on. Input signal I_iThe setup time and hold time of the flip-flop 211 regarding the input of the clock signal CLK_iDepends on the input signal I_jThe setup time and hold time of the flip-flop 212 regarding the input of the clock signal CLK_jDepends on. The setup time is the time from when the signal of the input terminal D is confirmed in the flip-flop to when the clock signal is started up. The hold time is the time during which the signal at the input terminal D must not be changed from the rising edge of the clock signal in the flip-flop.

The vendor provides the customer with a gate simulation model that is a black box. Clock signal CLK as above_i, CLK_jWhen the number of terminals of the test signal SCAN-IN and SCAN-OUT increases, it is necessary to increase the number of terminals of the timing wrapper in the hierarchy. In the gate simulation model, since the purpose is gate simulation, the terminals of the test signals SCAN-IN and SCAN-OUT are simply increased, and there is no problem even if the test function does not operate. On the other hand, regarding the clock terminals, the plurality of clock terminals in the netlist in FIG. 4 are returned to one in the gate simulation model in FIG. 5, and the input delay time and the output delay time extracted from the layout information are corrected.

That is, the netlist has more clock terminals and test terminals than the logic simulation model. The number of increases varies from layout to layout and is not fixed. Therefore, in the gate simulation model, the number of clock terminals of the logic simulation model is set to the same or close to the same number, and unified.

FIG. 5 is a diagram showing a configuration example of the gate simulation model 502 generated in step S109 of FIG. 1, and is a gate simulation model 502 generated based on the netlist of FIG. The gate simulation model 502 corresponds to the netlist of the layer 402 in FIG. 4, and is the same as the gate simulation model 310 in FIG. 3 in which the logic simulation model 203 is covered with the timing wrapper 503. The gate simulation model 502 is a black box that does not include circuit information of the functional block, and includes logical information and delay information between the input and output of the functional block.

Since the gate simulation model 502 is intended for gate simulation, there is no problem even if the test function using the test signal SCAN-IN and SCAN-OUT terminals does not operate. Therefore, the test signal SCAN-IN and SCAN-OUT terminals do not have any problem. Is not connected to the internal circuit.

The gate simulation model 502 is a logic simulation model 203 covered with a timing wrapper 503. In the netlist in Figure 4, the clock signal CLK with two layers 402_iAnd CLK_jHowever, in this gate simulation model 502, one clock signal CLK is similar to the logic simulation model 202 in FIG._jHas terminals of. Delay time α_i2Buffer output clock signal CLK_iIs disconnected outside the gate simulation model 502. Instead, the clock terminal of the flip-flop 211 has the same clock signal CLK as the clock terminal of the flip-flop 212._jIs the delay time α_j3Is input through the buffer of.

In the timing wrapper 503, the delay time β of the netlist in Fig. 4_i, β_j, γ_i, γ_jIs the delay time β'_i, β'_j, γ'_i, γ'_jIs replaced by. Since the clock signal input to the clock terminal of the flip-flop 211 has changed, the delay information between the clock signals before and after the change is the delay time β'of the input buffer of the flip-flop 211._iAnd output buffer delay time γ'_iWill be distributed to. Below, the delay time β'_i, β'_j, γ'_i, γ'_jThe calculation method of is described.

As a hypothesis, in the netlist of FIG. 4, a set of delay times from root buffer 411 to clock terminals such as arbitrary flip-flops 211 and 212 in layer 402 {Σα_i, ..., Σα_j} In Σα_jIs the minimum. Here, Σα_j= α_j1+ α_j2+ α_j3And. Σα_jΣα_n(However, n j)

Further, in the following discussion, the timing reference point is the output point of the root buffer 411 instantiated in an arbitrary hierarchy. Output signal O_i(However, i j) output timing To_iFrom Fig. 4, the delay time from the input of the clock signal of the flip-flop 211 to the output of the output terminal Q is T._QThen, it becomes as follows To_i= Σα_i+ T_Q+ γ_i

However, from Fig. 5, there is only one clock terminal of the gate simulation model 502, and the delay of the clock signal of the flip-flop 211 is Σα._jIt is represented by. Also, since there is no circuit information in the gate simulation model 502, the output delay time T of the flip-flop 211_QBecomes 0. Therefore, in FIG. 5, the output timing To_iIs expressed by the following equation.

To_i= Σα_j+ (Σα_i-Σα_j) + 0 + (T_Q+ γ_i) = Σα_j+ (T_Q+ γ_i+ S_i) (However, S_i= Σα_i-Σα_j) = Σα_j+ γ'_i

Therefore, γ'_iIs γ_i, T_QAnd S_iCan be expressed by the following relational expression using. γ'_i= (T_Q+ γ_i+ S_i)

Therefore, the clock signal is CLK._iFrom CLK_jEven if changed to, output delay γ_iSkew from the root buffer 411 of the clock signal (delay difference S)_i= Σα_i-Σα_j) And the output delay T of the flip-flop 211_QOutput timing To by adding_iTurns out to be compensateable.

Similarly, in the netlist of FIG. 4, the input signal I_iFlip-flop 211 setup time T for (where i j)_sui T the logical delay_logic, Clock period T_periodThen, it is expressed by the following equation. T_sui = T_period-T_logic-β_i+ Σα_i

However, in Fig. 5, there is only one clock terminal of the gate simulation model 502, and the delay time of the clock signal of the flip-flop 211 is Σα._jBecause it is represented by, the setup time T_sui is expressed by the following equation.

T_sui = T_period-T_logic-β_i+ Σα_j+ (Σα_i-Σα_j) = T_period-T_logic-(β_i-S_i) + Σα_j (However, S_i= Σα_i-Σα_j) = T_period-T_logic-β'_i+ Σα_j

From the above, the delay time β'_iIs the following relational expression. β'_i= β_i-S_i

Therefore, the clock input signal of the flip-flop 211 is CLK._iFrom CLK_jInput delay time β even if changed to_iSkew from the root buffer 411 of the clock signal from (delay difference S)_i= Σα_i-Σα_j) Is subtracted to set up time T_suIt turns out that i can be compensated.

Similarly, in FIG. 4, the input signal I_iHold time T of flip-flop 211 for (where i j)_hdi T the logical delay_logicThen, it is expressed by the following equation. T_hdi = T_logic+ β_i-Σα_i

However, in Fig. 5, there is only one clock terminal of the gate simulation model 502, and the delay time of the clock signal of the flip-flop 211 is Σα._jHold time T because it is represented by_hdi is expressed by the following equation.

T_hdi = T_logic+ β_i-Σα_j-(Σα_i-Σα_j) = T_logic+ (β_i-S_i)-Σα_j(However, S_i= Σα_i-Σα_j) = T_logic+ β'_i-Σα_j

From the above, the delay time β'_iIs the following relational expression. β'_i= β_i-S_i

Therefore, the clock signal of the flip-flop 211 is CLK._iFrom CLK_jInput delay time β even if changed to_iSkew from the root buffer 411 of the clock signal from (delay difference S)_i= Σα_i-Σα_jHold time T by subtracting)_hdIt turns out that i can be compensated.

In addition, the output signal O, which was excluded from the above discussion,_jDelay time To_jIs Σα from Fig. 5_jSince one clock terminal remains, it is expressed by the following equation.

To_j= Σα_j+ 0 + T_Q+ γ_j = Σα_j+ γ'_j

From this, the delay time γ'_jThe following relational expression holds. γ'_j= T_Q+ γ_j

In addition, the input signal I_jSetup time T_suj and hold time T_hdj has the following relational expression.

T_suj = T_period-T_logic-β_j+ Σα_j = T_period-T_logic-β'_j+ Σα_j T_hdj = T_logic+ β_j-Σα_j = T_logic+ β'_j-Σα_j

From this, the delay time β'_iIs the following relational expression. β'_j= β_j

As described above, the number of external clock terminals of the functional block in the gate simulation model of FIG. 5 is made smaller than the number of external clock terminals of the functional block in the netlist of FIG. The same or close to it can be processed in a unified manner.

In the netlist of FIG. 4, the first clock signal is input to the clock terminal of the flip-flop (logic circuit) 212, and the second clock signal is input to the clock terminal of the flip-flop 211. The first and second clock signals are signals branched from the same clock signal. In the gate simulation model of FIG. 5, the first clock signal is input to the clock terminals of the flip flops 211 and 212. The delay information between the first and second clock signals is the input buffer (β') connected to the input and output terminals of the flip flop 211._i) And output buffer (γ'_i) Is distributed.

Output delay information of flip-flop 211 T_QIs the output buffer (γ') connected to the output terminal of the flip-flop 211._i) Is distributed. Output delay information of flip flop 212 T_QIs an output buffer (γ') connected to the output terminal of the flip-flop 212._j) Is distributed.

FIG. 6 is a diagram showing another configuration example of the gate simulation model 502 generated in step S109 of FIG. The gate simulation model of FIG. 6 has a delay time α compared to that of FIG._j3The difference is that the buffer of is deleted.

In this case, the delay time γ'_iAnd β'_iIs expressed by the following equation. γ'_i= (T_Q+ γ_i+ S_i) β'_i= β_i-S_i Where S_i= Σα_i-(Α_j1+ α_j2)become.

Also, the delay time γ'_jAnd β'_jIs expressed by the following equation. γ'_j= (T_Q+ γ_j+ S_j) β'_j= β_j-S_j Where S_j= α_j3become.

Similarly, the delay time α_j1And α_j2Delete the buffer of, delay time delay time γ'_i, Beta'_i, Gamma'_jAnd β'_jMay be calculated.

As described above, in the net list of FIG. 4, the first clock signal is input to the clock terminal of the flip-flop 212, and the second clock signal is input to the clock terminal of the flip-flop 211. The first and second clock signals are signals branched from the same clock signal. In the gate simulation model 502 of FIG. 6, the third clock signal is input to the flip-flops 211 and 212, and the delay information between the first and third clock signals is the input / output buffer (β') of the flip-flop 212._jAnd γ'_j), And the delay information between the second and third clock signals is the input / output buffer (β') of the flip-flop 211._iAnd γ'_i) Is distributed.

FIG. 8A is a diagram showing wiring 802 connected to the inverter (gate) 801 and its output terminal. In SDF, the delay information of the inverter 801 and the delay information of the wiring 802 can be expressed.

FIG. 8B is a diagram corresponding to FIG. 4 and showing a configuration example of the netlist generated in step S108 of FIG. The output terminal of the inverter 811 and the input terminal of the inverter 813 are connected by wiring 812. The inverter 811 is arranged outside the layer 401. The inverter 813 has the delay information (time) D1 and is arranged in the functional block layer 402. The wiring 812 has the delay information D2 and exists at the boundary between the layers 401 and 402. When defining the delay information for wiring 812 at the boundaries of layers 401 and 402, it is necessary to separate the SDFs at this boundary. However, since the gate in the layer 402 on the receiving side is hidden by the gate simulation modeling, the delay time D2 of the wiring 812 cannot be defined.

FIG. 8C corresponds to FIG. 5 and shows a configuration example of the gate simulation model 502 generated in step S109 of FIG. 1, which is generated based on the netlist of FIG. 8B. The gate simulation model 502 corresponds to the netlist of the functional block hierarchy 402 in FIG. 8 (B). In the present embodiment, the delay information D2 of the wiring 812 in the final stage of the upper layer 401 is deleted (set to 0), and the delay information D2 is added to the delay information D1 of the first stage gate 813 of the lower layer 502 to achieve accuracy. Keep. Gate 813 is described as SDF delay information in the timing wrapper 503 of FIG.

As described above, the delay information of the wiring 812 connecting the layer 402 targeted by the gate simulation model and the upper layer 401 is D2. When generating the delay information of the gate simulation model, the delay information D2 of the wiring 812 is added to the delay information D1 of the gate 813 in the gate simulation model 502 and included, so that the design information including the simulation model and the original The equivalence of the delay information with the design information can be matched.

When replacing the hard IP with DSM, the delay information D2 of the wiring 812 existing at the boundary between the functional block layer 402 and the upper layer 401 that is the target of the gate simulation model is changed to the delay information D1 of the gate 813 in the gate simulation model 502. By adding it, the change timing of the output signal of the DSM can be exactly matched with the original hard IP. This makes it possible to more accurately reproduce the actual operation of the LSI in the gate simulation.

FIG. 9 is a diagram corresponding to FIG. 4 and showing a configuration example of the netlist generated in step S108 of FIG. The functional block layer 402 has, for example, three D-type flip-flops 911 to 913, a negative logical product (NAND) circuit 921, a negative logical sum (NOR) circuit 922, and an output terminal O1. The NAND circuit 921 inputs the output signals of the flip-flops 911 and 912 and outputs the NAND signal. The NOR circuit 922 inputs the output signal of the NAND circuit 921 and the output signal of the flip-flop 913, and outputs the NOR signal to the output terminal O1. The route buffer 901 is provided outside the functional block layer 402, and amplifies and outputs the clock signal CLK.

The output clock signal of the root buffer 901 is supplied to the clock terminal of the flip-flop 911 via a buffer having a delay time α1. The output clock signal of the root buffer 901 is supplied to the clock terminal of the flip-flop 912 via a buffer having a delay time α2. The output clock signal of the root buffer 901 is supplied to the clock terminal of the flip-flop 913 via a buffer having a delay time α3.

Three flip-flops 911 to 913 are connected to the output terminal O1, and the signal of each output terminal Q propagates to the output terminal O1 through different paths A1, A2, and A3 at different times. When the functional block layer 402 is replaced with DSM, the flip-flops 911 to 913 become invisible, and which of the routes A1 to A3 the signal output to the output terminal O1 is output through. Information will be deleted.

In the above, the method of selecting the path with the slowest signal transmission and the path with the fastest signal transmission by changing parameters such as temperature and voltage of a plurality of circuits has been described.

However, since there are originally multiple paths A1 to A3, if gate simulation is performed with the DSM replaced, there will be a discrepancy between the simulation result before replacing the DSM and the signal change timing at the output terminal O1. It is not possible to perform a perfect match simulation.

To solve this problem, add a terminal for delay control to the DSM. The SDF used in the gate simulation describes a function that can selectively change the signal delay time on the path from the input to the output of the black box according to the select signal. Assign the description of this SDF to the terminal for delay control added to the DSM. This makes it possible to adopt one of the plurality of routes A1 to A3 that is valid.

FIG. 10 is a diagram corresponding to FIG. 5 and showing a configuration example of the gate simulation model 502 generated in step S109 of FIG. 1, and is generated based on the netlist of FIG. The gate simulation model 502 corresponds to the netlist of the functional block hierarchy 402 in FIG. 9, and is a logic simulation model 203 covered with a timing wrapper 503.

The timing wrapper 503 has a buffer with a delay time B1, a buffer with a delay time B2, a buffer with a delay time B3, and a selector 931. The delay time B1 is the delay time of the output signal when the output signal is output from the output terminal O1 through the path A1. The delay time B2 is the delay time of the output signal when the output signal is output from the output terminal O1 through the path A2. The delay time B3 is the delay time of the output signal when the output signal is output from the output terminal O1 through the path A3. The timing wrapper 503 may be described as delay information of SDF, or the circuit information itself as described above may be described.

The output signal of the NOR circuit 922 is output to the selector 931 via the buffer of the delay time B1, the buffer of the delay time B2, and the buffer of the delay time B3, respectively. The selector 931 selects one of the three input signals according to the select signal SEL and outputs the output to the output terminal O1.

The state machine 932 outputs a select signal SEL indicating which of the paths A1 to A3 the signal is output to the output terminal O1 based on its own state signal and input signal. The select signal SEL is not limited to the case where it is generated by the state machine 932, and may be generated by a combinational circuit or may be an external signal itself.

As a result, a delay time B1 is added to the output signal when the output signal is output to the output terminal O1 via the path A1, and a delay time is added to the output signal when the output signal is output to the output terminal O1 via the path A2. When B2 is added and the output signal is output to the output terminal O1 via the path A3, the delay time B3 is given to the output signal.

As described above, when the netlist of FIG. 9 has a functional block layer 402 capable of outputting signals of a plurality of paths A1 to A3 to the same output terminal O1, the gate simulation model 502 of FIG. 10 has a plurality of paths A1 to A1 to. Includes delay information that changes the delay times B1 to B3 of the signal output from the output terminal O1 according to the path through which A3 passes. As a result, the time change of the signals of all paths A1 to A3 can be made exactly the same as the original hard IP.

As described above, according to the present embodiment, the vendor only needs to provide the customer with a gate simulation model which is a black box, and does not have to provide the netlist. Therefore, the circuit of the functional block (IP). Information and design know-how can be kept secret. Also, unlike the netlist, the gate simulation model does not have circuit information, so the speed of gate simulation can be improved. Further, since the gate simulation model only needs to include the delay information between the input and output, its size can be reduced, and the required file size and memory size can be significantly reduced.

FIG. 7 is a block diagram showing a hardware configuration example of a computer that performs the processing of FIG. The vendor processes on the vendor's computer, and the customer processes on the customer's computer. These computers can generate a logical simulation model, a netlist, a gate simulation model, and the like by CAD (computer-aided design). A central processing unit (CPU) 702, ROM703, RAM704, network interface 705, input device 706, output device 707, and external storage device 708 are connected to the bus 701.

The CPU 702 processes and calculates data, and controls the above-mentioned constituent units connected via the bus 701. A boot program is stored in ROM703 in advance, and when the CPU702 executes this boot program, the computer starts up. A computer program is stored in the external storage device 708, and the computer program is copied to the RAM 704 and executed by the CPU 702. This computer performs the processes of steps S101 to S114 of FIG. 1 by executing the computer program.

The external storage device 708 is, for example, a hard disk storage device, and the stored contents are not erased even when the power is turned off. The external storage device 708 can record a computer program, a logic simulation model, a netlist, a gate simulation model, etc. on a recording medium, and can read a computer program or the like from the recording medium.

The network interface 705 can input and output computer programs, gate simulation models, and the like to and from the network. That is, the logic simulation model, the gate simulation model, and the like can be transmitted and received between the vendor and the customer's computers. The input device 706 is, for example, a keyboard, a pointing device (mouse), or the like, and can perform various designations or inputs. The output device 707 is a display, a printer, or the like, and can display or print.

This embodiment can be realized by executing a program by a computer. Further, a means for supplying the program to a computer, for example, a computer-readable recording medium such as a CD-ROM recording the program or a transmission medium such as the Internet for transmitting the program is also applied as an embodiment of the present invention. Can be done. Further, a computer program product such as a computer-readable recording medium on which the above program is recorded can also be applied as an embodiment of the present invention. The above programs, recording media, transmission media and computer program products are included in the scope of the present invention. As the recording medium, for example, a flexible disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a magnetic tape, a non-volatile memory card, a ROM, or the like can be used.

It should be noted that all of the above embodiments merely show examples of embodiment in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from the technical idea or its main features.

Various applications of the embodiment of the present invention are possible, for example, as follows.

(Appendix 1) Steps to generate a netlist containing circuit information of electronic circuits using functional blocks, A step of deleting circuit information based on the netlist and generating a gate simulation model for timing verification including logical information and delay information between the input and output of the functional block. Simulation model generation method having. (Appendix 2) The gate simulation model is the simulation model generation method according to Appendix 1, wherein the delay information of the functional block is represented by the input / output buffer of the functional block. (Appendix 3) The simulation model generation method according to Appendix 2, wherein the number of external terminals of the functional block in the gate simulation model is smaller than the number of external terminals of the functional block in the netlist. (Appendix 4) The functional block includes first and second logic circuits. In the netlist, the first signal is input to the first logic circuit, the second signal is input to the second logic circuit, and the first and second signals are branched from the same signal. Is a signal In the gate simulation model, the first signal is input to the first and second logic circuits, and the delay information between the first and second signals is distributed to the input / output buffers of the second logic circuit. The simulation model generation method described in Appendix 3. (Appendix 5) The simulation model generation method according to Appendix 4, wherein the first and second signals are first and second clock signals. (Appendix 6) The first and second logic circuits are first and second flip-flops including a clock terminal, an input terminal, and an output terminal. In the net list, the first clock signal is input to the clock terminal of the first flip-flop, the second clock signal is input to the clock terminal of the second flip-flop, and the first and second The clock signal is a signal branched from the same clock signal, In the gate simulation model, the first clock signal is input to the clock terminals of the first and second flip-flops, and the delay information between the first and second clock signals is the delay information of the second flip-flop. The simulation model generation method according to Appendix 5, which is distributed to the input buffer and the output buffer connected to the input terminal and the output terminal. (Appendix 7) The output delay information of the first flip-flop is distributed to the output buffer connected to the output terminal of the first flip-flop. The simulation model generation method according to Appendix 6, wherein the output delay information of the second flip-flop is distributed to an output buffer connected to the output terminal of the second flip-flop. (Appendix 8) The simulation model generation method according to Appendix 7, wherein the first and second clock signals are signals branched from the same clock signal outside the functional block and are input to different external clock terminals of the functional block. (Appendix 9) Further, it has a step of generating a logic simulation model for performing logical verification of the functional block by including the logical information between the input and output of the functional block without including the circuit information of the functional block. The step of generating the gate simulation model is the simulation model generation method according to Appendix 8 for generating a gate simulation model by adding delay information to the logic simulation model. (Appendix 10) The simulation model generation method according to Appendix 9, wherein the number of external clock terminals of the functional block in the gate simulation model is the same as the number of external clock terminals of the functional block in the logic simulation model. (Appendix 11) In the netlist, the functional block has a test terminal connected to the internal circuit to test the internal circuit. In the gate simulation model, the test terminal of the functional block is not connected to the internal circuit. The simulation model generation method according to Appendix 10. (Appendix 12) The simulation model generation method according to Appendix 1, wherein the delay information includes delay information of wiring existing at a boundary of the functional block. (Appendix 13) The functional block includes first and second logic circuits. In the netlist, the first signal is input to the first logic circuit, the second signal is input to the second logic circuit, and the first and second signals are branched from the same signal. Is a signal In the gate simulation model, a third signal is input to the first and second logic circuits, and delay information between the first and third signals is distributed to input / output buffers of the first logic circuit. The simulation model generation method according to Appendix 3, wherein the delay information between the second and third signals is distributed to the input / output buffers of the second logic circuit. (Appendix 14) The simulation model generation method according to Appendix 13, wherein the first to third signals are first to third clock signals. (Appendix 15) The first and second logic circuits are first and second flip-flops including a clock terminal, an input terminal, and an output terminal. In the net list, the first clock signal is input to the clock terminal of the first flip-flop, the second clock signal is input to the clock terminal of the second flip-flop, and the first and second The clock signal is a signal branched from the same clock signal, In the gate simulation model, a third clock signal is input to the clock terminals of the first and second flip-flops, and delay information between the first and third clock signals is input to the first flip-flop. The delay information between the second and third clock signals is distributed to the input buffer and the output buffer connected to the terminal and the output terminal, and the delay information between the second and third clock signals is the input buffer and the input buffer connected to the input terminal and the output terminal of the second flip-flop. The simulation model generation method according to Appendix 14, which is distributed to the output buffer. (Appendix 16) The output delay information of the first flip-flop is distributed to the output buffer connected to the output terminal of the first flip-flop. The simulation model generation method according to Appendix 15, wherein the output delay information of the second flip-flop is distributed to an output buffer connected to the output terminal of the second flip-flop. (Appendix 17) The simulation model generation method according to Appendix 16, wherein the first and second clock signals are signals branched from the same clock signal outside the functional block and are input to different external clock terminals of the functional block. (Appendix 18) Further, it has a step of generating a logic simulation model for performing logical verification of the functional block by including the logical information between the input and output of the functional block without including the circuit information of the functional block. The step of generating the gate simulation model is the simulation model generation method according to Appendix 17, wherein the gate simulation model is generated by adding delay information to the logic simulation model. (Appendix 19) The simulation model generation method according to Appendix 18, wherein the number of external clock terminals of the functional block in the gate simulation model is the same as the number of external clock terminals of the functional block in the logic simulation model. (Appendix 20) The netlist has a functional block capable of outputting signals of a plurality of paths to the same output terminal. The simulation model generation method according to Appendix 1, wherein the gate simulation model includes delay information for changing the delay time of a signal output from the output terminal according to a path passing through the plurality of paths.

<figref num="1">It is a flowchart which shows the flow of the process example which creates the semiconductor integrated circuit (electronic circuit) in cooperation with the vendor and the customer by embodiment of this invention.</figref><figref num="2">It is a figure which shows the configuration example of the logic simulation model generated in step S101 of FIG.</figref><figref num="3">It is a figure which shows the configuration example of the gate simulation model generated in step S109 of FIG.</figref><figref num="4">It is a figure which shows the configuration example of the netlist generated in step S108 of FIG.</figref><figref num="5">It is a figure which shows the configuration example of another gate simulation model generated in step S109 of FIG.</figref><figref num="6">It is a figure which shows the configuration example of another gate simulation model generated in step S109 of FIG.</figref><figref num="7">It is a block diagram which shows the hardware configuration example of a computer.</figref><figref num="8">8 (A) to 8 (C) are diagrams showing delay information of wiring at the boundary of the functional block.</figref><figref num="9">It is a figure which shows the configuration example of another netlist generated in step S108 of FIG.</figref><figref num="10">It is a figure which shows the configuration example of another gate simulation model generated in step S109 of FIG.</figref>

Code description

201 hierarchy 202 Logic simulation model 203 Functional block logic simulation model 211 ~ 214 Flip flops 301 ~ 303 Input buffer 304,305 output buffer 310 Gate simulation model 311 Timing trumpet 401,402 tier 411 Root buffer 502 Gate simulation model 503 Timing trumpet 701 bus 702 CPU 703 ROM 704 RAM 705 network interface 706 Input device 707 Output device 708 External storage