Ultra low inductance multi layer ceramic capacitor

The present invention relates to the field of electronic devices, especially to ceramic capacitors. This application is in accordance with US Patent Law Article 119 (e) and Enforcement Rule 1.78, provisional application No. 60 / 468,380, 2003 entitled "Ultra Low Induction Multilayer Ceramic Condenser Structure" filed on May 6, 2003. Claim priority under Provisional Application No. 60 / 469,475 filed May 8, 2003 and Provisional Application No. 60 / 468,876 filed May 6, 2003. In addition, all of these provisional applications are incorporated herein by reference.

As the performance of computer and network communications improves, the demand for high-speed, high-density integrated circuits is increasing. Such high-performance integrated circuits (ICs) have come to require advanced noise filtering techniques such as decoupling capacitors in order to improve the reliability of the device. Decoupling capacitors are typically placed near a power supply and / or ground, such as a Vdd. Decoupling capacitors reduce noise and smooth out fluctuations in power supply voltage. Decoupling capacitors are typically mounted on a printed circuit board (PCB) close to the IC. As IC switching speeds increase, more demands are placed on decoupling capacitors. FIG. 1A shows a conventional decoupling capacitor 100. The capacitor 100 has a body 106 and two ends 102 and 104. A capacitor 100 having a typical physical size has a rectangular structure having W (width) × L (length) × H (height), in which L is the longest and H is the shortest. The two ends 102 and 104 give the capacitor 100 a potential known as the + and-poles. The structure of the capacitor 100 is typically referred to as the axial structure. FIG. 1B is a side view 140 of the capacitor 100 shown in FIG. 1A. In this, the capacitor 150 is mounted on the PCB 152. Typically, the wires or terminals 162 and 164 are used to connect the capacitor 150 to the PCB 152.

<p> The demand for larger decoupling capacitors is met by adopting larger and larger capacitors. However, the problem with conventional capacitors is the parasitic inductance. Typically, the larger the size of the capacitor, the larger the parasitic inductance. Parasitic inductance reduces the efficiency of the capacitor. Capacitors with large parasitic inductances have low resonant frequencies, which makes them unusable for many well-known high-speed applications. For example, it is known that there are low-power DC / DC or DC-DC converters that operate at 1 MHz, and some that operate at up to 2 MHz. However, high-power DC / DC converters work with about one-tenth of their low-power counterparts. One reason is related to the resonant frequency of large capacitors. Higher value multilayer ceramics typically have a resonant frequency less than 500kHz, while lower value multilayer ceramic capacitors have a resonant frequency greater than 2MHz. The relationship between the resonance frequency and the capacitance can be expressed by the following equation.<maths num="1"><img file="JP4498397B2_D0001.tif" /></maths>Where f represents the resonant frequency, L represents the parasitic inductance, also known as Equivalent Series Inductance (ESL), and C represents the capacitance. As can be seen, the smaller the inductance L, the larger the resonance frequency f.</p><p> Therefore, it is desirable to have a multilayer capacitor that provides a high capacitance and a small parasitic inductance.</p>

<p> The capacitors have m electrode plates arranged in parallel apart from each other. m is an integer greater than 1. Each of the m electrodes has a first extension. n external terminals are located on the first common outer surface of the capacitor. n is an integer greater than 1. The first extension of the even number of m electrode plates is connected to the even number of n external terminals. The first extension of the odd-numbered m electrode plates is connected to the odd-numbered n external terminals. The n external terminals are arranged at a predetermined minimum distance from each other so as to minimize the parasitic inductance.</p><p> In another feature, the predetermined minimum distance is the minimum distance that prevents crosstalk between the n first external terminals. n external terminals are arranged in parallel. In one embodiment, n = 2, and n first external terminals are configured in parallel. In another embodiment, n = 3 and n first external terminals are arranged in parallel. The even-numbered n first external terminals are located between the odd-numbered n first external terminals.</p><p> In another feature, a dielectric material is provided between each of the m electrode plates. The outer ones of the n first external terminals are provided on the common outer surface of the capacitor and on the corresponding side surface of the capacitor. In other embodiments, n = 4, and the first and second of the n first external terminals are arranged in the first row. The third and fourth of the n first external terminals are arranged in the second row. The first of the n first external terminals is adjacent to the second and fourth of the n first external terminals and of the n first external terminals. Arranged diagonally to the third. The second of the n first external terminals is located diagonally to the fourth of the n first external terminals.</p><p> In another feature, each of the m electrode plates has a second extension. The capacitor has s second external terminals. s is an integer greater than 1. The s second external terminals are located on the second common outer surface of the capacitor. The second extension of the even number of m electrode plates is connected to the even number of s second external terminals. The second extension of the odd-numbered m electrode plates is connected to the odd-numbered s external terminals.</p><p> In yet another feature, the second common outer surface is arranged to face the first common outer surface. Each of the m electrode plates has a second extension. The capacitor has s second external terminals, where s is greater than 1. The even-numbered s second external terminals are located on the third outer surface of the capacitor. The odd-numbered s of the second external terminals are located on the fourth outer surface of the capacitor. The second extension of the even number of m electrode plates is connected to the even number of s second external terminals. The second extension of the odd-numbered m electrode plates is connected to the odd-numbered s second external terminals.</p><p> The filter includes this capacitor and an inductor connected to the even number of n first external terminals. The output terminals are connected to the even-numbered n external terminals. The reference voltage is connected to the odd-numbered n external terminals. The voltage regulator is equipped with this filter.</p><p> The printed circuit board (PCB) includes a plurality of the above-mentioned capacitors, and further includes a plurality of PCB contacts. A plurality of capacitors are connected to a plurality of PCB contacts so as to facilitate parallel connection of at least two capacitors. The capacitor structure includes the above-mentioned capacitors, and further includes a second capacitor having x electrode plates connected in parallel and s third external terminals. Where x is an integer greater than 1.</p><p> In another feature, s = 2, s second external terminals are arranged in parallel, and s third external terminals are arranged in parallel. Alternatively, s = 3, s second external terminals are arranged in parallel, and the even-numbered s second external terminals are the odd-numbered s second external terminals. It is placed between things. The s third external terminals are arranged in parallel, and the even-numbered s third external terminals are arranged between the odd-numbered s third external terminals. The filter has a capacitor structure and also has inductors connected to the even number of n first external terminals. The output terminals are connected to the even-numbered n first external terminals. The reference voltage is connected to the odd-numbered n first external terminals.</p><p> The voltage regulator is equipped with this filter and is further equipped with a multi-layer printed circuit board. The capacitor structure is mounted on a multilayer printed circuit board. The inductor is connected to the first trace of the multilayer printed circuit board. The first trace is connected to the even number of n first external terminals via the first plurality of vias. The output terminal is connected to a second trace on the multilayer printed circuit board. The second trace is connected to the even number of n first external terminals via the second plurality of vias. The reference voltage is connected to a third trace on the multilayer printed circuit board. The third trace is connected to the odd-numbered n first external terminals via the third plurality of vias.</p><p> Those skilled in the art will appreciate that the broad teachings of the present invention can be realized in various forms from the above description. Thus, although the invention is described in the context of that particular embodiment, the true scope of the invention is not limited thereto. Other modifications will be apparent to those skilled in the art upon examination of the drawings, specification and claims.</p><p> The outline of the above invention does not enumerate all the necessary features of the present invention, and subcombinations of these feature groups can also be inventions.</p>

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention within the scope of the claims, and all combinations of features described in the embodiments are included. It is not always essential for the means of solving the invention. In the following embodiments, substantially the same components shall be represented by the same reference numerals.

A parallelepiped multi-layer capacitor with low parasitic inductance is disclosed. In order to maintain low parasitic inductance in multilayer ceramic capacitors, in certain embodiments, the external contact terminals of the capacitor are as much as possible before electrical crosstalk occurs between the external contact terminals and to reduce parasitic inductance. Must be located close together. In other words, reducing the physical distance between the external contact terminals of the capacitor will reduce the parasitic inductance.

FIG. 2A is a block diagram 200 showing the multilayer capacitor 202, which is mounted on the printed circuit board 208. In one embodiment, the capacitor 202 has two external contacts or contact terminals 204 and 206. The contact bar or terminal 204 is used as a terminal of one polarity of the capacitor 202, and the contact terminal 206 is used as a terminal of the other polarity. In some aspects, the width 222 of the capacitor 202 is shorter than the height 220 of the capacitor 202. A predetermined minimum distance of 210 is employed between the contact terminals 204 and 206 to minimize parasitic inductance. The distance 210 between the two polar contact bars 204 and 206 affects the parasitic inductance. The shorter the distance 210 between the opposite polarity contact bars 204 and 206, the smaller the parasitic inductance. This structure also reduces the effective series resistance. Preferably, the distance 210 is less than 12 mils, more preferably less than 8 mils.

FIG. 2B is a configuration 230 showing a bottom view of the contact terminals 204 and 206 of FIG. 2A. The contact terminals 204 and 206 are separated by a predetermined area or distance of 236 to minimize parasitic inductance. In one embodiment, the distance 210 must be kept to a minimum length to reduce the parasitic inductance of the capacitor. The distance 210 is also called a predetermined minimum distance. In the position embodiment, the predetermined minimum distance is the minimum distance that separates external contacts of different polarities. As described above, the distance 236 between the two polar contact bars 204 and 206 affects the parasitic inductance. The shorter the distance between the contact terminals of opposite polarity, the smaller the parasitic inductance.

With reference to FIGS. 2A and 2B again, in some aspects the structure of the capacitor 202 is referred to as the radial structure. This is because the radial structure of a multi-layer capacitor can be thought of as rotating the shaft structure 90 degrees and moving both terminals to one side of the capacitor instead of arranging them at the ends of the shaft structure capacitor. The advantage of the radial structure capacitor is that the external contact portions can be provided close to each other with a minimum separation distance. By reducing the distance between the external contacts, the parasitic inductance also decreases. In other words, radial capacitors provide low parasitic inductance, in part due to the small distance 210 between the terminals.

3A to 3C are various views of the electrode plate according to the embodiment of the present invention. FIG. 3A is a perspective view of the electrode plates 302 to 308 for the multilayer radiation structure capacitor. The electrode plates 302 to 308 further have contact fingers, i.e. extensions 312 to 318, respectively. Note that the dimensions of the electrode plates 302-308 and contact fingers 312-318 shown in FIG. 3A are not full-scale. In one embodiment, the electrode plates 312 and 316 are connected to potentials of the first polarity and the electrode plates 314 and 318 are connected to potentials of the other polarity. Note that the dielectric material (not shown in FIG. 3A) is placed between the electrode plates 302-308. Also note that the numbers of electrode plates 302 to 308 shown in FIG. 3A are exemplary. In one embodiment, the electrode plates 412 to 418 include one or more of copper, nickel, aluminum and other alloys.

FIG. 3B shows a top view of the electrode plates 302 to 308. FIG. 3C shows a bottom view of the electrode plates 302 to 308. In one embodiment, the electrode plates 302 and 306 transfer charges of one polarity and the electrode plates 304 and 308 transfer charges of the other polarity. FIG. 3C shows four contact fingers 312-318, with the contact fingers 312 and 316 connected to potentials of one polarity and the contact fingers 316 and 318 connected to potentials of the other polarity. Note that in one embodiment, the gap 382 affects the value of the parasitic inductance. Preferably, the gap 382 is less than 12 mils, more preferably less than 8 mils.

FIG. 4A is an exploded perspective view of the multilayer capacitor 400 according to the embodiment of the present invention. The capacitor 400 has a plurality of first and second electrode plates 412 to 418 and dielectric materials 402 to 410. In one embodiment, a dielectric material such as a ceramic compound is sandwiched between the electrode plates. Note that the dimensions of the dielectric materials 402-410 shown in FIG. 4A are exemplary and not full-scale. Capacitor 400 also has first and second external contacts 420 and 422 to provide electrical connectivity. The concept underlying the present invention does not change whether an electrode is added to the capacitor 400 or the electrode is removed from the capacitor 400.

Referring to FIG. 4A, each of the first electrodes 412 or 416, also known as the first internal electrode or electrode plate, has a first portion 440 and a second portion or extension 430. The first part 440 is the main part of the first electrode 412. The second part 430 is a contact part. In one embodiment, the width 434 of the capacitor 400 is smaller than the height 436 of the capacitor 400. Note that the contact finger 430 shown in Figure 4A is merely exemplary and not life-size. Further note that the first electrode 412 may have contact fingers.

Similarly, each of the second electrodes 414 or 418 has a first portion 442 and a second portion, i.e. extension 432. The first part 442 is the main part of the second electrode 418. The second part 432 is a contact finger. In one embodiment, the contact fingers 430 and 432 are used to provide electrical connections to the first and second external contacts 420 and 422. The distance 424 between the first and second external contacts 420 and 422 is minimized to reduce parasitic inductance.

The dielectric materials 402 to 410, also called a ceramic layer or a dielectric, are sandwiched between the first and second electrode plates 412 to 418. In one embodiment, the dielectric materials 402-410 are formed from one or more of barium titanate, titanium, zirconate, and other types of ceramic materials.

The first external contact portion 420, also known as an external terminal or external lead, is orthogonal to the electrode plates 412 to 418 and electrically connects to the contact finger 430 of the first electrode plates 412 and 416. The first external contact section 420 is used to provide an electrical connection between the first electrodes 412, 416 and other equipment via various connecting media such as printed circuit boards or wiring. Be done. In one embodiment, the first external contact section 420 is configured to connect to a printed circuit board. In other embodiments, the first external contact section 420 is configured to connect to other devices such as capacitors or inductors. For example, referring to Figures 9D and 10C, it shows stacked radial capacitors. The second external contact portion 422, also known as an external terminal or an external lead, is also arranged so as to be orthogonal to the electrode plates 412 to 418 and electrically attaches to the contact finger 432 of the second electrode layers 414 and 418. Connecting. The external contact portion 422 of the earth is used to provide an electrical connection between the second electrodes 412, 416 and other devices. In one embodiment, the second external contact portion 422 is configured to connect to a printed circuit board. In other embodiments, the second external contact 422 is configured to connect to a device such as another capacitor. The distance 424, also referred to as the minimum space, the minimum distance, or the predetermined minimum distance, is the physical distance between the first external contact portion 420 and the second external contact portion 422.

FIG. 4B shows the configuration of the multilayer capacitor 450 according to the embodiment of the present invention. The capacitor 450 has external contacts 452 and 454, a gap 456, and a body 456. In one embodiment, the external contacts 452 and 454 correspond to the external contacts 420 and 422 shown in FIG. 4A. Similarly, the width of the gap 456 corresponds to the minimum space 424 shown in FIG. 4A. In this embodiment, the width 460 of the capacitor 450 is shorter than the height 464. In other embodiments, the height 464 is longer than the length 462 of the capacitor 450. One of the effects of the present invention is related to the fact that it is possible to save the installation space on the PCB. It should be noted that the addition or omission of contact fingers does not deviate from the concept underlying the present invention.

FIG. 5 is a block diagram showing a multilayer capacitor mounted on a printed circuit board according to an embodiment of the present invention. Referring to FIG. 5, block diagram 500 has a capacitor 502 and a printed circuit board 512 connected through contacts 504-510. In one embodiment, the capacitor 502 is a multilayer ceramic capacitor, having a first external contact portion 506 and a second external contact portion 504. External contacts 504 and 506 are located at a minimum distance of 518 to reduce parasitic inductance. The printed circuit board 512 has metal traces 514 and 516 and metal contacts 508 and 510 for connecting to the capacitor 502. It should be noted here that even if the printed circuit board 512 has a multi-layered metal trace, the concept underlying the present invention does not change.

In one embodiment, the capacitor 502 is mounted by soldering it to a printed circuit board 512 using surface mount technology. In other embodiments, the capacitor 502 may be mechanically mounted on the printed circuit board via an adhesive or other adhesive material. The advantage of adopting this type of mounting technology for decoupling capacitors is that they are easy to mount and easy to rework.

6A-6D are block diagrams showing contact terminals of capacitors according to an alternative embodiment of the present invention. Referring to FIG. 6A, block diagram 600 is a bottom view of a bar-structured capacitor with three contact bars 604 to 610. In one embodiment, one polarity electrode plate of the capacitor is connected to the outer bars 604 and 606 and the other polarity electrode plate is connected to the inner bar 610. In other words, one of the contact terminals is located on the central bar of the capacitor and the other contact terminals are split into two parts and located on the outer edge of the capacitor 600. The bar structure provides low series resistance to the external contacts. For some applications, such as DC / DC converters, it is necessary to minimize the series resistance in order to achieve a relatively high performance DC / DC converter. In addition, high performance DC / DC converters or voltage regulators must minimize not only the internal series resistance, but also the series resistance generated through the traces and vias associated with the printed circuit board. In some aspects, the bar terminal structure reduces the coupling series resistance between the printed circuit board and the capacitor. Higher-order bar structures can also be adopted to create alternating contact terminals for capacitors. It should be further noted that as the available contact area of the terminals themselves decreases, the radial structure of the multilayer capacitor according to the invention increases the series parasitic inductance, whereas the effective series resistance increases. Therefore, it is an effect of the present invention that a larger number of external contacts may be used for larger capacitors.

With reference to FIG. 6B, block diagram 630 shows another embodiment of the external contact portion 632 having three contact bars 634-640 in a bar structure. In one embodiment, one polar electrode plate of the capacitor is connected to the inner finger 640 and the other polar electrode plate is connected to the outer bars 634 and 636. The external contact portion 632 shows a technique of extending a contact surface such as bars 634 to 636 beyond the surface of the capacitor 632 and wrapping the corner of the main body of the capacitor 632 with the contact surface. Note that increasing the area of the contact surface reduces the equivalent series resistance (ESR), which is effective in improving the performance of the capacitor. For any bottom area of a conventional capacitor, this technique can increase the area by 30%. Another advantage of using widened contact surfaces is that it creates a stronger connection between the capacitor and the printed circuit board. In another embodiment, the two contact bars 634 and 636 are configured to extend beyond the surface of the capacitor 632 and wrap around the corners of the capacitor 632 in order to further increase the contact area to reduce resistance.

FIG. 6C shows a higher order configuration 660 of the contact bar. This configuration 660 shows an alternative arrangement of contact bars 664 to 670. In one embodiment, the sensation between the contact bars 664-670 is minimized to reduce the parasitic inductance of the capacitor 632. FIG. 6D shows the configuration 680 of the contact bars 684 to 690 of the capacitor 682. The large contact surface of the contact bars 684 to 690 provides a low ESR of configuration 680. It should be noted that increasing the number of high-order contact bars from four bars does not deviate from the present invention. In one embodiment, the contact bars 684 to 690 are arranged to extend beyond the surface of the capacitor 682 and wrap around the corners of the capacitor 682 to further increase the contact area to reduce resistance.

Radial capacitors are used in one embodiment to perform filtering functions in high power DC / DC converters. A DC / DC converter, also known as a DC-DC converter, is a device that receives a DC input voltage and produces a DC output voltage. Normally, the output produced is at a different voltage level than the input. In other applications, DC / DC converters are used to provide noise isolation and / or power regulation and the like.

FIG. 6E is an exploded perspective view of a multilayer capacitor for the configuration shown in FIG. 6A according to an embodiment of the present invention. The electrode plates 614 and 616 include contact fingers 618 to 619, and the electrode plates 615 and 617 include contact fingers 620. Note that the dimensions of the electrode plates 614-617 and contact fingers 618-620 shown in FIG. 6E are not full-scale. The advantages and effects of the invention are obtained when the contact fingers 618 to 619 are slightly smaller or larger in size than the electrode plates 614 to 617. In one embodiment, the electrode plates 615 and 617 are connected to one polarity and the electrode plates 614 to 616 are connected to the other polarity. Note that a space or dielectric material (not shown in FIG. 6E) is inserted between the electrode plates 614 to 617. It should also be noted that the numbers of electrode plates 614 to 617 shown in FIG. 6E are exemplary. In one embodiment, the electrode plates 614-617 are formed from one or more of copper, nickel, aluminum, and other alloys.

FIG. 6F shows a capacitor 642 with external contact bars 646-649 similar to the contact structure 632 shown in FIG. 6B, according to an embodiment of the invention. In one embodiment, the main body 644 of the capacitor 642 has a plurality of electrode plates 614 to 617 shown in FIG. 6E. The external contact portions 646 to 648 wrap the corners of the main body 644 in order to maximize the contact area. In this embodiment, the external contact portions 646 to 648 are connected to one polarity and the external contact portion 649 is connected to the other polarity.

FIG. 6G is an exploded perspective view of a multilayer capacitor for the configuration shown in FIG. 6C, according to an embodiment of the present invention. The electrode plates 674 to 677 have contact fingers 650 to 656, the electrode plates 674 and 677 are connected to one polarity, and the electrode plates 675 to 676 are connected to the other polarity. Note that the dimensions of the electrode plates 674-677 and contact fingers 650-656 shown in Figure 6G are not full-scale. The advantages and effects of the invention are obtained when the contact fingers 650-656 are sized slightly smaller or larger than the electrode plates 674-677. Note that a space or dielectric material (not shown in Figure 6G) is inserted between the electrode plates 674-677. The numbers of electrode plates 674 to 677 shown in FIG. 6G are exemplary. In one embodiment, the electrode plates 674-677 are formed from one or more of copper, nickel, aluminum and other alloys.

FIG. 6H shows a capacitor 691 with external contact bars 693-696 similar to the contact structure 682 shown in FIG. 6D, according to an embodiment of the invention. In one embodiment, the body 692 of the capacitor 691 has a plurality of electrode plates 674-677 as shown in FIG. 6G. The external contact portions 693 to 696 wrap the corners of the main body 692 in order to maximize the contact area. Note that in one embodiment, the external contact bars 693-695 wrap around the front and back sides of the body 692.

FIG. 7A schematically shows a DC-DC converter 700 using a multilayer capacitor C according to an embodiment of the present invention. The converter 700 has a switch power supply 702, an inductor L and a capacitor 704. The switch power supply 702 further has a switch S1, a second switch S2, a Vcc, and a ground potential. Further, the capacitor 704 has a capacitance C and a parasitic inductance L._parhave. During operation, the inductor L smoothes the current fluctuations and the capacitor 704 smoothes the voltage fluctuations at the output. Note that the converter 700 is also called a DC-DC voltage regulator.

FIG. 7B shows another configuration of the DC / DC converter 750. The converter 750 has a switch power supply 752, an inductor L and a capacitor 754. The converter 750 is sometimes referred to as an LC configuration. The switch power supply 752 further has a first switch S1, a second switch S2, a Vcc, and a ground potential GND. Capacitor 754 contains three capacitive elements C1, C2, C3 with parasitic inductances L1, L2, L3, respectively. Capacitive elements C1, C2, and C3 are connected in parallel to increase the overall capacitance of the capacitor 754. During operation, the inductor L smoothes the current fluctuations and the capacitor 754 smoothes the voltage fluctuations at the output. 8A to 8C show the connection of the DC-DC converter according to the embodiment of the present invention. FIG. 8A shows a configuration 800 with an LC configuration such as a DC / DC converter. Configuration 800 has a capacitor 801 and an inductor L and an output. The capacitor 801 also has two external contact bars 802 and 804, and the terminal of the inductor L is connected to one end of the contact bar 802. The output is connected to the other end of the contact bar 802. The connection of contact bar 802 corresponds to the connection of node A shown in Figure 7A. In an alternative embodiment, the capacitor 801 has two contact pads of one polarity, the left part of the upper bar 802 is connected to the output of the inductor L of the DC / DC voltage regulator. The right part of the upper bar 802 is connected to the output of the voltage regulator. The lower finger 804 is connected to the reference potential.

FIG. 8B shows an alternative embodiment. Configuration 810 shows the connection of a DC-DC converter mounted on the printed circuit board 820. In one embodiment, the printed circuit board 820 has various vias 822-828. Configuration 810 includes a capacitor 811 with an inductor L and an output. The capacitor 811 further has two external contact bars 812-814, the contact bars 812-814 being further connected to a plurality of vias 822. The terminal of the inductor L is connected to a trace on the PCB, the trace is connected to via 824 of the printed circuit board 820, and the output is connected to the other via 826 of the printed circuit board 82-. It will be apparent to those skilled in the art that the addition of additional external contact bars does not deviate from the present invention. The ground or reference voltage is connected to bar 816 on the right side via via 828.

Figure 8C shows an alternative configuration 840 that includes a capacitor 850. This configuration 840 also includes three external contact bars 852-856. The contact bar 854 provides a potential of one polarity, and the contact bars 852, 856 provide a ground or reference potential to the capacitor 850. In some applications, the contact bar acts as a transmission line and the contact bars 852 and 856 provide a shield.

9A-9D show a laminated configuration for a multilayer capacitor according to an embodiment of the present invention. FIG. 9A shows a configuration 900 having a first electrode plate 904 and a second electrode plate 906. A gap due to a dielectric material or air may be used between the electrode plates. The first electrode plate 904 further has an upper contact finger or extension 908 and a lower contact finger or extension 910. The second electrode plate 906 also has an upper contact finger or extension 912 and a lower contact finger or extension 914. Note that the contact fingers 908 and 910, 912 and 914 are not drawn on the correct scale for the electrode plates 904-906.

FIG. 9B shows a capacitor 920 with external contact bars 926 and 928 on the top of the capacitor 920 and external contact bars 930 and 932 on the bottom. The main body 922 of the capacitor 920 has a plurality of electrode plates 904 and 906 as shown in FIG. 9A. In one embodiment, the gaps 924 and 925 are kept to a minimum to reduce parasitic inductance.

Figure 9C shows the configuration 940 of the physical connections between the various components for a DC / DC voltage regulator. The output terminal of the inductor L is connected to the upper external contact bar 926, and the lower external contact bar 930 is connected to the output terminal. Other external contact bars 932 are connected to ground or reference potential.

FIG. 9D shows a stacked configuration 960 in which two capacitors 962 and 964 forming a larger capacitor are stacked, as shown in schematic view 972. In one embodiment, to overlap the capacitors 962 and 964, the lower external contact bar 982 of the capacitor 962 is connected to the upper contact bar 986 of the capacitor 964, and the lower external contact bar 984 of the capacitor 962 It is connected to the external contact bar 988 on the upper side of the capacitor 964. In one aspect, the capacitor 966 in schematic diagram 972 can be a capacitor 964 and the capacitor 968 can be a capacitor 962. It will be apparent to those skilled in the art that overlaying additional capacitors on capacitors 962 and / or 964 does not deviate from the present invention.

FIGS. 10A-10E show a laminated structure for a multilayer capacitor according to the present invention. FIG. 10A shows a configuration 1000 having a first electrode plate 1002 and a second electrode plate 1004. The first electrode plate 1002 further comprises a first contact finger or extension 1012 and a second contact finger 1013. In one embodiment, the first contact finger 1012 extends to the side of the capacitor and the second contact finger or extension 1013 extends to the bottom of the capacitor. It should be noted that the contact fingers 1012 to 1015 are not drawn on the correct scale for the electrode plates 1002 to 1004. The second electrode plate 1004 also has a first contact finger or extension 1014 and a second contact finger or extension 1015, the first contact finger 1014 extending to the side of the capacitor and the second. Contact finger 1015 extends to the bottom of the capacitor.

FIG. 10B is a front view of the capacitor 1020. Capacitor 1002 has two side contact bars 1024 and 1026 and two bottom contact bars 1028 and 1030. The main body 1022 of the capacitor 1020 has a plurality of first and second electrode plates 1002 to 1004 shown in FIG. 10A. Note that the space between the contact bars must be kept to a minimum to reduce parasitic inductance. In one embodiment, the contact bars 1024 and 1030 are terminals of one polarity of the capacitor 1020 and the contact bars 1026 and 1028 are terminals of the other polarity.

FIG. 10C shows a stacked configuration 1040 in which two capacitors 1042 and 1044 are stacked to form a larger capacitive element. In one embodiment, stacking is achieved by connecting the external contact bar 1048 of the capacitor 1042 to the external contact bar 1050 of the capacitor 1044. Other contact bars 1054-1060 may be used to connect to other components such as printed circuit boards.

FIG. 10D shows configuration 1070 with a first electrode plate 1072 and a second electrode plate 1074. The first electrode plate 1072 further has a first contact finger 1073 and a second contact finger 1075. In one embodiment, the first contact finger 1073 extends to the bottom of the capacitor and the second contact finger 1075 extends to one of the outer surfaces of the capacitor. The second electrode plate 1074 has a first contact finger 1078 and a second contact finger 1079. The first contact finger 1078 of the second electrode plate 1074 extends to the bottom of the capacitor and the second contact finger 1079 extends to the other outer surface of the capacitor. In one embodiment, the first electrode plate 1072 propagates charges of one polarity and the second electrode plate 1074 propagates electrodes of the other polarity. Note that the contact fingers 1072-1079 are not drawn on the correct scale for the electrode plates 1072-1074.

FIG. 10E shows a stacked configuration 1080 in which two capacitors 1082 and 1084 are stacked to form a larger capacitive element. In one embodiment, the capacitors 1082 and 1084 are the capacitor device 1070 shown in FIG. 10D. With reference to FIGS. 10D and 10E, in one embodiment, the contact finger 1075 is connected to the external contact bar 1093 R hand-woven and the contact finger 1079 is connected to the external contact bar 1092. Further, the contact finger 1073 of the first electrode plate 1072 is connected to the external contact bar 1098, and the contact finger 1078 of the second electrode plate 1074 is connected to the external contact bar 1097. In this embodiment, the contact fingers 1092 and 1098 propagate charges of one polarity and the contact fingers 1092 and 1097 propagate charges of the other polarity.

In one embodiment, stacking is achieved by connecting the external contact bar 1088 of the capacitor 1082 to the external contact bar 1099 of the capacitor 1084. In this embodiment, the capacitors 1082 and 1084 are connected in parallel. Other contact bars 1094-1098 may be used to connect to other components such as printed circuit boards.

11A-11C show other embodiments of the laminated structure in a perspective view. FIG. 11A shows the first electrode plate 1102 and the second electrode plate 1104 of the multilayer capacitor. The first electrode plate 1102 further has a first contact finger or extension 1112 and a second contact finger or extension 1113. In one embodiment, the first contact finger 1112 extends to the left side of the capacitor and the second contact finger 1113 extends to the right side of the capacitor. Note that the contact fingers 1112-1114 are not drawn on the correct scale for the electrode plates 1102 and 1104. The second electrode plate 1104 has a contact finger or extension 1114 extending to the bottom of the capacitor.

FIG. 11B is a front view of the capacitor 1120, which has two side contact bars 1124 and 1126 and one bottom contact bar 1128. The body 1122 of the capacitor 1120 has a plurality of first and second electrode plates 1102 to 1104 shown in FIG. 11A. Note that the space between contact bars 1124 to 1128 must be kept to a minimum to reduce parasitic inductance. In one embodiment, the contact bars 1124 and 1126 are terminals of one polarity of the capacitor 1120 and the contact bars 1128 are terminals of the other polarity.

FIG. 11C is another front view of the capacitor 1120, which has two side contact bars 1144 to 1146 and one bottom contact bar 1148. The main body 1142 of the capacitor 1140 has a plurality of first and second electrode plates 1102 to 1104 shown in FIG. 11A. Note that the front view of the capacitor 1120 is similar to the front view of the capacitor 1140, except for the contact bars 1144-1148. The contact bars 1144 to 1148 wrap around the corners of the main body 1142 of the capacitor 1140. The space between the contact bars 1144 and 1148 must be kept to a minimum to reduce parasitic inductance. In the positional embodiment, the contact bars 1144 and 1146 are terminals of one polarity of the capacitor 1140, and the contact bars 1148 are terminals of the other polarity.

14A-14B show perspective views of other embodiments of the laminated configuration. The embodiments of FIGS. 14A-14B further have side electrodes of both polarities as compared to the embodiments of FIGS. 11A-11C. FIG. 14A shows the first electrode plate 1402 and the second electrode plate 1404 of the multilayer capacitor. The first electrode plate 1402 further has a first contact finger or extension 1412, a second contact finger or extension 1413, and a third contact finger or extension 1484. In one embodiment, the first contact finger 1412 extends to the left side of the capacitor, the second contact finger 1413 extends to the bottom of the capacitor, and the third contact finger 1434 extends to the right side of the capacitor. There is. Note that the contact fingers are not drawn on the correct scale for the electrode plates 1402-1404. The second electrode plate 1404 has a first contact finger or extension 1482, a second contact finger or extension 1418, and a third contact finger or extension 1482. As shown there, the first contact finger 1482 extends to the left side of the capacitor, the second contact finger 1415 extends to the bottom of the capacitor, and the third contact finger 1414 extends to the right side of the capacitor. It extends to the department.

FIG. 14B shows a stacked configuration 1440, in which two capacitors 1442 and 1444 are stacked to form a capacitive element. In one embodiment, capacitors 1442 and 1444 are capacitor devices 1402 shown in FIG. 14A. With reference to condenser 1444, the contact finger 1484 is connected to the external contact bar 1468, the contact finger 1414 is connected to the external contact bar 1452, the contact finger 1413 is connected to the external contact bar 1460, and the contact finger The 1415 is connected to the external contact bar 1458, the contact finger 1412 is connected to the external contact bar 1450, and the contact finger 1482 is connected to the external contact bar 1492. The capacitor 1442 is similarly configured. Capacitors 1490 and 1492 are arranged side by side, in which capacitors 1442 and 1444 are electrically connected to contact bars 1490 and 1492, as well as electrically connected contact bars 1448 and 1450. It is electrically connected by. Those skilled in the art will appreciate that additional capacitors may be stacked in this exemplary side-by-side configuration.

Although the embodiments shown in FIGS. 14A to 14B show that capacitors are connected in series, they can be reconfigured so that capacitors are stacked in parallel.

12A-12B show capacitors with caps according to embodiments of the present invention. FIG. 12A shows configuration 1200, showing a stacked capacitor with a cap 1212 according to an embodiment of the invention. Configuration 1200 has two capacitors 1202 and 1204, a cap 1212 and a printed circuit board 1220. Capacitor 1204, in one embodiment, has a plurality of external contact bars 1207-1210. The external contact bars 1207 and 1208 are on the top surface of the capacitor 1204, and the external contact bars 1209 and 1210 are on the bottom surface of the capacitor 1204. Capacitor 1204 is connected to the printed circuit board 1220 via contact bars 1209 and 1210, and capacitor 1202 is stacked on the top surface of capacitor 1204 via contact bars 1205-1028.

In one embodiment, the cap 1212 provides the ability to disperse the heat generated by the capacitors 1202 and 1204. The cap 1212 is known as a housing, holder and / or heat disperser, where these terms are used interchangeably. Cap 1212 may have special internal and external fins, but these are not shown in Figure 12A. Internal fins are used to disperse heat between stacked capacitors 1202 to 1204. Note that capacitors tend to get hot when operating at high frequencies.

In one embodiment, radiating capacitors can be placed in a holder 1212 for vertical stacking to form larger capacitors. The holder or cap 1212 may be formed from a plastic compound. Alternatively, the holder 1212 may be formed from an extruded aluminum material. The holder 1212 has a plurality of fins, which are used to provide a heat conduction path to the outer surface portion of the holder 1212. In other embodiments, the holder 1212 may be configured to have a chamber inside using extruded aluminum. In this case, each chamber is designed to fit the individual capacitors. Note that thermal dispersion is essential when the capacitor is operating at high speed.

FIG. 12B shows configuration 1250, which shows a capacitor in the form of being stacked in a holder 1256 according to an embodiment of the present invention. Configuration 1250 includes two capacitors 1252 and 1254, a holder, container, housing or cap 1258, and a printed circuit board 1270. In one embodiment, the capacitor 1252 has a plurality of contact bars 1262 to 1264 and 1270, the external contact bars 1262 to 1264 extend to the sides of the capacitor 1252, and the external contact bar 1270 extends to the bottom of the capacitor 1252. It's growing. Capacitor 1254 is similar to capacitor 1252 and they are stacked horizontally.

Holder 1256 may be formed from a thermally conductive material or may be used to disperse the heat generated by the capacitors 1252 and 1254. Holder 1256 also facilitates stacking of capacitors 1252 and 1254. In one embodiment, the space 1258 between the holder 1256 and the capacitors 1252 and 1254 is filled with a thermally conductive material to disperse heat more effectively. Alternatively, an optional element 1278 is provided to disperse the heat from the capacitor.

It is within the scope of the invention that the stacking capacitor arrangements of FIGS. 9D and 10C include various external terminal arrangements, for example as shown in FIGS. 6A-6D.

Holder 1256 may include any suitable container, magazine, etc. made of any suitable material. The holders may be manufactured by an injection molding process, or the stacked capacitors may be fixed to each other by an encapsulation process. The number of capacitors to be stacked may be any appropriate number.

FIG. 13 shows a stacked configuration 1300 of a plurality of capacitors according to an embodiment of the present invention. Configuration 1300 includes a bottom view 1301 of multiple capacitors and a top view 1320 of a printed circuit board (PCB). Bottom view 1301 includes external contact bars 1310 to 1314 for multiple capacitors 1302 to 1306. Each bottom view has a first polarity terminal 1310 and a second polarity terminal 1314. Space 1312 is provided to separate terminals 1310 and 1314. In one embodiment, space 1312 is the minimum distance to reduce parasitic inductance.

The PCB 1320 has a first contact portion 1322 and a second contact portion 1324, the first contact portion 1332 is a positive electrode terminal in one embodiment, and the second contact portion 1324 is a negative electrode terminal. .. The contacts 1322 and 1324 are separated by a space 1326, which ensures that they are separated by the minimum distance between the contacts 1322 and 1324. In one embodiment, the PCB 1320 provides a parallel connection of multiple capacitors. For example, the contact portion 1310 of the capacitors 1302 to 1306 is connected to the first contact portion 1322 of the PCB 1320, and the contact portion 1314 of the capacitors 1302 to 1306 is connected to the second contact portion 1324 of the PBC. The advantage of connecting multiple capacitors in parallel on a PCB is that the yield can be increased.

In the above description of the invention, specific exemplary embodiments have been referred to. However, it is clear that various improvements and changes may be made to it without departing from the broader scope of the invention. Therefore, the specification and drawings should be regarded as exemplary rather than in a limiting sense.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that the form with such modifications or improvements may also be included in the technical scope of the present invention.

The present invention can be applied to advanced noise filtering techniques such as decoupling capacitors required to improve device reliability in high-speed, high-density integrated circuits for high-performance computers and network communications. is there.

<figref num="1A">Figure 1A shows a conventional capacitor.</figref><figref num="1B">Figure 1B shows a conventional capacitor.</figref><figref num="2A">FIG. 2A is a block diagram showing a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="2B">FIG. 2B is a block diagram showing a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="3A">FIG. 3A shows a plurality of electrode plates of a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="3B">FIG. 3B shows a plurality of electrode plates of a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="3C">FIG. 3C shows a plurality of electrode plates of a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="4A">FIG. 4A is an exploded perspective view of a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="4B">FIG. 4B is a block diagram showing a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="5">FIG. 5 is a block diagram showing a multilayer capacitor mounted on a printed circuit board according to an embodiment of the present invention.</figref><figref num="6A">FIG. 6A is a block diagram showing a contact terminal for a capacitor according to an embodiment of the present invention.</figref><figref num="6B">FIG. 6B is a block diagram showing a contact terminal for a capacitor according to an embodiment of the present invention.</figref><figref num="6C">FIG. 6C is a block diagram showing a contact terminal for a capacitor according to an embodiment of the present invention.</figref><figref num="6D">FIG. 6D is a block diagram showing a contact terminal for a capacitor according to an embodiment of the present invention.</figref><figref num="6E">FIG. 6E is a block diagram showing a contact terminal for a capacitor according to an embodiment of the present invention.</figref><figref num="6F">FIG. 6F is a block diagram showing a contact terminal for a capacitor according to an embodiment of the present invention.</figref><figref num="6G">FIG. 6G is a block diagram showing a contact terminal for a capacitor according to an embodiment of the present invention.</figref><figref num="6H">FIG. 6H is a block diagram showing a contact terminal for a capacitor according to an embodiment of the present invention.</figref><figref num="7A">FIG. 7A is a schematic view showing a DC-DC converter using a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="7B">FIG. 7B is a schematic diagram showing a multilayer capacitor having a parasitic inductance in a DC-DC converter according to an embodiment of the present invention.</figref><figref num="8A">FIG. 8A is a block diagram showing the connection of capacitors in the DC-DC converter according to the embodiment of the present invention.</figref><figref num="8B">FIG. 8B is a block diagram showing the connection of capacitors in the DC-DC converter according to the embodiment of the present invention.</figref><figref num="8C">FIG. 8C is a block diagram showing the connection of capacitors in the DC-DC converter according to the embodiment of the present invention.</figref><figref num="9A">FIG. 9A shows a laminated configuration for a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="9B">FIG. 9B shows a laminated configuration for a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="9C">FIG. 9C shows a laminated configuration for a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="9D">FIG. 9D shows a laminated configuration for a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="10A">FIG. 10A shows a laminated configuration for a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="10B">FIG. 10B shows a laminated configuration for a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="10C">FIG. 10C shows a laminated configuration for a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="10D">FIG. 10D shows a laminated configuration for a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="10E">FIG. 10E shows a laminated configuration for a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="11A">FIG. 11A shows another laminated configuration according to one embodiment of the present invention.</figref><figref num="11B">FIG. 11B shows another laminated configuration according to one embodiment of the present invention.</figref><figref num="11C">FIG. 11C shows another laminated configuration according to one embodiment of the present invention.</figref><figref num="12A">FIG. 12A shows a capacitor with a cap according to an embodiment of the present invention.</figref><figref num="12B">FIG. 12B shows a capacitor with a cap according to an embodiment of the present invention.</figref><figref num="13">FIG. 13 shows a laminated structure of a multilayer capacitor according to an embodiment of the present invention.</figref><figref num="14A">FIG. 14A shows another laminated configuration according to one embodiment of the present invention.</figref><figref num="14B">FIG. 14B shows another laminated configuration according to one embodiment of the present invention.</figref>

Code description

202 Multilayer Capacitor 204, 206 Contact terminal (contact bar) 208 printed circuit board 302, 304, 306, 306 Electrode plate 312, 314, 316, 318 Contact finger (extension) 382 gap 400 multi-layer capacitors 412, 414, 416, 418 Electrode plate 412 ~ 418 402, 404, 406, 408, 410 Dielectric material 420 First external contact 422 Second external contact 450 multi-layer capacitor 452, 454 External contact 456 body 502 capacitor 504, 506, 508, 510 contacts 512 printed circuit board 514, 516 trace 600 capacitors 604, 606, 610 contact bar 614, 615, 616, 617 Electrode plate 618, 619, 620 contact finger 632 Capacitor 634, 636, 640 contact bar 642 Capacitor 646, 647, 648 External contacts 650, 652, 654, 656 contact finger 662 Capacitor 664, 666, 668, 670 contact bar 674, 675, 676, 677 Electrode plate 682 Capacitor 684, 686, 688, 690 contact bar 691 Capacitor 693, 694, 695 External contact bar