Semiconductor device and semicondutor memory using the same

[0001] [Technical field to which the invention belongs] The present invention relates to semiconductor devices and semiconductor memories. More specifically, the present invention relates to techniques useful for commonly connecting the source and drain regions of two transistors. [0002] [Conventional technology] Non-volatile memories such as EEPROM (Electrically Erasable Programmable Read Only Memory) are mounted on mobile phones and the like and are now widely used. The cell transistor of this EEPROM can store 1-bit information depending on the presence or absence of accumulated charge in the floating gate. [0003] On the other hand, recently, in order to reduce the size of a device, the development of a multi-value transistor capable of storing information of multiple bits instead of one bit is in progress. [0004] There are various types of multi-value transistors. Among them, the inventor of the present application is paying attention to a multi-valued transistor produced by forming a plurality of grooves on a silicon substrate and forming a floating gate on the side wall of the grooves (for example, Patent Document 1 by the inventor of the present application). See 2. ). [0005] In this type of multi-valued transistor, a source / drain region is formed on the bottom surface of the groove, and a channel region is formed on the surface of the silicon substrate. That is, this multi-valued transistor has a feature that the height positions of the source / drain region and the channel region are different. This feature is not found in typical MOS transistors in which both the source / drain region and the channel region are formed on the substrate surface, and is unique to this type of multi-valued transistor. [0006] [Patent Document 1] Patent No. 3249811 [Patent Document 2] Japanese Patent No. 3249812. [0007] [Problems to be Solved by the Invention] By the way, the semiconductor memory has not only the above-mentioned cell transistor but also a selection transistor for selecting the cell transistor and the bank. As the selection transistor, the above-mentioned MOS transistor is usually used. Then, the source / drain regions of the cell transistor and the selection transistor are commonly connected, and by turning on the selection transistor, the cell transistor or bank connected to the cell transistor or bank is selected. [0008] However, as described above, the source / drain region of the cell transistor is formed on the bottom surface of the groove, whereas the source / drain region of the selected transistor is formed on the surface of the substrate. Therefore, the source / drain region of each transistor is formed. Are not on the same plane and their height positions are different. Therefore, even if an attempt is made to connect them in common, there are technical difficulties, and the conventional technology cannot realize this connection. [0009] The present invention eliminates such drawbacks of the prior art, and easily connects the source / drain region of a transistor having a different height position between the channel region and the source / drain region to the source / drain region of another transistor. It is an object of the present invention to provide a semiconductor device and a semiconductor memory capable of the present invention. [0010] [Means for solving problems] The above-mentioned problems are the first transistor in which the source / drain region is formed below a part of the channel region, and the channel region and the source / drain at substantially the same height as the source / drain region of the first transistor. By a semiconductor device including a second transistor in which a region is formed, the source and drain regions of each of the first transistor and the second transistor are electrically connected in substantially the same plane. Solve. [0011] Alternatively, a single conductive semiconductor substrate having a plurality of convex portions formed therein, a counterconductive bit wire formed on the surface of the semiconductor substrate between the adjacent convex portions, and a plurality of opposite conductive type bit wires formed in the row direction and the column direction are arranged. A cell transistor in which the bit line is used as a source region or a drain region and a channel region is formed at least on the top surface of the convex portion, and a channel region and a source / drain region are formed at substantially the same height as the bit line. The problem is solved by a semiconductor memory including a selection transistor for selecting a bit line, and one source / drain region of the selection transistor and the bit line are electrically connected in substantially the same plane. [0012] Further, the cell transistor has a pair of side surfaces facing each other, and the cell transistor covers the first insulating film formed on the top surface of the convex portion, each side surface of the convex portion, and the source / drain region. A pair of floating gates formed in pairs on the second insulating film on both sides of the convex portion and facing the side surface of the convex portion and the source / drain region via the second insulating film, and each floating gate. It is characterized by having a third insulating film formed above and a control gate facing each floating gate via the third insulating film and facing the top surface of the convex portion via the first insulating film. It is solved by the semiconductor memory. [0013] Further, a semiconductor memory is characterized in that a plurality of cell transistors are divided into banks by (1 column) × (predetermined row), and an odd-numbered row bank and an even-numbered row bank are selected by a virtual ground method with a selection transistor. Will also be resolved. [0014] According to these inventions, the source / drain regions of the first transistor and the second transistor are located substantially in the same plane, and their height positions are not different as in the conventional case, so that they are in the same plane. The common connection can be easily made with the above, and the technical difficulty of the common connection that has been seen in the past is overcome. [0015] The semiconductor memory includes a drive transistor for driving the cell transistor, the drive transistor is at a different height position from the selection transistor, and the drive transistor and the selection transistor may be formed at the same time by the same process. Although they are at different heights, they are formed at the same time, so the number of steps can be reduced. [0016] Further, it is preferable that a protective insulating film is provided at the end of the convex portion in the column direction, and the protective insulating film is simultaneously formed by the same process as the sidewall insulating film of the transistor having the LDD structure included in the semiconductor memory. Since the protective insulating film and the sidewall insulating film are formed at the same time, the number of steps can be reduced. [0017] In a semiconductor memory including a plurality of cell transistors arranged in the row direction, each cell transistor has a source / drain region formed below a part of a channel region, includes a control gate, and is oriented in the row direction. Multiple arrayed cell transistors share a control gate, multiple arrayed cell transistors in the row direction are divided into multiple blocks, and the semiconductor memory has an insulation separation area provided between adjacent blocks. A transistor (for example, a metal wire) provided in the row direction connected to the control gate may be included in a plurality of regions provided with an insulation separation region. The conductor can substantially reduce the low resistance of the control gate. [0018] Further, when a plurality of cell transistors are arranged in the column direction, the cell transistors arranged in the column direction are divided into a plurality of groups, and within each group, the cell transistors share a channel area and a semiconductor memory. Includes an insulating separation region provided at the end of each group, and preferably separates the groups by an insulating separation region. This makes it possible to control the cell transistors for each group. [0019] Further, in a semiconductor memory including a plurality of cell transistors arranged in a row direction and a column direction, each cell transistor has a source / drain region formed below a part of a channel region, and includes a control gate. A plurality of cell transistors arranged in the row direction share a control gate, a plurality of cell transistors arranged in the row direction are divided into a plurality of blocks, and a semiconductor memory is isolated and isolated between adjacent blocks. The cell transistors including the area and arranged in the column direction are divided into a plurality of groups. Within each group, the cell transistors share a channel area, and the semiconductor memory is an insulation provided at the end of each group. It includes a separation region, and it is possible to separate groups from each other by an insulation separation region. As a result, since the cell transistor is electrically divided in the row direction and the column direction, it can be individually controlled in block and group units in both the row direction and the column direction. [0020] By the way, in a semiconductor memory including a plurality of cell transistors arranged in a column direction, the source / drain region of each of the cell transistors is formed below a part of the channel region, and the cell transistors are a plurality of groups. The source / drain areas of the cell transistors adjacent to each other in the column direction are at least common within each group, and the semiconductor memory has a connection area provided for the group and a plurality of connection areas. Can include a conductor (eg, a metal wire) provided in the column direction connecting to the source / drain region. The conductor can substantially reduce the columnar resistance of the source / drain region. [0021] [0021] In this semiconductor memory, the cell transistors share a channel region within each group, and the semiconductor memory includes an insulation separation region provided at the end of each group, and the groups can be separated from each other by the insulation separation region. .. At this time, it can be controlled in group units. [0022] In the semiconductor memory, by writing or reading in parallel to a plurality of cell transistors belonging to different blocks, the writing or reading speed of the semiconductor memory as a whole can be increased. [0023] In a semiconductor memory including a plurality of cell transistors arranged in the row direction and a column direction, each of the cell transistors includes a control gate, and the cell transistors arranged in the row direction share a control gate and are cell transistors. In each of the above, the source / drain region is formed below a part of the channel region, the source / drain regions of the cell transistors adjacent to each other in the column direction are common, and the semiconductor memory is provided in the column direction. A conductor (eg, a metal wire) is included, and the conductor is connected to the source / drain region between the control gates adjacent to the column direction, and the resistance of the source / drain region in the column direction can be substantially reduced. [0024] At this time, it is difficult to secure an area for connection in a highly integrated semiconductor memory because the area between control gates adjacent to each other in the column direction is narrow, and the conductor is connected to the source / drain area. It can be difficult to do. At that time, if there is a margin for the connection in at least one of the row direction and the column direction, it is easy to secure the area in manufacturing. [0025] By the way, in a semiconductor memory including cell transistors arranged in the column direction and the row direction, the source / drain regions of each of the cell transistors are formed below a part of the channel region and are adjacent to each other in the column direction. The source / drain region of the cell transistor is common, and the cell transistors adjacent to each other in the row direction share the source / drain region between the cell transistors, and the middle portion of the source / drain region is the same as the source / drain region. A conductive high-concentration region is provided, and the high-concentration region can be common to a plurality of cell transistors arranged in the column direction. Since the resistance value is low in the high concentration region, the resistance in the column direction of the source / drain region can be substantially reduced by the high concentration region. [0026] BEST MODE FOR CARRYING OUT THE INVENTION Next, examples of the present invention will be described in detail with reference to the accompanying drawings. [0027] (1) Explanation of preliminary matters Before explaining the features of the present invention, first, the cell transistor, the circuit configuration, and the like of the semiconductor memory according to the present embodiment will be described. [0028] (Structure of cell transistor) FIG. 1 is a cross-sectional view of a cell transistor according to this embodiment. [0029] The cell transistor TC is formed on a p-type silicon substrate 12 which is a monoconductive semiconductor substrate, and a p-well 13 is formed on the p-type silicon substrate 12. A convex portion 13a is formed on the p-type silicon substrate 12. [0030] A plurality of convex portions 13a are provided on the p-type silicon substrate 12. The bit lines BL1 and BL2 are formed on the surface of the p-well 13 sandwiching the convex portion 13a. The bit wires BL1 and BL2 are formed by ion-implanting n-type impurities, which are opposite conductive types, at predetermined locations on the surface of the p-well 13. The bit lines BL1 and BL2 are integrated in the column direction, and a plurality of bit lines BL1 and BL2 are formed in the row direction. [0031] A gate insulating film 15c, which is the first insulating film, is formed on the top surface 13c of the convex portion 13a. Further, the convex portion 13a has a pair of side surfaces 13b and 13b facing each other, and an n-type region 17 is formed on the surface layer of each side surface 13b. The impurity concentration of the n-type regions 17 and 17 is selected to be 1/100 to 1/10000, preferably about 1/1000, as compared with the impurity concentration of the bit lines BL1 and BL2. [0032] In the figure, the tunnel insulating film 15a, which is the second insulating film, covers the side surfaces 13b and 13b and the bit wires BL1 and BL2. As will be described later, since the bit lines BL1 and BL2 also function as a source / drain area, the bit lines BL1 and BL2 are also referred to as source / drain areas below. [0033] Floating gates FG1 and FG2 are provided on each side surface side of the convex portion 13a. The floating gates FG1 and FG2 face the source / drain regions BL1 and BL2 and the side surfaces 13b and 13b, respectively, via the tunnel insulating film 15a. The interpoly insulating film 15b, which is the third insulating film, is formed on the surfaces of the floating gates FG and FG. The tunnel insulating film 15a, the interpoly insulating film 15b, and the gate insulating film 15c are all made of a silicon oxide film in this embodiment. [0034] The control gate CG faces the floating gates FG1 and FG2 via the interpoly insulating film 15b, and faces the top surface 13c via the gate insulating film 15c. In this control gate CG, a portion facing the floating gates FG1 and FG2 via the interpoly insulating film 15b and a portion facing the top surface 13c via the gate insulating film 15c are electrically and independently formed. However, these may be electrically controlled independently. [0035] Floating gates FG1, FG2, and control gate CG are all made of polysilicon. Of these, the control gate CG is integrated in the row direction, and a plurality of control gate CGs are formed in the column direction as described later, and each of them functions as a word line WL0, WL1, .... [0036] In this embodiment, the channel region is three-dimensionally formed on the surface layers of the side surfaces 13b, 13b and the top surface 13c of the convex portion 13a. Therefore, the height positions of the channel region and the source / drain regions BL1 and BL2 are different, and the source / drain region is located below a part of the channel region. This feature is not found in typical MOS transistors in which both the source / drain region and the channel region are formed on the substrate surface. [0037] FIG. 2 is a diagram schematically showing an equivalent circuit of this cell transistor TC, and shows various capacitances. The meaning of each capacity is as follows. C_CG... The opposite capacitance between the control gate CG and the top surface 13c of the convex portion 13a. C_CF1(C_CF2) The opposite capacitance between the control gate CG and the floating gate FG1 (FG2). C_FG1(C_FG2) ... The opposite capacitance between the floating gate FG1 (FG2) and the side surface 13b of the convex portion 13a. C_FS(C_FD) ... The opposite capacitance between the floating gate FG1 (FG2) and the source / drain region BL1 (BL2). [0038] (How to drive a cell transistor) Next, a method of driving the above-mentioned cell transistor TC will be described. [0039] i) Write operation First, the writing operation will be described with reference to FIG. FIG. 3 is a cross-sectional view showing a writing operation to the cell transistor TC. [0040] A pair of floating gates FG1 and FG2 are provided on both sides of the convex portion 13a, and according to this embodiment, electrons can be injected independently into the floating gates FG1 and FG2. [0041] For example, to inject electrons into the floating gate FG2 on the right side, write voltage V to the control gate CG as shown in Fig. 3._G, For example, 2.2V is applied. Then, the voltage V is applied to the source / drain region BL2 on the side where the electrons are injected._DD, For example, apply 6V. The substrate 12 and the source / drain region BL1 on the side where electrons are not injected are grounded. As a result, a potential difference for writing, that is, 6V is applied between the source / drain regions BL1 and BL2. [0042] According to this, since a positive potential is applied to the control gate CG, an inversion layer 13d is formed on the surface layer of the top surface 13c, and the n-type regions 17 and 17 are electrically connected to each other by the inversion layer 13d. Further, since the n-type regions 17 and 17 are in contact with the same conductive type, that is, the n-type source / drain regions BL1 and BL2, the source / drain regions BL1 and BL2 are electrically connected in the end. [0043] Therefore, the carrier (electron in this embodiment) flows along the paths indicated by arrows 50 and 52 in the figure. Pay particular attention to the electrons flowing on the top surface 13c. Seen from this electron, the floating gate FG2 on the right side is located in the direction of motion. Therefore, in order for the electrons to be injected into the floating gate FG2, it is not necessary to change the direction of movement of the electrons, so that the gate voltage for attracting the electrons to the floating gate FG2, that is, the writing voltage V_GCan be made smaller. [0044] Moreover, by providing the n-type regions 17 and 17 on the side surface 13b, the side surface 13b has a low resistance, and the voltage drop there is suppressed. Therefore, a high voltage slightly lower than the voltage between the source / drain regions BL1 and BL2 (6V in this embodiment) is applied to both ends of the top surface 13c, and this voltage causes electrons to accelerate vigorously on the top surface 13c. Then, electrons are efficiently injected into the floating gate FG2 as shown by arrow 52. In this way, the n-type regions 17 and 17 also have a write voltage of V._GContributes to reducing. [0045] In FIG. 3 above, electrons are injected only into the floating gate FG2 on the right side, but in order to inject electrons into the floating gate FG1 on the left side, the voltages in the source / drain regions BL1 and BL2 may be exchanged. [0046] Therefore, in the present invention, the four states shown in FIGS. 4 (a) to 4 (d) can be obtained. [0047] FIG. 4 (a) shows the (1, 1) logical state in which electrons are not injected into both floating gates FG1 and FG2. [0048] Figures 4 (b) and 4 (c) show the "(1, 0)" and "(0, 1)" logical states in which electrons are injected into only one of the floating gates FG1 and FG2. [0049] FIG. 4 (d) shows the (0, 0) logical state in which electrons are injected into both floating gates FG1 and FG2. To obtain this state, for example, electrons may be injected into the floating gate FG2 on the right side and then electrons may be injected into the floating gate FG1 on the left side. [0050] Thus, in the present invention, one cell transistor TC has two bits of data (1, 1) to (0,,. 0) can be written. [0051] In the present invention, two floating gates FG1 and FG2 are provided, and electrons exist independently in each of the floating gates FG1 and FG2. Therefore, even when cell reduction is attempted, which floating gate FG1 or FG2 has electrons. It can be clearly distinguished. [0052] ii) Read operation Next, the reading operation will be described with reference to FIGS. 5 (a) to 5 (b). To read the data, first, as shown in Fig. 5 (a), read voltage V to the control gate CG._G, For example, 2.2V is applied. Then, the voltage V in one of the source / drain regions BL2_DDFor example, 1.6V is applied to ground the other source / drain region BL1 and the substrate 12. As a result, a potential difference for reading, that is, 1.6 V is applied between the source / drain regions BL1 and BL2. [0053] Due to this potential distribution, the control gate CG becomes a positive potential, so that the inversion layer 13d is formed on the top surface of the convex portion 13a. Therefore, the first drain current I in the direction of the arrow in the figure_d1Flows. [0054] Then, as shown in FIG. 5 (b), the read voltage V_GThat is, 2.2V remains the same, and the voltages in the source / drain regions BL1 and BL2 are exchanged. In this way, the potential difference between the source / drain regions BL1 and BL2 is reversed, so the second drain current I in the direction of the arrow in the figure._d2Flows. [0055] In this embodiment, two types of drain currents I are performed by exchanging the voltages of the source / drain regions BL1 and BL2 as described above._d1, I_d2To measure. Drain current I_d1, I_d2The size of is different depending on each state of the quaternary state as described later. Therefore, a set of two types of drain current values (I)_d1, I_d2) And each state have a one-to-one correspondence, so that which state is stored can be read out. [0056] Next, the drain current values in each of the logical states (1, 1) to (0, 0) will be described. [0057] (a) (1, 0) logical state 6 (a) to 6 (b) are cross-sectional views when reading the (1, 0) logical state. In FIG. 6 (a), the voltage applied to each member is as shown in FIG. 5 (a) described above, and the drain current I is caused by this voltage._d1Flows. [0058] [0058] In the state of FIG. 6A, the potential of the floating gate FG2 on the right side drops due to the injection of electrons. However, the potential of the floating gate FG2 is the opposite capacitance C._CF2, C_FDThe control gate CG potential (2.2V in this example) and source / drain BL2 potential (1.6V in this example) are raised to the positive potential side. [0059] Therefore, in the end, since the potential drop of the floating gate FG2 is suppressed, the channel resistance in the vicinity of the floating gate FG2 is not so large. Therefore, the drain current I_d1The current value of is relatively large. [0060] In particular, when the n-type region 17 is provided as shown in the figure, the n-type region 17 is in contact with the source / drain region BL2, so that the potential of the n-type region 17 is almost the same as that of the source / drain region BL2. Therefore, the potential of the floating gate FG2 is the opposite capacitance C._FG2It is also pulled up to the source / drain BL side. Therefore, the channel resistance near the floating gate FG2 on the right side becomes smaller, and the drain current I_d1The current value of is even larger. [0061] On the other hand, in Fig. 6 (b), the voltage of the source / drain BL1 and BL2 is exchanged, and the drain current I_d2This is the case. In this case, the injected electrons lower the potential of the floating gate FG2 on the right side. Moreover, since the source / drain region BL2 on the right side is grounded, the potential of the floating gate FG2 is the capacitance C facing the source / drain region BL2._FDIs pulled down to the ground side. Therefore, since the potential of the floating gate FG2 is lower than that in the case of FIG. 6 (a), the channel resistance in the vicinity of the floating gate FG2 becomes large, and the drain current I_d2Is the first I_d1Is smaller than [0062] In particular, when the n-type region 17 is provided, the potential of the floating gate FG2 on the right side is the opposite capacitance C._FG2Also pulled down to the ground side by, drain current I_d2Becomes even smaller. [0063] Thus, the (1, 0) logical state is (I_d1, I_d2) = (Large, small) Can be identified by. This drain current I_d1, I_d2The magnitude of the above is determined by the sense amplifier described later in comparison with the reference current. [0064] (b) (0, 1) logical state In the "(0, 1)" state, electrons are injected into the floating gate FG1 on the left side, contrary to the above. Therefore, each drain current I_d1, I_d2The current value of is evaluated in the same way as in the discussion above. (I_d1, I_d2) = (Small, large) Will be. [0065] (c) (1, 1) logical state In the (1, 1) logical state, no electrons are injected into any of the floating gates FG1 and FG2. Therefore, the potentials of the floating gates FG1 and FG2 cannot be lowered by electrons, so I_d1, I_d2Both will be large. Also, since this state is symmetrical, I_d1And I_d2There is no difference between (I_d1, I_d2) = (Large, Large) Will be. [0066] (d) (0, 0) logical state The (0, 0) logical state is symmetrical because electrons are injected into both floating gates FG1 and FG2. Therefore, I_d1And I_d2There is no difference between (I_d1, I_d2) = (Small, small) Will be. [0067] iii) Erase operation Next, a method of erasing the electrons injected into the floating gates FG1 and FG2 will be described. To extract the stored electrons, a high potential V is applied to the control gate CG as shown in Fig. 7._GFor example, 12V is applied to ground the substrate 12 and the source / drain regions BL1 and BL2. Here, the potential difference between the control gate CG and the substrate 12 and the source / drain regions BL1 and BL2 can be set relatively. For example, 6V is set for the control gate CG and -6V is set for the source / drain regions BL1 and BL2. May be applied. [0068] According to this potential distribution, when viewed from the floating gate FG1 (FG2), the potential on the control gate CG side is high, so that the stored electrons are drawn out to the control gate CG via the interpoly insulating film 15b. Contrary to the above, it is also possible to set the substrate 12 side to a higher potential than the control gate CG and extract the stored electrons to the substrate 12 side. [0069] iv) When not selected The above i) to iii) are all cases where the cell transistor TC is selected. In actual operation, the cell transistor TC is not always selected and may be in a non-selected state. [0070] Even in the non-selected state, the voltage V for each operation is used to select another cell transistor TC, for example, for the bit line BL1._DDMay be applied. In this case, the floating gate FG1 of the non-selective cell transistor TC has a large facing capacitance C with the bit line BL1._FSIs attracted to the potential of the bit line BL1. Therefore, since the potential difference between the floating gate FG1 and the source / drain region BL1 becomes small, the tunnel insulating film 15a between them is not exposed to a high electric field. Therefore, it becomes difficult for the tunnel current to flow through the tunnel insulating film 15a, and deterioration of the tunnel insulating film 15a can be prevented. [0071] Here, in order to obtain the advantages of i) to iv) during driving, the facing capacitance C between the floating gate FG1 (FG2) and the source / drain region BL1 (BL2)_Fs(C_FDNote that) plays an important role. In this embodiment, by lining the floating gate FG1 (FG2) on the source / drain region BL1 (BL2), the distance between the floating gates FG1 to FG2 is narrowed to reduce the size of the device, and the facing capacity C_FD, C_FSMakes a lot of money and makes it easier to get the above benefits. The facing area between the floating gate FG1 (FG2) and the source / drain region BL1 (BL2) is not limited. The larger the facing area, the easier it is to obtain the above-mentioned advantages, but it is possible to obtain even a small facing area. [0072] (Circuit configuration) Next, the circuit configuration of the semiconductor memory according to this embodiment will be described. FIG. 8 is a circuit configuration diagram of the semiconductor memory according to this embodiment. In the figure, the cell transistor TC_{i, j}Represents the cell transistor in the i-row j column, and its structure and operation are as described above. And cell transistor TC_{i, j}Each of the banks (1 column) x (n row) bank BNK_jIt is divided into banks (j = 0,1,2, ...). Note that n in (n column) represents a predetermined natural number, and its value is not particularly limited. Also, Bank BNK_jIn j is the cell transistor TC belonging to that bank_{i, j}Represents the common column number of. [0073] Each bank BNK_j(j = 0,1,2, ...) is the selection transistor STE for selecting it_{i, j}, STO_{i, j}Is connected. Of these, the selected transistor STE_{i, j}Is an even bank BNK_j(j = 0,2,4 ...) It is for selection, and is also called an even bank selection transistor below. Also, STO_{i, j}Is an odd bank BNK_j(j = 1,3,5 ...) It is for selection, and is also called an odd bank selection transistor below. [0074] As shown in the figure, even bank selection transistor STE_{i, j}In each of these, one of the sources and drains is commonly connected every other column, and the virtual ground line VG is connected to the common connection nodes A, D, and E._i(i = 0,2,4 ...) is connected. Odd bank selection transistor STO_{i, j}The same applies to, but the common connection point is the even bank selection transistor STE._{i, j}It is off by one column from that of. [0075] The even-numbered bank selection transistor STE in this figure._{i-1, j}(j = 0,1,2,3 ...) selects an even bank in the i-1st bank counting in the column direction. And odd bank selection transistor STO_{i + 1, j}(j = 0,1,2,3 ...) selects the odd bank in the i + 1th bank counting in the column direction. [0076] Also, the virtual ground wire VG_i(i = 0,2,4, ...) is made of a metal such as aluminum to reduce its electrical resistance. On the other hand, bit line BL_i(i = 0,1,2 ...) consists of a diffusion layer whose electrical resistance is the virtual ground line VG_iMuch higher than that of. [0077] The circuit operation is as follows. In this circuit, instead of selecting a cell transistor by combining a word line and a bit line, first the even bank group BNK_j(i = 0,2,4 ...) and odd bank group BNK_jSelect one of the groups (i = 1,3,5 ...) and then that bank BNK_jOne of the cell transistors TC_{i, j}Select. [0078] For example, cell transistor TC_0、0Consider the case of selecting. Cell transistor TC_0、0Is an even bank BNK₀Belongs to. Therefore, first of all, even bank group BNK_jEven bank selection line SE to select (i = 0,2,4 ...)_iTo high level, each even bank selection transistor STE_{i, j}Turn on (j = 0,1,2 ...). [0079] Other selection lines (SE_i-1, SO_i, SO_{i + 1}) Is all low level, and all the transistors whose selection line is connected to the gate are turned off. [0080] [0080] According to the voltage distribution described above, the even bank selection transistor STE in the on state_{i, 0}, STE_{i, 1}Bit lines BL0 and BL1 are selected by, and bit lines BL0 and BL1 are virtual ground lines VG.₀, VG₂It will be electrically connected to. Other even banks BNK₂, BNK₄Similarly, the bit wire connected to is electrically connected to the virtual ground wire. In this way, first even bank group_j(i = 0,2,4 ...) is selected. [0081] Next, the target cell transistor TC_0、0In the case of read operation, the bit line BL0 connected to it is set to the ground level, and the voltage V is set to the bit line BL1._DD1.6V is applied as. And the word line WL₀Read voltage V_GApply 2.2V as. In addition, each bit line BL_iThe application of various voltages to (i = 1,2 ...) Is performed by the data line / ground line selector 302 via the bank selector 300. [0082] Due to these voltage values, the cell transistor TC, as described in FIG. 5 (a),_0,0First drain current I_d1Flows. This first drain current I_d1The current path of is the sense amplifier 304 data line / ground line selector 302 bank selector 300 virtual ground line VG.₂ Node D Node C Even bank selection transistor STE_{i, 1} Bit line BL1 Cell transistor TC_0,0 Bit line BL0 Even bank selection transistor STE_{i, 0} Node B Node A Virtual ground line VG₀ Bank selector 300 Data line / ground line selector 302. [0083] At this time, due to the function of the bank selector 300, BNK₀Even banks other than (BNK)₂, BNK₄Since the cell transistor in (, ...) is not selected, no drain current flows through the cell transistor. [0084] Next, the potential difference between the bit lines BL0 and BL1 is inverted, and the other voltage values are left as described above. In this way, as explained in FIG. 5 (b), the cell transistor TC_0,0Second drain current I_d2Flows. This second drain current I_d2The current path of the above is the first drain current I above._d1Is the opposite of that. [0085] As described above, cell transistor TC_0,01st drain current I_d1And the second drain current I_d2Is measured by a sense amplifier, and the cell transistor TC_0,0Which of the four-valued states "(1, 1)" to "(0, 0)" is stored is identified. [0086] According to this circuit configuration, the first drain current I_d1Does not always flow in the high resistance bit lines BL0 and BL1 consisting of the diffusion layer, but does not always flow in the target bank BNK.₀Virtual ground wire VG made of low resistance aluminum until it reaches₂Flowing inside, the target bank BNK₀After reaching, the bit line BL1 will flow. And cell transistor TC_0,0After flowing through, the first drain current I_d1Is a virtual ground line VG via bit line BL0₀Flow. [0087] In this way, the resistance is lower than when it always flows in the bit wires BL0 and BL1, so in this embodiment, the first drain current I_d1Can be read at high speed. Second drain current I_d2The same advantage can be obtained with. [0088] In the above, even bank BNK₀Cell transistor TC inside_0,0Was selected. On the other hand, odd bank group BNK_jCell transistor TC in (i = 1,3,5 ...)_{i, j}To select, odd bank selection line SO_iTo high level, each odd bank selection transistor STO_{i, j}Turn on (j = 0,1,2 ...). And other selection lines (SE_i, SE_i-1, SO_{i + 1}) Is all low level, and all the transistors whose selection line is connected to the gate are turned off. Other than this, it is the same as the case of selecting an even bank, so the odd bank will not be described further. [0089] The above-mentioned cell transistor selection method is also called a virtual grounding method. For details on this method, see Japanese Patent Application Laid-Open No. 3-179775. [0090] (2) Features of the present invention FIG. 9 is a notched cross-sectional view of a main part of the semiconductor memory according to the present embodiment. In FIG. 9, the same members as described above are given the same reference numbers. In the figure, the conductive plug 63 is embedded in an interlayer insulating film (not shown). Then, the virtual ground wire VG is placed on the interlayer insulating film.₄Is formed and the virtual ground line VG₄And the conductive plug 63 are electrically connected. The conductive plug 63 corresponds to node E in FIG. 8 and is an even bank selection transistor STE._{i, 3}And STE_{i, 4}It is electrically connected to the common source / drain connection point with. In addition, word line WL₀, WL₁Is a series of control gate CGs in FIG. 1 in the low direction. [0091] Cell transistor TC_0,1The channel region is formed on the side surface 13b and the top surface 13c, and the source / drain region BL2 is located below the channel region formed on the top surface 13c. On the other hand, even bank selection transistor STE_{i, 2}Is a known MOS transistor, and its source / drain region 50 and channel region 51 are located in substantially the same plane. [0092] As is clear from the figure, even bank selection transistor STE_{i, 2}Is the height position L of the surface of the silicon substrate 12 as in the conventional example.₁Rather than being formed at a lower height position L₂Is formed in. This height position L₂Is a cell transistor TC_0、1Approximately equal to the height position of the source / drain region BL2 of. [0093] Therefore, these two transistors STE_{i, 2}, TC_0、1Since the source / drain areas 50 and BL2 of the above are located in almost the same plane and their height positions are not different from each other as in the past, it is easy to connect the source / drain areas 50 and BL2 in the horizontal direction. It can be electrically connected to the common connection, and can overcome the technical difficulties of the common connection that have been seen in the past. [0094] (3) Manufacturing process Next, the method of manufacturing the semiconductor memory according to this embodiment will be described with reference to FIGS. 10 to 35. First, as shown in FIG. 10, a groove 12a for an insulation separation region (STI (Shallow Trench Isolation) in this embodiment) is formed on the p-type silicon substrate 12 by a known method. Then, for example, by using a CVD method (chemical vapor deposition method), an insulating material 10 such as a silicon oxide film is embedded in the groove 12a. Then, the surface of the substrate 12 is thermally oxidized to form a silicon oxide film 18. [0095] The p-type silicon substrate 12 has, for example, a boron concentration of about 4.0 × 10.¹⁸cm^-3P⁺Boron concentration is about 1.0 x 10 on the substrate¹⁵cm^-3The p-type epicital layer of. [0096] Next, as shown in FIG. 11, p-well 13 is formed on the p-type silicon substrate 12 by ion implantation. Ion implantation was performed 4 times, and the conditions for each time are as follows. [0097]<img file="JP4472934B2_D0001.tif" />Next, as shown in FIG. 12, the silicon oxide film 18 is etched and removed. Subsequently, as shown in FIG. 13, the surface of the substrate 12 is thermally oxidized again to form a gate insulating film 15c made of a silicon oxide film. The film thickness of the gate insulating film 15c is about 10 nm. [0098] Then, a silicon nitride film 25 (thickness is about 10 nm), a silicon oxide film 26 (thickness is 4 nm), and a silicon nitride film 27 (thickness is 50 nm) are formed on the gate insulating film 15c in this order. The function of each membrane will be clarified in a later process. All of these films are formed by a known CVD method. [0099] Next, as shown in FIG. 14, the photoresist 45 is applied onto the uppermost silicon nitride film 27. After coating, the photoresist 45 is patterned into strips by photolithography. Then, by using the photoresist 45 as an etching mask, the gate insulating film 15c, the silicon nitride film 25, the silicon oxide film 26, the silicon nitride film 27, the insulating material 10, and the p-well 13 are etched. [0100] As a result, the trench 28 is formed at the portion where the cell transistor is formed later (hereinafter referred to as the memory cell portion). The size of this trench is not limited, but in this embodiment, the depth is about 380 nm. The distance between adjacent trenches 28 is about 160 nm. [0101] On the other hand, at the portion where the selective transistor is formed later (hereinafter referred to as the selective transistor portion), the p-well 13 and the insulating material 10 are uniformly etched so as to appear on substantially the same surface. After this etching, the photoresist 45 is ashed and removed. [0102] Next, as shown in FIG. 15, a silicon oxide film 29 (thickness of about 20 nm) is formed on the entire exposed surface. The silicon oxide film 29 is formed by a CVD method. Subsequently, as shown in FIG. 16, the silicon oxide film 29 is anisotropically etched in the thickness direction, and the silicon oxide film 29 remains on the side surface of the trench 28. This etching is performed by, for example, RIE (Reactive Ion Etching). [0103] Next, as shown in FIG. 17, a photoresist 60 is formed in a band shape in the selective transistor portion, and arsenic is ion-implanted using the photoresist 60 as a mask. As a result, bit lines BL1 to BL4 are formed in the p-well 13. At the time of this ion implantation, a silicon oxide film 29 is formed on the side surface of the trench 28, so that arsenic is prevented from being implanted on the side surface. Further, since the convex portion 13a functions as a mask, each bit line BL1 to BL4 can be self-aligned at the bottom of the trench 28. [0104] The conditions for this ion implantation are as follows. [0105] Ion species: As (arsenic) Acceleration energy: 15 (KeV) Doze amount: 2.0 x 10¹⁴(cm^-2) Note that FIG. 18 is a diagram in which the photoresist 60 is represented by a dotted line in order to make it easier to see the planar shape of each bit line BL1 to BL4. [0106] Next, as shown in FIG. 19, the silicon oxide film 29 is etched to a thickness of about 10 nm. Since it is thin, the remaining silicon oxide film 29 is omitted in the figure. Next, as shown in FIG. 20, arsenic is ion-implanted into both side surfaces 13b of the convex portion 13a to form an n-type region 17. To implant the ions into the side surface 13b, the substrate 12 may be tilted with respect to the incident direction of the ions. In this embodiment, the normal n of the p-type silicon substrate 12₁, Ion incident direction n₀Tilt about +/- 20 ° with respect to. [0107] The conditions for this ion implantation are as follows. [0108] Ion species: As (arsenic) Acceleration energy: 10 (KeV) Dose amount: 5.0 × 10¹¹(cm^-2) Since the thinned silicon oxide film 29 (FIG. 18) remains on the side surface 13b during ion implantation, it is possible to prevent excessive arsenic injection into the side surface 13b. [0109] After this ion implantation is complete, the photoresist 60 is ashed and removed. [0110] By the way, the surface layer of the trench 28 is a part that becomes a channel of the device, and its property greatly affects the characteristics of the device. Therefore, it is necessary to prevent the surface of the trench 28 from being contaminated in various subsequent steps. [0111] In view of this point, in this embodiment, as shown in FIG. 21, the sacrificial silicon oxide film 31 is formed on the side surface and the bottom surface of the trench 28. The film thickness of the sacrificial silicon oxide film 31 is about 4 nm, which is formed by thermal oxidation. [0112] Since the surface of the trench 28 is covered and protected by this sacrificial silicon oxide film 31, it is prevented from being contaminated in a later process. Moreover, since the silicon oxide film 31 also functions to remove lattice defects on the surface layer of the trench 28, it is possible to prevent deterioration of device characteristics due to lattice defects. The sacrificial silicon oxide film 31 is also formed on the bit lines BL1 to BL4 of the portion of the selective transistor portion that is not covered with the photoresist 60. [0113] After that, the silicon nitride film 30 is formed on the entire exposed surface including the inside of the trench 28. The film thickness of the silicon nitride film 30 is about 60 nm, which is formed by the CVD method. Then, the photoresist 61 is formed in a band shape on the silicon nitride film 30 of the selective transistor portion. [0114] Next, as shown in FIG. 22, the silicon nitride film 30 is anisotropically etched in the thickness direction. As a result, in the trench 28, the elongated hole 30a is formed in the silicon nitride film 30. On the other hand, in the selective transistor section, the photoresist 61 serves as a mask, so that the shape of the photoresist 61 is transferred to the silicon nitride film 30. [0115] Subsequently, as shown in FIG. 23, the silicon nitride film 30 is used as an etching mask, and the sacrificial silicon oxide film 31 and a part of each bit line BL1 to BL4 are selectively etched. By this etching, recesses (dents) 32 (depth of about 10 nm) are formed in each bit BL1 to BL4. [0116] Next, as shown in FIG. 24, arsenic is ion-implanted into the bit wires BL1 to BL4 through the elongated holes 30a in order to reduce the resistance of the bit wires BL1 to BL4. The site 33 where arsenic was implanted by this ion implantation is in the high concentration region, that is, n.⁺It is a region, which reduces the resistance of the bit lines BL1 to BL4 in the column direction. The conditions for ion implantation are as follows. [0117] Ion species: As (arsenic) Acceleration energy: 30 (KeV) Doze amount: 3.0 x 10¹⁵(cm^-2) Then, as shown in FIG. 25, the silicon nitride film 30 is used as a mask, and the recess 32 is selectively thermally oxidized to form the selective oxide film 15d. In the selective transistor portion, the bit lines BL1 to BL4 in the portion not covered by the silicon nitride film 30 are also oxidized, and the selective oxide film 15d is formed there. [0118] After forming the selective oxide film 15d as described above, the photoresist 61 is first removed by ashing. Then, the silicon nitride films 27 and 30 are etched and removed. In this etching, the silicon oxide film 26 and the sacrificial silicon oxide film 31 function as an etching stopper. [0119] Next, the silicon oxide film 26 is etched and removed. This time, the silicon nitride film 25 functions as an etching stopper. This etching is performed to the extent that the silicon oxide film 26 is completely removed and the selective oxide film 15d remains. FIG. 26 shows a state after the above steps are completed. [0120] Next, as shown in FIG. 27, the bottom surface and the side surface of the trench 28 are thermally oxidized again to form a tunnel insulating film 15a having a film thickness of about 5 nm. Since the tunnel insulating film 15a has a great influence on the device operation, it is preferable to form the tunnel insulating film 15a so as to have a good film quality. [0121] In this embodiment, a plasma oxidation method is used to form a high-quality tunnel insulating film 15a. In the plasma oxidation method, a microwave-excited high-density plasma apparatus using a radial line slot antenna is used. Then, in the device, krypton (Kr) and oxygen (O)₂) And introduce a mixed gas. [0122] Krypton excited by microwaves is oxygen (O₂) And a large amount of atomic oxygen O^*To generate. Atomic oxygen O^*Easily penetrates the surface of the trench 28. Therefore, all the plane orientations are uniformly oxidized at substantially the same oxidation rate without depending on the plane orientation. Therefore, as shown in the circle in the figure, the tunnel insulating film 15a can be formed in the corner portion of the trench 28 with a uniform film thickness. For details on the above plasma oxidation method, refer to "48th Joint Lecture Meeting on Applied Physics, Proceedings 29p-YC-4" and Japanese Patent Application Laid-Open No. 2001-160555. The tunnel insulating film 15a is also formed on the bit lines BL1 to BL4 of the portion of the selective transistor portion that is not covered with the selective oxide film 15d. [0123] Next, as shown in FIG. 28, the polysilicon film 34 is formed on the tunnel insulating film 15a and the silicon nitride film 25. The polysilicon film 34 is pre-doped with phosphorus (P) in-situ. The film thickness of the polysilicon film 34 is about 50 nm. [0124] Next, as shown in FIG. 29, the polysilicon film 34 is anisotropically etched in the thickness direction. As a result, the polysilicon film 34 on the silicon nitride film 25 (see FIG. 27) is removed, while the polysilicon film 34 remains on the tunnel insulating film 15a on the side surface of the trench 28. The remaining polysilicon film 34 becomes floating gates FG1 and FG2. After forming the floating gates FG1 and FG2, the silicon nitride film 25 (see FIG. 28) is etched and removed. [0125] By providing the silicon nitride film 25 on the gate insulating film 15c, it is possible to prevent the gate insulating film 15c from being damaged in various processes until the floating gates FG1 and FG2 are formed. [0126] Then, as shown in FIG. 30, the entire exposed surface is oxidized by the plasma oxidation method described above. As a result, the silicon under the gate insulating film 15c is oxidized, so that the gate insulating film 15c becomes a thick film. At the same time, the surfaces of the floating gates FG1 and FG2 are also oxidized to form an interpoly insulating film 15b. The film thickness of the interpoly insulating film 15b is about 8 nm. [0127] Since the floating gates FG1 and FG2 are made of polysilicon, a large number of crystal grains having various plane orientations are formed on the surface thereof. Even if the plane orientations are different as described above, according to the above-mentioned plasma oxidation method, a silicon oxide film can be uniformly formed without depending on the plane orientation. Therefore, it is possible to prevent the film thickness of the interpoly insulating film 15b from being locally thinned, and there is no inconvenience that the insulating characteristics at the thin portion are deteriorated. This advantage can also be obtained when polysilicon is doped with phosphorus (P). [0128] Subsequently, as shown in FIG. 31, a polysilicon film 37 is first formed on the entire surface, a tungsten silicide film 36 is formed on the polysilicon film 37, and a cap film 38 made of a silicon oxide film is further formed on the tungsten silicide film 36. Then, by patterning these laminated films, the word line WL₀, WL₁And even bank selection line SE_i, SE_i-1To form. The tungsten silicide film 36 described above functions to reduce the resistance of each of these wires. [0129] Next, as shown in FIG. 32, the photoresist 39 is applied to the entire surface. After application, word line WL by photolithography₀, WL₁Leave the photoresist 39 on the top and on the selected transistor section. [0130] Subsequently, as shown in FIG. 33, photoresist 39 was used as an etching mask and the word line WL₀, WL₁The interpoly insulating film 15b of the part not covered with is etched and removed. During this etching, the word line WL₀, WL₁The gate insulating film 15c between them is also slightly etched. In addition, change the etchant, word line WL₀, WL₁The floating gates FG1 and FG2 that are not covered with are etched and removed. [0131] Next, as shown in FIG. 34, the device separation region 40 is formed. The site where the element separation region 40 should be formed is the word line WL.₀, WL₁The side surface 13b and the top surface 13c of the convex portion 13a not covered with. Side surface 13b and top surface 13c are word lines WL₀, WL₁Below is the channel region, but due to this element separation region 40, the adjacent word line WL₀, WL₁Channels are electrically separated. [0132] To form the device separation region 40, the photoresist 39 is used as a mask and boron is ion-implanted. When implanting ions, the substrate 12 is tilted with respect to the incident direction of ions so that the element separation region 40 is formed on the side surface 13b of the convex portion 13a. In this embodiment, the normal n of the p-type silicon substrate 12₁, Ion incident direction n₀Tilt about +/- 20 ° with respect to. [0133] The conditions for this ion implantation are as follows. [0134] Ion species: BF₂Acceleration energy: 20 (KeV) Doze amount: 1.0 x 10¹³(cm^-2) Next, as shown in FIG. 35, the photoresist 39 is ashed and removed. [0135] Then even bank selection line SE_i, SE_i-1A low concentration of arsenic is ion-implanted into the p-wells 13 on both sides of the. And even bank selection line SE_i, SE_i-1A sidewall insulating film 62 made of, for example, a silicon oxide film is formed on the side surface of the above by a known method. Next, by using this sidewall insulating film 62 as a mask and ion-implanting a high concentration of arsenic, an even-numbered bank selection transistor STE having a source / drain region 50 having an LDD (Lightly Doped Drain) structure is provided._{i, j}To form. Even bank selection transistor STE_{i, j}In, the tunnel insulating film 15a functions as a gate insulating film. [0136] After that, as shown in FIG. 9, an interlayer insulating film such as a silicon oxide film (not shown) is formed as a whole, and a contact hole is formed between the interlayer insulating film and the selective oxide film 15d to form a contact hole. Embed the conductive plug 63. The conductive plug 63 has, for example, a two-layer structure of TiN (titanium nitride) and W (tungsten). Then, by forming an aluminum film on the above interlayer insulating film and patterning it, a virtual ground wire VG electrically connected to the conductive plug 63₄To form. As described above, the semiconductor memory according to this embodiment is completed. [0137] Next, another embodiment of the present invention will be described. In the following description, the same reference numerals will be used for those having the same functions as the components of the above-described embodiment, and the description thereof will be partially omitted. [0138] Generally, a semiconductor memory includes a drive transistor for driving a cell transistor. In this embodiment, although the drive transistor is at a different height position from the selection transistors STE and STO, the drive transistor and the selection transistors STE and STO are simultaneously formed by the same process. [0139] Further, a protective insulating film is provided at the end of the convex portion in the column direction, and the protective insulating film is a transistor having an LDD structure included in the semiconductor memory. It is formed at the same time as the STO sidewall insulating film by the same process. [0140] Further, a plurality of cell transistors TC arranged in the row direction are divided into a plurality of blocks, and are connected to a control gate CG in a plurality of element separation regions STIa, which will be described later, and a plurality of element separation regions STIa provided between adjacent blocks. A metal wire (hereinafter referred to as a first metal wire) provided in the row direction is provided. As a result, it is possible to write or read in parallel to a plurality of cell transistors TC belonging to different blocks. [0141] In this embodiment, similarly to the above-described embodiment, the cell transistors share the channel region in each bank, the element separation region STIb is provided at the end of each bank, and the banks are provided with the element separation region STIb. Is separated. The same applies to the fact that a virtual grounding method is adopted, and a metal wire (hereinafter referred to as a second wire) connected to a source / drain region (that is, a bit wire) in a plurality of connection regions provided for a bank. (Also called a metal wire), that is, a virtual ground wire VG is provided in the column direction. [0142] In this embodiment, as a third metal wire, a metal wire 306 provided in the column direction (see FIG. 37) is included, and this metal wire is used as a source / drain between control gates adjacent to the column direction. Connected to the region, it substantially reduces the columnar resistance of the source and drain regions along with the virtual ground wire. The third metal wire is provided independently for each bank. [0143] An example of arranging these three types of metal wires will be described with reference to FIGS. 36 and 37. FIG. 36 is a perspective view of a semiconductor memory using the virtual grounding method according to the present embodiment. The circuit configuration in this figure is the same as that shown in FIG. In this figure, in addition to the transistor TC constituting each bank BANK shown in FIG. 8, the element separation region STIa and the first metal wire 38 connected to the control gate CG in the element separation region STIa are also shown. [0144] Although the element separation region STIb is shown at the end of the convex portion in the column direction in FIG. 36, the protective insulating film provided at the end of the element separation region STIb is shown in FIG. 36 to prevent complication of the drawing. Not shown in. Selective transistor STE, Similarly, the sidewall insulating film of STO is not shown. Details of these will be described later. [0145] The reason for providing the element separation region STIa is as follows. In order to achieve an increase in write / read speed, it is preferable to divide a plurality of transistor TCs into a plurality of blocks 212, and among the blocks 212 arranged in the row direction, blocks are formed between adjacent blocks 212. An element separation region STIa for separating 212 from each other is provided. Each block 212 contains, for example, 32 or 64 transistors TC in the row direction, and the source and drain BLs of the transistors TC contained in one block 212 are connected in series in the row direction, and of a plurality of transistors TC The control gate CG is connected in common. [0146] The reason for providing the element separation region STIa will be further described. When the source and drain BLs of multiple transistor TCs are connected in series, write to multiple transistor TCs among these transistor TCs at the same time. case of vomiting, with respect to the transistor TC which is not a writing target However, there is a possibility that writing will be performed. The element separation region STIa separates the blocks into a plurality of blocks 212, and within one block 212, the plurality of transistors TCs belonging to different blocks 212 do not have to be written to the plurality of transistors TC at the same time. This problem does not occur if writing is performed at the same time. Moreover, the writing speed can be maintained at a high speed. Further, even at the time of reading, if reading is performed simultaneously only for a plurality of transistor TCs belonging to different blocks 212, it is possible to prevent the problem that a current flows through the transistor TCs that are not read. [0147] In this semiconductor memory, the element separation region STIa is defined as STI (Shallow Trench Isolation). If so, the occupied area of the separated area can be reduced, which is effective for miniaturization of the semiconductor memory. [0148] Further, this semiconductor memory includes a conductor (for example, an aluminum wire) 38 for connecting the control gate CGs of a plurality of transistors TC in common, and a contact portion 54 for connecting the aluminum wire 38 and the control gate CG. The position of the contact portion 54 can be above the element separation region STIa. The conductor 38 can reduce the resistance of the control gate CG. In the column direction, an element separation region STIb for separating each bank BANK is provided. The element separation region STIb is also STI. The figure also shows the connection point 218 where the virtual ground wire VG is connected to the bit wire BL. [0149] FIG. 37 specifically shows three types of metal wires VG, 38, 306. These metal wires VG, 38, 306 is an Al line or the like. In this embodiment, the second metal wire VG is placed in the layer below the first metal wire 38, and the third metal wire 306 is placed in the layer below it. That is, the height from the substrate has a magnitude relationship of the height of the first metal wire 38 308&gt; the height of the second metal wire VG 310&gt; the height of the third metal wire 306 313. [0150] The first metal wire 38 is connected to the control gate CG at both ends of the block 212 by the plug 54, and the second metal wire VG is selected by the plug 312 in the selected transistor STE, Connected to STO. The third metal wire 306 is connected to the source / drain region BL by the plug 314. The plug 314 is provided between the control gate CG. In FIG. 37, the third metal wire 306 is shown only on the bit wire BL at the end of the block 212, but is actually provided on the bit wire BL other than the end of the block 212. [0151] In this embodiment, similarly to the above-described embodiment, the cell transistors adjacent to each other in the row direction share the source / drain region between the cell transistors, and the source / drain region is located in the middle of the source / drain region. The same conductive type high-concentration region as is provided, and the high-concentration region is common to a plurality of cell transistors arranged in the column direction. [0152] Next, the method of manufacturing the semiconductor memory of this embodiment will be described with reference to FIGS. 38 to 47. In this embodiment, the manufacturing process of the cell transistor can be performed in compatibility with the manufacturing process of the CMOS transistor which is the drive transistor. Therefore, in the following, not only the cell transistor but also the manufacturing process of the CMOS transistor will be described together. In the figure, the CMOS transistor section CM refers to a portion where a CMOS transistor is formed. The cell transistor portion CT refers to a portion where the cell transistor is formed. Further, in FIGS. 38 to 47 below, the manufacturing process of the element separation region STIb is also shown. [0153] FIG. 38 (a) and FIG. 38 (b) each consist of three cross-sectional views. The first cross-sectional view from the left is a cross-sectional view of the cell transistor portion CT in the low direction. The second cross-sectional view from the left is for showing a method of manufacturing the element separation region STIb in the column direction, and is a cross-sectional view of the element separation region STIb in the column direction as seen in the AA direction in FIG. 36. The cross-sectional view at the right end is for showing the manufacturing method of the bank selection transistors STO, STE, and the bank selection transistor STO, seen in the BB direction in FIG. It is sectional drawing in the column direction of STE. Similarly, in FIGS. 39 to 57 below, cross-sectional views of the element separation region STIb and the bank selection transistors STO and STE in the column direction are also shown. [0154] First, as shown in FIG. 38 (a), one of the conductive semiconductor substrates is p.^-Molded silicon substrate (Boron concentration 1.0 × 10 in this example¹⁶cm^-3) Prepare 12. A silicon thermal oxide film 18 is formed on the surface thereof, and a silicon nitride film 19 is formed on the silicon thermal oxide film 18. From FIG. 38 (a) to FIG. 40 (b), the element separation region STIa in the row direction and the column direction, This is a process for forming STIb. [0155] Next, the resist 100 is applied to develop and expose the resist 100 to form a pattern. The silicon nitride film 19 is patterned by this pattern to form openings 19a to 19d (FIG. 38 (b)). The opening 19a is formed in the element separation region between the CMOS transistors in the CMOS transistor section CM. The opening 19b is formed in the element separation region of the CMOS transistor portion CM and the cell transistor portion CT. The opening 19c is formed in the element separation region STIa in the row direction in the cell transistor portion CT. The opening 19d is formed in the element separation region STIb in the column direction in the cell transistor portion CT. [0156] Next, the resist 100 is removed, and the silicon oxide film 18 and the silicon substrate 12 are etched using the patterned silicon nitride film 19 as a mask to form openings 102a to 102d (FIG. 39 (a)). Silicon oxide 104 for device separation is deposited by the CVD method to a thickness of, for example, 400 nm to fill the openings 102a to 102d (Fig. 39 (b)). [0157] Subsequently, the deposited silicon oxide 104 is polished and flattened by a CMP (Chemical Mechanical Polishing) method (Fig. 40 (a)). Polishing is stopped in the middle of the nitride film 19. After that, the nitride film 19 is removed and the surface is flattened (Fig. 40 (b)). [0158] Next, photoresist 20 is applied to the entire surface. By exposing and developing the photoresist 20, an opening 20a is formed in the CMOS transistor section CM. Then, using the photoresist 20 as a mask, arsenic and phosphorus are ion-implanted to form an n-well 21 under the opening 20a (Fig. 41 (a)). Arsenic and phosphorus are injected separately, arsenic is injected deep and phosphorus is injected shallow. [0159] After forming the n-wells 21, the photoresist 20 is removed. Apply a new photoresist 22 to the entire surface. The photoresist 22 is exposed and developed to form an opening 22a in the CMOS transistor section CM. Then, using the photoresist 22 as a mask, BF2 (boron trifluoride) and boron are ion-implanted to form a p-well 23 under the opening 22a (Fig. 41 (b)). BF2 and boron are injected separately, boron is injected deep and BF2 is injected shallow. After forming the p-well 23, the photoresist 22 is removed. [0160] Next, photoresist 24 is applied to the entire surface. An opening 24a is formed in the photoresist 24 by exposure and development. The opening 24a is formed in the cell transistor portion CT. Using this photoresist 24 as a mask, BF2 and boron are ion-implanted, and p layer 106 is in the shallow position and p is in the deep position.⁺Layer 108 is formed (Fig. 42 (a)). BF2 and boron are injected separately, boron is injected deep and BF2 is injected shallow. The conditions for each ion implantation are as follows, for example. [0161] Ion species: BF2 Acceleration energy: 35 (KeV) Dose amount: 4.0 × 10¹¹ (cm^-2) Ion species: B (boron) Acceleration energy: 20 (KeV) Doze amount: 2.0 x 10¹² (cm^-2) By ion implantation, p layer 106 at a shallow position and p at a deep position⁺Layer 108 is formed. The p layer 106 serves as a channel for the cell transistor, and p⁺Layer 108 prevents punch-through of cell transistors. Next, the resist 24 is removed, and the silicon oxide film 18 is etched and removed (FIG. 42 (b)). [0162] Then, the surface of the substrate 12 is thermally oxidized again to form the gate insulating film 15c. The film thickness of the gate insulating film 15c is about 3 nm. On the gate insulating film 15c, in order, a gate insulating film (silicon nitride film) 15e having a film thickness of about 20 nm, a silicon oxide film 110a having a film thickness of about 20 nm, and a silicon nitride film 110b having a film thickness of about 20 nm. A silicon oxide film 110c having a film thickness of about 4 nm, a silicon nitride film 110d having a film thickness of about 100 nm, and a silicon oxide film 110e having a film thickness of about 50 nm are deposited (Fig. 43 (a)). The function of each membrane will be clarified in a later step. All of these films are formed by a known CVD method, that is, a chemical vapor deposition method. [0163] Next, a photoresist (not shown) is applied on the uppermost silicon oxide film 110e. After coating, the photoresist is exposed and developed to form a band-shaped opening (not shown). The silicon oxide film 110e is etched using this opening as an etching mask. By etching, band-shaped openings 45a and 45b are formed in the silicon oxide film 110e (Fig. 43 (b)). The opening 45a is opened in the region where the source / drain region of the cell transistor is formed. The opening 45b is opened in the region where the element separation region STIb and the bank selection transistors STO and STE are formed. [0164] After that, the resist is removed, and the silicon nitride film 110d is removed by RIE (Reactive Ion Etching), which is anisotropic etching, using the openings 45a and 45b as masks. Subsequently, the silicon oxide films 110e and 110c are etched, the silicon nitride film 110b is removed by RIE, and the silicon oxide film 110a is etched. Furthermore, the silicon nitride film 15e is removed by RIE, and the silicon layers P layer 106 and P are removed.⁺Trench 28, 28, ... Are dug in layer 108 by RIE (Fig. 44 (a)). The size of the trenches 28, 28, ... Is not limited, but in this embodiment, the depth is about 40 nm. Also, adjacent trenches 28, 28, The interval between ... (that is, the width of the convex portion 13a) is about 130 nm. [0165] Subsequently, a silicon oxide film 29 having a film thickness of about 20 nm is formed on the entire exposed surface (Fig. 44 (b)). The silicon oxide film 29 is formed by a CVD method. [0166] Next, the silicon oxide film 29 is anisotropically etched in the thickness direction. This etching is done by RIE. As a result, the silicon oxide film 29 is removed, leaving behind what is formed on the side surface 13b of the convex portion 13a. Next, thermal oxidation is performed to form a silicon oxide film 114 having a film thickness of 3 nm at the bottom of the trench 28 (Fig. 45 (a)). [0167] After that, the resist 112 is applied, the resist 112 is exposed and developed using a mask, and the resist 112 is removed leaving the CMOS transistor portion CM and the resist 112 in the rightmost STI portion. Using this resist 112 as a mask, arsenic is divided into two parts and ion-implanted to the bottom of trenches 28, 28, ...⁺Form a layer (Fig. 45 (b)). N⁺The layers are bit lines BL1, BL2, ... The ion implantation amount is, for example, as follows. [0168] First time: Acceleration energy: 10 (KeV) Doze amount: 1.5 x 10¹⁴ (cm^-2) Second time: Acceleration energy: 30 (KeV) Doze amount: 1.0 x 10¹⁴ (cm^-2) At the time of ion implantation, since the silicon oxide film 29 is formed on the side surface 13b, arsenic is not implanted on the side surface 13b. Further, since the convex portion 13a functions as a mask, each bit line BL1, BL2, ... Can be self-aligned at the bottom of the trench 28. [0169] After the ion implantation is completed, the silicon oxide film 29 remaining on the side surface 13b and the silicon oxide film 114 remaining on the bottom surface are etched and removed (FIG. 46 (a)). [0170] Next, arsenic is ion-implanted into both side surfaces 13b, 13b of the convex portion 13a to form n-type regions 17, 17, ... Which are regions having opposite conductive types (FIG. 46 (b)). To implant the ions into the side surface 13b, the substrate 12 may be tilted with respect to the incident direction of the ions. In this embodiment, the normal n of the p-type silicon substrate 12₁, Ion incident direction n₀Tilt about +/- 20 ° with respect to. The conditions for this ion implantation are as follows. [0171] Ion species: As (arsenic) Acceleration energy: 15 (KeV) Doze amount: 2.0 x 10¹²(cm^-2) By the way, the surface layer of trenches 28, 28, ... Is a part that becomes a channel of the device, and its property greatly affects the characteristics of the device. Therefore, it is necessary to prevent the surfaces of the trenches 28, 28, ... From being contaminated in the various subsequent steps. In view of this point, in this embodiment, the sacrificial silicon oxide film 31 is formed on the side surface and the bottom surface of the trenches 28, 28, ... (Fig. 47 (a)). The film thickness of the sacrificial silicon oxide film 31 is about 4 nm, and is formed by thermal oxidation. [0172] Since the surfaces of the trenches 28, 28, ... Are covered and protected by the sacrificial silicon oxide film 31, it is prevented from being contaminated in a later process. Moreover, since the silicon oxide film 31 also functions to remove lattice defects on the surface layers of trenches 28, 28, ..., It is possible to prevent deterioration of device characteristics due to lattice defects. [0173] After that, the silicon nitride film 30 used as the mask film was applied to the trenches 28, 28, ... Formed on the entire exposed surface including the inside (Fig. 47 (b)). The film thickness of the silicon nitride film 30 is about 60 nm, and the film is formed by the CVD method. [0174] Subsequently, as shown in FIG. 48A, the resist 116 is applied to remove the resist 116 in the source / drain region of the cell transistor portion CT. Using this resist 116 as a mask, the silicon nitride film 30 is anisotropically etched in the thickness direction to form a long hole (that is, an opening) 30a in the column direction. Note that the slot 30a is narrower than the trench 28. After forming the elongated hole 30a, the silicon nitride film 30 is used as an etching mask to selectively etch the sacrificial silicon oxide film 31 and a part of each bit wire BL1, BL2, .... By this etching, recesses 32, which are dents, are formed in each bit line BL1, BL2, .... Its depth is about 10 nm. [0175] Then, in order to reduce the resistance of the bit wires BL1, BL2, ..., Arsenic is ion-implanted into the bit wires BL1, BL2, ... Through the elongated hole 30a. In the figure, the site where arsenic was implanted by this ion implantation (n)⁺Region) 33 is shown. The conditions for ion implantation are as follows. [0176] Ion species: As (arsenic) Acceleration energy: 40 (KeV) Dose amount: 5.0 × 10¹⁵(cm^-2) Next, the resist 116 is removed, and the recesses 32, 32, ... Are selectively thermally oxidized using the silicon nitride film 30 as a mask to form the selective oxide films 234, 234, ... (FIG. 48). (b)). The reason why the oxide film 234 is expanded and thickened by thermal oxidation is that the pressure resistance of the oxide film 234 needs to be increased because the control gate CG and the source / drain region BL are closest to each other in this portion. [0177] After forming the selective oxide films 234, 234, ..., The silicon nitride films 30, 110d are etched and removed (Fig. 49 (a)). In this etching, the silicon oxide film 110c and the sacrificial silicon oxide film 31 function as an etching stopper. [0178] The silicon oxide film 110c and the sacrificial silicon oxide film 31 are then etched and removed (FIG. 49 (b)). This time, the silicon nitride film 110b functions as an etching stopper. This etching is performed to the extent that the silicon oxide film 110c and the sacrificial silicon oxide film 31 are completely removed and the selective oxide films 234, 234, ... Are left. [0179] Then trench 28, 28, A tunnel insulating film (plasma oxide film) 15a having a film thickness of about 3 nm and a tunnel insulating film (plasma nitride film) 15d having a film thickness of about 3 nm are formed on the bottom surface and the side surface of ... (Fig. 50). (a)). Since the tunnel insulating films 15a and 15d have a great influence on the device operation, it is preferable to form the tunnel insulating films 15a and 15d so as to have a good film quality. [0180] In this embodiment, in order to form high-quality tunnel insulating films 15a and 15d, the tunnel insulating film is a laminated film composed of a plasma oxide film 15a and a plasma nitride film 15d formed on the plasma oxide film 15a. The plasma oxide film 15a is formed by oxidizing the bottom surface and the side surface of the trenches 28, 28, ... According to the plasma oxidation method. In the plasma oxidation method, for example, a microwave-pumped high-density plasma apparatus using a radial line slot antenna is used. [0181] In the plasma oxidation method using the device, krypton (Kr) and oxygen (O) are contained in the device.₂) And introduce a mixed gas. The introduced krypton is excited by microwaves emitted by the radial line slot antenna. Krypton excited by microwaves is oxygen (O₂) And a large amount of atomic oxygen O^*To generate. Atomic oxygen O^*Easily penetrates into the surface layer of trenches 28, 28, ..., regardless of the plane orientation of the silicon. As a result, all plane orientations are uniformly oxidized at approximately the same oxidation rate. After forming the oxide film, the introduction of the mixed gas is stopped, the radiation of microwaves is also stopped, and the gas in the apparatus is exhausted. [0182] Next, the plasma nitride film 15d is formed on the plasma oxide film 15a. The plasma nitride film 15d is formed, for example, by using a microwave-pumped high-density plasma apparatus using a radial line slot antenna, similarly to the plasma oxide film 15a. [0183] In the plasma nitriding method using the device, krypton (Kr) and ammonia (NH) are contained in the device.₃) And introduce a mixed gas. The introduced krypton is excited by microwaves emitted by the radial line slot antenna. Krypton excited by microwaves is ammonia (NH₃) Collision with ammonia radical NH^*To generate. Ammonia radical NH^*Formes a plasma nitride film on the surface layer of trenches 28, 28, ... Then, the plasma nitride film is formed without depending on the plane orientation of silicon. [0184] After the tunnel insulating film 15d is formed as described above, the polysilicon film 34, which is a conductive film, is formed on the tunnel insulating film 15d and the silicon nitride film 110b (FIG. 50 (b)). The polysilicon film 34 is pre-doped with phosphorus (P) by in-situ doping. The reason for doping phosphorus is that since the polysilicon film 34 is used as floating gates FG1 and FG2, it is preferable to reduce the resistance by doping phosphorus. The film thickness of the polysilicon film 34 is about 60 nm. [0185] Next, the polysilicon film 34 is anisotropically etched in the thickness direction. As a result, the polysilicon film 34 on the silicon nitride film 110b is removed, and the polysilicon film 34 remains on the tunnel insulating film 15d on the side surfaces of the trenches 28, 28, .... Trench 28, 28, Etching is performed so that the upper end of the polysilicon film 34 on the side surface of ... Is higher than the top surface of the convex portion 13a. The remaining polysilicon film 34 becomes the floating gates FG1 and FG2. [0186] Floating gate FG1, After forming FG2, the silicon nitride film 110b and the silicon oxide film 110a are etched and removed (Fig. 51 (a)). Attention should be paid to the roles played by the silicon nitride film 110b and the silicon oxide film 110a (see FIG. 50 (b)). The silicon nitride film 110b and the silicon oxide film 110a were first formed on the gate insulating film 15e in the process of FIG. 43 (a). Then, until the step of FIG. 50 (b), the gate insulating film 15e was covered and protected by the silicon nitride film 110b and the silicon oxide film 110a. [0187] The gate insulating film 15e has a great influence on the operation of the device. Therefore, if the gate insulating film 15e is protected by the silicon nitride film 110b and the silicon oxide film 110a as described above, the gate insulating film 15e is subjected to various processes such as ion implantation, etching, and film formation of different types of films. It is possible to prevent the film quality from deteriorating. As a result, it is possible to prevent deterioration of the operating characteristics of the device. [0188] The entire exposed surface is then oxidized by the plasma oxidation method described above. As a result, the floating gate FG1, The surface of FG2 is oxidized to form an interpoly insulating film 15b. At this time, a small amount of nitrogen is mixed into the oxide film to form a nitride film. This is because the nitride film makes the film denser and prevents boron from escaping. Further, an oxide film 108 is formed on the element separation region STIb in the column direction and the bank selection transistors STO and STE (Fig. 51 (b)). The film thickness of the interpoly insulating film 15b is about 12 nm. [0189] Subsequently, photoresist 35 is applied to the entire surface. After coating, the photoresist 35 is exposed and developed to form an opening 35a on the CM of the CMOS transistor portion. Further, this photoresist 35 is used as an etching mask to etch the gate insulating films 15e and 15c on the CMOS transistor section CM. This exposes the surfaces of the n-well 21 and p-well 23 of the CMOS transistor (Fig. 52 (a)). Gate insulating film 15e, The reason for etching 15c is that the gate insulating film 15c has been damaged by the previous treatment. [0190] Subsequently, after removing the resist 35, plasma oxidation is performed to form a gate oxide film 120 having a film thickness of about 3 nm on the surfaces of the n-well 21 and the p-well 23 of the CMOS transistor (Fig. 52 (b)). .. At this time, carbon C in the resist 35, which may remain on the surface of the interpoly film 15b due to plasma oxidation, is CO.²There is also an advantage that the resist 35 is removed. [0191] Next, polysilicon CG is deposited by the CVD method, and the surface of the deposited polysilicon CG is polished and flattened by the CMP method to form tongue ten silicide (WSi), on which the silicon oxide film 36 is deposited ( Figure 53 (a)). In this figure, the polysilicon CG and the tongue ten silicide on the polysilicon CG are indicated by the same reference code CG. By this step, a plurality of control gate CGs integrated in the row direction are formed. At the same time, the gate electrode 41 is formed on the p-well 23 and the n-well 21 on the CMOS transistor section. The gate electrode 41 is mainly composed of a polysilicon film 37, and its resistance is reduced by the WSi film. Since the WSi film is also formed on the control gate CG, the resistance of the control gate CG is also reduced. [0192] The reason for depositing the silicon oxide film 36 on the polysilicon CG is to pattern the polysilicon CG using the silicon oxide film 36 as a mask. This is because the mask of the silicon oxide film 36 is more suitable than the patterning of polysilicon CG using a resist as a mask. Patterning of polysilicon CG is performed in the next step. [0193] That is, the resist 127 is applied, the resist 127 is exposed and developed for patterning, and the silicon oxide film 36 is patterned using the patterned resist 127. Polysilicon CG is patterned using the patterned silicon oxide film 36 (Fig. 53 (b)). As shown in this figure, the polysilicon CG, that is, the part where the control gate CG is removed, is the part 129a where the source / drain region of the CMOS transistor part CM is formed, and the STIb in the column direction of the cell transistor part CT is formed. Part 129b, bank selection transistor STO, The portion 129c where the source / drain region of the STE is formed, and the region 40 (see FIG. 34) between the control gate CGs continuous in the row direction. [0194] After this, interpoly insulation is formed on the side surface of the convex portion 13a in the element separation region STIb, which is a portion not covered by the control gate CG, and the side surface of the convex portion 13a in the element separation region 40 shown in FIG. 34. Remove film 138 and polysilicon 140. Therefore, after removing the resist 127, a mask 130 is formed, and the mask 130 is used to remove the interpoly insulating film 138 and polysilicon 140 at these sites. The etchant is changed when removing the interpoly insulating film 138 and when removing the polysilicon 140. In this way, the floating gates FG1 and FG2 in the part not covered by the control gate CG are removed. By this process, the adjacent control gate CG, CG, During ..., the tunnel insulating film 15d is exposed. Then, after removing the polysilicon 140, an oxidation treatment is performed to round the corner portion 132 of the exposed silicon nitride film 15d to form an oxide at the corner portion 132 (FIG. 54 (a)). [0195] In FIGS. 38 to 47 other than FIG. 54 (a), the region 134 shown in this figure shows a cross section in the row direction (cross section DD in FIG. 36) of the region in which the source / drain of the cell transistor portion CT is formed. However, only in this figure, the cross section in the row direction of the element separation region 40 (cross section CC in FIG. 36) is shown. [0196] After that, the steps of forming the NMOS123 and PMOS124 of the CMOS transistor section CM, and the bank selection transistors STO and STE are performed. As shown below, the MEMS123 of the CMOS transistor section CM and the bank selection transistor STO, STEs are formed simultaneously by the same process. Further, the insulating protective film 318 at the end of the convex portion and the sidewall insulating film 136b of the NMOS 123 and the MIMO 124 are also formed at the same time by the same process. [0197] First, the resist 130 is removed, the resist 138 is applied, and the resist 138 is exposed and developed to open the parts of the oligonucleotide 138, the MIMO 123 and the bank selection transistors STO and STE. Then, LDD (Lightly Doped Drain) 136c is formed by ion-implanting arsenic into these places. At this time, the silicon oxide film 36 also functions as a mask (Fig. 54 (b)). [0198] Similarly, the LDD 136c is formed in the MIMO 124, and then the sidewall insulating film 136b made of the silicon nitride film is formed in the convex portion 13a of the MIMO 124, the NMOS 123, the bank selection transistors STO, STE, and the device separation region STIb. (Fig. 55 (a)). [0199] Subsequently, the resist 140 is applied, the resist 140 is exposed and developed, and the MIMO 123 of the resist 140 and the bank selection transistor STO, Open the STE site. Then, the source / drain region 136a is formed by ion-implanting arsenic into these locations. At this time, the silicon oxide film 36 also functions as a mask (Fig. 55 (b)). [0200] Similarly, a source / drain region 136a is formed in the MIMO 124. In this way, the NMOS123 and PMOS124 of the CMOS transistor section CM, and the bank selection transistors STO and STE are formed. Next, BPSG film (Boro-Phospho Silicate Glass film) 36 is deposited. The BPSG film is for flattening the surface for Al rays. After depositing the BPSG film, the surface irregularities can be alleviated by heat-treating the BPSG film at a high temperature. After the heat treatment, the BPSG film is flattened by the CMP method (Fig. 56 (a)). [0201] Subsequently, a hole is made in the silicon oxide film 36 using a mask (not shown), tungsten plugs (contacts) 54, 320, and 322 are embedded in the holes, and after embedding, the surface is flattened by the CMP method ((not shown). Figure 56 (b)). Tungsten plug 54, 320, 322 is for connecting the control gate CG and the Al film 38 in the cell transistor section CT, and connecting the source / drain and the Al film 324, 326 in the CMOS transistor section CM and the bank selection transistors STO and STE. Al films 38, 324 and 326 are formed in the following steps. [0202] In the final step, the Al film 38, 324, 326 is first deposited, and the Al film 38, 324, 326 formed by the vapor deposition is deposited. Pattern 326. Next, a silicon oxide film 56 is deposited, and a protective film 58 is formed on the silicon oxide film 56 (Fig. 57). Although the second metal wire VG and the third metal wire 306 do not appear in this figure, the second metal wire VG and the third metal wire 306 are formed before forming the protective film 58. In this way, the semiconductor memory is completed. [0203] According to this embodiment, although the drive transistor is at a different height position from the selected transistor, it is formed at the same time by the same process, so that the number of steps can be reduced. [0204] Further, since the protective insulating film at the end of the convex portion in the column direction is formed at the same time as the sidewall insulating film of the transistor having the LDD structure included in the semiconductor memory by the same process, the number of steps can be reduced. [0205] The cell transistor is divided into a plurality of blocks in the row direction, and the control gate is connected to a metal wire provided in the row direction in the STI region provided between the adjacent blocks. In this way, the low resistance of the control gate can be substantially reduced. [0206] Further, the cell transistor shares a channel region in each bank, and the banks are separated from each other by the element separation region STIb provided at the end of each bank. This makes it possible to control the cell transistor for each bank. [0207] By the way, the resistance in the column direction of the source / drain region can be substantially reduced by the virtual ground line VG connected to the source / drain region in the connection region 218 provided for the bank. [0208] In the semiconductor memory, by writing or reading in parallel to a plurality of cell transistors belonging to different blocks, the writing or reading speed of the semiconductor memory as a whole can be increased. [0209] The third metal wire provided in the column direction is connected to the source / drain region between the control gates adjacent to the column direction, so that the resistance in the column direction of the source / drain region can be substantially reduced. it can. [0210] By the way, cell transistors adjacent to each other in the row direction share a source / drain region between the cell transistors, and a conductive high concentration region 33 which is the same as the source / drain region is provided in the middle portion of the source / drain region. The high concentration region 33 is common to a plurality of cell transistors arranged in the column direction. Since the resistance value is low in the high concentration region, the resistance in the column direction of the source / drain region can be substantially reduced by the high concentration region. [0211] In the above examples, the shapes of the floating gates FG1 and FG2 are fan-shaped, but the present invention is not limited to this, and can be applied to cell transistors having floating gates FG1 and FG2 other than the fan shape. Such a cell transistor will be described below. [0212] FIG. 58 shows the floating gate FG1, which is different from the cell transistor of FIG. It is explanatory drawing which shows the structure of one Example of the semiconductor memory which the shape of FG2 is different. The semiconductor memory of this embodiment is a flash memory 200. The flash memory 200 includes a p-type semiconductor substrate provided with a convex portion 13a having a pair of opposite side surfaces 13b, a gate insulating film 15c formed on the top surface 13c of the convex portion 13a, and a semiconductor sandwiching the convex portion 13a. It includes a pair of n-type source / drain regions BL1 and BL2 formed on the surface of the substrate, and a tunnel insulating film 15a that covers the side surface 13b of the convex portion 13a and the source / drain regions BL1 and BL2. Further, the flash memory 200 is provided with a pair of floating gates FG1 and FG2 provided on each side surface 13b side of the convex portion 13a and facing the side surface 13b and the source / drain regions BL1 and BL2 via the tunnel insulating film 15a, and each floating gate. Each floating gate FG1, via the interpoly insulating film 15b formed on the gates FG1 and FG2 and the interpoly insulating film 15b. It has a control gate CG that faces the FG2 and faces the top surface 13c of the convex portion 13a via the gate insulating film 15c. [0213] At least a part of the control gate CG faces the floating gates FG1 and FG2 via the interpoly insulating film 15b, and faces the top surface 13c via the gate insulating film 15c. In this control gate CG, a portion facing the floating gates FG1 and FG2 via the interpoly insulating film 15b and a portion facing the top surface 13c via the gate insulating film 15c are electrically and independently formed. However, these may be electrically controlled independently. [0214] The cross-sectional shape of each floating gate FG1 and FG2 perpendicular to the column direction is substantially rectangular in this embodiment, and one side of the rectangle faces the side surface of the convex portion 13a via the tunnel insulating film 15a and is rectangular. One side is the source / drain area BL1, It faces BL2 via the tunnel insulating film 15a. These two sides are adjacent sides, and one side of the rectangle faces the control gate CG via the interpoly insulating film 15b. In the following, this transistor is referred to as an S (Square) type memory because the shapes of the floating gates FG1 and FG2 are substantially quadrangular. [0215] In this embodiment, the interpoly insulating film 15b is a film in which the silicon oxide film 202a, the silicon nitride film 202b, and the silicon oxide film 202c are arranged in this order, and the gate insulating film 15c is these films 202a, 202b. , 202c, and the silicon oxide film 204a and the silicon nitride film 204b formed under the silicon oxide film 204a are included. [0216] The silicon oxide film 204a can be formed by the same manufacturing method as a conventionally known gate insulating film (thermal oxide film). As for the interpoly insulating film 15b, the films 202a, 202b and 202c can be manufactured by the prior art. Further, after flattening the surfaces of the floating gates FG1 and FG2 facing the control gate CG by the CMP method, the interpoly insulating film 15b, that is, the film 202a, 202b and 202c are formed to form a film having excellent pressure resistance. That is, for example, polysilicon used for the floating gates FG1 and FG2 has a rough surface shape, and if an interpoly insulating film 15b is formed on the polysilicon, there is a risk that the pressure resistance of the interpoly insulating film 15b cannot be guaranteed. Is large. Therefore, by flattening the surfaces of the floating gates FG1 and FG2 in contact with the interpoly insulating film 15b by the CMP method and then forming the interpoly insulating film 15b, a film having excellent pressure resistance can be formed. Since these individual manufacturing process techniques are known, the flash memory 200 of this embodiment has an advantage that there is little manufacturing risk. [0217] Since the floating gates FG1 and FG2 of this embodiment are quadrangular, there is an advantage that the coupling ratio CR is smaller than that of the floating gates FG1 and FG2 shown in FIG. Here, the coupling ratio CR is the opposite capacitance C between the control gate CG and the floating gate FG1 (FG2)._CF1(C_CF2) / (Floating gate FG1 (FG2) and facing capacitance C between the side surface 13b of the convex portion 13a_FG1(C_FG2) + Floating gate FG1 (FG2) and source / drain area BL1 (BL2) facing capacitance C_FS(C_FD)), That is, C_CF1/ (C_FG1+ C_FS), Or C_CF2/ (C_FG2+ C_FD). [0218] In the case of the transistor shown in FIG. 1, the coupling ratio CR is about 0.37, but in the case of this embodiment, the coupling ratio CR is 0.35 or less, and about 0.32 can be realized. The reason why the bond ratio CR is small is that the shapes of the floating gates FG1 and FG2 shown in FIG. 1 are close to a fan shape with a central angle of 90 degrees, but in the case of this embodiment, they are quadrangular, and this embodiment. This is because the area where the floating gates FG1 and FG2 face the control gate CG is smaller. [0219] A sufficiently small capacity ratio is preferable in terms of characteristics when reading data from the memory. This is because the coupling between the floating gates FG1 and FG2 and the source / drain regions BL1 and BL2 is strong at this time, so that the potentials of the floating gates FG1 and FG2 are sufficiently affected by the potentials of the source / drain regions BL1 and BL2. Because it receives. As a result, the current window becomes large and the data read speed becomes high. [0220] As a method of reducing the capacitance ratio CR, the film thickness of the tunnel insulating film is made thinner than the film thickness of the interpoly insulating film. Floating gate FG1, The area where the FG2 faces the control gate CG may be made as small as possible compared to the area where the source / drain areas BL1 and BL2 face each other. In order to reduce the area, for example, there is a method of changing the shape of the floating gates FG1 and FG2 into a trapezoid in which the area facing the control gate CG is small and the area facing the source / drain areas BL1 and BL2 is large. [0221] Regarding the relationship between capacitance ratio CR and erasure, when the charge is removed from the floating gates FG1 and FG2 to the control gate CG, the smaller the capacitance ratio CR, the greater the potential difference between the source / drain regions BL1 and BL2 and the control gate CG. It can be small. This is because a potential difference is likely to occur between the floating gates FG1 and FG2 and the control gate CG. [0222] Conversely, when removing charges from the floating gates FG1 and FG2 to the source / drain regions BL1 and BL2, if the capacitance ratio CR is too small, the potential difference between the source / drain regions BL1 and BL2 and the control gate CG will increase. There must be. Floating gate FG1, This is because a potential difference is unlikely to occur between FG2 and the source / drain regions BL1 and BL2. [0223] By the way, in the semiconductor memory of the present embodiment, the plurality of transistors are arranged in the direction connecting the source / drain regions BL1 and BL2, and one of the plurality of adjacent transistors, the floating gate FG1, and the other floating. Between the gate FG2 and the control gate CG and the source / drain area BL1, An insulating film 15f that electrically separates the BL2 from the BL2 is provided. The reason for providing this is as follows. [0224] In the transistor of FIG. 1, the control gate CG and the bit line BL2 face each other in the A portion between the cell transistors TC and TC adjacent in the row direction. Therefore, in part A, it is conceivable that a leak current flows between the control gate CG and the bit line BL2 during various operations. [0225] If this point is a concern, as shown in Fig. 1, a fourth insulating film, the selective oxide film 234, is provided by connecting it to the tunnel insulating film 15a, and the thickness thereof is made thicker than the tunnel insulating film 15a. Then it is good. In this way, the above-mentioned leak current can be prevented depending on the thickness of the selective oxide film 234. In the example of Fig. 1, control gate CG and bit line BL1, A fourth insulating film is formed by selective oxidation to prevent leakage current from BL2. [0226] In the S-type memory, the floating gates are separated by etching to form floating gates so as to be adjacent to each other, and then an insulator is filled in the separation space between these floating gates to form an insulating film 15f, and the insulating film 15f is formed on the floating gates. In addition, the control gate CG was formed. When an insulator is buried between the control gate CG and the bit wires BL1 and BL2 in this way, the floating gates FG1 and FG2 face the control gate CG only in the portion via the interpoly insulating film 15b. [0227] Writing, reading, and erasing the transistor of this embodiment are performed in the same manner as the transistor of FIG. It is preferable that the erasing is performed from the floating gates FG1 and FG2 to the source / drain regions BL1 and BL2. Table 1 shows an example of the voltage setting values of the source / drain areas BL1 and BL2 and the control gate CG during writing, reading, and erasing. [0228] [table 1]<img file="JP4472934B2_D0002.tif" />[0229] Next, another cell transistor having floating gates FG1 and FG2 other than the fan shape will be described. FIG. 59 is an explanatory diagram showing the configuration of this cell transistor. This is the flash memory 206. The flash memory 206 includes a p-type semiconductor substrate provided with a convex portion 13a having a pair of opposite side surfaces 13b, a gate insulating film 15c formed on the top surface 13c of the convex portion 13a, and a semiconductor sandwiching the convex portion 13a. It includes a pair of n-type source / drain regions BL1 and BL2 formed on the surface of the substrate, and a tunnel insulating film 15a that covers the side surface 13b of the convex portion 13a and the source / drain regions BL1 and BL2. Further, the flash memory 206 is provided with a pair of floating gates FG1 and FG2 that are provided on each side surface 13b side of the convex portion 13a and face the side surface 13b and the source / drain regions BL1 and BL2 via the tunnel insulating film 15a, and each floating gate. Each floating gate FG1, via the interpoly insulating film 15b formed on the gates FG1 and FG2 and the interpoly insulating film 15b. It has a control gate CG that faces the FG2 and faces the top surface 13c of the convex portion 13a via the gate insulating film 15c. [0230] Similar to the example of FIG. 58, this control gate CG also has a portion facing the floating gates FG1 and FG2 via the interpoly insulating film 15b and a portion facing the top surface 13c via the gate insulating film 15c. May be formed electrically independently, and these may be electrically controlled independently. [0231] The cross-sectional shape of each floating gate FG1 and FG2 perpendicular to the column direction is such that the area of the surface 208 of the floating gates FG1 and FG2 facing the control gate CG via the interpoly insulating film 15b is the area of the surface 208 of the floating gates FG1 and FG2 via the tunnel insulating film 15a. It is smaller than the area of the surface of the floating gates FG1 and FG2 facing the source / drain regions BL1 and BL2. Among such cross-sectional shapes, this embodiment is particularly L-shaped, with the L-shaped side portion facing the side surface 13b of the convex portion 13a via the tunnel insulating film 15a, and the L-shaped bottom portion. Source / drain region BL1, via the tunnel insulating film 15a Facing BL2. Further, the top of the L-shaped side portion faces the control gate CG via the interpoly insulating film 15b. In the following, this transistor is referred to as an L-shaped memory because the shapes of the floating gates FG1 and FG2 are substantially L-shaped. [0232] In this embodiment, the interpoly insulating film 15b is a silicon oxide film produced by a plasma oxidation method, and the gate insulating film 15c is a silicon oxide film 210a formed under the film 15b and silicon. Nitride film 210b<u style="single">And</u>Including. The tunnel insulating film 15a is also a silicon oxide film obtained by the plasma oxidation method. [0233] By the plasma oxidation method, a uniform silicon oxide film can be formed regardless of the direction of the surface. That is, a silicon oxide film having a thickness substantially equal to that of the (100) plane and the (111) plane is formed. This is preferable when simultaneously forming the tunnel insulating film 15a including the horizontal plane and the vertical plane. In addition, the oxide film produced by the plasma oxidation method represents the resistance of the oxide film to time breakdown (TDDB)._BDHas the advantage of being high. It also has the advantage of low SILC (Stress Induced Leakage Current), which indicates resistance to dielectric breakdown. [0234] In the example shown in FIG. 59, similarly to the embodiment shown in FIG. 58 above, the surfaces of the floating gates FG1 and FG2 facing the control gate CG are flattened by the CMP method, and then the interpoly insulating film 15b, that is, the film.<u style="single">210c</u>To form a film having excellent pressure resistance. That is, for example, polysilicon used for the floating gates FG1 and FG2 has a rough surface shape, and if an interpoly insulating film 15b is formed on the polysilicon, there is a risk that the pressure resistance of the interpoly insulating film 15b cannot be guaranteed. Is large. Therefore, by flattening the surfaces of the floating gates FG1 and FG2 in contact with the interpoly insulating film 15b by the CMP method and then forming the interpoly insulating film 15b, a film having excellent pressure resistance can be formed. Since the CMP method is a known manufacturing process technique, it has an advantage that there is little manufacturing risk. [0235] Since the floating gates FG1 and FG2 of this embodiment are L-shaped, there is an advantage that the coupling ratio CR described above is smaller than that of the floating gates FG1 and FG2 shown in FIGS. 1 and 58. [0236] In the case of the transistor shown in FIG. 1, the coupling ratio CR is about 0.37, and in the case of the S-type memory shown in FIG. 58, it is about 0.32, but in the case of this embodiment, the coupling ratio CR is 0.20 or less. About 0.17 can be fully realized. The reason why the bond ratio CR is small is that the floating gate FG1, This is because the shape of the FG2 is L-shaped in the case of this embodiment, and the area of the surface 208 on which the floating gates FG1 and FG2 face the control gate CG is smaller in this embodiment. [0237] When the capacity ratio is sufficiently small, as described above, it is preferable in terms of characteristics when reading data from the memory. That is, the smaller the capacitance ratio, the larger the current window, and as a result, the faster the data read speed. In this embodiment, it is easy to reduce the capacitance ratio as compared with the transistor of FIG. 1 and FIG. 58, and the data read speed can be easily increased as compared with the case of the transistor of FIG. 1 and FIG. it can. [0238] Regarding erasure, since the capacitance ratio CR is small in this embodiment, the floating gate FG1, can be erased only by applying a relatively small voltage for the reason described above. Charges can be removed from the FG2 to the control gate CG. [0239] In this embodiment as well, as in the example of FIG. 58 described above, the floating gates are separated by etching to form floating gates so as to be adjacent to each other, and then an insulating material is filled in the separation space between these floating gates. , An insulating film 15f can be formed, and a control gate CG can be formed on the insulating film 15f. When an insulator is buried between the control gate CG and the bit wires BL1 and BL2 in this way, the floating gates FG1 and FG2 face the control gate CG only in the portion via the interpoly insulating film 15b. [0240] Further, if the area filled with the insulating film 15f is increased, the lower side portion of the L-shaped floating gate portion is substantially removed, and the floating gates FG1 and FG2 can be substantially formed into an I-shape. In this way, the opposite capacitance C of the floating gates FG1 and FG2 with respect to the bit lines BL1 and BL2_FS, C_FDHowever, it is possible to further integrate the memory while maintaining the effect in this embodiment. [0241] Writing, reading, and erasing the transistor of this embodiment are performed in the same manner as the transistor of FIG. It is preferable that the erasing is performed from the floating gates FG1 and FG2 to the control gate CG. Table 2 shows an example of the voltage setting values of the source / drain areas BL1 and BL2 and the control gate CG during writing, reading, and erasing. [0242] [Table 2]<img file="JP4472934B2_D0003.tif" />[0243] Common to the examples shown in FIGS. 58 and 59, the surfaces of the floating gates FG1 and FG2 facing the interpoly insulating film 15b are flattened by the CMP method, and then the interpoly insulating film 15b is formed to withstand the pressure. The point of forming a film with excellent properties and the adjacent floating gate FG1, The feature is that the separation space between FG2 is filled with an insulating material to form an insulating film 15f, and a control gate CG is formed on the insulating film 15f. [0244] Although the plurality of examples have been described in detail above, the present invention is not limited to the above examples. The present invention can be appropriately modified within a range that does not deviate from the gist thereof. For example, although the semiconductor memory has been described above, the present invention can be applied to semiconductor devices other than the semiconductor memory. Further, in the above, the p-type is used as the monoconductive type and the n-type is used as the counter-conductive type. Instead, the n-type may be used as the monoconductive type and the p-type may be used as the counterconductive type. .. [0245] [Effect of the invention] As described above, according to the present invention, the source / drain regions of the first transistor and the second transistor are located in substantially the same plane, and their height positions are not different as in the conventional case, so that they are the same. The common connection can be easily made in the plane, and the technical difficulty of the common connection that has been seen in the past can be overcome. [0246] Further, since the drive transistor is formed at the same time by the same process even though it is at a different height position from the selection transistor, the number of steps can be reduced. [0247] Since the protective insulating film at the end of the convex portion in the column direction is formed at the same time as the sidewall insulating film of the transistor having the LDD structure included in the semiconductor memory by the same process, the number of steps can be reduced. [0248] The cell transistor is divided into a plurality of blocks in the row direction, and in the insulation separation region provided between the adjacent blocks, the conductor provided in the row direction is connected to the control gate, so that the control gate is in the row direction. The resistance can be substantially reduced. [0249] Further, the cell transistor shares a channel region in each bank, and the banks are separated from each other by the STIb provided at the end of each bank. This makes it possible to control the cell transistor for each bank. [0250] By the way, the resistance in the column direction of the source / drain region can be substantially reduced by the virtual ground line VG provided in the column direction connecting to the source / drain region in the connection region 218 provided for the bank. [0251] In the semiconductor memory, by writing or reading in parallel to a plurality of cell transistors belonging to different blocks, the writing or reading speed of the semiconductor memory as a whole can be increased. [0252] The third conductor provided in the column direction is connected to the source / drain region between the control gates adjacent to the column direction, and the resistance in the column direction of the source / drain region can be substantially reduced. .. [Simple explanation of drawings] FIG. 1 is a cross-sectional view of a cell transistor according to an embodiment of the present invention. FIG. 2 is a diagram schematically showing an equivalent circuit of a cell transistor according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing a writing operation to a cell transistor according to an embodiment of the present invention. FIG. 4 is a cross-sectional view showing four states obtained by the cell transistor according to the embodiment of the present invention. FIG. 5 is a cross-sectional view showing a reading operation of a cell transistor according to an embodiment of the present invention. FIG. 6 shows, in the cell transistor according to the embodiment of the present invention, (1, 0) is a cross-sectional view when reading out the state. FIG. 7 is a cross-sectional view showing an erasing operation of a cell transistor according to an embodiment of the present invention. FIG. 8 is a circuit configuration diagram of a semiconductor memory according to an embodiment of the present invention. FIG. 9 is a notched cross-sectional view of a main part of the semiconductor memory according to the embodiment of the present invention. FIG. 10 is a cross-sectional view (No. 1) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 11 is a cross-sectional view (No. 2) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 12 is a cross-sectional view (No. 3) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 13 is a cross-sectional view (No. 4) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 14 is a cross-sectional view (No. 5) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 15 is a cross-sectional view (No. 6) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 16 is a cross-sectional view (No. 7) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 17 is a cross-sectional view (No. 8) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 18 is a cross-sectional view (No. 9) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 19 is a cross-sectional view (No. 10) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 20 is a cross-sectional view (No. 11) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 21 is a cross-sectional view (No. 12) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 22 is a cross-sectional view (No. 13) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 23 is a cross-sectional view (No. 14) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 24 is a cross-sectional view (No. 15) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 25 is a cross-sectional view (No. 16) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 26 is a cross-sectional view (No. 17) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 27 is a cross-sectional view (No. 18) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 28 is a cross-sectional view (No. 19) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 29 is a cross-sectional view (No. 20) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 30 is a cross-sectional view (No. 21) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 31 is a cross-sectional view (No. 22) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 32 is a cross-sectional view (No. 23) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 33 is a cross-sectional view (No. 24) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 34 is a cross-sectional view (No. 25) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 35 is a cross-sectional view (No. 26) showing a method of manufacturing a semiconductor memory according to an embodiment of the present invention. FIG. 36 is a perspective view of a semiconductor memory according to another embodiment of the present invention. FIG. 37 is a perspective view showing three types of metal wires according to the embodiment of FIG. 36. 38 is a cross-sectional view (No. 1) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. 39 is a cross-sectional view (No. 2) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. 40 is a cross-sectional view (No. 3) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. 41 is a cross-sectional view (No. 4) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. 42 is a cross-sectional view (No. 5) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. FIG. 43 is a cross-sectional view (No. 6) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. 44 is a cross-sectional view (No. 7) showing a method of manufacturing the semiconductor memory of FIG. 36. 45 is a cross-sectional view (No. 8) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. FIG. 46 is a cross-sectional view (No. 9) showing a method of manufacturing the semiconductor memory of FIG. 36. 47 is a cross-sectional view (No. 10) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. FIG. 48 is a cross-sectional view (No. 11) showing a method of manufacturing the semiconductor memory of FIG. 36. 49 is a cross-sectional view (No. 12) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. 50 is a cross-sectional view (No. 13) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. 51 is a cross-sectional view (No. 14) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. 52 is a cross-sectional view (No. 15) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. FIG. 53 is a cross-sectional view (No. 16) showing a method of manufacturing the semiconductor memory of FIG. 36. 54 is a cross-sectional view (No. 17) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. FIG. 55 is a cross-sectional view (No. 18) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. 56 is a cross-sectional view (No. 19) showing a method of manufacturing the semiconductor memory of FIG. 36. 57 is a cross-sectional view (No. 20) showing a method of manufacturing the semiconductor memory of FIG. 36. FIG. FIG. 58 is a cross-sectional view of an S-type memory. FIG. 59 is a cross-sectional view of an L-shaped memory. [Explanation of symbols] 12 p-type silicon substrate (single conductive semiconductor substrate) 13 p well 13a convex part 13b Side of convex part 13c Convex top surface 15a Tunnel insulating film (second insulating film) 15b Interpoly insulating film (third insulating film) 15c Gate insulating film (first insulating film) 15d selective oxide film 17 n-type area 18, 26, 29 Silicon oxide film 25, 27, 30 Silicon nitride film 30a Silicon nitride film slot 28 trench 31 Sacrificial Silicon Oxide Film 32 recess 33 n⁺region 34, 37 polysilicon film 36 Tungsten Silicide Membrane 38 Cap membrane 39, 45, 60, 61 photoresist 40 element separation area 50 Source / Drain Area 51 channel area 62 sidewall insulating film 63 Conductive plug FG1, FG2 floating gate WL₀, WL₁~ WL_n-1, WL_n Word line BL0 ~ BL4 bit line BNK₀~ BNK₃ bank STE_{i-1, 0}~ STE_{i-1, 4}, STE_{i, 0}~ STE_{i, 4} Even bank selection transistor STO_{i-1, 0}~ STO_{i-1, 4}, STO_{i, 0}~ STO_{i, 4} Odd bank selection transistor SE_i-1, SE_i Even bank selection line SO_i-1, SO_i Odd bank selection line TC, TC_{i, j} Cell transistor VG₀, VG₂, VG₄ Virtual ground wire