Manufacturing methods of laminate and semiconductor device

[0001] [Technical field to which the invention belongs] The present invention is manufactured using the Metalorganic Vapourous Growth Method (MOCVD).<u style="single">Product</u>The present invention relates to a semiconductor device having a layered body. [0002] [Conventional technology] High Electron Mobility Transistors (HEMTs, hereinafter referred to as HEMTs) that utilize two-dimensional electron gas (2DEG) quantized at the heterojunction interface of heterogeneous compound semiconductor layers have high-speed and high-frequency operating characteristics. Since it has excellent low noise characteristics, it is currently used in high output devices such as microwave devices. In particular, the GaN channel layer and n-type Al_xGa_1-xGallium nitride (GaN) -based HEMTs (more specifically, GaN / AlGaN-based HEMTs) that have heterojunctions with the N (0 <x <1) electron supply layer exhibit a variety of excellent electrical properties. Currently, research is being actively conducted. [0003] By the way, when such a compound semiconductor layer is epitaxially grown on a substrate to form a heterojunction, the metal-organic chemical vapor deposition (MOCVD, hereinafter referred to as MOCVD) is widely used. .. The MOCVD method is a film forming technique for forming a desired crystal layer by sequentially supplying a predetermined raw material gas onto a substrate and epitaxially growing it under a predetermined high temperature. [0004] [Non-Patent Document 1] S.keller, TF.Wu, N.Ziang, JJXu, BpKeller, P.Denbaars, UKMishra, IEEE Transaction on Electron Devices, vol.48, 552 (2001) "Gallium Nitride Based High Power Heterojunction Field Effect Transisitor: Process Development and Present Status at UCSB" [0005] [Problems to be Solved by the Invention] However, there are the following problems when forming a film using the MOCVD method. [0006] By the MOCVD method, on a substrate, for example, a GaN layer and Al_xGa_1-xIn some cases, N (0 <x <1) layers are sequentially crystal-grown to form a laminate. At this time, in the cooling (lowering temperature) step after crystal growth, an undesired internal stress due to the difference in the coefficient of thermal expansion (linear expansion coefficient) from that of the GaN layer is applied to the AlGaN layer whose surface is exposed. [0007] As a result, the inventor of this application found that Al was flat (smooth) immediately after crystal growth._xGa_1-xIt has been confirmed by the image by the atomic force microscope (Atomic Force Microscopy: AFM, hereinafter referred to as AFM) shown in FIG. 11 that the surface of the N layer exhibits a cracked structure at room temperature after cooling. Figure 11 shows Al cooled with the surface exposed._xGa_1-xThis is an AFM image when scanning (scanning speed: about 1.2 Hz) is performed on a region of 1 μm in length and 1 μm in width in the N layer. The white region shown in (a) in the figure is a reference plane (contact surface with the AFM probe), and the black region shown in (c) is a concave region having a depth of about 10 nm from the reference plane. The gray region shown in (b) is a concave region having a shallower depth (<10 nm) than the black region (c). As shown in Figure 11, Al_xGa_1-xA plurality of concave regions are formed on the surface of the N layer, and the surface state is extremely rough. More specifically, it has been confirmed that these cracks have a depth of about 3 nm to 7 nm and a width of about 10 nm to 30 nm. [0008] Therefore, for example, like GaN-based HEMT, Al_xGa_1-xIn the case of a configuration in which a gate electrode is provided on the N layer, Al_xGa_1-xSince the contact surface between the N layer and the gate electrode becomes uneven, normal FET operation is impaired, and it is not possible to accurately evaluate the electrical characteristics of the device. [0009] In addition, due to the unevenness of the contact surface, Al_xGa_1-xSince the adhesion between the N layer and the gate electrode is weakened, the gate electrode may fall off. [0010] Therefore, according to Non-Patent Document 1 described above, Al by the MOCVD method_xGa_1-xCrystal growth of N layer, ammonia (NH₃) By using low flow rate of gas and high surface movement speed of metal species, Al as shown in Fig. 11_xGa_1-xIt is disclosed that the generation of grains (crystal particles) that induce a crack-like structure on the surface of the N layer can be suppressed. [0011] However, by optimizing the ammonia flow rate, Al_xGa_1-xIt is difficult to apply the method of flattening the N-layer surface to the MOCVD method, which is highly device-dependent. [0012] That is, the ammonia flow rate described in Non-Patent Document 1 is not always the optimum value applied to all MOCVD devices, and for example, the ammonia flow rate exceeding the control capacity of the device itself is the optimum value. In some cases, it cannot be said that the method described in Non-Patent Document 1 is a general-purpose flattening method. [0013] Therefore, conventionally, it has been desired to develop a method of flattening the surface of a laminate formed by crystal growth by a metalorganic vapor phase growth method. [0014] [Means for solving problems] Therefore, of this invention<u style="single">Semiconductor device</u>The manufacturing method of No. 1 has the following structural features. [0015] That is,<u style="single">The method for manufacturing the first semiconductor device is to use Al having a coefficient of thermal expansion B (however, A <B) on a first semiconductor layer made of GaN having a coefficient of thermal expansion A.</u>_{<u style="single">x</u>}<u style="single">Ga</u>_{<u style="single">1-x</u>}<u style="single">It is a manufacturing method of a semiconductor device including a laminate in which a second semiconductor layer consisting of N (0 <x <1) is laminated as a substrate main body, and is predetermined by an organic metal vapor phase growth method on the substrate. High temperature T</u>_{<u style="single">1</u>}<u style="single">A structure forming step of sequentially providing a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer made of GaN having a coefficient of thermal expansion A at ° C to form a structure, and a structure at a predetermined temperature. T</u>_{<u style="single">2</u>}<u style="single">° C (however, T</u>_{<u style="single">2</u>}<u style="single"><T</u>_{<u style="single">1</u>}<u style="single">), And a third semiconductor layer removing step of removing the third semiconductor layer by reactive ion etching to expose the second semiconductor layer, and exposing after the third semiconductor layer removing step. It is characterized by including an electrode forming step of forming a metal control electrode, a first main electrode and a second main electrode, which are separated from each other, on the surface of the second semiconductor layer.</u><u style="single">The second semiconductor device manufacturing method is a method for manufacturing a semiconductor device including the above-mentioned first semiconductor layer and the above-mentioned second semiconductor layer laminated as a substrate main body, and the above-mentioned structure formation. An insulating layer forming step of forming an insulating layer on an exposed second semiconductor layer after the third semiconductor layer removing step, including the above-mentioned cooling step and the above-mentioned third semiconductor layer removing step, and insulation. The control electrode forming step of forming the control electrode on a part of the layer and the position of the insulating layer sandwiching the insulating layer between the control electrode and the second semiconductor layer are removed to expose the second semiconductor layer. The step of removing the insulating layer and the step of forming the first and second main electrodes so as to be non-contact with the control electrode on each of the exposed second semiconductor layers are performed. It is characterized by including.</u><u style="single"> The third method for manufacturing a semiconductor device is a method for manufacturing a semiconductor device including a laminate obtained by laminating the above-mentioned first semiconductor layer and the above-mentioned second semiconductor layer as a substrate main body, and the above-mentioned structure formation. A first step including the above-mentioned cooling step, the above-mentioned third semiconductor layer removing step, and a predetermined distance on the third semiconductor layer after the cooling step and before the third semiconductor layer removing step. In the first and second main electrode forming steps in which the main electrode and the second main electrode are formed, respectively, and in the third semiconductor layer removing step, the portion of the third semiconductor layer in which the first main electrode is formed and the second The third semiconductor layer is removed so as to remain separated from the portion where the main electrode is formed by a predetermined distance, and after the third semiconductor layer removing step, on the second semiconductor layer exposed between the first and second main electrodes. It is characterized by including a control electrode forming step of forming a control electrode so as to be non-contact with each of the third semiconductor layers.</u>[0016] The present invention<u style="single">Semiconductor device</u>According to the manufacturing method of No. 1, the internal stress generated in the second semiconductor layer due to the difference in the coefficient of thermal expansion between the first semiconductor layer and the second semiconductor layer in the cooling (lowering temperature) process is conventionally applied. 3 It can be relaxed (reduced) by the semiconductor layer. As a result, the surface of the second semiconductor layer after the third semiconductor layer removing step can be made flatter (smoothed) than before. [0017] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 10. In addition, each figure is a process diagram which shows one structural example of the manufacturing method of the semiconductor device which concerns on this invention by the cut end of the cross section. It should be noted that each figure merely shows roughly the shape, size and arrangement relationship of each component to the extent that the present invention can be understood, and the present invention is not limited to the illustrated examples. In addition, in order to make the figure easier to understand, the hatching (diagonal line) showing the cross section is omitted except for a part. Further, in the following description, specific materials and conditions may be used, but these materials and conditions are only one of the preferable examples, and therefore are not limited thereto. Further, in each figure, the same constituent components are indicated by the same numbers, and the duplicated description thereof may be omitted. [0018] <First embodiment> A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 5 and 10. Note that FIG. 10 is a diagram schematically showing the relationship between each step described below and the substrate temperature (° C) corresponding to each step. [0019] In this embodiment, a method for manufacturing a GaN-based HEMT will be described as an example. The film formation of each layer described below is performed by using a general organic metal vapor phase growth method (MOCVD) method, and the group III raw material to be supplied is an organic metal compound having an alkyl group as a constituent element. Trimethylgallium (Ga (CH)₃)₃) Trimethylaluminum (Al (CH)₃)₃) Is used, and ammonia (NH) is used as the Group V element.₃) Is used. Moreover, since the specific method for crystal growth of each layer is conventionally known, detailed description thereof will be omitted. [0020] First, as a structure forming step, a predetermined high temperature T is placed on the substrate by the MOCVD method.₁At ° C, the first semiconductor layer with a coefficient of thermal expansion A, the second semiconductor layer with a coefficient of thermal expansion B (where A> B or A <B), and C> B in the case of A> B. , A <B, a third semiconductor layer having a coefficient of thermal expansion C that satisfies C <B is sequentially provided to form a structure. [0021] [0021] Therefore, first, C-axis oriented sapphire (Al)₂O₃) On the substrate 12, the GaN channel layer 20 as the first semiconductor layer (coefficient of thermal expansion (here, the coefficient of linear expansion) A = 5.4 × 10)^-6/ K) and n-type Al as the second semiconductor layer_0.2Ga_0.8N electron supply layer 22 (coefficient of thermal expansion B = 5.6 ~ 5.7 × 10)^-6A precursor laminate 25'with / K) is formed in sequence (Fig. 3 (A)). [0022] More specifically, inside the MOCVD equipment (the temperature inside the equipment at this time is T.₂Let it be ° C. This temperature T₂° C is, for example, a temperature in the range of 20 ° C to 100 ° C. ), For example, the temperature T in the range of 400 ° C to 600 ° C._aAfter heating to ° C, the surface of the GaN layer 14 (low temperature buffer layer) in an amorphous state at low temperature is flattened on the sapphire substrate 12 with a film thickness in the range of, for example, 10 nm to 50 nm. Form (Fig. 1 (A)). In Fig. 10, the time t_AIs when the board is installed, and time t_AFrom time t_BIs the substrate heating time, time t_BFrom time t_CUp to is the film formation time of the amorphous GaN layer 14. [0023] The sapphire substrate 12 is then placed at a temperature in the range of 950 ° C to 1150 ° C (ie, growth temperature T).₁As ° C), for example, in the heating process of heating to about 1040 ° C, the following formations are sequentially performed. [0024] First, the growth temperature T₁In the heating process up to ° C (here, about 1040 ° C), the amorphous GaN layer 14 is reformed into the crystalline GaN layer 16. [0025] More specifically, T₁In the process of raising the temperature up to ° C, the amorphous GaN layer 14 is transformed from the substrate surface side into a columnar structure having a large number of growth nuclei. During the alteration to the columnar structure, the etching of the amorphous GaN layer 14 by the reaction gas also proceeds at the same time, but the GaN buffer layer 16 can be uniformly formed on the substrate surface due to the increase in the alteration rate of the columnar structure. it can. The growth temperature T₁The temperature rise time to ° C is sufficient for the GaN layer 14 which is the low temperature buffer layer to be transformed into the GaN buffer layer 16 which is the columnar structure, and the growth temperature T₁It is necessary to set the GaN layer 14 within the time remaining without being etched by the reaction gas during the heating process up to ° C. [0026] So, for example, T_aAfter depositing the amorphous GaN layer 14 with a film thickness of 20 nm at = 500 ° C, T₁When the amorphous GaN layer 14 is modified into the GaN buffer layer 16 in the heating process up to = 1040 ° C, the optimum value of the heating time is about 7 minutes. The optimum value of the temperature rise time is not limited to this, and depends on the type of low temperature buffer layer (GaN or AlN), film thickness, gas type at the time of deposition, gas flow rate, specifications of MOCVD equipment, and the like. .. Also, the growth temperature T₁The ° C is preferably a temperature in the range of 950 ° C to 1150 ° C, and more preferably a temperature in the range of 1000 ° C to 1100 ° C. By doing so, the GaN buffer layer 16 having good crystallinity can be formed. In Fig. 10, the time t_CFrom time t_DUp to is the solid phase growth time of the GaN buffer layer 16. [0027] Then T₁After reaching ° C, GaN growth nuclei 18 are formed on the GaN buffer layer 16 by the organic metal vapor phase growth method so as to be uniform and dense (Fig. 1 (B)). [0028] Then, the growth temperature T₁At ° C, the GaN growth nuclei 18 are used as seeds to re-grow a large number of GaN grain boundaries whose crystal orientations are slightly different from each other. As a result, by repeating coalescence and dislocation of adjacent crystal grains, a good single crystal (undoped) GaN channel layer 20 having uniform crystal orientation and relatively few defects can be obtained, for example, in the range of 2000 nm to 5000 nm. It can be formed with the inner film thickness (Fig. 1 (C)). In Fig. 10, the time t_DFrom time t_EUp to is the film formation time of the GaN channel layer 20. Further, in order to obtain a GaN channel layer 20 having good crystallinity with few defects, it is preferable that the film thickness of the GaN channel layer 20 is 100 nm or more. [0029] Therefore, FIG. 2 (A) shows an AFM image of the surface of the GaN channel layer 20 in a state where the crystal orientation is uniform, that is, in a state where the crystal growth conditions are optimized, which is obtained through the above process. FIG. 2 (A) is an AFM image when scanning (scanning speed: about 0.9 Hz) is performed on a region of 1 μm in length and 1 μm in width on the surface of the GaN channel layer 20. The white region shown in (a) in the figure is used as a reference plane, and the black region shown in (c) is a concave region having a depth of about 10 nm from the reference plane. The gray region shown in (b) is a concave region having a shallower depth (<10 nm) than the black region (c). [0030] As shown in Fig. 2 (A), the surface of the GaN layer 20 with optimized crystal growth conditions is mostly larger than the white region (a), that is, the C-axis length (about 0.518 nm) of hexagonal GaN. It has an extremely flat surface condition with low step steps (generally a step of about 0.2 nm to 4 nm) (specifically, an average of 10 on the surface of the GaN layer 20).¹⁰/cm²There are pits (dents) at a certain density. ). [0031] Then, the growth temperature (T)₁Al on GaN channel layer 20 under ° C)_0.2Ga_0.8The N-electron supply layer 22 is formed, and here, silicon (Si), which is an n-type impurity, is 5 × 10.¹⁸cm^-3Crystal growth while adding, n-type Al with a film thickness in the range of 10 nm to 20 nm_0.2Ga_0.8N The electron supply layer 22 is formed. In Fig. 10, the time t_EFrom time t_FUp to n-type Al_0.2Ga_0.8This is the film formation time of the N electron supply layer 22. At this time, the GaN channel layer 20 and the n-type Al_0.2Ga_0.8A 2DEG (two-dimensional electron gas) 23 is formed at the interface with the N electron supply layer 22 due to the difference in band gap. Also, Al_0.2Ga_0.8The crystal growth conditions of the N layer 22 may be the optimization conditions already set when the GaN layer 20 is crystal-grown, and there is no need to perform new optimization. [0032] Thus, on the sapphire substrate 12, the GaN buffer layer 16, the GaN channel layer 20, and Al_0.2Ga_0.8A precursor laminate 25'with an N electron supply layer 22 is formed (Fig. 3 (A)). The GaN channel layer 20 and n-type Al_0.2Ga_0.8Undoped Al at the hetero interface with the N electron supply layer 22_0.2Ga_0.8An N spacer layer may be provided. The electron mobility in the GaN channel layer 20 can be further increased by interposing the spacer layer. [0033] In the conventional manufacturing process of GaN-based HEMT, after this, the precursor laminate 25'is n-type Al._0.2Ga_0.8The laminate was produced by cooling to a predetermined temperature with the surface of the N electron supply layer 22 exposed. However, in the present invention, A> is further formed on the second semiconductor layer 22 before the cooling is performed. A third semiconductor layer having a coefficient of thermal expansion C that satisfies C> B in the case of B and C <B in the case of A <B is provided to form a structure. The growth temperature at this time is T, which is the same as the growth temperature of the first and second semiconductor layers described above.₁Let it be ° C. [0034] In this embodiment, as described above, A (= 5.4 × 10)^-6/ K) <B (= 5.6 ~ 5.7 × 10)^-6Since / K), as a third semiconductor layer having a coefficient of thermal expansion C satisfying C <B, for example, a GaN layer (coefficient of thermal expansion C (= A) = 5.4 × 10)^-6/ K) 26 with n-type Al with a film thickness in the range of 10 nm to 20 nm_0.2Ga_0.8It is formed on the N electron supply layer 22 to obtain the structure 50 (Fig. 3 (B)). In Fig. 10, the time t_FFrom time t_GUp to is the film formation time of the GaN layer 26, and the structure 50 is completed. Further, while the GaN layer 26 is formed, the vapor deposition and evaporation of the constituent atoms of the GaN layer 26 are repeated on the surface layer portion of the GaN layer 26. Further, the third semiconductor layer 26 is not limited to the GaN layer, and may be any material having a coefficient of thermal expansion C that satisfies the above-mentioned conditions. However, by using the same material as the GaN channel layer 20 for the third semiconductor layer, it is not necessary to add a new supply gas for crystal growth of the third semiconductor layer, and the MOCVD apparatus configuration can be simplified, which is preferable. [0035] Next, as a cooling step, the structure 50 is brought to a predetermined temperature T.₂° C (however, T₂<T₁). T here₂° C is, for example, a temperature in the range of 20 ° C to 100 ° C. [0036] For example, structure 50 is T₂After allowing to cool to ° C, remove from MOCVD equipment. In Fig. 10, the time t_GFrom time t_HUp to is the cooling time of the structure 50. Further, this cooling step can be performed, for example, by turning off the power of the heater in the MOCVD apparatus immediately after the film formation is completed and allowing the temperature to drop naturally. Although it depends on the ambient temperature, the laminate 50 can be taken out from the MOCVD apparatus by leaving it for about 1 hour to 1 hour and 30 minutes after turning off the heater power. In addition, the surface of the GaN layer 26, which is the third semiconductor layer after cooling, is a step (generally about 0.518 nm) at a height lower than the C-axis length (about 0.518 nm) of hexagonal GaN, substantially similar to FIG. , With a step of about 0.2 nm to 4 nm), and exhibits an extremely flat surface state. [0037] The predetermined temperature T₂The temperature of ° C is not necessarily limited to the temperature in the range of 20 ° C to 100 ° C, and the temperature is set so that the GaN layer 26 on the surface layer of the structure 50 does not deteriorate, from the surface layer portion of the GaN layer 26 to the GaN layer. The temperature at which the evaporation (here, re-evaporation) after vaporization of the constituent atoms of the 26 layers stops can be set to a temperature lower than the growth temperature of the low temperature buffer layer, for example. [0038] Next, as a third semiconductor layer removing step, the cooled third semiconductor layer 26 is removed to expose the second semiconductor layer 22. [0039] Specifically, chlorine (Cl), which causes relatively small damage to the sample.₂) System and boron chloride (BCl)₃The GaN layer 26 is removed in a room temperature environment by using dry etching such as inductively coupled plasma reactive ion etching (ICP-RIE) or electron cycloton reactive ion etching (ECR) using) or the like as the etching gas. [0040] Therefore, as an etching gas, hydrogen (H)₂) And methane (CH₄) Is used for ICP-RIE to remove the GaN layer 26, and Al_0.2Ga_0.8N The surface of the electron supply layer 22 is exposed (Fig. 3 (C)). [0041] Therefore, in Fig. 2 (B), Al exposed by this dry etching_0.2Ga_0.8An AFM image of the surface of the N electron supply layer 22 is shown. FIG. 2 (B) shows a case where scanning (scanning speed: about 1.0 Hz) is performed on a 1 μm square region as in FIG. 2 (A), and the white region shown by (a) in the figure is used as a reference. As a surface, the black region shown in (c) is a concave region having a depth of about 10 nm from the reference surface. The gray region shown in (b) is a concave region having a shallower depth (<10 nm) than the black region (c). As shown in Fig. 2 (B), Al exposed in a room temperature environment._0.2Ga_0.8The surface of the N-electron supply layer 22 is substantially the same as in FIG. 2 (A), with steps having a height lower than the C-axis length (about 0.518 nm) of hexagonal GaN (generally, a step of about 0.2 nm to 4 nm). It can be seen that the surface state is extremely flat, and the crack structure as in the conventional case is not formed. [0042] In this way, the laminate 25 having a flat (smooth) surface of the second semiconductor layer can be obtained. [0043] From this, the third semiconductor layer 26 is Al in the cooling process._0.2Ga_0.8It has a function of relaxing (reducing) the internal stress generated in the N electron supply layer 22 due to the difference in the coefficient of thermal expansion from the GaN channel layer 20 as the temperature returns to room temperature. In addition, Al_0.2Ga_0.8Since the etching selectivity of N / GaN is small, Al is used when etching and removing the GaN layer 26._0.2Ga_0.8N layer 22 may be overetched, but Al after overetching_0.2Ga_0.8It has been confirmed that the surface of N layer 22 is also in a good flattened state. [0044] Then, for the laminate 25, nitrogen (N)₂) Or in an argon (Ar) atmosphere at a temperature of 400 ° C or higher, annealing treatment for about 5 to 20 minutes is performed, and n-type Al_0.2Ga_0.8N Removes unnecessary etching gas species adsorbed on the surface of the electron supply layer 22. [0045] Figure 4 shows Al under each of the conditions described below._0.2Ga_0.8The measurement result (XPS spectrum) of X-ray photoelectron spectroscopy (XPS) on the surface of N layer 22 is shown. In the figure, the horizontal axis shows the binding energy (eV), and the vertical axis shows the peak intensity (arbitrary). [0046] The measurement graph shown in (A) in FIG. 4 shows the above-mentioned ICP-RIE (here, BCl as the etching gas).₃use. ) Immediately after Al_0.2Ga_0.8It is a spectrum of the surface of N layer 22. The measurement graph shown in (B) shows Al immediately after the above-mentioned annealing treatment._0.2Ga_0.8It is a spectrum of the surface of N layer 22. The measurement graph shown in (C) is, for comparison, Al._0.2Ga_0.8Al immediately after the formation of N layer 22 (see Fig. 3 (A)) and surface cleaning with ammonia boil (about 15 minutes at a temperature of 50 ° C)._0.2Ga_0.8It is a spectrum of the N layer 22 surface. [0047] As is clear from the spectra of (A) and (B) shown in FIG. 4, the peak attributed to the Cl atom near the binding energy of 199.5 (eV) disappears due to the annealing treatment, and thus n-type Al_0.2Ga_0.8It can be seen that the Cl adsorbed on the surface of the N layer 22 was removed. [0048] Next, using the above-mentioned laminate 25 as the substrate main body, the main electrodes of the semiconductor are formed on the substrate main body. As an electrode forming step, a control electrode, a first main electrode, and a second main electrode, which are separated from each other, are formed on the upper side of the exposed second semiconductor layer 22. In this configuration example, these electrodes are formed on the upper surface of the second semiconductor layer. [0049] Specifically, n-type Al_0.2Ga_0.8A resist pattern (not shown) that exposes at least a part of the N electron supply layer 22 by a predetermined width, for example, in a stripe shape is formed by photolithography (hereinafter, simply referred to as forming a resist pattern). [0050] Then, using this resist pattern as a mask, for example, nickel (Ni) and gold (Au) are sequentially vapor-deposited as a metal for a control electrode (gate electrode) from above the mask to form the first laminated metal 32. More specifically, as an example, nickel is vapor-deposited so that the film thickness of nickel is 50 nm and the film thickness of gold is 700 nm. After that, the resist pattern is removed by the lift-off method, and n-type Al_0.2Ga_0.8A striped gate electrode 32 having a predetermined width made of the first laminated metal is formed on the N electron supply layer 22 (FIG. 5 (A)). [0051] After that, n-type Al_0.2Ga_0.8A resist pattern that exposes a region of the N-electron supply layer 22 that sandwiches the gate electrode 32 and is in non-contact with the gate electrode 32 by a predetermined width, for example, in a stripe shape. (Not shown) is formed. [0052] Then, using this resist pattern as a mask, from above the mask, as metals for the first main electrode (source electrode) and the second main electrode (drain electrode), for example, titanium (Ti), aluminum (Al) and gold ( Au) is sequentially deposited to form the second laminated metal 33. More specifically, as an example, the titanium film thickness is 15 nm, the aluminum film thickness is 200 nm, and the gold film thickness is 600 nm. After that, the resist pattern is removed by the lift-off method, and n-type Al_0.2Ga_0.8A striped source electrode 34 and drain electrode 36 having a predetermined width made of a second laminated metal are formed on the N electron supply layer 22 to complete the GaN-based HEMT10 (FIG. 5 (B)). [0053] As is clear from the above description, in this embodiment, the first semiconductor layer (here, GaN layer 20) and the second semiconductor layer (here, Al)._0.2Ga_0.8Al by the third semiconductor layer (here, GaN layer 26) that satisfies the coefficient of thermal expansion determined based on the relationship of the coefficient of thermal expansion of N layer)_0.2Ga_0.8The cooling (lowering temperature) process is performed with the N layer 22 coated. [0054] As a result, Al as before_0.2Ga_0.8Compared to the case where the cooling process was performed with the surface of the N electron supply layer 22 exposed, the GaN layer 20 and Al were provided by the third semiconductor layer._0.2Ga_0.8Al due to the difference in thermal expansion coefficient with N electron supply layer 22_0.2Ga_0.8The internal stress generated in the N electron supply layer can be relaxed. [0055] Therefore, n-type Al obtained by removing the third semiconductor layer after the cooling step._0.2Ga_0.8The surface of N layer 22 can be flattened more than before. [0056] Therefore, Al_0.2Ga_0.8The contact state between the N layer 22 and each electrode (gate electrode 32, source electrode 34, and drain electrode 36) is improved as compared with the conventional case, and a GaN-based HEMT having good electrical characteristics can be obtained. [0057] <Second embodiment> A method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 6 and 7. [0058] [0058] In the second embodiment, as in the first embodiment, the substrate body is composed of the laminate 25 from the substrate 12 to the second semiconductor layer 22, but the n-type of the second semiconductor layer is further formed. Al_0.2Ga_0.8The difference is that a MISFET (Metal Insulator Semiconductor FET) having a heterostructure is formed by forming a control electrode on the N layer 22 via an insulating film. Hereinafter, this difference will be mainly described, and the description overlapping with the first embodiment will be omitted (the same applies to the following embodiments). [0059] First, the structure forming step to the third semiconductor layer removing step are performed in the same manner as in the first embodiment. [0060] Next, after the third semiconductor layer removing step, an insulating layer is formed on the exposed second semiconductor layer as an insulating layer forming step. [0061] Specifically, n-type Al, which is the exposed second semiconductor layer._0.2Ga_0.8On the N electron supply layer 22, as an insulating layer, for example, a silicon oxide film (SiO)₂) 30 is formed so as to have a film thickness in the range of, for example, 10 nm to 15 nm (Fig. 6 (A)). In this way, in this configuration example, a MOSFET (Metal Oxide Semiconductor FET) is manufactured. In addition to the silicon oxide film, the insulating layer is a silicon nitride film (Si).₃N₄) Etc. may be used. When a silicon nitride film is used, the film thickness can be in the range of 10 nm to 30 nm, for example. [0062] After that, as a control electrode forming step, a striped control electrode having a predetermined width made of the first laminated metal is formed on a part of the silicon oxide film 30 which is an insulating layer by the same method as in the first embodiment. The gate electrode 32 is formed (Fig. 6 (B)). [0063] After that, as a step of removing the insulating layer, the gate electrode 32 and the n-type Al of the insulating layer_0.2Ga_0.8Remove each of the positions sandwiching the insulating film between the N electron supply layer 22 and n-type Al._0.2Ga_0.8N The electron supply layer 22 is exposed. [0064] Specifically, the n-type Al is located at the position where the gate electrode 32 is sandwiched and the first and second main electrodes (source electrode 34 and drain electrode 36) are formed in the subsequent process._0.2Ga_0.8Each of the silicon oxide films overlying the N-electron supply layer 22 is removed by optional suitable photolithography etching (Fig. 6 (C)). [0065] After that, as the first and second main electrode forming steps, the n-type Al exposed by the insulating layer removing step_0.2Ga_0.8A first main electrode (for example, a source electrode 34) and a second main electrode (for example, a drain electrode 36) are formed on each of the N electron supply layers 22 so as to be in non-contact with the gate electrode 32. [0066] Specifically, the exposed n-type Al_0.2Ga_0.8After forming a resist pattern (not shown) that exposes the N electron supply layer 22 in a striped shape, for example, using this resist pattern as a mask, the same as in the first embodiment from above the mask. The second laminated metal 33 is formed by the method. After that, the resist pattern is removed by the lift-off method, and n-type Al_0.2Ga_0.8A striped source electrode 34 and drain electrode 36 having a predetermined width made of a second laminated metal are formed on the N electron supply layer 22, and a MOSFET 15 having a heterostructure is completed (FIG. 7). [0067] Further, in the MOSFET 15, the regions other than the source electrode 34 and the drain electrode 36 in the surface region of the laminated body 25 are covered with the silicon oxide film 30. Therefore, the silicon oxide film 30 can be used as a protective film for the device, and a MISFET (MOSFET) having stable electrical characteristics can be obtained. [0068] As is clear from the above description, in this embodiment, as in the first embodiment, the n-type Al obtained by removing the third semiconductor layer after the cooling step._0.2Ga_0.8The surface of N layer 22 can be flattened more than before. [0069] Therefore, Al_0.2Ga_0.8Contact state between N layer 22 and source electrode 34 and drain electrode 36, and Al_0.2Ga_0.8The contact state between the N layer 22 and the silicon oxide film 30 which is the gate insulating layer is improved as compared with the conventional case, and a MISFET (MOSFET) having good electrical characteristics can be obtained. [0070] <Third embodiment> A method for manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 8 and 9. [0071] In the third embodiment, as in the first embodiment, the substrate body is composed of the laminate 25 from the substrate 12 to the second semiconductor layer 22, but the n-type of the second semiconductor layer is further formed. Al_0.2Ga_0.8The main difference is that a recess structure is formed by leaving a part of the third semiconductor layer 27 as a contact layer on the N layer 22. [0072] First, the structure forming step is performed in the same manner as in the first embodiment. In this embodiment, the third semiconductor layer is formed of silicon, which is an n-type impurity, in an amount of 5 × 10.¹⁸cm^-3Crystal growth is performed while adding to form an n-type GaN layer 27 (Fig. 8 (A)). The growth temperature at this time is the above-mentioned T.₁Let it be ° C. Then, as in the first embodiment, the room temperature T₂Perform the cooling process up to ° C. [0073] Next, before the third semiconductor layer removing step, as the first and second main electrode forming steps, the n-type GaN layer 27, which is the third semiconductor layer, is separated by a predetermined distance, for example, a striped first electrode. A main electrode (source electrode) and a second main electrode (drain electrode) are formed, respectively. That is, in this configuration example, these electrodes are formed on the upper side of the second semiconductor layer 22 via the contact layer 27. [0074] Specifically, in the n-type GaN layer 27, a resist pattern (not shown) that is exposed by a predetermined width, for example, in a stripe shape is formed in a region separated by a predetermined distance, respectively, and the first embodiment The second laminated metal 33 is vapor-deposited by the same method as in the above. [0075] Then, the resist pattern is removed by the lift-off method to form a striped source electrode 34 and drain electrode 36 having a predetermined width made of the second laminated metal on the n-type GaN layer (FIG. 8 (B)). [0076] Next, in the third semiconductor layer removing step, the third semiconductor layer 27 on which the source electrode 34 and the drain electrode 36 are formed is removed from the third semiconductor layer 27 so as to remain separated by a predetermined distance. [0077] Specifically, in the n-type GaN layer 27, a resist pattern (not shown) is formed so as to expose the region sandwiched between the source electrode 34 and the drain electrode 36 by a predetermined width, for example, in a stripe shape, and resist. Perform ICP-RIE using the pattern as a mask. Thus, n-type Al_0.2Ga_0.8A part of the N electron supply layer 22 is exposed and the remaining n-type GaN contact layer 27 is formed, and then the resist pattern is removed (FIG. 8 (C)). [0078] After that, the exposed n-type Al_0.2Ga_0.8A resist pattern is formed so as to expose at least a part of the N electron supply layer 22 by a predetermined width, for example, in a stripe shape, and the first laminated metal 32 is vapor-deposited by the same method as in the first embodiment. [0079] After that, the resist pattern is removed by the lift-off method, and Al_0.2Ga_0.8A striped gate electrode 32 having a predetermined width made of the first laminated metal is formed on the N electron supply layer 22, and a GaN-based HEMT10 having a recess structure is completed (Fig. 9). [0080] [0080] In this embodiment, the gate electrode 32 is formed after the source electrode 34 and the drain electrode 36 are formed, but the source electrode 34 and the drain electrode 36 may be formed after the gate electrode 32 is formed. However, since the formed source electrode 34 and drain electrode 36 are usually subjected to an annealing treatment, the gate electrode can be configured not to be exposed to the annealing treatment by the forming method of this embodiment. Good shot key contact is obtained. [0081] As is clear from the above description, the GaN-based HEMT produced in this embodiment can obtain the same effect as that in the first embodiment. [0082] Further, in this embodiment, Al_0.2Ga_0.8This is a recess structure in which the contact state between the N layer 22 and the gate electrode 32 is improved, and the source electrode 34 and the drain electrode 36 are formed on the n-type GaN contact layer. [0083] Therefore, the ohmic contact resistance between the n-type GaN contact layer 27 and the source electrode 34 and the drain electrode 36 can be reduced, and a GaN-based HEMT having even better electrical characteristics can be obtained. [0084] As described above, the present invention is not limited to the combination of the above-described embodiments. Therefore, the present invention can be applied by combining suitable conditions at any suitable stage. [0085] For example, the semiconductor device to which the present invention is applied is not limited to the HEMT described above, and may be an HFET, a MISFET, or the like. [0086] Further, the present invention can be appropriately applied to a configuration in which the second semiconductor layer, which requires flatness, is finally used as the outermost layer, and also in a configuration in which the second semiconductor layer is used as a laminated interface. [0087] Further, although a sapphire substrate is used in each embodiment, a silicon carbide (SiC) substrate or the like may be used. When a silicon carbide substrate is used, it is preferable to form the buffer layer with aluminum nitride (AlN). [0088] The composition ratio of the second semiconductor layer in each embodiment is Al._0.2Ga_0.8The composition ratio is not limited to N, and can be any suitable composition ratio depending on the purpose and design. [0089] [Effect of the invention] As is clear from the above description, according to the present invention, by covering the second semiconductor layer with the third semiconductor layer, the surface of the second semiconductor layer is exposed and the cooling process is performed as in the conventional case. In comparison with the above, the internal stress generated in the second semiconductor layer can be relaxed due to the difference in the coefficient of thermal expansion between the first semiconductor layer and the second semiconductor layer. [0090] As a result, the surface of the second semiconductor layer obtained by removing the third semiconductor layer can be made flatter than before, so that there is no concern that the surface roughness of the second semiconductor layer impairs the electrical characteristics. A semiconductor device can be obtained. [Simple explanation of drawings] 1A to 1C are cross-sectional views provided for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is an atomic force electron microscope (AFM) image provided for the description of the first embodiment of the present invention. 3A to 3C are cross-sectional views provided for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 4 is a measurement spectrum by X-ray photoelectron spectroscopy (XPS), which is used for explaining the first embodiment of the present invention. 5A and 5B are cross-sectional views for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention. 6 (A) to 6 (C) are cross-sectional views provided for explaining a manufacturing process of a semiconductor device according to a second embodiment of the present invention. FIG. 7 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the second embodiment of the present invention. 8 (A) to 8 (C) are cross-sectional views provided for explaining a manufacturing process of a semiconductor device according to a third embodiment of the present invention. FIG. 9 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the third embodiment of the present invention. FIG. 10 is a diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention. FIG. 11 is a diagram for explaining the surface state of a conventional AlGaN layer. [Explanation of symbols] 10: GaN-based HEMT 12: Sapphire substrate 14: Amorphous GaN layer 16: GaN buffer layer 15: MOSFET 18: GaN growth nucleus 20: GaN channel layer 22: n-type Al_0.2Ga_0.8N electron supply layer 23: 2DEG (two-dimensional electron gas) 25': Precursor laminate 25: Laminate 26: GaN layer 27: n-type GaN layer 30: Silicon oxide film 32: Gate electrode (first laminated metal) 33: Second laminated metal 34: Source electrode 36: Drain electrode 50: Structure