Nonvolatile semiconductor memory

The present invention relates to a metal wiring layer of a non-volatile semiconductor storage device, and is particularly represented by aluminum (Al) wiring, tungsten (W) wiring, and copper (Cu) wiring of block-type memory cells such as NAND-type EEPROM and AND-type EEPROM. Used for patterning and layout of metal wiring.

Examples of NAND type EEPROM as a conventional non-volatile semiconductor storage device are shown in FIGS. 88 to 96. FIG. 88 shows an enlarged schematic planar pattern diagram of the memory cell array region, and FIGS. 89 to 91 show schematic cross-sectional structural views in the II line direction, the II-II line direction, and the III-III line direction in FIG. 88. Shown. Further, FIG. 92 shows an overall planar pattern configuration diagram of the memory cell array area 1. Further, FIG. 93 shows a detailed planar pattern configuration diagram of the memory sectional area 1 when the width of the source line SL2 is formed wide, and FIGS. 94 to 96 show IV-IV line, VV line, and VI in FIG. 93, respectively. -Shows a schematic cross-sectional structure along the VI line.

As shown in FIG. 88, the conventional non-volatile semiconductor storage device extends in the direction of the data transfer line BL, the data selection line WL arranged so as to be orthogonal to the data transfer line BL, and the data transfer line BL. Element region 10, element separation region 12, selective gate transistors SGD, SGS, source line contact CS, data transfer line contact CB, via contact 16, first source line SL0, second It has a source line SL2. As shown in FIG. 88, the circular or elliptical source line contact CS and the data transfer line contact CB are arranged in the direction orthogonal to the data transfer line BL. The pitch of the contacts in the III-III direction depends on the width of the element region 10 and the element separation region 12, but for example, the minimum processing dimension is F, and the contacts are arranged at a very dense interval of 2 to 3F. Further, the pitches of the data transfer line contact CB and the source line contact CS in the II direction orthogonal to this are larger than those in the III-III direction. For example, in the NAND flash memory, they are arranged at intervals of 40 to 100F. In FIG. 88, the width of the second source line SL2 is shown as x and the interval is shown as u.

As shown in FIG. 89, the cross-sectional structure of the conventional non-volatile semiconductor storage device in the line II direction includes a p-well or a semiconductor substrate 26, a diffusion layer 18, a memory cell 20, selective gate transistors SGS and SGD, and a barrier. Insulating film 22, data transfer line contact CB, source line contact CS, first source line SL0, data transfer line leader 14, via contact 16, data transfer line BL, interlayer insulating film 23, Equipped with 24. Furthermore, the cross-sectional structures of conventional non-volatile semiconductor storage devices in the II-II and III-III directions are as shown in FIGS. 90 and 91, with a p-well or semiconductor substrate 26 and diffusion layers 18 and 19. , Barrier insulating film 22, data transfer line contact CB, source line contact CS, first source line SL0, data transfer line leader 14, first via contact 16, and data transfer line BL. The source shunt wire SH1 and the well shunt wire SH2, the second via contact 17, the second source wire SL2, and the interlayer insulating films 23 and 27 are provided. In FIG. 91, the distance from the surface of the semiconductor substrate 26 to the second source line SL2 is shown as y, and the width of the second source line SL2 is shown as x.

The data transfer line contact CB and the first via contact 16 are embedded with a metal such as polycrystalline silicon or W which is highly doped with impurities such as phosphorus (P), and the data transfer line leader 14 and the first source are used. Line SL0 is embedded in metal such as W. As the wiring layer, a data transfer line leader 14 longer than 7F in the data transfer line BL direction is assumed here, but of course, a longer linear dense metal pattern is sufficient, and the first via contact. The following holds even in a structure in which 16 and the data transfer line lead-out unit 14 are omitted, and the data transfer line BL is considered as wiring and a direct contact is formed. The data transfer line BL, the second via contact 17, and the second source line SL2 are made of a metal such as Al or Cu.

The data transfer lines BL are arranged at very dense intervals of 2 to 3F with the minimum machining dimension F perpendicular to the III-III direction. For example, about 530 data transfer lines BL are configured as one memory cell array block. ing. For example, if a 16-bit memory cell is arranged in series as a 1NAND memory cell unit, 530 1NAND memory cell units are arranged in parallel in the II-II line direction to form a 1NAND memory cell block. .. Further, the substrate contact SB with the semiconductor substrate 26, the source shunt line SH1 connected to the contact with the source line SL, and the well shunt line SH2 connected to the contact with the well are placed between the memory cell array blocks (for example, a data transfer line). BLs are arranged every 530). The source line SL0 is formed in the II-II direction and serves as a ground wire for the source line SL between the data transfer lines BL. Further, in the direction orthogonal to the II-II direction (II direction), the ground wire of the source line is formed by the source line SL2 as shown in the II-II cross section. The source wire SL2 and the source shunt wire SH1 form a ground wire with the source wire in a grid pattern. The source line SL2 is arranged in the direction extending in the II direction, for example, on the source shunt line SH1 so that wiring having a width of about 15 to 20F does not cover the memory cell array. If a 1NAND memory cell unit is a unit in which 16-bit memory cells are arranged in series between the bit line side selection gate transistor SGD and the source line side selection gate transistor SGS, about 2048 blocks are arranged in the II direction. Therefore, it is easy to imagine that the source line SL2 is also long enough.

The first problem in the conventional example is the reduction of the space between memory cell arrays due to miniaturization and the increase of wiring resistance due to the reduction of the wiring width itself. When the source line SL2 is arranged linearly between the memory cell arrays as in the prior art, the space between the memory cell arrays is reduced, which means that the source wiring width that can be arranged between the spaces is reduced. Further, when miniaturization is required, it is possible to reduce the space between the memory cell array by reducing the wiring itself, but in either case, the wiring width itself is reduced. , It is inevitable that the wiring resistance will increase.

As shown in FIG. 92, the overall plane pattern configuration of the memory cell array area includes the semiconductor chip 6, the memory cell array area 1 shown by the part inside the broken line, the source line SL2, the data selection line control circuit 2, and the sense. It includes an amplifier or data latch 4, a source line shunt transistor 3, and a power supply wiring pad (pad) 5. In particular, as shown in FIG. 92, when the area of the power supply wiring pad 5 is arranged only on one side of the semiconductor chip 6, when the chip area is reduced, the data selection line control circuit 2 is close to the memory cell array area 1. And because the sense amplifier or data latch 4 is densely formed, it is not possible to arrange the power supply wiring thickly around it. In particular, in a non-volatile semiconductor storage device in which a positive potential is applied to the p-well 26 formed in the memory cell array region 1 to erase it, the second source line SL2 connected to the memory cell is positively equal to or higher than the voltage of the p-well 26. Keeping the voltage is necessary to prevent leakage current from the source line SL2. Therefore, in order to realize both conductive and non-conducting states between the source line SL2 and the power supply wiring pad 5 at the ground potential, a source line shunt is provided around the memory cell array area 1 as shown in FIG. Transistor 3 is required. In order to reduce the wiring and chip area, it is desirable that the source wire shunt transistor 3 is arranged on one side because the thick wiring area up to the source wire shunt transistor 3 and the power supply wiring pad 5 can be reduced. In this case, in the memory cell array area 1 arranged at the upper end of FIG. 92, the source line SL2 becomes a long wiring substantially corresponding to the length of one side of the semiconductor chip 6, and the voltage drop due to the wiring resistance and the memory cell operation Serious problems such as its own location dependence occur. For example, such a voltage drop causes the voltage of the source line to rise at the time of reading the verification operation at the time of writing, and causes a widening of the writing threshold value (see, for example, Patent Document 1). In particular, it causes a write failure in a memory cell using a multi-valued threshold value that requires accurate control of the threshold value.

As the second problem, when the width of the source line SL2 is widened for the purpose of reducing the wiring resistance in order to solve the first problem, a part of the source line SL2 becomes a NAND column on the memory cell array area 1. It will be covered. FIGS. 93 to 96 show a state in which the width of the source line SL2 is formed to be wide corresponding to FIGS. 88 to 91, and the NAND column is partially covered with the source line SL2. In particular, FIG. 96 shows the cross-sectional structure of the region where the source line SL2 covers the NAND row in the corresponding cross-sectional structure of FIG. 91. The structure of each part of the conventional example of FIGS. 93 to 96 is substantially the same as the structure shown in FIGS. 88 to 91, and the description of the common part will be omitted. The difference is that the width of the second source line SL2 is extended to the memory cell array area 1 to form a wide structure, and the SiN film 7 is provided as the final passivation film.

In the conventional example, for example, as shown in FIG. 88 or 91, the distance from the tunnel insulating film 44 of the memory cell (see FIGS. 1 and 2 as an enlarged configuration diagram) to the source line SL2 is y, and the source line is the source line. Assuming that the width of SL2 is x and the spacing (space) of the source line SL2 is u, the source line SL2 so as to satisfy y <x / 2 and y <u / 2 in order to reduce the resistance of the source line SL2. The width x and the arrangement interval (space) u of the source line SL2 were formed to be thick. After the source line SL2 is formed, a passivation film such as a silicon nitride film (SiN film) 7 is usually formed, but the hydrogen generated at that time is also diffused into the memory cell. When the source line SL2 does not cover the memory cell array region 1, the diffused hydrogen easily reaches the tunnel insulating film 44 or the gate insulating film of the selective gate transistors SGD and SGS, and the tunnel insulating film 44 or the gate. By being trapped in the insulating film, it has the effect of repairing some of the defects in the tunnel insulating film 44 or the gate insulating film. Further, by reaching the interface between the tunnel insulating film 44 or the gate insulating film and the semiconductor substrate 26, the interface state is terminated, the threshold value of the nMOS transistor is lowered, and the subthreshold coefficient is reduced. However, when the source line SL2 covers the memory cell array region 1, the diffused hydrogen is trapped by the barrier metal layer such as Ti / TiN of the source line SL2 and reaches the tunnel insulating film 44 or the gate insulating film. There is nothing to do. In particular, when hydrogen diffuses isotropically as in the case where a thermal process is applied after forming a passivation film such as SiN film 7, y < When it becomes x / 2, under the condition that the diffusion length of hydrogen is y or more and x / 2 or less, hydrogen diffuses to the tunnel insulating film 44 or the gate insulating film in the portion where the source line SL2 is not formed, while the source line SL2 Hydrogen may not sufficiently diffuse into the central tunnel insulating film 44. Therefore, it is clear that the hydrogen concentration distribution in the tunnel insulating film 44 is location-dependent. Therefore, there arises a problem that the reliability behavior of the memory cell differs depending on the NAND column of the part where the source line SL2 is formed and the part where the source line SL2 is not formed. Furthermore, when anisotropic etching (RIE) is used as the processing of the source line SL2, the formation probability of the upper source line SL2 differs greatly depending on the NAND row. Therefore, damage due to etching ions is introduced into the etched portion, which also causes a problem that the reliability behavior of the memory cell is different.

Further, in the case of FIGS. 93 to 96, the data transfer line BL connected to the NAND column covered by the source line SL2 is compared with the data transfer line BL connected to the NAND column not covered by the source line SL2. Then, the capacity for the source line SL2 is greatly increased by (NAND column) × (number of NAND blocks). As a result, the capacitance between the data transfer lines varies, so that the CR time constant of the data transfer line at the time of reading differs depending on the data transfer line. Therefore, a margin is required for the timing at the time of reading.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 11-260076</text></patcit>

<p> In the conventional metal wiring, the memory cell array formed with the minimum processing size is linearly arranged between the memory cell array without covering it, but with the miniaturization, the space between the memory cell array and the metal wiring itself are also miniaturized. As the process progresses, it has become a problem that the resistance of metal wiring increases accordingly.</p><p> An object of the present invention is to improve the resistance of metal wiring by devising a pattern and layout for source electrode wiring that supplies ground potential or low-level potential Vss, and connecting conventional linear wirings in a ladder shape, for example. By arranging these connection wirings periodically at the same time, the influence of hydrogen diffused from the outside on a single memory cell becomes almost constant, and there is no difference in load capacity between data transfer lines. The purpose is to provide a non-volatile semiconductor storage device for layout.</p>

<p> In order to achieve the above object, the features of the present invention are the semiconductor substrate, the gate insulating film formed on the semiconductor substrate, and the first selective gate transistor formed on the gate insulating film. The gate electrode, the second gate electrode of the second selection gate transistor formed on the gate insulating film, and the gate insulating film formed on the gate insulating film between the first and second gate electrodes and the first. A memory cell unit including a third gate electrode of a plurality of memory cell transistors arranged along a first direction connecting the first and second gate electrodes, and the memory cell unit orthogonal to the first direction. A memory cell array block configured by arranging a predetermined number of memory cell array blocks in the second direction, a memory cell array block configured by arranging the memory cell array blocks in a matrix in the first and second directions, and the second memory cell array block. A first selection gate line formed along the second direction so as to connect between the first gate electrodes of each memory cell unit adjacent to the direction, and each memory cell adjacent to the second direction. Corresponds to the second selection gate line formed along the second direction so as to connect the second gate electrodes of the unit and the third gate electrode arranged in the first direction. Then, a plurality of data selection lines formed along the second direction so as to connect between the third gate electrodes of each memory cell unit adjacent to the second direction + direction, and the second Corresponding to each of the plurality of memory cell units arranged in the above direction, the corresponding memory is formed above the memory cell unit and along the first direction via a first interlayer insulating film. The cell unit<u style="single">Drain electrode of first-choice gate transistor</u>A plurality of data transfer lines connected to the above, and the second data transfer line formed between the data transfer line and the semiconductor substrate and along the second direction.<u style="single">Source electrode of select gate transistor</u>The memory cell array block is formed in a layer above the data transfer line via a first source line and a second interlayer insulating film connected to the above, and along the first direction and the second direction. It is a gist that it is a non-volatile semiconductor storage device provided between the first source line and the second source line connected to the first source line.</p>

<p> According to the non-volatile semiconductor storage device of the present invention, the pattern and layout for the source electrode wiring that supplies the ground potential or the low-level potential Vss are devised, and the conventional linear wirings are connected to each other in a ladder shape, for example. Wiring resistance can be improved. Further, by arranging these connection wirings periodically at the same time, the influence of hydrogen diffused from the outside on a single memory cell can be made almost constant. In addition, by laying out so that there is no difference in load capacitance between the data transfer lines, the capacitance variation between the data transfer lines is suppressed, and the CR time constant of the data transfer line at the time of reading is made uniform by the data transfer line. , It is also possible to allow a margin for the timing at the time of reading.</p>

In the embodiment of the present invention, the pattern and layout for the source electrode wiring that supplies the ground potential or the low-level potential Vss are devised, and the resistance of the metal wiring is made by connecting the conventional linear wirings to each other, for example, on a ladder. By improving the above and arranging these connection wirings periodically at the same time, the influence of hydrogen diffused from the outside on a single memory cell becomes almost constant, and there is a difference in load capacity between data transfer lines. Provided is a non-volatile semiconductor storage device having a layout that does not exist.

Next, the first to sixth embodiments of the present invention will be described with reference to the drawings. In the description of the drawings below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that the drawings include parts having different dimensional relationships and ratios from each other.

In addition, the first to sixth embodiments shown below exemplify devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is a component component. The material, shape, structure, arrangement, etc. are not specified as follows. The technical idea of the present invention can be modified in various ways within the scope of claims.

(First Embodiment) In the first embodiment, an example of a NAND type EEPROM, which is a typical non-volatile memory, will be described with reference to FIGS. 1 to 9. 3 and 4 show the equivalent circuit diagram and the plan view of the memory cell, and FIGS. 1 and 2 show the cross-sectional view. In the equivalent circuit diagram, the selective gate transistors SGD and SGS have a structure different from that of the memory cells M0 to M15 (a structure without a charge storage layer 49), but as a structure having a charge storage layer 49 like the memory cells M0 to M15. Is also good.

As shown in FIG. 4, a plurality of memory cells M0 to M15 are connected in series between the source line contact CS and the data transfer line contact CB via the selection transistors SGS and SGD. As the structure of the memory cells M0 to M15, a type having a floating gate 40 as shown in FIG. 1 and a type having an insulating film composed of a charge storage layer 49 can be used as shown in FIG. As shown in FIG. 1, a memory cell of the type having a floating gate 40 is formed on a diffusion layer 18 which is a source region or a drain region formed in a p-type well or a semiconductor substrate 26 and a p-type well or a semiconductor substrate 26. The formed tunnel insulating film 44, a floating gate 40, an interpoly insulating film 42, a control gate electrode 46, a mask insulating film 48, and an interlayer insulating film 24 are provided.

As shown in FIG. 2, the type of memory cell having an insulating film composed of the charge storage layer 49 includes a p-type well or a diffusion layer 18 which is a source region or a drain region formed on the semiconductor substrate 26, and a p-type well or a p-type well. A tunnel insulating film 44 formed on the semiconductor substrate 26, a charge storage layer 49, a block insulating film 52, a control gate electrode 46, a mask insulating film 48, and an interlayer insulating film 24 are provided.

As an example of FIG. 2, a silicon nitride film, an oxynitride film, or an alumina film may be used as the charge storage layer 49. Here, the memory cell has a charge storage layer 49 in which charges are injected or discharged from a source or drain diffusion layer 18 or a p-type well or semiconductor substrate 26, depending on the data to be retained. Further, in the NAND structure of the non-volatile semiconductor storage device according to the first embodiment, a plurality of memory cells M0 to M15 are formed so that data can be rewritten.

These non-volatile memory cells are connected in series, and as shown in FIG. 3, one end of the source electrode or drain electrode 54 of the memory cell M0 is connected to the data transfer line BL via the selection gate transistor SGD and the data transfer line contact CB. Is electrically connected to. Further, one end of the source electrode or drain electrode 54 of the memory cell M15 is electrically connected to the common source line SL via the selection transistor SGS and the source line contact CS. Further, each transistor is formed on the same p-type well 26. Further, each memory cell control electrode is connected to the data selection lines marked WL0 to WL15. Further, since one NAND memory cell unit 51 is selected from the NAND memory cell blocks having a plurality of NAND memory cell units along the data transfer line BL and connected to the data transfer line BL, the selection transistor SGD is controlled. The electrodes are connected to the block selection gate line SSL. Further, the control electrode of the selection gate transistor SGS is connected to the block selection gate line GSL, forming a so-called NAND memory cell block. Here, the memory cell block may have at least one SSL and GSL block selection gate line, and it is desirable that the memory cell block is formed in the same direction as the data selection lines WL0 to WL15 for high density. The number of memory cells connected to the data transfer line and data selection line may be multiple, 2ⁿIt is desirable that (n is a positive integer) for address decoding.

The NAND memory cell unit 51 shown in FIG. 3 is formed adjacent to each other in a plurality of matrix forms in the data transfer line BL direction and the data selection lines WL0 to WL15 directions. Specifically, as shown in FIG. 4, a similar memory cell array is formed in the left-right direction of the paper surface, and SSL, WL0 to WL15, GSL, and SL are shared. Further, a similar memory cell array is formed in the vertical direction of the paper surface of FIG. 4, and a data transfer line (BL) is commonly connected to the memory cell array formed above. In such an array layout, since it is necessary to store independent data in each memory cell, the data transfer line BL between adjacent memory cells and the wiring of the data transfer line lead-out unit 14 are the selection transistors SGD of each memory cell. Must be connected independently to the n-type drain diffusion layer of. As for the structure below the data transfer line BL, for example, the NAND structure described in detail in JP-A-2002-150783 may be used, and is omitted here.

Detailed structural diagrams of the first embodiment of the present invention are shown in FIGS. 5 to 9. Examples of NAND-type EEPROM as the non-volatile semiconductor storage device according to the first embodiment of the present invention are shown in FIGS. 5 to 9. FIG. 5 shows an enlarged schematic planar pattern diagram of the memory cell array region, and FIGS. 6 to 8 show schematic cross-sectional structural views in the II line direction, the II-II line direction, and the III-III line direction in FIG. Shown. Further, FIG. 9 shows an overall planar pattern configuration diagram of the memory cell array area.

As shown in FIG. 5, the non-volatile semiconductor storage device according to the first embodiment of the present invention includes a data transfer line BL and a data selection line WL arranged so as to be orthogonal to the data transfer line BL. , Bit line side selection gate line SSL, source line side selection gate line SGL, multiple memory cell units 51, element area 10 and element separation area 12 extending in the data transfer line BL direction, and selection gate transistor SGD, It includes an SGS, a source line contact CS, a data transfer line contact CB, a via contact 16, a data transfer line leader 14, a first source line SL0, and a second source line SL2.

As shown in FIG. 5, the circular or elliptical source line contact CS and the data transfer line contact CB are aligned in the direction perpendicular to the data transfer line BL. The pitch of the contacts in the III-III direction depends on the width of the element region 10 and the element separation region 12, but for example, the minimum processing dimension is F, and the contacts are arranged at a very dense interval of 2 to 3F. The pitch of the contacts in the II direction orthogonal to this is larger than that in the III-III direction. For example, in the NAND flash memory, the contacts are arranged at intervals of 40 to 100F. In FIG. 5, the width of the second source line SL2 is indicated as x and the interval is indicated as u.

As shown in FIG. 6, the cross-sectional structure of the non-volatile semiconductor storage device according to the first embodiment of the present invention includes a p-well or a semiconductor substrate 26, a diffusion layer 18, a memory cell 20, and a memory cell 20. Selective gate transistors SGS, SGD, barrier insulating film 22, data transfer line contact CB, source line contact CS, source line SL0, data transfer line leader 14, via contact 16, data transfer line BL , The source line SL2 and the interlayer insulating films 23 and 24 are provided. Furthermore, as shown in FIGS. 7 and 8, the cross-sectional structure of the non-volatile semiconductor storage device according to the first embodiment of the present invention in the line II-II direction and the line III-III direction is a p-well or a semiconductor. Substrate 26, diffusion layers 18 and 19, barrier insulating film 22, data transfer line contact CB, source line contact CS, first source line SL0, data transfer line leader 14, and first via The contact 16, the data transfer line BL, the source shunt line SH1 and the well shunt line SH2, the second via contact 17, the second source line SL2, and the interlayer insulating films 23 and 27 are provided. As shown in FIG. 6, the memory cell 20 is covered with a barrier insulating film 22 such as a silicon nitride film, a silicon oxynitride film, and an aluminum oxide film, and the barrier insulating film 22 is covered with a data transfer line contact CB and a source line contact CS. It plays the role of an etching stopper that prevents the device from falling into the element separation groove. In FIG. 6, the distance from the surface of the semiconductor substrate 26 to the second source line SL2 is shown as y, and the width of the second source line SL2 is shown as x.

As shown in FIG. 9, the overall planar pattern configuration of the memory cell array area 1 consists of the semiconductor chip 6, the memory cell array area 1 indicated by the portion inside the broken line, and a plurality of memory cell array arranged in the memory cell array area 1. Block 53, a plurality of first source lines SL0, a second source line SL2, SL2EL1 (source line 2 element 1) connecting the second source lines in a grid pattern, and a data selection line control circuit 2 A sense amplifier or a data latch 4, a source line shunt transistor 3, and a power supply wiring pad (pad) 5 are provided. A power supply line is connected to the power supply wiring pad 5. In particular, as shown in FIG. 9, the source line SL2 includes the source line 2 element 1 (SL2EL1) in the data selection line WL direction at the upper part of the source line SL0, and is arranged in a grid pattern as a whole. Further, it is the same as the description of FIG. 5 that a plurality of memory cell units 51 are arranged in each memory cell array block 53 in the data selection line WL direction.

The data transfer line contact CB and via contact 16 are embedded with a metal such as polycrystalline silicon or W which is highly doped with impurities such as phosphorus (P), and the data transfer line leader 14 and the source line SL0 are W or the like. It is embedded in metal. Here, as the wiring layer, it is assumed that the data transfer line leader portion 14 is longer than 7F in the data transfer line BL direction, but of course, a longer linear dense metal pattern is sufficient, and the via contact 16 and the data The following holds even in a structure in which the transfer line lead-out portion 14 is omitted, the data transfer line BL is considered as wiring, and a direct contact is formed. The data transfer line BL, via contact 17, and source line SL2 are made of a metal such as Al or Cu.

The data transfer lines BL are arranged at very dense intervals of 2 to 3F with the minimum machining dimension F perpendicular to the III-III direction. For example, about 530 data transfer lines BL are configured as one memory cell array. There is. Further, the source shunt line SH1 and the well shunt line SH2 connected to the contact with the semiconductor substrate 26 and the contact with the source line SL are arranged between the memory cell array (for example, every about 530 data transfer lines). The source line SL0 is formed in the II-II direction and serves as a ground wire for the source line SL between the data transfer lines BL. Further, in the direction orthogonal to the II-II direction (II direction), the ground wire of the source line is formed by the source line SL2 as shown in the II-II cross section. These source lines SL2, SL2E1 and source shunt line SH1 form a source line ground wiring in a grid pattern. The source line SL2 is arranged in the direction perpendicular to the III-III direction, for example, on the source shunt line SH1 so that wiring having a width of about 15 to 20F does not cover the memory cell array. Further, assuming that one block is one block in which 16-bit memory cells are arranged in series between the bit line side selection gate transistor SGD and the source line side selection gate transistor SGS, about 2048 blocks are arranged in the II direction. From this, it is easy to imagine that the source line SL2 is also long enough.

The source line SL2 is arranged between the memory cell array in the direction perpendicular to the line III-III as before. In addition, in the first embodiment, the source line SL2 is arranged in the direction of the line III-III. Hereinafter, this part will be referred to as "source line SL2 element 1 (SL2EL1)". In addition, the source line SL2 element 1 formed so as to extend in the III-III direction is arranged so as to be a constant multiple of the period of the NAND column in the II direction, and the source line SL2 covers the memory cell array. Not located on the bit line side select gate transistor SGD and source line side select gate transistor SGS in the III-III direction, or only in the region between the bit line side select gate transistor SGD and the source line side select gate transistor SGS. .. To reduce the resistance in the III-III direction, the coverage of SL2E1 (source line 2 element 1) in the NAND column should be placed in all areas between the bit line side selection gate transistor SGD and between the source line side selection gate transistor SGS. Can be made uniform, the influence of SL2E1 (source line 2 element 1) formation can be made uniform, and although it is desirable for resistance reduction, the following characteristics can be obtained even with a constant multiple of the period of the NAND column in the II direction. .. Alternatively, it may be formed only between the source line side selection gate transistors SGS, or may be formed between the bit line side selection gate transistors SGD. Further, the difference from the conventional example is that SL2E1 (source line 2 element 1) is formed inside the memory cell array.

In the present embodiment, the source line SL2 does not cover the memory cell array. Therefore, hydrogen diffused from above the memory cell is not shielded by the source line SL2, and the uniformity of memory cell reliability can be ensured. Further, since the source wiring 2 is connected in a grid pattern, the resistance of the wiring can be reduced.

Further, since the source line SL2 can be arranged on both the bit line side selection gate transistor SGD and the source line side selection gate transistor SGS as compared with the conventional example, the source line SL0 and the source line SL2 in the III-III direction can be arranged. Even when the wiring widths are equalized, the wiring resistance can be reduced to 0.5 times or less. Furthermore, as the source line SL2, for example, a low resistivity wiring material such as Al or Cu is used, and as the source line SL0, a refractory metal such as W, TiN, WSi or a barrier metal, which is more than twice as high as the former source line SL2. When a wiring material having a resistivity is used, the resistance reduction between the source lines can be further increased. Further, in order to realize the low resistance in the III-III direction, it is not necessary to form the source line SL0 thickly as in the case where the low resistance is realized only by the source line SL0 as in the conventional example. Therefore, it is not necessary to form the source line SL0 on the memory cell, and if it is formed in the range on the selection gate line SGL as shown in FIGS. 5 and 7, the voltage rise of the source line can be suppressed. Therefore, it is possible to reduce the variation in characteristics in the memory cell caused by shielding the hydrogen diffused from above by the pattern of the source line SL0 as compared with the conventional example. Further, it is possible to prevent the problem that the potential of the memory cell changes depending on the potential of the source line SL0. Further, in particular, in a non-volatile semiconductor memory in which a positive potential is applied to the wells in which the memory cells are formed to erase them, it is possible to keep the source line connected to the memory cells at a positive voltage equal to or higher than the well voltage. Required to prevent leakage current.

Therefore, the source line shunt transistor 3 is required as shown in FIG. 9 in order to realize both conductive and non-conducting states between the source line SL2 and the power supply wiring pad 5 at the ground potential. Here, as shown in FIG. 9, when the number of source line shunt transistors 3 is reduced from the number of source lines SL2 in the vertical direction of the paper surface and arranged at the end of the memory cell array, for example, the source lines in the III-III direction are used. It is desirable that the SL2 conductance is large because the potential rise of the source line is small. In this example, the wiring conductance in the III-III direction can be increased by the added SL2E1 (source line 2 element 1) x (the number of additional elements) compared to the conventional example, and the memory array cell can be increased as in the conventional example. There is a large resistance reduction effect compared to the case where wiring in the III-III direction is added only to the end.

Furthermore, since SL2E1 (source line 2 element 1) is formed in a grid shape, there is a cross section of wiring in both the II direction and the III-III direction. Therefore, even when a substance having poor adhesion such as SiOF (fluoridated correlated silicon insulating film), SiC, HSQ, or MSQ is used as the wiring base, the surface area increases in the cross section and the adhesion is improved. Therefore, the problem of peeling is less likely to occur.

As shown in FIG. 6, the width z of SL2E1 (source line 2 element 1) is z / 2, where y is the distance from the interface between the tunnel insulating film of the memory cell and the semiconductor substrate 26 to the source line SL2. It is desirable to form so that &lt;y, and it is desirable to form z at 0.1 μm or more and 2 μm or less. This is because, after the formation of the source line SL2, a passivation film such as a silicon nitride film is usually formed, and hydrogen generated at that time is also diffused into the memory cell. When the source line SL2 does not cover the memory cell array, the diffused hydrogen easily reaches the gate insulating film and is trapped in the insulating film to repair some of the defects in the insulating film. Brings. Further, by reaching the interface between the insulating film and the substrate, the interface state is terminated, the threshold value of the nMOS transistor is lowered, and the subthreshold coefficient is reduced. Here, when hydrogen diffuses isotropically as in the case where a heat step is applied after the passivation film is formed, when z / 2 &lt;y, the diffusion length of hydrogen from the passivation becomes y or more. Therefore, hydrogen diffuses to the gate insulating film of the transistor under SL2E1 (source line 2 element 1). Therefore, the location dependence of the hydrogen concentration distribution in the gate insulating film of the selective gate transistors SGD and SGS can be made uniform, and a more reliable semiconductor storage device can be realized.

Further, as is clear from FIG. 5, the source line SL2 is uniformly covered between the selection gate line SSL or the selection gate line SGL. Therefore, all data transfer lines BL maintain a substantially constant interlayer capacity with the source line SL2 at positions between the selected gate line SSL or the selected gate line SGL. Therefore, the variation in the capacitance between the data transfer lines BL can be reduced, and the variation in the data transfer line of the CR time constant of the data transfer line at the time of reading can be reduced. Therefore, it is possible to reduce the margin at the timing of reading, and to realize a faster semiconductor storage device. In addition, the amount of charge charged and discharged from the data transfer line can be kept low, and high-speed reading can be realized with low power consumption. As for the data transfer line BL in the memory cell array area, the source line SL2 is formed only between the selected gate line SSL or the selected gate line SGL, so that the capacitance coupling between the source line SL2 and the data transfer line BL is established. It becomes smaller. Therefore, the capacity of the data transfer line can be reduced to almost the same level as in the conventional example.

(Production method) An example of a manufacturing method for realizing the non-volatile semiconductor storage device according to the first embodiment of the present invention will be described with reference to FIGS. 14 to 65.

(a) First, on a first conductive semiconductor substrate or well 26 having a depth of, for example, 0.3 μm to 2 μm, an element separation region 12 made of a silicon insulating film or a silicon nitride film is formed, for example, from 0.1 μm to 0.4. It is formed at a depth of μm. The depth of the element separation region 12 is a depth at which adjacent second conductive element regions 10 are separated from each other via the element separation region 12. In the figure, the first conductive type is p-type and the second conductive type is n-type, but of course, the first conductive type may be n-type and the second conductive type may be p-type. In such a structure, the element separation region 12 is formed at the same pitch as the data transfer line contact CB formed later in the II line direction, and has a depth shallower than the element separation region 12, for example, a depth of 0.05 μm to 0.3 μm. By adding an impurity having conductivity opposite to that of the semiconductor substrate 26 on the semiconductor surface, the diffusion layer (n-type region) 18 of each semiconductor surface separated by the element separation region 12 is connected to each wiring. Further, the plurality of n-type regions 18 on the semiconductor surface can be electrically separated from each other. In addition, the process of forming such a contact opening becomes a problem especially with a design rule of 0.13 μm or less that resolves using a phase shift mask in a KrF or ArF exposure device, and the pitch of this contact is 0.13 μm × 2F = 0.26. It is desirable that it is F μm or less. Subsequently, a conductor film such as polycrystalline silicon or tungsten silicide doped with impurities such as P at a high concentration is voluminous at about 500 nm to 1000 nm, and then the data transfer line BL is patterned by lithography and patterned by anisotropic etching. ..

(b) Next, a barrier insulating film 22 made of a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film is deposited in the range of 10 nm to 1000 nm. Here, if the etching controllability is insufficient during the formation of the source line contact CS and the data transfer line contact CB and excessive etching is performed, the source line contact CS and the data transfer line contact CB fall into the element separation region 12 and p-type wells are formed. There is a problem that the withstand voltage between 26 and the source line contact CS and the data transfer line contact CB cannot be secured. On the other hand, if etching is insufficient when forming the source line contact CS and the data transfer line contact CB, there arises a problem that the contact resistance between the n-type region 18 and the data transfer line contact CB increases. Therefore, when forming this data transfer line contact, the barrier insulating film 22 is etched under the condition that the etching speed is slow and the selective ratio can be obtained with respect to the interlayer insulating film 23, and then the barrier insulating film 22 is etched thereafter. It is possible to reduce the influence of the film thickness variation of the interlayer insulating film 23 during contact etching. Further, before depositing the barrier insulating film 22, a silicon insulating film in the range of 1 nm to 50 nm may be formed on the surface of the semiconductor substrate 26 by an oxidation or deposition method. Further, an interlayer insulating film 23 composed of a silicon insulating film, a silicon nitride film, silicade glass such as BPSG, PSG, and an interlayer film such as HSQ, MSQ, and SiLK is deposited on the film at about 10 nm to 1000 nm (FIGS. 14 to 17). ). The material of the barrier insulating film 22 needs to have an etching selectivity with respect to the interlayer insulating film 23. The thickness of the barrier insulating film 22 is about 10 to 1000 nm, and a thickness having a sufficient processing margin is required depending on the thickness of the interlayer insulating film 23 and the etching selectivity.

(c) Next, the data transfer line contact CB and the source line contact CS are patterned by lithography, and the interlayer insulating film 23 is patterned by anisotropic etching (FIGS. 18 to 21). The etching conditions need to have a selective ratio with respect to the resist 58 and the barrier insulating film 22.

(d) Then, after removing the resist 58, the barrier insulating film 22 is anisotropically etched (FIGS. 22 to 25). At this time, setting the condition to have a selective ratio with respect to the semiconductor substrate 26 and the interlayer insulating film 23 does not require a wet step of peeling the barrier insulating film 22 as a post-process, and is applied to the interlayer insulating film 23. It is desirable because there is no setback, the forward taper is maintained, and the contact diameter can be kept small.

(e) After patterning, the source line contact CS and the data transfer line contact CB are heavily doped with, for example, phosphorus or arsenic impurities (polycrystalline silicon (wiring layer and another material (second contact embedding material 70))). It is embedded in and etched back by anisotropic etching or isotropic etching such as chemical dry etching (CDE) (Figs. 26 to 29). Higher aspect ratios of source line contact CS and data transfer line contact CB tend to result in inadequate coverage of barrier metal 64 and embedded metal (second contact embedding material 70), resulting in anomalous embedding metal deposition and The leakage current between the contact and the semiconductor substrate 26 (or lower layer wiring) increases.

In the non-volatile semiconductor storage device according to the first embodiment of the present invention, since the source line contact and the data transfer line contact CB are embedded in a semiconductor such as polycrystalline silicon, a barrier is formed in the data transfer line contact CB portion having a high aspect. No metal is required. Therefore, it is possible to prevent an increase in leakage current due to insufficient coverage of the barrier metal, and since the lower part of the data transfer line contact CB is embedded first, the aspect for embedding the wiring layer and the upper part of the data transfer line contact CB is small. Therefore, the barrier metal and the embedding characteristics of the metal are improved. Further, since a semiconductor such as polycrystalline silicon is embedded, it is not necessary to implant n-type impurities into the bottom of the data transfer line contact CB, and a data transfer line contact CB having a very shallow junction depth can be formed. Therefore, the punch-through withstand voltage between the n-type diffusion layers 18 forming the data transfer line contact CB can be improved. Furthermore, when polycrystalline Si or SiGe, or amorphous Si or SiGe is used for the second contact embedding material 70, Si or SiGe can be embedded by a CVD method with much better coverage than metal, resulting in a high aspect. It can be stably embedded even in the structure. When polycrystalline Si or SiGe is used for the second contact embedding material 70 to which impurities have been added, the impurities are diffused to the semiconductor substrate 26 to provide stable contact resistance without re-diffusion ion implantation. Obtainable. Further, since the barrier metal is not required for embedding the lower part of the contact, stable contact resistance with the n-type region can be realized even if the contact becomes finer.

(f) Next, the substrate contact SB is patterned by lithography, and the interlayer insulating film 23 is patterned by anisotropic etching to form the substrate contact SB opening 38 (FIGS. 30 to 33). At this time, since it is important that the resist is embedded and protected inside the data transfer line contact CB and the source line contact CS formed earlier, the etching condition should be a selection ratio for the resist and the barrier insulating film 22. It is necessary to have the conditions to have.

(g) Then, after removing the resist 58, the barrier insulating film 22 is anisotropically etched (FIGS. 34 to 37). At this time, it is a wet step of peeling the barrier insulating film 22 as a post-process that the condition has a selective ratio with respect to the semiconductor substrate 26, the interlayer insulating film 23, and the second embedded material 70 embedded earlier. It is desirable because it does not require a recess, does not recede with respect to the interlayer insulating film 23, maintains a forward taper, and keeps the contact diameter small.

(h) After this, for example, phosphorus and arsenic impurities are added, for example, 1 × 10.¹³cm^-2Above 1 × 10¹⁶cm^-2Ion implantation may be performed with the following dose to reduce the resistivity of the n-type region of the contact portion.

(i) After that, patterning of lithography for the source line SL0 and the data transfer line lead-out portion 14 is performed, and the interlayer insulating film 23 is patterned by anisotropic etching (FIGS. 38 to 41).

(j) After etching the groove in which the source line SL0 and the data transfer line lead-out portion 14 are embedded, the resist 58 is removed, and the barrier metal 64 such as Ti, Ta, TaN, TiN is placed in the range of 1 nm to 100 nm, for example, sputtering or CVD. After depositing in the contact and wiring layer by the method, a metal material such as tungsten, aluminum and copper is deposited to a thickness of 10 nm to 1000 nm to embed the contact and wiring layer. It should be noted that the wiring groove formation for the source line SL0 and the data transfer line leader portion 14 described in FIGS. 14 to 41, the process of forming the contact opening of the data transfer line BL portion, and the contact opening of the source line SL portion The forming process may be performed in any order. However, when the contact diameter is small, it is difficult to perform high-resolution lithography on the stepped substrate. Therefore, at least the method of opening the data transfer line contact CB first, and preferably the first embodiment of the present invention. It is desirable to open in the order described in the form of. After that, it is flattened by chemical mechanical polishing technology (CMP) or the like (Figs. 42 to 45). As the barrier metal 64, the CVD method is preferable because it can be uniformly deposited in contact holes having a higher aspect.

(k) After that, an interlayer insulating film 23 composed of a silicon insulating film, silicade glass such as BPSG and PSG, and an interlayer film such as HSQ, MSQ and SiLK is deposited at about 10 nm to 1000 nm.

(l) Next, the first via contact 16 is patterned by lithography, and the interlayer insulating film 23 is patterned by anisotropic etching (FIGS. 46 to 49). The etching conditions need to have a selective ratio with respect to the wiring material 69 (metal) or the barrier metal 64 embedded in the resist 58 and the lower layer contact.

(m) Then, after removing the resist 58, barrier metals 64 such as Ti, Ta, TaN, and TiN were deposited in the range of 1 nm to 100 nm in the first via contact 16 by, for example, sputtering or CVD method, and then W, Metallic materials such as Al and Cu are deposited with a thickness of 10 nm to 1000 nm, and via contact 16 is embedded. After that, it is etched back by CMP or the like and flattened (FIGS. 50 to 53).

(n) After that, for example, Al and AlCu are deposited at about 10 nm to 1000 nm.

(o) Further, Al or AlCu is processed into strips in the II line direction by anisotropic etching to form the data transfer line BL and the source shunt line SH1.

(p) After that, an interlayer insulating film 23 composed of a silicon insulating film, a silicon nitride film, silicade glass such as BPSG, PSG, and an interlayer film such as HSQ, MSQ, and SiLK is deposited at about 10 nm to 1000 nm (Fig. 54 to 1000 nm). Figure 57).

(q) Next, the second via contact 17 is patterned by lithography, and the interlayer insulating film 23 is patterned by anisotropic etching (FIGS. 58 to 61). The etching conditions need to have a selectivity for the metal or barrier metal 64 embedded in the resist 58 and the underlying contact.

(r) Then, after removing the resist 58, a barrier metal 64 such as Ti, Ta, TaN, TiN is applied in the range of 1 nm to 100 nm, for example, in the second via contact 17 and on the interlayer insulating film 23 by a sputtering method or a CVD method. After the deposition, metal materials such as W, Al, and Cu are deposited with a thickness of 10 nm to 1000 nm, and at the same time as embedding in the second via contact 17, they are also deposited as a wiring material for the source line SL2 (Figs. 62 to 62). Figure 65). Of course, as shown in the manufacturing method of the first via contact 16 and the data transfer line BL, the inside of the contact is made of a barrier metal 64 such as Ti, Ta, TaN, TiN in the range of 1 nm to 100 nm, for example, by sputtering or CVD method. After deposition, metal materials such as W, Al, and Cu are deposited to a thickness of 10 nm to 1000 nm, and after embedding the second via contact 17 and flattening with CMP or the like, Al and AlCu are used as wiring materials at 10 to 1000 nm. Although there is a method of depositing to some extent, in the first embodiment of the present invention, the process process can be simplified by simultaneously depositing the conductive material of the second via contact 17 and the second source line SL2. It shows that there is.

(s) Finally, the shape of the non-volatile semiconductor storage device according to the first embodiment of the present invention can be obtained by processing the deposited Al, AlCu, etc. of about 10 nm to 1000 nm by anisotropic etching by lithography. (Figs. 62 to 65).

Although details are omitted below, for example, by depositing a passivation of a silicon nitride film or polyimide formed by a plasma deposition method on the source line SL2, for example, about 0.05 to 2.0 μm, alpha rays, ultraviolet rays, the atmosphere, etc. We try to reduce the effects of external stress. As the silicon nitride film, a silicon nitride film formed by using hexachlorodisilane (HCD) may be used.

In the non-volatile semiconductor storage device according to the first embodiment of the present invention, when patterning the source line SL2, the source lines SL2 between the cell array extending in the II line direction are formed in III- of about 1 μm as compared with the conventional conditions. The wiring resistance of the source line SL2 itself can be reduced by directly connecting with the additional wiring of the source line SL2 in the direction of line III. Further, the additional wiring connected between the source lines SL2 is arranged on the bit line side selection gate transistor SGD and the source line side selection gate transistor SGS and does not cover the memory cell array area 1, so that it is an upper layer. When hydrogen diffuses from the portion, the hydrogen distribution reaching the cell is uniform, so that it is possible to suppress an abnormality in the distribution of cell reliability.

(Modified example of the first embodiment) 10 to 13 show schematic plane pattern diagrams of one plane of the memory cell array region of the non-volatile semiconductor storage device according to the first to fourth embodiments of the present invention.

In the modified examples 1 to 4 of the first embodiment of the present invention, SL2EL2 (source line 2 element 2) is arranged in a grid shape between SL2EL1 (source line 2 element 1) as shown in FIGS. 10 to 13. Has been added. The difference between the modified examples 1 to 4 is that, as shown in FIGS. 10 to 13, the pitch of SL2E2 arranged between SL2E1 and the shape of the grid-like pitch are different. For example, in FIG. 10, SL2E2 is arranged in a substantially grid pattern and every other SL2E2. On the other hand, in FIG. 11, SL2E2 are arranged in a row in the diagonal direction. Further, in FIG. 12, SL2E2 are regularly arranged in the diagonal direction and in the crossing direction. Further, in FIG. 13, SL2E2 is formed as a wide region, the space between SL2E1 is filled with SL2E2, and SL2E1 is arranged at a predetermined pitch.

Since SL2EL2 (source line 2 element 2) is formed in a grid shape, in either the cross-sectional structure in the line II direction in which the data transfer line BL extends or the cross-sectional structure in the line III-III direction in which the data selection line WL extends. There is also a cross section of the source line SL2. Therefore, even when a substance having poor adhesion such as SiOF (fluoridated correlated silicon insulating film), SiC, HSQ, or MSQ is used as the wiring base, the surface area increases in the cross section and the adhesion is improved. Therefore, the problem of peeling is less likely to occur.

Further, it is desirable to form the width r of SL2EL2 (source line 2 element 2) so that the distance from the tunnel insulating film 44 of the memory cell to the source line SL2 is y and r / 2 &lt;y. For example, it is desirable to form r at 0.1 μm or more and 2 μm or less.

After the formation of the source line SL2, a passivation film such as a silicon nitride film is usually formed, but the hydrogen generated at that time is also diffused into the memory cell. When the source line SL2 does not cover the memory cell array region 1, the diffused hydrogen easily reaches the tunnel insulating film (gate insulating film) 44 and is trapped in the tunnel insulating film 44 to form a tunnel. It has the effect of repairing some of the defects in the insulating film 44. Further, by reaching the interface between the tunnel insulating film 44 and the semiconductor substrate 26, the interface state is terminated, the threshold value of the nMOS transistor is lowered, and the subthreshold coefficient is reduced. Here, when hydrogen diffuses isotropically as in the case where a heat step is applied after the passivation film is formed, when r / 2 &lt;y, the diffusion length of hydrogen from the passivation film is y or more. Therefore, hydrogen diffuses to the gate insulating film of the transistor under SL2EL2 (source line 2 element 2). Therefore, the location dependence of the hydrogen concentration distribution in the gate insulating film of the bit line side selective gate transistor SGD and the source line side selective gate transistor SGS can be made uniform, and a more reliable semiconductor storage device can be realized.

Further, in the non-volatile semiconductor storage device according to the first to fourth embodiments of the present invention, the low resistance SL2EL2 (source line 2 element 2) is formed in the II direction as well. The resistance in the II direction can be reduced.

Further, in the modified examples 1 to 4 of the first embodiment of the present invention, all the data transfer lines BL are all over the data transfer line BL by arranging SL2EL2 (source line 2 element 2) on the grid. The ratio of the source line SL2 formed on the data transfer line BL can be reduced to less than half as compared with the case where the source line SL2 is covered. Therefore, the capacitance coupling between the source line SL2 and the data transfer line BL becomes small, and the capacitance of the data transfer line BL can be reduced as compared with the case where the source line SL2 is formed on one surface of the data transfer line BL. Therefore, the amount of charge for charging / discharging the data transfer line BL can be suppressed to be relatively small, the time required for charging / discharging can be shortened, and high-speed reading can be realized with low power consumption. Further, in the modified examples 1 to 4 of the first embodiment of the present invention, the ratio of being covered by the source line SL2 is uniform in all the data transfer lines BL extending in the vertical direction of the paper surface. As a result, the variation in capacitance between the data transfer lines BL can be reduced as compared with the case of the conventional example shown in FIG. Therefore, the variation in the CR time constant of the data transfer line BL at the time of reading can be suppressed by the amount that the variation in the capacitance of the data transfer line BL can be reduced. Therefore, the timing margin at the time of reading can be further reduced, and a higher-speed non-volatile semiconductor storage device can be realized.

(Second embodiment) FIG. 66 shows an enlarged schematic plane pattern in the memory cell array region 1 of the non-volatile semiconductor storage device according to the second embodiment of the present invention. Further, in FIG. 66, the schematic element cross-sectional structure in the line II direction is shown in FIG. 67, the schematic element cross-sectional structure in the line II-II direction is shown in FIG. 68, and the schematic element cross-sectional structure in the line III-III direction is shown in FIG. 69. Each is shown in. Hereinafter, the same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. It goes without saying that the non-volatile semiconductor storage device according to the second embodiment of the present invention can be arranged with various source electrodes depending on the arrangement shape of the source lines SL2 and SL2E1 and SL2E2. Therefore, by adopting the same source electrode arrangement as in FIGS. 10 to 13, it is possible to obtain the same effect as that described in the modified examples 1 to 4 of the first embodiment.

The difference from the non-volatile semiconductor storage device according to the first embodiment shown in FIGS. 5 to 9 is that it is also on the memory cell array area 1 for the purpose of positively reducing the wiring resistance of the source line SL2. This is the point where the additional wiring section SL2A for the source line is located. Since the potential of the source line SL2 is transferred in the direction of line II, the effect is not sufficient even if it is connected by additional wiring in the direction of line III-III (direction perpendicular to the direction of line II) for the purpose of reducing resistance. There may be cases. Therefore, in the non-volatile semiconductor storage device according to the second embodiment of the present invention, as shown in FIG. 66, the additional wiring flows in the II line direction by forming the source line additional wiring portion SL2A in a stepped shape. It reduces the wiring resistance with respect to the current. In addition, FIG. 70 shows a specific element (EL) pattern configuration of the source line SL2 in the NAND memory cell column portion. In FIG. 70, the pattern of SL2E2 (source line 2 element 2) of one NAND block part is shown by a broken line. In FIG. 70, as an example, a NAND block consisting of 32 data selection lines WL and one selection gate line SSL and SGL is shown, and memory is stored at the intersection of each element area and the memory cell data selection line WL. A cell is formed.

A feature of the non-volatile semiconductor storage device according to the first embodiment of the present invention is that SL2E2 (source line 2 element 2) is formed in a stepped manner in one NAND block portion. That is. In particular, the number of data selection lines WL (16 in the figure) included in the range of width a shown in FIG. 70, and the data included in the range of width b and the range of width c shown in FIG. 70. The sum of the number of selection lines WL (8 + 8 = 16 in the figure) is made almost equal, and the coverage of the source line SL2 formed on the upper part of one NAND row is made almost uniform. In this way, for the NAND columns included in all the data transfer lines BL, the coverage of the source line SL2 formed on the upper part of one NAND column is almost uniform. Further, in the non-volatile semiconductor storage device according to the second embodiment of the present invention, by matching the layout pattern of the source line SL2 with the cell pitch, the area of the source line SL2 covering per single cell is the selection gate. When viewed within the area (= 1 block) defined between the line SSL / selected gate line SGL and between the source line SL2, the ratio can be secured to be constant. Therefore, even if hydrogen diffuses from the upper layer and is trapped by the barrier metal 64 of the source line SL2 and the hydrogen does not reach the gate insulating film of the lower layer, as described above, the layout of the source line SL2 can be adjusted to the cell pitch. The non-uniformity can be suppressed as compared with the modified examples 1 to 4 of the first embodiment of the present invention. Further, since the coverage of the source line SL2 formed on the upper part of each NAND row is made almost uniform, SL2E2 (source line 2 element) is more than the modified examples 1 to 4 of the first embodiment of the present invention. The period in the block direction of 2) can be made finer. Therefore, since the periodicity with respect to the data transfer line BL can be secured at the same time, there is a feature that the load capacitance between the data transfer lines BL is unlikely to differ.

In FIG. 70, the structure includes 16 memory cell data selection lines WL as the width a and the width (b + c), but it may be a divisor of the number of NAND columns. For example, if the number of NAND columns is 32, it may be 16, 8, 4, or 2. However, since the thick source line SL2 is processed, the minimum processed line width of the source line SL2 is usually four times or more larger than the minimum processed line width of the memory cell, which is sufficiently large. Therefore, any of 2, 4, 8 or 16 is desirable, and the line width is preferably 0.1 μm or more. The width d of SL2EL2 (source line 2 element 2) in the data selection line WL extension direction does not have to be uniform, but it is preferably 0.1 μm or more and 2 μm or less in order to sufficiently diffuse hydrogen into the memory cells below it. ..

Since the manufacturing method is almost the same as the manufacturing steps of FIGS. 14 to 65 described in the first embodiment of the present invention, the description thereof will be omitted. After the formation of the second via contact 17, a barrier metal 64 such as Ti, Ta, TaN, TiN is deposited in the range of 1 nm to 100 nm, for example, in the second via contact 17 and on the interlayer insulating film 23 by a sputtering method or a CVD method. After that, metal materials such as W, Al, and Cu are deposited with a thickness of 10 nm to 1000 nm, and at the same time as embedding in the second via contact 17, they are also deposited as a wiring material for the source line SL2. After that, by forming the patterning by the lithography process in a desired stepped shape, the layout of the source line SL2 shown in the non-volatile semiconductor storage device according to the second embodiment of the present invention can be easily obtained (FIGS. 66 to 66 to 6). Figure 70).

(Third embodiment) FIG. 71 shows an enlarged schematic planar pattern in the memory cell array region 1 of the non-volatile semiconductor storage device according to the third embodiment of the present invention. Further, in FIG. 71, the schematic element cross-sectional structure in the line II direction is shown in FIG. 72, the schematic element cross-sectional structure in the line II-II direction is shown in FIG. 73, and the schematic element cross-sectional structure in the line III-III direction is shown in FIG. 74. Each is shown in.

The difference from the non-volatile semiconductor storage device according to the second embodiment of the present invention shown in FIGS. 66 to 70 is that the source line additional wiring unit SL2A is not only connected in a stepped manner, but also the wiring resistance is further reduced. The point is that additional wiring is added in a grid pattern for the purpose of doing so. In addition, by adjusting the additional wiring to the cell pitch, the periodicity for the memory cell and the data transfer line BL can be ensured, and the influence of hydrogen diffused in the passivation process on the memory cell and the load capacity on the data transfer line BL can be ensured. Uniformity can be ensured. The method for manufacturing the non-volatile semiconductor storage device according to the third embodiment of the present invention is substantially the same as the method for manufacturing the non-volatile semiconductor device according to the first embodiment described so far in FIGS. 14 to 65. Is similar to. As shown in FIG. 71, the shape of the third embodiment of the present invention can be easily obtained by arranging the lithography pattern of the second source line SL2 in a grid pattern. Since the effect on the non-volatile semiconductor storage device according to the third embodiment of the present invention is the same as the modified examples 1 to 3 of the first embodiment, it will be omitted.

(Modified example of the third embodiment) FIG. 75 shows an enlarged schematic plane pattern in the memory cell array region of the non-volatile semiconductor storage device according to the modified example of the third embodiment of the present invention. Further, in FIG. 75, the schematic element cross-sectional structure in the line II direction is shown in FIG. 76, the schematic element cross-sectional structure in the line II-II direction is shown in FIG. 77, and the schematic element cross-sectional structure in the line III-III direction is shown in FIG. 78. Each is shown in.

The source line additional wiring unit SL2A described in the third embodiment shown in FIGS. 71 to 74 was laid out in a grid pattern with a cell pitch, whereas in this modification, an integral multiple of the cell pitch, for example, , It is characterized by having a pattern in which source lines SL2 are connected in a grid pattern every 4 cells (2X2). The effect is the same as when connecting at a cell pitch, but a lithography margin can be secured by increasing the wiring width. In this modification, the source line SL2 is connected every 4 cells, but if additional wiring is connected periodically in a grid pattern, any wiring width such as every 6 cells or every 8 cells can be used. It doesn't matter. The manufacturing method is the same as that of the first embodiment or the third embodiment described so far, and the lithography pattern of the source line SL2 is easily arranged in a grid pattern as shown in FIG. A modified embodiment of the third embodiment of the invention can be obtained. The effect on the non-volatile semiconductor storage device according to the modified example of the third embodiment of the present invention is the same as that of the modified examples 1 to 4 of the first embodiment, and thus is omitted.

(Fourth Embodiment) FIG. 79 shows an enlarged schematic planar pattern in the memory cell array region of the non-volatile semiconductor storage device according to the fourth embodiment of the present invention. Further, in FIG. 79, the schematic element cross-sectional structure in the line II direction is shown in FIG. 80, the schematic element cross-sectional structure in the line II-II direction is shown in FIG. 81, and the schematic element cross-sectional structure in the line III-III direction is shown in FIG. 82. Each is shown in.

The difference between the second embodiment of the present invention shown in FIGS. 66 to 70 and the third embodiment of the present invention shown in FIGS. 71 to 74 is that the source line additional wiring SL2A is stepped and laddered. It is a point that is not connected in a shape, but is connected by a "diagonal line". Here, the "diagonal line" indicates that there is a component that is diagonal to the data transfer line direction and the data selection line direction, and may be a straight diagonal line or a fine structure. This includes the case where it has a fine stepped shape.

In the non-volatile semiconductor storage device according to the fourth embodiment of the present invention, SL2E2 (source line 2 element 2) has the same wiring width and periodic pattern pitch as compared with the second embodiment. 2 The peripheral length and total length of the wiring of element 2) can be reduced. Therefore, the resistance of the vertical component can be reduced to the minimum by connecting the wirings with "diagonal lines" as in the fourth embodiment of the present invention. Further, the damage applied to the wiring edge during processing of the source line SL2 can be reduced as compared with the case of the non-volatile semiconductor storage device according to the second embodiment, and the reliability can be improved.

In addition, Fig. 83 shows the specific pattern configuration of the element of the source line SL2 in the NAND memory cell column portion. In FIG. 83, the pattern of SL2E2 (source line 2 element 2) of one NAND block portion is shown by a broken line. In FIG. 83, as an example, a NAND block consisting of 32 data selection lines WL and one selection gate line SSL and SGL is shown, and memory is stored at the intersection of each element area and the memory cell data selection line WL. A cell is formed. The characteristic point as compared with the non-volatile semiconductor storage device according to the second embodiment of the present invention shown in FIGS. 66 to 70 is that SL2E2 (source line SL2 element 2) is contained in one NAND block portion. Is formed in an oblique shape. In particular, the number of data selection lines WL included in the range of width a in FIG. 83 (14 in the figure) and the number of data selection lines WL included in the range of width b and width c in FIG. The sum (12 + 2 = 14 in the figure) is made almost equal, and the coverage of the source line SL2 formed on the upper part of one NAND row is made almost uniform.

In this way, for the NAND columns included in all the data transfer lines BL, the coverage of the source line SL2 formed on the upper part of one NAND column is almost uniform. In FIG. 83, the structure includes 14 memory cell data selection lines WL as the width a and the width (b + c), but any number may be used as long as the width a is almost equal to the width (b + c). .. However, since the thick source line SL2 is processed, the minimum line width of the source line SL2 is usually sufficiently larger than the minimum line width of the memory cell by 4 times or more. Therefore, two or more lines are desirable, and the line width is preferably 0.1 μm or more and 2 μm or less. The width d of SL2E2 (source line 2 element 2) in the extending direction of the data selection line WL does not have to be uniform, but it should be 0.1 μm or more and 2 μm or less in order to sufficiently diffuse hydrogen into the memory cells below it. desirable. Further, as the angle of the diagonal line, 45 degrees is desirable for mask data processing.

Further, in the non-volatile semiconductor storage device according to the fourth embodiment of the present invention, as in the case shown in the second embodiment and the third embodiment, the source line covering the single cell. The additional wiring part SLA is devised so that it is constant within one block. Since the effect is as described in the second embodiment of the present invention, the description thereof will be omitted. Further, since the manufacturing method is also as described in the first embodiment, the description thereof will be omitted.

(Fifth Embodiment) (Virtual ground AND type) FIGS. 84 to 85 show the semiconductor storage device according to the fifth embodiment of the present invention. In the fifth embodiment of the present invention, the NAND memory cell unit 51 of the first to fourth embodiments is changed to the virtual grounded memory cell unit 83. The common parts from the first embodiment to the fourth embodiment are designated by the same reference numerals and the description thereof will be omitted.

FIGS. 84 and 85 are a schematic circuit configuration diagram and a schematic plane pattern diagram of the virtual grounded memory cell unit, respectively. In FIG. 84, the virtual grounded memory cell unit 83 is a first memory cell unit 80 connected between the local data lines 82a and 82b and a second memory cell unit connected between the local data lines 82b and 82c. Equipped with 81. Non-volatile memory cells M0a to M15a having a basic structure as shown in FIGS. 1 and 2 are connected in parallel with current terminals, and one end is connected to a data transfer line BL1a via a block selection transistor S1a. The other end is connected to the adjacent data transfer line BL2 via the block selection transistor S2. The control electrodes of the non-volatile memory cells M0a to M15a are connected to the data selection lines WL0 to WL15. Further, since one memory cell block is selected from a plurality of memory cell blocks along the data transfer line BL and connected to the data transfer line BL, the control electrode of the block selection transistor S1b is connected to the block selection line SSL. .. Further, the control electrode of the block selection transistor S2 is connected to the block selection line GSL. Further, the non-volatile memory cells M0b to M15b are formed adjacent to the non-volatile memory cells M0a to M15a in the extending direction of the data selection lines WL0 to WL10, respectively, and share the local data transfer line 82b with each other. As a result, a so-called virtual grounded memory cell unit 83 (dotted line area) is formed. Here, in the fifth embodiment, the block selection gate lines SSL and GSL are formed by wiring in the same layer as the data selection lines WL0 to WL15 of the memory cell element. Further, one virtual grounded memory cell unit 83 may have at least one block selection line, and it is desirable that the block selection line is formed in the same direction as the data selection line for high density. In the fifth embodiment, 16 = 2 in the virtual grounded memory cell unit 83.⁴An example in which one memory cell is connected is shown, but the number of memory cells connected to the data transfer line BL and the data selection line WL may be multiple, and 2ⁿThe number (n is a positive integer) is desirable for address decoding. In Figure 84, the gate control line 90 is used to make the cell structure easier to understand._WL0~90_WL15Only the structures below are shown.

Block selection line 90_SSLAnd 90_GSLAre connected to the selection gate lines SSL and GSL, respectively, and are formed in the same layer as the control lines WL0 to WL15 of the EEPROM. Here, as shown in FIGS. 84 and 85, the block selection transistor S1 has the n-type diffusion layers 85 and 85d as source or drain regions, and the block selection line 90._SSLIs formed as a MOSFET with the gate electrode as the gate electrode, and the block selection transistor S2 has the n-type diffusion layers 85 and 85s as the source or drain regions, and the block selection line 90._GSLIs formed as a MOSFET as a gate electrode.

In the fifth embodiment of the present invention, since the virtual grounded memory cell is used, the series resistance of the memory cell unit can be made small and constant, and the threshold value when the value is increased is stabilized. Suitable for. Further, depending on the direction of the flowing current, one bit can be stored and read out in the vicinity of two n-type diffusion layers for one transistor, which is desirable for high density. Further, in the fifth embodiment, in addition to the features from the first embodiment to the fourth embodiment, since the memory cells are connected in parallel, a large cell current can be secured. Data can be read at high speed.

In the first to fourth embodiments of the present invention, a non-volatile semiconductor storage device having a NAND memory cell unit as a basic structure of a memory cell array region has been described, but a similar power supply electrode arrangement configuration has a selection gate. The same can be applied to a non-volatile semiconductor storage device in which a virtual ground type memory cell unit in which memory cells are separated is used as the basic structure of a memory cell array area, and the same effect can be expected. it can.

(Modified example of the fifth embodiment) (AND type) 86 to 87 show a modification of the non-volatile semiconductor storage device according to the fifth embodiment of the present invention. FIG. 86 shows a schematic circuit configuration diagram of an example of an AND type memory cell unit, and FIG. 87 shows a schematic plane pattern diagram of an example of an AND type memory cell unit 100 corresponding to FIG. 86. The basic structure of the AND type memory cell unit is substantially the same as the virtual grounded AND type structure described in the fifth embodiment. That is, as is clear by comparing FIG. 84 and FIG. 86 or FIG. 85 and FIG. 87, one side of the virtual ground type memory cell unit 83 composed of the first memory cell unit 80 and the second memory cell unit 81. The AND type memory cell unit 100 is formed by taking out only the memory cell unit 80 or 81 of the above. Therefore, since the circuit configuration and the plane pattern configuration of the AND type memory cell unit 100 are substantially the same as those of the virtual ground type memory cell unit, the description thereof will be omitted.

In the first to fourth embodiments of the present invention, a non-volatile semiconductor storage device having a NAND memory cell unit as a basic structure of a memory cell array region has been described, but a similar power supply electrode arrangement configuration has a selection gate. The same can be applied to a non-volatile semiconductor storage device having an AND type memory cell unit in which memory cells are separated as a basic structure of a memory cell array area, and the same effect can be expected.

(Other embodiments) As mentioned above, the present invention has been described in accordance with the first to fifth embodiments, but the statements and drawings that form part of this disclosure should not be understood to limit the invention. Various alternative embodiments, embodiments and operational techniques will be apparent to those skilled in the art from this disclosure.

It goes without saying that the present invention includes various embodiments not described here.

The element separation membrane and the insulating film forming method itself use other methods for converting silicon into a silicon insulating film or a silicon nitride film, for example, a method of injecting oxygen ions into the deposited silicon or a method of oxidizing the deposited silicon. It doesn't matter. Further, the interpoly insulating film 42 is TiO.₂And Al₂O₃Alternatively, a tantalum insulating film, strontium titanate, barium titanate, lead zirconium titanate, a ZrSiO film, an HfSiO film, a ZrSiON film, or a laminated film composed of an HfSiON film may be used. The side wall insulating film and the mask insulating film may be any insulating film having oxidation resistance, for example, Al.₂O₃, ZrSiO film, HfSiO film, ZrSiON film, or HfSiON film, SiN film, SiON film, or a laminated film thereof. As an embodiment, a p-type silicon substrate is assumed as the semiconductor substrate 26, but instead, an n-type silicon substrate, an SOI silicon layer of an SOI substrate, or a single crystal semiconductor substrate containing silicon such as SiGe mixed crystal or SiGeC mixed crystal. It should be. Further, although the formation of the n-type MOSFET on the p-type semiconductor substrate 26 has been described, it may be replaced with the formation of the p-type MOSFET on the n-type semiconductor substrate. In that case, the n-type of the above-described embodiment is replaced with the p-type. , P-type may be read as n-type, and the doping impurity species As, P, Sb may be read as any of In and B. The gate electrode is a Si semiconductor, SiGe mixed crystal and SiGeC mixed crystal can be used, and a laminated structure of these can be used, and the control gate metal is SiO such as TiSi, NiSi, CoSi, TaSi, WSi, MoSi, polyside, Ti, Al, Cu, TiN. , W and other metals can be used. Further, although a new layout is shown for the source line SL2 in this example, the same layout may be used for the well shunt wiring of the memory cell array as well. In this case, the formed p-well potential of the memory cell becomes more constant. Therefore, for example, it is possible to suppress the floating of the well potential that occurs when the data transfer line required for reading or writing is boosted, and it is possible to reduce the timing margin until the well potential becomes constant. Therefore, reading and writing can be realized at higher speed.

In addition, various modifications can be made without departing from the gist of the present invention. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention relating to the reasonable claims from the above description.

<figref num="1">Schematic cross-sectional structure diagram of a floating gate type memory cell applied to the non-volatile semiconductor storage device of the present invention.</figref><figref num="2">Schematic cross-sectional structure diagram of a MONOS type memory cell applied to the non-volatile semiconductor storage device of the present invention.</figref><figref num="3">The circuit block diagram of the NAND type memory cell unit applied to the non-volatile semiconductor storage device of this invention.</figref><figref num="4">The plan pattern block diagram of the NAND type memory cell unit applied to the non-volatile semiconductor storage device of this invention.</figref><figref num="5">FIG. 3 is a detailed planar pattern configuration diagram of a memory cell array region of the non-volatile semiconductor storage device according to the first embodiment of the present invention.</figref><figref num="6">FIG. 3 is a detailed planar pattern configuration diagram of a memory cell array region of the non-volatile semiconductor storage device according to the first embodiment of the present invention.</figref><figref num="7">Schematic cross-sectional structural view along line II-II in FIG.</figref><figref num="8">Schematic cross-sectional structural view along lines III-III of FIG.</figref><figref num="9">FIG. 3 is an overall planar pattern configuration diagram of a memory cell array region of the non-volatile semiconductor storage device according to the first embodiment of the present invention.</figref><figref num="10">FIG. 5 is a planar pattern configuration diagram illustrating a detailed pattern of a source line of a memory cell array region of the non-volatile semiconductor storage device according to the first modification of the first embodiment of the present invention.</figref><figref num="11">FIG. 5 is a planar pattern configuration diagram illustrating a detailed pattern of a source line of a memory cell array region of a non-volatile semiconductor storage device according to a second modification of the first embodiment of the present invention.</figref><figref num="12">FIG. 5 is a planar pattern configuration diagram illustrating a detailed pattern of a source line of a memory cell array region of the non-volatile semiconductor storage device according to the third modification of the first embodiment of the present invention.</figref><figref num="13">FIG. 5 is a planar pattern configuration diagram illustrating a detailed pattern of a source line of a memory cell array region of a non-volatile semiconductor storage device according to a modification 4 of the first embodiment of the present invention.</figref><figref num="14">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="15">Schematic cross-sectional structural view along line II of FIG.</figref><figref num="16">Schematic cross-sectional structural view along line II-II in FIG.</figref><figref num="17">Schematic cross-sectional structural view along lines III-III of FIG.</figref><figref num="18">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="19">Schematic cross-sectional structural view along line II of FIG.</figref><figref num="20">Schematic cross-sectional structural view along lines II-II of FIG.</figref><figref num="21">Schematic cross-sectional structural view along lines III-III of FIG.</figref><figref num="22">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="23">Schematic cross-sectional structural view along line II of FIG.</figref><figref num="24">Schematic cross-sectional structural view along line II-II in FIG.</figref><figref num="25">Schematic cross-sectional structural view along lines III-III of FIG.</figref><figref num="26">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="27">Schematic cross-sectional structural view along line II of FIG.</figref><figref num="28">Schematic cross-sectional structural view along line II-II in FIG.</figref><figref num="29">Schematic cross-sectional structural view along lines III-III of FIG.</figref><figref num="30">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="31">Schematic cross-sectional structural view along line II of FIG.</figref><figref num="32">Schematic cross-sectional structural view along line II-II in FIG.</figref><figref num="33">Schematic cross-sectional structural view along lines III-III of FIG.</figref><figref num="34">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="35">Schematic cross-sectional structural view along line II of FIG.</figref><figref num="36">Schematic cross-sectional structural view along line II-II in FIG.</figref><figref num="37">Schematic cross-sectional structural view along lines III-III of FIG.</figref><figref num="38">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="39">Schematic cross-sectional structural view along line II of FIG. 38.</figref><figref num="40">Schematic cross-sectional structural view along lines II-II of FIG. 38.</figref><figref num="41">Schematic cross-sectional structural view along lines III-III of FIG. 38.</figref><figref num="42">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="43">Schematic cross-sectional structural view along line II of FIG.</figref><figref num="44">Schematic cross-sectional structural view along line II-II in FIG.</figref><figref num="45">Schematic cross-sectional structural view along lines III-III of FIG. 42.</figref><figref num="46">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="47">Schematic cross-sectional structural view along line II of FIG.</figref><figref num="48">Schematic cross-sectional structural view along lines II-II of FIG.</figref><figref num="49">Schematic cross-sectional structural view along lines III-III of FIG.</figref><figref num="50">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="51">Schematic cross-sectional structural view along line II of FIG.</figref><figref num="52">Schematic cross-sectional structural view along line II-II in Figure 50.</figref><figref num="53">Schematic cross-sectional structural view along lines III-III of FIG.</figref><figref num="54">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="55">Schematic cross-sectional structural view along line II of FIG. 54.</figref><figref num="56">Schematic cross-sectional structural view along line II-II in FIG. 54.</figref><figref num="57">Schematic cross-sectional structural view along lines III-III of FIG. 54.</figref><figref num="58">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="59">Schematic cross-sectional structural view along line II of FIG.</figref><figref num="60">Schematic cross-sectional structural view along line II-II in FIG.</figref><figref num="61">Schematic cross-sectional structural view along lines III-III of FIG.</figref><figref num="62">It is a figure explaining one step of the manufacturing method of the non-volatile semiconductor storage device which concerns on 1st Embodiment of this invention, and is the detailed plane pattern block diagram of the memory cell array area.</figref><figref num="63">Schematic cross-sectional structural view along line II of FIG.</figref><figref num="64">Schematic cross-sectional structural view along line II-II of FIG.</figref><figref num="65">Schematic cross-sectional structural view along lines III-III of FIG. 62.</figref><figref num="66">FIG. 3 is a detailed planar pattern configuration diagram of a memory cell array region of the non-volatile semiconductor storage device according to the second embodiment of the present invention.</figref><figref num="67">Schematic cross-sectional structural view along line II of FIG.</figref><figref num="68">Schematic cross-sectional structural view along lines II-II of FIG.</figref><figref num="69">Schematic cross-sectional structural view along lines III-III of FIG.</figref><figref num="70">The plan pattern block diagram explaining the detailed pattern of the source line of the memory cell array area of the non-volatile semiconductor storage device which concerns on 2nd Embodiment of this invention.</figref><figref num="71">FIG. 3 is a detailed planar pattern configuration diagram of a memory cell array region of the non-volatile semiconductor storage device according to the third embodiment of the present invention.</figref><figref num="72">Schematic cross-sectional structural view along line II of FIG. 71.</figref><figref num="73">Schematic cross-sectional structural view along line II-II in Figure 71.</figref><figref num="74">Schematic cross-sectional structural view along lines III-III of FIG. 71.</figref><figref num="75">FIG. 3 is a detailed planar pattern configuration diagram of a memory cell array region of a non-volatile semiconductor storage device according to a modified example of the third embodiment of the present invention.</figref><figref num="76">Schematic cross-sectional structural view along line II of FIG. 75.</figref><figref num="77">Schematic cross-sectional structural view along line II-II in FIG.</figref><figref num="78">Schematic cross-sectional structural view along lines III-III of FIG. 75.</figref><figref num="79">FIG. 3 is a detailed planar pattern configuration diagram of a memory cell array region of the non-volatile semiconductor storage device according to the fourth embodiment of the present invention.</figref><figref num="80">Schematic cross-sectional structural view along line II of FIG. 79.</figref><figref num="81">Schematic cross-sectional structural view along lines II-II of FIG. 79.</figref><figref num="82">Schematic cross-sectional structural view along lines III-III of FIG. 79.</figref><figref num="83">The plane pattern block diagram explaining the detailed pattern of the source line of the memory cell array area of the non-volatile semiconductor storage device which concerns on 4th Embodiment of this invention.</figref><figref num="84">The circuit block diagram of the virtual ground AND type memory cell array of the non-volatile semiconductor storage device which concerns on 5th Embodiment of this invention.</figref><figref num="85">FIG. 5 is a plan view of a virtual grounded AND type memory cell array of a non-volatile semiconductor storage device according to a fifth embodiment of the present invention.</figref><figref num="86">The circuit block diagram of the AND type memory cell array of the non-volatile semiconductor storage device which concerns on 6th Embodiment of this invention.</figref><figref num="87">The plan view of the AND type memory cell array of the non-volatile semiconductor storage device which concerns on 6th Embodiment of this invention.</figref><figref num="88">FIG. 3 is a detailed planar pattern configuration diagram of a memory cell array region of a non-volatile semiconductor storage device according to a conventional example.</figref><figref num="89">Schematic cross-sectional structural view along line II of FIG. 88.</figref><figref num="90">Schematic cross-sectional structural view along line II-II of FIG. 88.</figref><figref num="91">Schematic cross-sectional structural view along lines III-III of FIG. 88.</figref><figref num="92">FIG. 3 is an overall planar pattern configuration diagram of a memory cell array region of a non-volatile semiconductor storage device according to a conventional example.</figref><figref num="93">FIG. 3 is a detailed planar pattern configuration diagram of a memory cell array region when a wide source line is formed in the non-volatile semiconductor storage device according to the conventional example.</figref><figref num="94">Schematic cross-sectional structure diagram along the IV-IV line of FIG. 93.</figref><figref num="95">Schematic cross-sectional structure diagram along the VV line of FIG. 93.</figref><figref num="96">Schematic cross-sectional structure diagram along the VI-VI line of FIG. 93.</figref>

Code description

1 ... Memory cell array area 2 ... Data selection line control circuit 3 ... Source wire shunt transistor 4 ... sense amplifier or data latch 5 ... Power wiring pad 6 ... Semiconductor chip 7 ... SiN film 10 ... Element area (second semiconductor area) 12 ... Element separation area 14 ... Data transfer line lead-out section 15 ... Data transfer line wiring section 16 ... (first) via contact 17 ... (second) via contact 18 ... Diffusion layer (n-type region) 19 ... Diffusion layer (p-type region) 20 ... memory cell 22 ... Barrier insulating film 21,23,24,27 ... interlayer insulating film 26 ... p-type well or semiconductor substrate 28 ... Source wire contact CS opening 32 ... Data transfer line contact CB opening 34,36 ... Via contact opening 38 ... board contact SB opening 40 ... floating gate 42 ... Interpoly insulating film 44 ... Tunnel insulating film (gate insulating film) 46 ... Control gate electrode 48 ... Mask insulating film 49 ... Charge storage layer 51 ... NAND memory cell unit 52 ... Block insulating film 53 ... Memory cell array block 54 ... Source or drain electrode 58 ... resist 64 ... Barrier metal 69 ... Wiring material 70 ... Second contact embedding material (CB, CS) 80 ... 1st memory cell unit 81 ... 2nd memory cell unit 82a, 82b, 82c ... local data line 83 ... Virtual ground AND type memory cell unit 84_SSL... gate insulating layer 85,85_S,85_d... n-type diffusion layer 86 ... 1st charge storage layer 90_WL0~90_WL15... gate control line 90_SSL,90_GSL... block selection line 100 ... AND type memory cell unit M0, M1, M2, M3, ..., M14, M15, M0a ~ M15a, M0b ~ M15b ... Non-volatile memory cells SSL, SGL, GSL ... (block) Select gate line BL, BL1a, BL1b ... Data transfer line (bit line) WL, WL0, WL1, WL2, WL3, ..., WL14, WL15 ... Data selection line (word line) CS, CSL ... Source line contacts CB, CBL, CBL1a, CBL1b, CBL2 ... Data transfer line contacts SB ... board contact SGS, SGD, S1, S1a, S1b, S2 ... Selective gate transistor SL ... (common) source line SL0 ... (first) source line SL2 ... (second) source line SH1 ... Source shunt line SH2 ... Wel shunt line SL2A ... Source line additional wiring section SL2E1 ... Source line 2 Element 1 SL2E2 ... Source line 2 Element 2