Set of integrated capacitor arrangements, especially integrated grid capacitors

The present invention relates to an integrated capacitor structure that includes at least one circuit-effective main capacitor.

Due to the integrated structure, individual parts cannot be mechanically separated from each other without breaking the parts. In particular, a layer forming method and a layer patterning method are used as a technique for manufacturing an integrated structure.

The capacitor contains two electrodes facing each other with a dielectric placed between them. As an example of an integrated capacitor: --So-called MIM capacitors (metal-insulator-metal), --A stack capacitor, also called a sandwich capacitor, or --Gitter Capacitor There is.

The capacitance is effective in the circuit not only when it is parasitic, that is, when it is inherently inconvenient, but also when it is required as a function of the circuit structure. For example, a valid capacitor in the circuit is: --Block capacitor or protection capacitor, --Part of the switching circuit, --Charging capacitor, or --Accumulation of digital information Functions as.

<p> In the production of so-called BEOL (Back End Of Line) capacity or Far-BEOL capacity in the integrated form, the capacity value fluctuates considerably. This variation is caused by geometric differences based on process unevenness. Fluctuations occur within one semiconductor substrate or wafer, within one production batch, and within different production batches. When the capacitance value exceeds a predetermined specification limit, so-called production loss or even yield loss of the corresponding integrated circuit occurs.</p><p> An object of the present invention is to provide a set of capacitor structures that can be easily manufactured and whose capacitance is as close as possible to a predetermined desired capacitance. In particular, it is to provide a set of grid capacitors.</p>

<p> This problem is solved by a capacitor structure set having the characteristics provided in claim 1. Further forms are provided in the dependent claims.</p><p> The set according to the invention includes at least two integrated capacitor structures. At least two integrated capacitor structures are manufactured with the same geometric design or layout and each include a circuit-effective main capacitor and at least one modified capacitor. One capacitor structure includes a conductive bond between the modified capacitor and the main capacitor, where the conductive bond is generated after the manufacture of the main capacitor of this capacitor structure. Other capacitor structures include an electrically insulating cut between the same modified capacitor and the main capacitor, where the electrically insulating cut is manufactured by the geometric design.</p><p> If, for example, only 20% of the manufactured capacitor structure must be modified to obtain the desired capacitance, the cost is significantly reduced compared to modification means where the modification can only be performed by separating the capacitors. That is, in such a case, the capacitors would have to be locally separated in 80% of the capacitor structures.</p><p> In a further form, the bond is produced by local heating, which is a simple method, so that the components around the bond are protected from high heat loads. In addition, local heating, which is a simple method, can produce continuous bonds. Bonding by local heating can be performed at lower temperatures compared to the formation of cuts by local heating. Therefore, the heat load is small, especially when a plurality of bonds are manufactured on the semiconductor substrate.</p><p> Local heating is performed, for example, using laser light. This provides a means of increasing or decreasing the capacitance of the circuit-effective main capacitor by connecting the modified capacitors in parallel or in series. By this modification means, an integrated capacitor structure having a predetermined capacitance value can be produced by a simple method.</p><p> In a further form, the bond comprises two separate conductor path portions in which the dielectric is simply placed. The material of the conductor path and the dielectric is selected so that heating causes a material strain (Verwerfung) that penetrates the dielectric. For example, here, otherwise inconvenient "spyking" can be utilized for electrical coupling. In other forms, the dielectric comprises a dope atom that changes the conductivity of the dielectric upon heating. In this connection, activation of the dope atom can also be mentioned. However, there are also means to bond manufacturing, also called antifuse.</p><p> In the next further form, the circuit structure comprises at least one additional modified capacitor that is separated from or connected to the main capacitor.</p><p> The further form derives from the consideration that the capacitance values of the integrated capacitors originally produced at the same time are dispersed above and below the desired value. The correction may be made to the capacity value correction means for increasing the capacity value, or to the capacity value correction means for decreasing the capacity value. Even if it can be limited to a minimum. Further correction capacitors provide this second correction means as compared to the above correction capacitors in which the capacitors are connected in parallel.</p><p> In a further form, further cutting for the separation of the additional modified capacitors is produced by local heating. Local heating can be performed, for example, by shrinking the conductor path with a laser beam or with a surge current.</p><p> In another further form, the dielectric of the capacitor is formed by the dielectric between the metallized layers. The connection portion of the connection to the integrated semiconductor element of the integrated capacitor structure is located in the metallized layer. Other dielectrics, such as dielectrics with a high dielectric constant, can be used in the region of the capacitor rather than in the remaining region between the metallized layers. Examples of such capacitors are stack capacitors or grid capacitors. In other words, the electrodes of the capacitor are located within two or more metallized layers. In such a capacitor, at the time of formation, not only the electrodes in the upper metallized layer but also the electrodes in the lower metallized layer are circuit-separated or added in a circuit by modification. The coupling elements and cuts for the lower electrodes are located within the lower metallized layer, so that, for example, a corresponding deep cutout for laser light is provided. Alternatively, the coupling elements and cuts for the lower electrode are located in the upper metallized layer, which provides a connection to the lower metallized layer.</p><p> In another further form, the dielectric of the capacitor has a thickness substantially less than the thickness of the dielectric between the metallized layers. For example, such a capacitor is a MIM capacitor. In other words, at least one electrode of the capacitor is located outside the metallized layer.</p><p> In the next further embodiment, the capacitance of the modified capacitor is less than 1/3, less than 1/10, less than 1/100, or less than 1/1000 of the capacitance of the main capacitor. This procedure provides a means of fine-tuning. Therefore, by the correction means in the region of 1/1000, the capacitance values of the two capacitor structures of the same integrated circuit structure exactly match each other. This is unavoidably required for the same application.</p><p> The present invention particularly relates to a grid capacitor set having modified lateral electrodes. The individual transverse electrodes of the grid capacitors also provide a means of capacitance correction during manufacturing. Therefore, the above technical effect is particularly effective for grid capacitors.</p>

Hereinafter, examples of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows a plan view of the MIM capacitor structure 10. The MIM capacitor structure 10 includes a main capacitor 12 connected to an electronic circuit and a plurality of separable capacitors located to the right of the main capacitor 12, of which only one separable capacitor 14 is shown. For clarity, no dielectric is shown in FIG.

Within the capacitor structure 10, a plurality of connectable capacitors are located to the left of the main capacitor 12, and FIG. 1 shows one connectable capacitor 16. Capacitors (12-16) are formed identically, except for the length dimension. Capacitors (12, 14 or 16) include bottom electrodes (18, 20 or 22) closer to the substrate and electrodes (24, 26 or 28) farther from the substrate, respectively. The bottom electrodes (18, 20 or 22) closer to the substrate are each longer than the corresponding electrodes far from the substrate (24, 26 or 28) and longitudinally from both sides of the electrodes far from the substrate (24, 26 or 28). It's sticking out. As a result, the bottom electrode (18, 20 or 22) near the substrate provides a connection area for the vertically extending contacts 30.

The main capacitor 12 and the separable capacitor 14 are electrically connected in parallel by a conductor path 32 between the bottom electrodes (18, 20) and by a conductor path 34 between the electrodes (24, 26) far from the substrate. However, geometrically, the separable capacitors 14 are arranged in a row with each other. The conductor path (32,34) is located in the upper metallized layer. A cutout (36 or 38) leads to the conductor path (32,34) in an insulating material (not shown) covering the conductor path (32,34). When modifying the capacitance of the main capacitor 12, the region (40 or 42) can be evaporated using laser light through the cutouts (36 or 38). As a result, cutting occurs.

On the other hand, the connectable capacitor 16 is electrically parallel to the main capacitor 12 by the conductor path 52 between the bottom electrodes (18,22) or by the conductor path 54 between the electrodes (24,28) far from the substrate. Connected to. However, geometrically, the connectable capacitors 16 are arranged in a row with each other. The conductor path (52,54) is also located within the upper metallized layer.

The cutout (56 or 58) runs through an insulating material (not shown) to the coupling region (60 or 62) of the conductor path (52,54). The coupling region (60,62) is a so-called anti-fuse, that is, a connection that creates a continuous conductive connection between the conductor paths (52) or between the conductor paths (54) by irradiation with laser light. Form the means.

The main capacitor 12 has a length La larger than the length Lb of the separable capacitor 14 or larger than the length Lc of the connectable capacitor 16 in the longitudinal direction of the capacitor structure 10. Therefore, the capacitance C (0) of the main capacitor 12 is also larger than the capacitance Cm (I) of the separable capacitor 14. Where I is a natural number indicating the last separable capacitor 14. Separable capacitors (not shown) have a capacitance from Cm (1) to Cm (I-1) equal to the capacitance Cm (I).

Similarly, the capacitance C (0) of the main capacitor 12 is greater than the capacitance Cp (1) of the connectable capacitor 16. Connectable capacitors not shown in FIG. 1 have a capacitance from Cp (2) to Cp (N) equal to the capacitance Cp (1) or capacitance Cm (I). Where N is a natural number indicating the last connectable capacitor.

Modification of the capacitance of the main capacitor 12 is described in detail with reference to FIG.

In another embodiment, there is simply one separable capacitor 14 or just one connectable capacitor 16 to the right or left of the main capacitor 12. In the following embodiment, there is simply one or more separable capacitors 14 or just one or more connectable capacitors 16 to the right or left of the main capacitor 12. In the next embodiment, the capacities of the capacitor structure 10 from Cm (1) to Cm (I) are different from each other. Further, the capacitances from Cp (1) to Cp (N) of the capacitor structure 10 can be formed differently from each other.

FIG. 2 shows a plan view of the grid capacitor structure 110. The grid capacitor structure 110 includes a main capacitor 112 connected to an electronic circuit and a plurality of separable capacitors, of which one separable capacitor 114 is shown in FIG. The grid capacitor structure 110 further includes a plurality of connectable capacitors, of which one connectable capacitor 116 is shown in FIG. In FIG. 2, only the main capacitor 112 or the capacitor 114 or the upper electrode of the capacitor 116 is shown. In the metallized layer located below it, there are other electrodes running in the same manner as the upper electrode. In the first embodiment, the electrodes located in different metallized layers of the capacitor (112, 114 or 116) are connected to each other by at least vertical contacts. The conductor path between the capacitors (112, 114 and 116) exists only in the upper metallized layer.

The main capacitor 112 contains two comb-shaped electrodes in which its teeth mesh with each other in the upper metallized layer. From the longitudinal (langs) electrode 118, for example, four lateral (quer) electrodes (120 to 126) arranged in the same pattern size branch off. A plurality of horizontal electrodes (130 to 136), that is, four horizontal electrodes (130 to 136) are placed on the vertical electrode 128 facing the vertical electrode 118 in a horizontal direction with respect to the vertical electrode 128, as in the case of the vertical electrode 118. Up to) are arranged. The four transverse electrodes (130 to 136) extend into the intermediate region between the transverse electrodes (120 to 126). As a result, a meandering intermediate region is formed between the electrodes (120 to 126) and the transverse electrodes (130 to 136), and the intermediate region is filled with a dielectric. Let La be the meandering length of the main capacitor 112 again.

The separable capacitor and the connectable capacitor are formed similar to the main capacitor 112, however, each includes, for example, a short longitudinal electrode (140, 142, 144 or 146) in which two transverse electrodes (150 to 160) branch off.

A region 162 through which a cutout portion 164 from the upper surface of the integrated circuit communicates is located between the vertical electrode 118 and the vertical electrode 142 of the capacitor 114. A region 166 is located between the vertical electrode 128 and the vertical electrode 140 of the capacitor 114 through which an additional cutout 168 from the top surface of the integrated circuit communicates. Cuts within the region (162 or 164) between the longitudinal electrodes (118 and 142) or between the longitudinal electrodes (128 and 140) using laser light through the cutouts (164 and 166). Can be generated. As a result, the entire separable capacitor 114 is separated from the main capacitor 112. There are also additional regions (170 and 172) through which the cutouts (174 and 176) pass between the additional separable capacitors, so that they can be separated elsewhere.

There is a coupling region 180 between the longitudinal electrode 118 and the longitudinal electrode 146 of the correction capacitor 116. A coupling region 182 exists between the vertical electrode 128 and the vertical electrode 144 of the correction capacitor 116. The cutout (184 or 186) leads to the coupling region 180 or the coupling region 182. Through the cutouts (184 or 186), the coupling regions (180 and 182) can be locally heated using laser light. Local heating results in a bond between the vertical electrode 118 and the vertical electrode 146, or a bond between the vertical electrode 128 and the vertical electrode 144. Additional coupling regions (190,192) through which the cutouts (194 or 196) pass can be used to create additional conductive connections to connectable capacitors 116. The meandering of the main capacitor 112 has a length La greater than the meandering length Lb of the separable capacitor 114 or greater than the meandering length Lc of the connectable capacitor 116. Therefore, the capacitance C (0) of the main capacitor 112 is larger than the capacitance Cm (I) of the separable capacitor 114. The additional capacitance from Cm (1) to Cm (I-1) of the additional separable capacitor is equal to the capacitance Cm (I). The capacitance Cp (1) of the connectable capacitor 116 is equal to Cm (1). The capacitance from Cp (2) to Cp (N) of the additional connectable capacitor 116 is equal to the capacitance Cp (1).

Modification of the capacitance of circuit structure 110 is described in detail with reference to FIG.

In another embodiment, there is a cutout that leads to a different metallized layer, eg, a connecting means or cutting means that is offset from the connecting means or cutting means located above or below it. In other embodiments, the binding or cutting region is located within the upper metallized layer, albeit related to the electrodes placed in the lower metallized layer. Further, the capacitances of Cm (1) to Cm (I) or Cp (1) to Cp (N) of the capacitor structure 110 may have different capacitances from each other.

FIG. 3 shows the side (quer) electrode 200 of the grid capacitor. The transverse electrode 200 has a region 202 at a point approximately one-third of its length and a region 204 at a point approximately two-thirds of its length. The cutout portion 206 communicates with the region 202, and the cutout portion 208 communicates with the region 204. When the capacitance of the grid capacitor to which the lateral electrode 200 belongs is changed, a cut in the region 202 or a cut in the region 204 is generated. If a cut is generated within region 202, only approximately one-third of the transverse electrode 200 is circuit-enabled. On the other hand, if a cut is generated within region 204, approximately two-thirds of the lateral electrode 200 is still circuit effective. By selecting region 202 or region 204, the capacitance of the grid capacitor can be changed in the range of 1/1000.

The length of the transverse electrode 200 is, for example, 10 micrometers (μm). Its width is, for example, 0.5 μm. Therefore, cutting with a laser beam is possible without any problem.

FIG. 4 shows a lateral electrode 220 through which the cutout portion 222 communicates. The cutout portion 222 extends substantially above the overall length of the lateral electrode 220. Therefore, the lateral electrode 220 can be cut at any position. In other words, the cutting points can be placed continuously along the long axis of the lateral electrode 220.

According to other embodiments of the transverse electrodes (200 and 220), the coupling region is used in place of or in combination with a region that functions for cutting. The cutting region or coupling region is arranged at one lateral electrode of the grid capacitor or at multiple transverse electrodes of the grid capacitor.

FIG. 5 shows a method step for modifying the capacitance of an integrated capacitor structure according to, for example, FIG. 1, FIG. 2, FIG. 3 or FIG. In the design and simulation prior to this method, variations in the desired capacitance of the capacitance of the integrated capacitor structure are determined, for example, empirically or based on simulation results (see Method Step 300). Corrective means are prepared in advance depending on the capacity fluctuation (see method step 302). Corrective measures are, for example, separable capacitors, connectable capacitors, separable capacitor regions, and / or connectable capacitor regions. The corrective measures in Method Step 302 are predetermined to minimize the generation of cuttings and bonds by heating with laser light in all manufacturing steps, taking into account expected capacitance fluctuations.

The actual modification method begins in method step 304, where the wafer treatment ends (see method step 306). For example, a transistor is generated in a semiconductor material of a wafer. Subsequently, a metallized layer is formed, and at that time, a capacitor is also generated.

Method In step 308, the measurement grasps the actual capacitance of the integrated capacitor structure, in particular the capacitance of the main capacitor (12,112) with the capacitance of the separable capacitor (14,114).

In the subsequent method step 310, the actual volume and the desired volume are compared. If the actual capacity is less than or greater than the desired capacity, especially if it is less than or greater than a predetermined tolerance, method step 312 is immediately followed by method step 312. Method In step 312, it is checked whether the actual volume is greater than the desired volume. If the actual volume is greater than the desired volume, method step 312 is immediately followed by method step 314. Method In step 314, laser light is used to generate a cut in the integrated capacitor structure. At that time, the separable capacitor (14,114) is separated from the main capacitor (12,112). The capacity of the capacitor structure is reduced. In addition, a part of the electrode is separated from the horizontal electrode.

On the other hand, in the method step 312, when it is determined that the actual capacity is smaller than the desired capacity, the method step 316 follows immediately after the method step 312. Method In step 316, a laser beam is used to heat the coupling region. As a result, the connectable capacitor (16,116) is additionally connected to the main capacitor (12,112) or to the main region. As a result, the capacitance of the capacitor structure increases towards the desired capacitance. In addition, a part of the electrodes of the horizontal electrode is also connected.

On the other hand, in the method step 310, when it is determined that the actual capacity and the desired capacity match, the method step 318 is immediately followed. Method step 318 is also performed after method step 314 or method step 316. Method In step 318, the wafer is further processed. At that time, in particular, a passivation layer is formed to seal the cutout portion for the laser beam.

Further Method In step 320, the circuits arranged on the wafer are individually disrupted and housed in the hysing. The method ends in method step 322.

In other embodiments, modifications are made after the circuit is disrupted. For example, a surge current is used to heat the cutting or coupling region. Also, the questions in method steps 310 and 312 can be expressed elsewhere.

The methods provided have the following benefits: --Capacitor variation due to geometric or process variation can be corrected later by a simple method. As a result, yield or productivity can be improved. --In addition, later modifications provide capacitance that is individually adapted to each integrated circuit. As a result, capacitance adaptation specifically adapted to other circuit elements, such as capacitance adaptation for setting the optimum operating point, can be made. Therefore, this is especially useful when other circuit elements can no longer be modified.

Therefore, the effect of process or geometric variation on the parameters of the main capacitor, especially on capacitance and resistance (and thus on the RC constants), by separating or adding regions of the capacitor using so-called fuses or anti-fuse. However, it can be corrected later.

The following equation may be used in the modifications in method step 310 through method step 316: Ckorr = C (0) -sum (Cm (i), i = 1 ~ I1) + Sum (Cp (n), n = 1 ~ N1) Here, the quantities used have already been mentioned above, with the exception of quantities I1 and N1. The subscript i when summing the capacitance Cm must take into account all the separated capacitors. In that case, I1 indicates the last capacitor separated. The subscript when summing the capacitance Cp must take into account all connected capacitors. In that case, N1 indicates the last capacitor connected. In addition, attention must be paid to whether the capacitors are connected or disconnected.

If the capacitances Cm or Cp are all equal, they can be integrated by a factor indicating the number of separated or connected capacitors instead of the sum.

The following valid relationships for planar capacitors can be used in determining capacitance fluctuations: C = ε0 εr Aeff / Deff Here, ε0 and εr indicate the corresponding permittivity, Aeff indicates the effective electrode area, and Deff indicates the effective electrode spacing. At this time, the area variation ΔAeff or the interval variation ΔDeff is the capacitance variation: ΔC = ΔAeff / Aeff or ΔC = ΔDeff / Deff Limited by.

In the first approximation, the effective electrode area is: a) In MIM capacitors: Area of overlapping electrodes, b) In sandwich capacitors: metal electrode area, c) In grid capacitors: the side area of the conductor path resulting from length L and thickness T, Corresponds to.

Effective electrode spacing is: a) For MIM capacitors: Dielectric thickness different from the dielectric between metallized layers, b) In sandwich capacitors: Intermetall dielectric thickness, c) In grid capacitors: Corresponds to the thickness of the Intrametall dielectric, the so-called spacing.

Another influencing factor, for example, in the case of grid capacitors, is the formation of corners. This amount of influence is at least measured technically and can therefore be taken into account.

Capacity fluctuations have the following process-limited causes: a) In MIM capacitors: Fluctuations within the thickness of the MIM dielectric, for example due to non-uniform deposition rates above the wafer or due to non-uniform roughness of the bottom electrodes. b) For sandwich capacitors: Thickness variations due to variations in the thickness of the intermetallic dielectric, such as polishing non-uniformity or variations in etching depth above the wafer. c) In grid capacitors: variations in electrode spacing limited by changes in the thickness of the metal inner dielectric, eg, lithography when using aluminum, by RIE (reactive ion etching) patterning, or using copper. Fluctuations in electrode spacing due to trench etching in case. A further cause is the variation in electrode area due to changes in the thickness of the conductive path or due to CMP (Chemical Polishing) fluctuations when using copper, so-called dishing, asymmetric trench formation, or uneven deposition rates. Is.

In the case of MIM capacitors or sandwich capacitors, the capacitance is modified by direct separation or connection by the M area segments of the electrodes: A = A0 ± sum (Ai, i = 1 ~ M), Where A0 is the uncorrectable basic electrode area, M is a natural number, and Ai is a separable or connectable individual area element. A minus sign is valid for separable area elements, and a plus sign is valid for connectable area elements.

In the case of grid condensate, the electrode area A is set via the length L of the conductor path: A = L · T, where T is the average conductor path thickness inside the capacitor structure. Is. Separation or connection of M conductor path segments modifies, for example, n individual segments Li of the electrode: L = L0 ± sum (Li, i = 1 ~ M), Here, L0 is the uncorrectable basic electrode length, M is a natural number, and Li is a separate or connectable individual conductor path segment. A minus sign is valid for separable conductor path segments, and a plus sign is valid for connectable conductor path segments.

<figref num="1">It is a top view of the MIM capacitor structure.</figref><figref num="2">It is a top view of the grid capacitor structure.</figref><figref num="3">A horizontal electrode having two cutting means of a grid capacitor is shown.</figref><figref num="4">A horizontal electrode having a continuous cutting means of a grid capacitor is shown.</figref><figref num="5">The method step for capacity correction of an integrated capacitor is shown.</figref>