Semiconductor memory device

[0001] [Technical field to which the invention belongs] The present invention relates to a semiconductor storage device, and more particularly to SRAM (static random access memory). [0002] [Conventional technology] In recent years, with the miniaturization of semiconductor processes, the variation in transistor characteristics has increased. This has a great effect on the yield of circuits, so it will become more important in the future to design to suppress variations in transistor characteristics. [0003] Conventionally, a CMOS type SRAM memory cell having a 6-transistor configuration is known. It is composed of a total of three types (six) of transistors: a pair of MIMO access transistors, a pair of MIMO drive transistors, and a pair of MIMO load transistors. [0004] A horizontal cell structure has been devised in order to suppress manufacturing variations in SRAM memory cells, to reduce the memory cell area, and to reduce the bit line capacitance. This is unlike a vertical cell structure with an N-well in the upper half of one memory cell area and a P-well in the lower half, and a pair of MIMOs in the N-well located in the center of the memory cell area. The load transistor is a P-well on the left side with a first MIMO access transistor and a first MIMO drive transistor, and a P-well on the right side with a second MIMO access transistor and a second MIMO drive transistor. Here, the traveling direction of the bit line is defined as the vertical direction, and the traveling direction of the word line is defined as the horizontal direction (see Patent Documents 1 and 2). [0005] According to the vertical cell structure, the gate of the access transistor and the gate of the drive transistor are laid out so as to be perpendicular to each other. On the other hand, according to the horizontal cell structure, the gate of the access transistor and the gate of the drive transistor are laid out in parallel with each other, so that the manufacturing variation is strong. Further, since the wasted space generated in the vertical cell structure is reduced, the area of the memory cell is reduced, the bit line length is also shortened, and the capacity is reduced. [0006] By the way, one of the stability indexes of the memory cell is the static noise margin at the time of reading. This is an index indicating whether or not the data held in the memory cell is destroyed when the word line is activated, and the larger the static noise margin, the more stable the memory cell at the time of reading (Patent Document 3). reference). [0007] Conventionally, in order to increase the static noise margin at the time of reading, the current drive capability of the drive transistor is larger than that of the access transistor in the memory cell. Specifically, the ratio of the gate width of the access transistor and the drive transistor was set to, for example, about 1: 1.5. [0008] [Patent Document 1] JP-A-9-270468 [Patent Document 2] Japanese Unexamined Patent Publication No. 10-178110 [Patent Document 3] Japanese Patent Application Laid-Open No. 2002-042476 [0009] [Problems to be Solved by the Invention] When the horizontal cell structure is adopted for SRAM as described above and the gate width of the access transistor is made smaller than the gate width of the drive transistor, the diffusion layer of the access transistor has a concave shape at the gate portion. In the process of manufacturing such a SRAM memory cell, if the gate of the access transistor is deviated in the channel direction of the transistor, the effective gate width of the access transistor becomes large and its electrical characteristics fluctuate greatly. As a result, the static noise margin becomes small, a malfunction occurs at the time of reading, and there arises a problem that the yield is significantly reduced. [0010] An object of the present invention is to provide a semiconductor storage device that operates stably even in the case of SRAM memory cells having the same gate width between the access transistor and the drive transistor. [0011] [Means for solving problems] In connection with the present invention in order to achieve the above object.<u style="single">Half</u>The conductor storage device includes a memory cell having a 6-transistor configuration and a word line and bit line pair connected to the memory cell, and the voltage of the bit line pair before reading the memory cell is a predetermined voltage lower than the power supply voltage. It was decided to set to. By lowering the voltage of the bit line pair in this way, when the word line is activated for reading, the bit line pair is formed in the memory cell because it has an intermediate potential lower than the power supply voltage. As a result of the lower voltage of the low-side storage node among the high-side storage node and the low-side storage node, the current drive capability of the access transistor even when the gate widths of the access transistor and the drive transistor are equal. Is apparently lowered and the static noise margin is increased, so that malfunction at the time of reading can be prevented. [0012] More specifically, it relates to the present invention.<u style="single">Half</u>The conductor storage device is a means for precharging a bit line pair to a power supply voltage, and what is a bit line pair?<u style="single">Differently not connected to a memory cell</u>A dummy bit wire, a means for discharging this dummy bit wire to a first voltage lower than the power supply voltage, a bit wire pair precharged to the power supply voltage, and a dummy bit wire charged to the first voltage. The voltage of the bit line pair before reading the memory cell is set to a second voltage lower than the power supply voltage by adopting a configuration provided with a means for equalizing. [0015] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the CMOS type SRAM, which is the semiconductor storage device according to the embodiment of the present invention, will be described in detail with reference to the drawings. [0016] (First Embodiment) FIG. 1 shows the configuration of the semiconductor storage device according to the first embodiment of the present invention. In FIG. 1, the memory cell 10 has a 6-transistor configuration composed of a pair of MIMO access transistors 11,21, a pair of MIMO drive transistors 12,22, and a pair of MIMO load transistors 13,23. It is a memory cell. 30 is a word line (WL), 31, 32 is a bit line pair (BL, / BL), 33 is a dummy bit line (DBL), 40 is a discharge circuit, 41 is an equalize circuit, 42 is a precharge circuit, and memory. Cell 10 connects the word line 30 and the bit line pairs 31,32. The discharge circuit 40 is connected to the dummy bit line 33 and receives the discharge control signal DC as an input. The equalization circuit 41 is connected to the bit line pairs 31, 32 and the dummy bit line 33, and receives the equalization control signal EQ as an input. The precharge circuit 42 is connected to bit line pairs 31, 32, and the precharge control signal PC is used as an input. [0017] The precharge circuit 42 precharges the bit line pairs 31, 32 to the power supply voltage when the precharge control signal PC is at the L level (ground voltage: 0V). The discharge circuit 40 discharges the dummy bit line 33 to the ground voltage when the discharge control signal DC is at the L level. The equalization circuit 41 equalizes the voltage between the bit line pairs 31, 32 and the dummy bit line 33 when the equalization control signal EQ is at H level (power supply voltage). [0018] 2 to 4 are layout diagrams of the memory cells 10 in FIG. 1, FIG. 2 shows the base, FIG. 3 shows the base to the first metal wiring layer, and FIG. 4 shows the layer above the first metal wiring layer. Are shown respectively. FIG. 2 shows the diffusion layers 101 and 102 of the memory cell 10 and the polysilicon layer 103. FIG. 3 shows a first metal wiring layer 201, a first via 202, a ground 203, and a power supply 204 formed on the second metal wiring layer 201. FIG. 4 shows the second metal wiring layer 301, the second via 302, the third metal wiring layer 303, and the third via 304. The first via 202 is the diffusion layers 101, 102, the polysilicon layer 103 and the first metal wiring layer 201, the second via 302 is the first metal wiring layer 201 and the second metal wiring layer 301, and the third via 304 is the second. 2 The metal wiring layer 301 and the third metal wiring layer 303 are connected to each other. [0019] More specifically, in FIG. 2, 101 and 102 are diffusion layers, 103 are polysilicon layers, 110 are P wells, and 111 are N wells. 104,105 are access transistors (corresponding to MIMO access transistors 11 and 21 in FIG. 1), 106 and 107 are drive transistors (corresponding to MIMO drive transistors 12 and 22 in FIG. 1), and 108 and 109 are load transistors (PMOS in FIG. 1). It corresponds to load transistors 13 and 23). The drive transistor 106 and the load transistor 108 are connected to the inverter by the first metal wiring layer 201, and similarly, the drive transistor 107 and the load transistor 109 are connected to the inverter by the first metal wiring layer 201. The drain of the access transistor 104 and the drain of the drive transistor 106 are connected by a diffusion layer, and the drain of the access transistor 105 and the drain of the drive transistor 107 are connected by a diffusion layer. As shown in FIGS. 3 and 4, the gates of the access transistors 104 and 105 are formed by the first via 202, the first metal wiring layer 201, the second metal wiring layer 301, the second via + the third via 304, and the word line 30. Connect to a third metal wiring layer 303. The source of the access transistors 104, 105 is connected to the second metal wiring layer 301, which is a bit line pair 31,32, by the first via 202, the first metal wiring layer 201, and the second via 302. The gates of the access transistor 104 and the drive transistor 106 are arranged in parallel with each other, the gate widths are equal, and the diffusion layer is arranged in a shape without unevenness. Similarly, the access transistor 105 and the drive transistor 107 are arranged so that the gates are parallel to each other, the gate widths are equal, and the diffusion layer is not uneven. [0020] As shown in FIG. 4, the dummy bit wire 33 formed by the second metal wiring layer 301 is arranged between the bit wire pairs 31, 32. Therefore, the dummy bit wire 33 acts as a shield, and crosstalk between the bit wire pairs 31, 32 can be eliminated. Further, since the wiring area of the dummy bit wire 33 is not the area where the wiring originally exists, no area penalty is generated. [0021] [0021] By adopting the configurations shown in FIGS. 2 to 4, even if the gates of the access transistors 104 and 105 are displaced in the channel direction of the transistors in the manufacturing process, the effective gate width of these access transistors 104 and 105 does not increase, so that the effective gate width at the time of reading is not increased. The static noise margin is not reduced, and fluctuations in its electrical characteristics can be minimized. Therefore, it is possible to prevent a decrease in yield due to a malfunction at the time of reading. [0022] FIG. 5 shows the voltages of the precharge control signal PC, the discharge control signal DC, the equalize control signal EQ, the word line WL, the bit line pair BL, / BL, and the dummy bit line DBL at the time of reading out the semiconductor storage device of FIG. The waveform is shown. Vdd is the power supply voltage. [0023] According to FIG. 5, the precharge control signal PC and the discharge control signal DC are set to the L level at time t1. That is, the precharge control signal PC precharges the bit line pair BL, / BL to the power supply voltage Vdd, and the discharge control signal DC discharges the dummy bit line DBL to the ground voltage (0V) (T1 period). After the completion of the precharge of the bit line pair BL, / BL and the discharge of the dummy bit line DBL, the bit line pair BL, / BL and the dummy bit line DBL are equalized by the equalization control signal EQ (T2 period). As a result of this operation, the electric charge existing in the bit line pair BL, / BL is distributed to the dummy bit line DBL, the voltage of the bit line pair BL, / BL is lowered to a voltage lower than the power supply voltage Vdd. At this time, since the bit line pair BL, / BL and the dummy bit line DBL are not affected by the manufacturing variation of the transistor, a stable intermediate potential between the power supply voltage Vdd and the ground voltage (0V) can be obtained. After this operation, the word line WL is selected at time t5 and the reading of the memory cell 10 is started. [0024] According to the first embodiment described above, when the word line 30 is activated for reading by lowering the precharge voltage of the bit line pairs 31, 32 by using the dummy bit line 33, the bit Since the line pairs 31 and 32 have an intermediate potential lower than the power supply voltage Vdd, the voltage of the low-side storage node in the memory cell 10 becomes low, and as a result, the MIMO access transistors 11,21 and the MIMO drive transistors 12, 22 Even when the gate widths are the same as those of the above, the current drive capability of the MIMO access transistors 11 and 21 is apparently reduced, and the static noise margin is increased, so that malfunction at the time of reading can be prevented. [0025] Moreover, the dummy bit wire 33 can be arranged without increasing the layout area, and the increase in the layout area can be suppressed in that it is not necessary to use a plurality of power supplies. Further, since the dummy bit wire 33 acts as a shield, the coupling capacity between the bit wire pairs 31 and 32 can be reduced, and the read speed of the memory cell 10 can be increased. [0026] (Second embodiment) FIG. 6 shows the configuration of the semiconductor storage device according to the second embodiment of the present invention. The configuration of FIG. 6 is first in that, for example, a MIMO transistor is provided as a transistor 43 for electrically dividing the dummy bit line (DBL) 33 into two when the dummy bit line adjustment signal DA is at H level. Different from the embodiment. Other points are the same as those in the first embodiment. [0027] FIG. 7 shows the read operation of the semiconductor storage device of FIG. According to FIG. 7, when the dummy bit line adjustment signal DA is at the L level and the MIMO transistor 43 is in the active state, the same as in the first embodiment. . On the other hand, when the dummy bit line adjustment signal DA is at H level and the MIMO transistor 43 is in the inactive state, the voltage of bit line vs. BL, / BL is small because the charge transfer is small when equalizing during the T2 period. The drop can be reduced. [0028] According to the second embodiment described above, the dummy bit line capacitance can be changed by the dummy bit line adjustment signal DA, and thus the voltage of the equalized bit line pairs 31, 32 can be variably controlled. [0029] The dummy bit line 33 may be electrically divided into three or more by increasing the dummy bit line adjustment signal DA and the MIMO transistor 43. By finely setting the dummy bit line capacitance, the voltage adjustment unit of the bit line pair 31,32 after equalization can be reduced. It is also possible to change the dummy bit line capacitance by variably controlling the number of divisions of the dummy bit line 33. Increasing the dummy bit line capacitance allows the equalized bit line pair 31,32 voltage to be set lower. [0030] Further, when the static noise margin becomes smaller than the desired value due to manufacturing variation and a reading malfunction occurs, the dummy bit line capacitance is changed so that the static noise margin becomes large so that the reading malfunction does not occur. It can also be adjusted as follows. By greatly changing the precharge voltage of bit wire pairs 31, 32, it is possible to deal with large manufacturing variations. [0031] (Third embodiment) FIG. 8 shows the configuration of the semiconductor storage device according to the third embodiment of the present invention. In the configuration of FIG. 8, the discharge circuit 40 in the first embodiment is composed of a MIMO transistor 44 for extracting the electric charge of the dummy bit line (DBL) 33. The discharge circuit 40 of the present embodiment discharges the dummy bit line 33 to the threshold voltage Vt of the MIMO transistor 44 when the discharge control signal DC is at the L level. SC is a substrate potential control signal for variably controlling the substrate potential of the MIMO transistor 44. Other points are the same as those in the first embodiment. [0032] FIG. 9 shows the read operation of the semiconductor storage device of FIG. According to the configuration of FIG. 8, the threshold voltage Vt of the MIMO transistor 44 can be changed by the substrate potential control signal SC. For example, if Vt = 0, the dummy bit line DBL is discharged to the ground voltage (0V) during the T1 period. On the other hand, if Vt&gt; 0, the voltage after discharge of the dummy bit line DBL in the T1 period becomes a predetermined positive voltage. Therefore, the substrate potential control signal SC can variably and continuously control the voltage of the bit line pair BL, / BL after equalization in the T2 period. [0033] According to the third embodiment described above, the charge amount of the dummy bit wire 33 after discharge is changed by the substrate potential control signal SC, and the voltage of the equalized bit wire pairs 31, 32 is variably controlled. it can. [0034] In addition, when the static noise margin becomes smaller than the desired value due to manufacturing variations and causes a reading malfunction, the substrate potential control signal SC is input so as to increase the discharge amount of the bit line pairs 31, 32. , It can also be adjusted so that reading malfunction does not occur. [0035] (Fourth Embodiment) FIG. 10 shows the configuration of the semiconductor storage device according to the fourth embodiment of the present invention. In FIG. 10, the memory cell 10 is a memory cell having a 6-transistor configuration having a horizontal cell structure shown in FIGS. 2 to 4. However, the dummy bit wire 33 is unnecessary. 30 is word line (WL), 31,32 is bit line pair (BL, / BL), 45 is word line driver, 50 is precharge circuit, 60 is bit line discharge circuit, 70 is equalize circuit, 80 is bit line It is a discharge voltage control circuit, and the memory cell 10 is connected to the word line 30 and the bit line pairs 31, 32. [0036] The precharge circuit 50 is configured by connecting the drains of a pair of MIMO transistors 51 and 52 to the bit wire pairs 31 and 32, connecting the source to the power supply, and inputting the precharge control signal PC to the gate. The bit line discharge circuit 60 is configured by connecting the drain of a pair of MIMO transistors 61, 62 to the bit line pairs 31, 32, connecting the source to the ground, and inputting the discharge control signal DC to the gate. The equalization circuit 70 is configured by connecting the drain and the source of the MIMO transistor 72 to bit line pairs 31 and 32, respectively, and inputting the output of the logic circuit 71 to the gate. The logic circuit 71 gives the logical product of the precharge control signal PC and the inversion of the discharge control signal DC to the gate of the MIMO transistor 72. Therefore, the equalization of the bit line pairs 31,32 is executed at the precharge time and the discharge time of the bit line pairs 31,32, respectively. The bit line discharge voltage control circuit 80 inputs the precharge control signal PC and the pulse control signals PLS1 to 3 and outputs the discharge control signal DC so as to variably control the discharge time of the bit line pairs 31, 32. The circuit is composed of a buffer 81,82,83, an inverter 84,85,86, a MOS switch 91,92,93, and an AND circuit 94. This bit line discharge voltage control circuit 80 selects one of three different delay signals based on the precharge control signal PC with the pulse control signals PLS1 to 3, and the selected result and the precharge control signal PC are combined. The configuration is such that the logical product is the discharge control signal DC. Only one pulse control signal PLS1 to 3 inputs the H level, and the others input the L level. [0037] FIG. 11 shows the voltage waveforms of the pulse control signal PLS1, the precharge control signal PC, the discharge control signal DC, the word line WL, and the bit line pair BL, / BL at the time of reading out the semiconductor storage device of FIG. .. Vdd is the power supply voltage. [0038] According to FIG. 11, the discharge time of the bit line pair BL, / BL is determined by first setting any one of the pulse control signals PLS1 to 3 (for example, PLS1) to the H level at time t1. At this time, one of the three stages of discharge time can be selected. Next, by setting the precharge control signal PC to L level at time t2, the bit line pair BL, / BL is precharged and equalized to the power supply voltage Vdd. After the precharge during the T1 period, when the precharge control signal PC is returned to the H level and the precharge of the bit line vs. BL, / BL is completed, the discharge and equalization of the bit line vs. BL, / BL are started from time t4. To. The bit line discharge time T2 is a length corresponding to the delay selected by the pulse control signals PLS1 to 3 in the bit line discharge voltage control circuit 80. As a result, the bit line pair BL, / BL voltage is lowered to a voltage lower than the power supply voltage Vdd. After this discharge is completed, the word line WL is selected at time t6 and the reading of the memory cell 10 is started. [0039] According to the fourth embodiment described above, when the word line 30 is activated for reading by lowering the precharge voltage of the bit line pair 31,32 before reading the memory cell 10, the bit line Since the pair 31 and 32 have an intermediate potential lower than the power supply voltage Vdd, the voltage of the low-side storage node in the memory cell 10 becomes low, and as a result, the MIMO access transistors 11 and 21 and the MIMO drive shown in FIG. 1 become low. Even when the gate widths of the transistors 12 and 22 are the same, the current drive capability of the MIMO access transistors 11 and 21 apparently decreases, and the static noise margin increases, so that malfunction at the time of reading can be prevented. [0040] Moreover, according to the present embodiment, it is not necessary to use a plurality of power sources, and an increase in the layout area can be suppressed. Further, unlike the first to third embodiments, the dummy bit wire 33 is not required, so that the adverse effect of the speed decrease due to the increase in the adjacent load capacitance between the bit wire pairs 31, 32 and the dummy bit wire 33 can be avoided. [0041] Further, when the static noise margin becomes smaller than the desired value due to manufacturing variation and causes a read malfunction, the bit line discharge voltage control circuit 80 is used to lengthen the discharge time of the bit line pairs 31, 32 to read out. It can also be adjusted so that the malfunction of is not caused. [0042] When discharging a plurality of bit line pairs, the discharge time of all the bit line pairs can be controlled by a single control circuit 80, so that there is an advantage that it is easy to align the discharge amounts of these bit line pairs. [0043] (Fifth Embodiment) FIG. 12 shows the configuration of the semiconductor storage device according to the fifth embodiment of the present invention. In FIG. 12, the memory cell 10 is a memory cell having a 6-transistor configuration having a horizontal cell structure shown in FIGS. 2 to 4. However, the dummy bit line 33 can be omitted. 30 is a word line (WL), 31, 32 is a bit line pair (BL, / BL), 45 is a word line driver, 95 is a word line voltage setting circuit, and memory cell 10 is a word line 30 and a bit line pair 31. , 32 and connect to. The ward line voltage setting circuit 95 is composed of, for example, an NMOS transistor 96. The gate of the ward line voltage setting 96 is connected to the power supply, the source is connected to the output of the ward line driver 45, and the drain is connected to the ward line 30. [0044] According to this embodiment, assuming that the power supply voltage is Vdd and the threshold voltage of the MIMO transistor 96 is Vtn, the activation voltage of the word line 30 when the word line 30 is selected, that is, shown in FIG. The gate voltage of both MIMO access transistors 11 and 21 is a predetermined voltage (Vdd-Vtn) lower than the power supply voltage Vdd. As a result, the on-resistance of the MIMO access transistors 11 and 21 at the time of reading becomes larger than the on-resistance of the MIMO drive transistors 12 and 22, so that the voltage of the low-side storage node becomes low. Therefore, even when the gate widths of the MIMO access transistors 11 and 21 and the MIMO drive transistors 12 and 22 are the same, the static noise margin becomes large and a malfunction at the time of reading can be prevented. The activation voltage of the word line 30 may be variably controlled. [0045] [Effect of the invention] As described above, according to the present invention, the voltage of the bit line pair before reading the memory cell is set to a predetermined voltage lower than the power supply voltage.<u style="single">Determine</u>Therefore, it is possible to provide a semiconductor storage device that operates stably even in the case of SRAM memory cells in which the gate widths of the access transistor and the drive transistor are the same. [0046] The voltage setting of the bit wire pair is by equalizing the bit wire pair precharged to the power supply voltage and the dummy bit wire charged to a voltage lower than the power supply voltage.<u style="single">Rita</u>Made. [Simple explanation of drawings] FIG. 1 is a circuit diagram of a semiconductor storage device according to the first embodiment of the present invention. FIG. 2 is a background layout diagram of memory cells in FIG. FIG. 3 is a layout diagram from the base of the memory cell in FIG. 1 to the first metal wiring layer. FIG. 4 is a layout diagram of a layer above the first metal wiring layer of the memory cell in FIG. 5 is a timing chart showing a read operation of the semiconductor storage device of FIG. 1. FIG. FIG. 6 is a circuit diagram of a semiconductor storage device according to a second embodiment of the present invention. 7 is a timing chart showing a read operation of the semiconductor storage device of FIG. 6. FIG. FIG. 8 is a circuit diagram of a semiconductor storage device according to a third embodiment of the present invention. 9 is a timing chart showing a read operation of the semiconductor storage device of FIG. 8. FIG. FIG. 10 is a circuit diagram of a semiconductor storage device according to a fourth embodiment of the present invention. 11 is a timing chart showing a read operation of the semiconductor storage device of FIG. 10. FIG. FIG. 12 is a circuit diagram of a semiconductor storage device according to a fifth embodiment of the present invention. [Explanation of symbols] 10 memory cells 11,21 NMOS access transistor 12,22 NMOS drive transistor 13,23 photoresist load transistor 30 word line (WL) 31,32-bit line pair (BL, / BL) 33 Dummy bit line (DBL) 40 Discharge circuit 41 Equalize circuit 42 precharge circuit 43,44 epitaxial transistor 45 word line driver 50 precharge circuit 51,52 epitaxial transistor 60-bit line discharge circuit 61,62 NMOS transistor 70 equalize circuit 71 Logic circuit 72 epitaxial transistor 80-bit line discharge voltage control circuit 81,82,83 buffer 84,85,86 Inverter 91,92,93 MOS switch 94 AND circuit 95 word line voltage setting circuit 96 NMOS transistor 101,102 Diffusion layer 103 polysilicon layer 104,105 access transistor 106,107 drive transistor 108,109 Load transistor 110 P well 111 N well 112 cell border 201 1st metal wiring layer 202 202 1st Via 203 Grand 204 power supply 301 Second metal wiring layer 302 2nd Via 303 Third metal wiring layer 304 2nd Via + 3rd Via DA dummy bit line adjustment signal DC discharge control signal EQ equalize control signal PC precharge control signal PLS1 ~ 3 Pulse control signal SC board potential control signal