Computing circuit

The present invention relates to an arithmetic circuit in which an arithmetic unit and a memory are integrated.

By configuring a logic circuit using a non-volatile device, in order to realize a circuit that does not lose information even when the power is turned off or a circuit that does not require data transfer with RAM on another chip, logic in Research on a configuration called memory is underway.

Then, as a non-volatile device used in logic-in-memory, for example, a device using a floating gate MOS transistor, a ferroelectric device, a TMR device, or the like has been proposed (for example, Non-Patent Documents 1 to Non-Patent Documents 1 to Non-Patent Documents). 4).

Logic-in-memory is an integration of an arithmetic unit and memory (storage device), which are separately arranged in the current circuit. By integrating the arithmetic unit and memory, it becomes possible to eliminate the performance bottleneck caused by wiring delay, which is a problem in current integrated circuits.

If you try to distribute the arithmetic functions to the memory, the circuit will usually be large, but if you use a device with a non-volatile storage function, you can realize a compact and high-performance circuit. it can. The reason why this compact and high-performance circuit can be realized will be described below.

In a normal digital circuit, a configuration called a static circuit, that is, a configuration using a bistable flip-flop as a storage circuit like a basic circuit of SRAM is adopted. Since this circuit is bistable, it is suitable for high-speed operation and has the advantages of low static current consumption. However, since a 1-bit memory is composed of 6 elements, it is not suitable for high integration.

On the other hand, if a configuration called a dynamic circuit, that is, a configuration in which the basic circuit of DRAM is used as a storage circuit, a 1-bit memory can be configured with two elements, which has an advantage that it is suitable for high integration. However, since this circuit is monostable and destructive read, precharging for rewriting (refreshing) and small signal amplification is required, which hinders high-speed operation and increases current consumption. As described above, when a dynamic circuit is adopted, it cannot be operated at high speed without processing such as refreshing, so that it is not generally adopted.

Therefore, if a device having a non-volatile storage function is introduced into the storage circuit, rewriting (refreshing) and precharging for small signal amplification become unnecessary, and the logic using the above-mentioned dynamic circuit can be realized with a small number of elements. The circuit can be used without operational restrictions. As a result, a compact and high-performance logic circuit can be realized.

Next, the configuration and operating principle of the logic circuit using this dynamic circuit will be described. In a logic circuit using a dynamic circuit, a configuration called a functional pass gate (FPG) is adopted as a circuit for performing a logical operation. This functional passgate has a configuration including an arithmetic element, a memory element, and a passgate transistor. The memory element stores storage data for arithmetic operation, and the arithmetic element performs an arithmetic operation using the stored data, and the arithmetic element performs an arithmetic operation. The calculation result is input to the gate of the pass gate transistor, and the pass gate transistor is turned on / off according to the calculation result.

In the dynamic circuit, the pass gate transistor of the functional pass gate is connected to the match line, and for example, a precharge transistor is provided between the match line on one terminal side of the pass gate transistor and the power supply voltage, and the other pass gate transistor is provided. An Evaluation transistor is provided between the match line on the terminal side and the ground potential. Further, a precharge line is connected to each gate of the precharge transistor and the evaluation transistor, and the precharge line is configured so that only one of the precharge transistor and the evaluation transistor is turned on (for example, non-charged transistor). See FIGS. 2 and 4 of Patent Document 4).

Function The passgate operation is roughly divided into a write operation and a calculation / read operation. In the writing operation, for example, a voltage or current for writing is applied to the memory element to write the stored data. In the calculation / reading operation, the process of precharging the match line and the process of performing the calculation of the external input and the stored data are executed in this order. Specifically, first, the precharge transistor is turned on to precharge the match line. After that, the precharge transistor is turned off and the calculation is performed. At this time, whether or not the charge precharged in the match line escapes to the ground potential through the pass gate transistor and the evaluation transistor changes depending on the calculation result, so that the output is 1 or 0. Is decided. Since the output is retained until the next precharge starts, the functional passgate has a function of latching the output.

In addition, if the functional path gates are connected in series, an AND (logical product) operation is performed, and if they are connected in parallel, an OR (logical sum) operation is performed, so that the calculation results can be easily calculated.

Next, logic-in-memory using various non-volatile devices will be briefly described. First, as an example of logic-in-memory using a non-volatile device, a case where a ferroelectric memory (FeRAM) element is used will be described (see Non-Patent Document 1). A ferroelectric device called an MFS (Metal Ferroelectric Semiconductor) FET is used for the ferroelectric memory element. This MFS FET consists of three layers: an electrode, a ferroelectric thin film, and a semiconductor, and is a SiO in a normal MOSFET (MOS field effect transistor).₂It has a structure in which the layer is replaced with a ferroelectric thin film.

Then, in the ferroelectric substance, when a voltage V exceeding a certain voltage Vc is applied from the outside, the relationship between the voltage V and the polarization P in the ferroelectric substance has hysteresis. Therefore, the threshold voltage Vth of the MFS FET changes depending on the remanent polarization state of the ferroelectric substance. Therefore, the threshold voltage that changes depending on the residual polarization state can correspond to 1 and 0 of the stored data.

When MFSFET is used as a memory element, it has the following advantages. (1) Compared to the floating gate MOS transistor used in flash memory, etc., the write voltage is low, about ± 6V. (2) The stored data can be read without destroying it. (3) Since the polarization change in the ferroelectric substance is fast, high-speed writing is possible.

Using this MFSFET, it is possible to configure an arithmetic circuit that calculates input data and stored data. Specifically, for example, one terminal A of the MFS FET is grounded, the other terminal B is connected to the match line (potential Vm), and a transistor for precharging is connected to the other terminal B, as described above. It constitutes a functional path gate (see Non-Patent Document 1). Then, when the input data s = 1,0 is applied to the gate potential Vg of the MFSFET and the stored data b = 1,0 is applied to the threshold voltage Vth of the MFSFET, the switching characteristic f (s, b) of the functional path gate is set to the following. Can be defined as. f (s, b) = 1 (A and B are connected) f (s, b) = 0 (A and B are not connected) This indicates that f (s, b) = 1 if the potential Vm of the match line drops to the ground potential (GND), and f (s, b) = 0 otherwise. .. When the two types of voltage thresholds Vth0 and Vth1 are Vth1> Vth0, the three types of gate voltages Vg0, Vg1 and Vg2 are defined so as to be Vg2> Vth1> Vg1> Vth0> Vg0. At this time, if Vg0 is applied to b = 0 and Vg1 is applied to b = 1, f (s, b) = 1 only when S = 1, b = 0, so f (s, b) = s & It becomes ~ b, and the logical product of s and ~ b is obtained. On the other hand, if Vg1 is applied to b = 0 and Vg2 is applied to b = 1, then f (s, b) = 0 only when s = 0, b = 1, so f (s, b) = s | It becomes ~ b, and the logical sum of s and ~ b is obtained. In this way, if the gate voltage corresponding to 1/0 of the input data s is set to three values, the OR / AND operation with the stored data b can be performed.

Further, as an application example of this, a match search circuit called CAM (Content Addressable Memory), which is one of the associative memories, can be configured. It is an EXOR operation that detects a bitwise match, and this EXOR operation can be executed by connecting two FPGs that calculate the logical product in parallel. A match search circuit can be configured by arranging two FPGs connected in parallel for one word and combining them so that if any one of them does not match, the output becomes "0". By building a circuit with MFSFET in this way, for example, a 16-bit match detection circuit requires 160 transistors in a SRAM-based static circuit, whereas 64 transistors are required in an MFS FET-based dynamic circuit. It can be realized (see Non-Patent Document 1).

Next, a logic-in-memory using a ferroelectric capacitor as a non-volatile device will be described (see Non-Patent Document 2 and Non-Patent Document 3). The ferroelectric capacitor has a structure in which the insulating film of a normal capacitor is replaced with a ferroelectric thin film, and polarization occurs when different voltages are applied to both ends of the ferroelectric capacitor. The state of the remanent polarization of the ferroelectric capacitor is determined by the state of the remanent polarization before the voltage is applied and the potential difference at the time of applying the voltage. Therefore, by applying the voltages Vy1 and Vy2 applied to both ends of the ferroelectric capacitor to the two input data y1 and y2 and applying the residual polarization state to the stored data S, the calculation result by the two input data y1 and y2 can be obtained. It can be stored as a residual polarization state. This calculation result is saved even when the power is turned off.

At this time, the operation between the two input data y1 and y2 is changed to an AND (logical product) operation or an OR (logical sum) operation depending on the residual polarization state, that is, the stored data S. It is also possible to perform an AND operation or an OR operation between the external input data y1 or y2 and the stored data S.

Therefore, the ferroelectric capacitor can simultaneously realize the logical operation function and the memory function. Then, the ferroelectric capacitor and the pass gate transistor can be connected to form the above-mentioned functional pass gate. Furthermore, by configuring a dynamic circuit that turns this functional passgate on and off, a basic circuit composed of a logic gate and a memory by a normal CMOS static circuit can be realized with only one functional passgate. For example, in the case of a CMOS static circuit, a logical operation and latch circuit that requires 14 transistors can be realized with only 5 transistors (see Non-Patent Document 3). In this way, if a logic circuit using a dynamic circuit using a ferroelectric capacitor is configured, the logic circuit can be constructed more compactly as compared with a logic circuit using a static CMOS circuit having the same function.

Next, as a final example of logic-in-memory using a non-volatile device, a TMR (ferromagnetic tunnel magnetoresistive effect) element used in MRAM (magnetic random access memory) or the like will be described. (See Non-Patent Document 4). The TMR element consists of a ferromagnetic layer (magnetization free layer) whose magnetization direction changes due to an external magnetic field, an ultra-thin insulating layer, and a ferromagnetic layer (magnetization fixed layer) whose magnetization direction is constant regardless of the external magnetic field. It is a structure in which layers are laminated. This TMR element has the property of increasing or decreasing the electrical resistance by changing the direction of magnetization of the magnetization free layer due to an external magnetic field. That is, the resistance decreases when the magnetization directions of the magnetization free layer and the magnetization fixed layer are parallel, and increases when the magnetization free layer and the magnetization fixed layer are antiparallel. Therefore, the resistance value of this TMR element can be stored as storage data.

In order to operate the TMR element as a memory element, for example, a writing line is arranged parallel to the easy axial direction of the ferromagnetic material of the magnetization free layer for each TMR element, and the ferromagnetic material of the magnetization free layer is operated. Arrange the bit lines parallel to the direction of the difficult magnetization axis. Then, when writing data to the TMR element, by passing currents through the bit line and the writing line, respectively, the data of "1" and "0" is applied to the TMR element according to the direction of the combined magnetic field of the magnetic field due to these currents. Is written. More precisely, a magnetic field due to the writing line is generated along the direction of the difficult-to-magnetize axis of the ferromagnet in the free-magnetized layer, thereby reducing the diamagnetism of the ferromagnet in the free-magnetized layer. At the same time, a magnetic field due to a bit line is generated along the direction of the easy-magnetization axis of the magnetic material of the magnetization free layer, and data of "1" and "0" are written depending on this direction. On the other hand, when reading the data written in the TMR element, a current is passed from the bit line to the TMR element, and the data "1" and "0" are discriminated according to the magnitude of the flowing current.

Then, for example, two TMR elements Rs, Rs ́ are complementarily arranged, and a reading transistor sandwiched between these two TMR elements Rs, Rs ́ and a passgate transistor constitute a functional passgate. (See Fig. 4 of Non-Patent Document 4). Bit lines BL1 and BL2 are arranged corresponding to each of the two TMR elements Rs and Rs ́. Then, when writing the stored data, the stored data is written by the magnetic field generated by the bit line and the writing line. When reading the written data, the reading transistor is turned on and a current is passed through the TMR element. When performing the calculation, a voltage corresponding to the external input is applied to one bit line BL1. The gate voltage of the pass gate transistor changes according to the calculation result of the external input and the stored data, and the on / off state of the pass gate transistor changes. With such a configuration, an AND (logical product) operation between the external input and the stored data can be performed.

<nplcit num="1"><text>Kimura, Hanyu, Kameyama "Logic-in-memory VLSI using ferroelectric devices and its applications" Journal of the Institute of Electronics, Information and Communication Engineers C, Vol.J83-C, No.8, August 2000, p.749-756</text></nplcit><nplcit num="2"><text>Kimura, Hanyu, Kameyama, Fujimori, Nakamura, Takasu "Configuration of Logic-In-Memory VLSI Using Ferroelectric Devices", IEICE Transactions C, Vol.J86-C, No.8, August 2003, p.886-893</text></nplcit><nplcit num="3"><text>Hidemi Takasu "Logic Application of Ferroelectrics" FED Review., Vol.2, No.7, February 24, 2003, p.1-24</text></nplcit><nplcit num="4"><text>Kimura, Hanyu, Kameyama "Configuration of Logic-In-Memory VLSI Using Non-Volatile Devices" IEICE Technical Report TECHNICAL REPORT OF IEICE., ICD 2003-5, April 2003, P.23-27</text></nplcit>

<p> However, there are some problems even when the logic-in-memory is configured by using the above-mentioned three types of non-volatile devices.</p><p> First, the one using MFSFET has the following problems. First, the write voltage is lower than that of a floating gate MOS transistor, but it is still too large compared to the power supply voltage of a normal CMOS circuit, so a separate power supply or booster circuit is required. Secondly, since an offset is given to the external input data to switch between the AND operation and the OR operation, the gate voltage becomes three values and the peripheral circuit becomes complicated. Thirdly, although it is possible to perform operations between the external input data and the stored data, it is not configured to be able to perform operations between the two external input data.</p><p> On the other hand, in the case of using a ferroelectric capacitor, it is possible to perform an operation between two external input data and also to perform an operation between the external input data and the stored data. However, the following problems remain with the one using a ferroelectric capacitor. First, since the contents of the stored data change as a result of the calculation, a set operation or a reset operation is required. Secondly, since the area occupied by the ferroelectric capacitor is large, it is not suitable for high integration.</p><p> In addition, the one using the TMR element has the following problems. First, AND (logical product) operation between external input data and stored data is possible, but OR (logical sum) operation is not possible. Secondly, it is not configured to be able to perform operations between two external input data.</p><p> Therefore, if there is a non-volatile device that satisfies all of the following conditions, it is considered that an ideal configuration can be obtained as a logic-in-memory. First, it does not require a high voltage and operates at a voltage similar to the power supply voltage of a CMOS circuit. Secondly, both AND operation and OR operation of external input data and stored data are possible, and these operations can be switched. Third, both AND and OR operations between two external input data are possible, and the AND operation and OR operation can be switched according to the stored data. Fourth, it is possible to switch between the case of calculating without destroying the stored data and the case of leaving the calculation result as stored data, depending on how it is used.</p><p> In order to solve the above-mentioned problems, in the present invention, it is possible to realize a compact and high-speed logic-in-memory circuit, and to provide a highly versatile arithmetic circuit capable of various arithmetic operations. It is to provide.</p>

<p> In the arithmetic circuit of the present invention, a variable resistor whose resistance state reversibly changes between a high resistance state and a low resistance state by applying voltages of different polarities between one electrode and the other electrode. A memory element having an element and one or more transistors connected to both ends of the memory element are provided, and potential is supplied to both ends of the memory element through the transistors to store data in the memory element. Or, an operation is performed on the external data input via any of the transistors, and the result of the operation is output from the memory element.<u style="single">Further, in the memory element, one electrode of each element of the two variable resistance elements is connected to form a common terminal, and the other electrode of each element of the two variable resistance elements is independently provided with a terminal, for a total of three. One or more transistors are connected to the terminals provided on the other electrodes of the memory element, which are configured as terminals, and the result of the calculation is output from the common terminal.</u></p><p> According to the above-described configuration of the arithmetic circuit of the present invention, a memory element having a variable resistance element and one or more transistors connected to both ends of the memory element are provided, and potentials are applied to both ends of the memory element through the transistors. By being supplied, data is stored in the memory element and calculation is performed on the external data input via any of the transistors, and the calculation result is output from the memory element. Therefore, the characteristics of the variable resistance element. Therefore, the resistance value of the variable resistance element can be changed at a relatively low voltage, and the data can be stored in the memory element. Further, a non-destructive operation in which the data stored in the memory element is not changed even after the calculation by controlling the potential supplied to both ends of the memory element, and a destruction operation in which the data stored in the memory element is changed by the calculation. And can be done respectively. Therefore, by controlling the potentials supplied to both ends of the memory element, it is possible to perform an operation between the external data and the data stored in the memory element and an operation between the external data. Further, by changing the potential or the like supplied to both ends of the memory element, it is possible to switch between the AND (logical product) operation and the OR (logical sum) operation in the non-destructive operation and the destructive operation, respectively.</p><p><u style="single">Further, in the arithmetic circuit of the present invention,</u>The memory element connects one electrode of each element of the two variable resistance elements to form a common terminal, and the other electrode of each element of the two variable resistance elements is provided independently to provide a terminal, for a total of three terminals. One or more transistors are connected to the terminals provided on the other electrodes of the memory element, and the result of the calculation is output from the common terminal.<u style="single">It is said.</u> With such a configuration<u style="single">By doing</u>In the memory element, since one electrode of the two variable resistance elements is a common terminal, the two variable resistance elements are connected in series between the other electrodes of the two variable resistance elements. Then, when a voltage is applied between these other electrodes, the voltage acts on one of the two variable resistance elements so as to change from a high resistance state to a low resistance state, and the other variable resistance. It acts complementarily to the element so as to change from a low resistance state to a high resistance state. As a result, one variable resistance element can be changed to a low resistance state and the other variable resistance element can be changed to a high resistance state, and the changed state can be stably maintained. Further, when a voltage having a polarity opposite to the above-mentioned voltage is applied between the other electrodes, one variable resistance element is changed to a high resistance state and the other variable resistance element is changed to a low resistance state. The combination of the resistance states of the 1 variable resistance element and the 2nd variable resistance element can be changed. Taking advantage of this, the combination of the resistance states of the first variable resistance element and the second variable resistance element is a high resistance state / low resistance state and a low resistance state / high resistance state. This makes it possible to store the data in the memory element.</p><p> Furthermore, when the resistance states of the two variable resistance elements change, the variable resistance element that was in the high resistance state first changes to the low resistance state, and then the variable resistance element that was in the low resistance state changes to the high resistance state. Therefore, the two variable resistance elements go through an intermediate state in which both are in a low resistance state. Since the time of the intermediate state is short and one of the other two variable resistance elements is in the high resistance state, the combined resistance of the entire memory element becomes high and constant, and the current flowing through the memory element becomes small. As a result, it is possible to reduce the current that flows by applying a voltage to the memory element when recording / erasing information or reading information. Further, the potential of the common terminal, that is, the output terminal of the memory element changes greatly depending on the combination of the resistance states of the first variable resistance element and the second variable resistance element, which is the content of the stored data of the memory element. A sufficient potential difference can be obtained at the output terminal where the result of the calculation is output. In addition, the voltage value of the output terminal can be set to two values.</p>

<p> According to the above-mentioned arithmetic circuit of the present invention, it is possible to realize a function considered to be ideal as a logic-in-memory that satisfies all of the following conditions. First, it does not require a high voltage and operates at a voltage similar to the power supply voltage of a CMOS circuit. Second, both AND (logical product) operations and OR (logical sum) operations of external input data and stored data are possible, and these operations can be switched. Third, both AND and OR operations between two external input data are possible, and the AND operation and OR operation can be switched according to the stored data. Fourth, it is possible to switch between the case of calculating without destroying the stored data and the case of leaving the calculation result as stored data according to the usage.</p><p> In particular, the memory element has a 3-terminal configuration in which two variable resistance elements are connected.<u style="single">By</u>Since the potential difference of the output depending on the calculation result can be increased, the margin for stable operation is widened regardless of whether the passgate transistor is turned on or off by the output or the output is amplified by a sense amplifier or the like. Can be secured. Further, since the voltage value of the output terminal can be set to two values, the output threshold voltage can be set to one type, so that the configuration of the next stage of the arithmetic circuit can be simplified. Then, it is possible to switch the operation of the logical product and the logical sum with a soft correspondence without changing the threshold voltage. Further, since the combined resistance in the stable state is high and constant, the current flowing through the variable resistance element becomes small, and the power consumption can be suppressed.</p>

As an embodiment of the present invention, FIG. 1 shows a schematic configuration diagram (circuit configuration diagram) of an arithmetic circuit. This arithmetic circuit constitutes the logic-in-memory described above, and is composed of one non-volatile device and four MOS transistors for control.

In the arithmetic circuit of the present embodiment, in particular, the variable resistance element R is used as the non-volatile device instead of the various non-volatile devices (ferroelectric, ferroelectric capacitor, TMR element) described above.

The variable resistance element R is provided with terminals Z1 and Z2 at both ends. In the MOS transistor MRD, the source is connected to the terminal Z1, the drain is connected to the terminal of the external input X, and the terminal of the clock CKX is connected to the gate. In the MOS transistor MRS, the source is connected to the terminal Z2, the drain is connected to the terminal of the external input W, and the terminal of the clock CKW is connected to the gate. In the MOS transistor MW1, the source is connected to the terminal Z1, the drain is connected to the terminal of the external input Y1, and the terminal of the clock CKY is connected to the gate. In the MOS transistor MW2, the source is connected to the terminal Z2, the drain is connected to the terminal of the external input Y2, and the terminal of the clock CKY is connected to the gate. Although it has been described here that the drain and the source are connected separately, since these can be interchanged with the MOS transistor, either of them may be connected to the external input side.

As the variable resistance element R, for example, the variable resistance element R having a film configuration shown in the cross-sectional view of FIG. 2A can be used. The variable resistance element R shown in FIG. 2A has a film structure in which a conductor film 3 and an insulator film 4 are sandwiched between two electrodes 1 and 2. When a voltage is applied so that the current I flows from the conductor film 3 to the insulator film 4, the variable resistance element R changes to a low resistance and data is written, and the current is written from the insulator film 4 to the conductor film 3. When a voltage is applied so that the current flows, the variable resistance element R changes to a high resistance and the data is erased. Further, the variable resistance element R can be described by a circuit symbol similar to the circuit symbol of a general variable resistor as shown in FIG. 2B, and the direction of the arrow is shown in FIG. 2A at the time of writing. It is made equal to the direction of the current I.

Examples of the conductor film 3 constituting the variable resistance element R include a metal film containing a metal element such as Cu, Ag, and Zn, an alloy film (for example, a CuTe alloy film), and a metal compound film. Further, as the insulator film 4, for example, amorphous Gd₂O₃Or SiO₂Insulators such as.

As a specific film configuration, for example, a CuTe film is formed as a conductor film 3 with a film thickness of 20 nm, and an amorphous Gd is formed as an insulator film 4 on the CuTe film.₂O₃A film is formed with a film thickness of 5 nm.

When such a material film is used, the metal elements such as Cu, Ag, and Zn contained in the conductor film 3 have a property of being ionized and attracted to the cathode side. Therefore, when a voltage is applied between the upper and lower electrodes 1 and 2 of the variable resistance element R so that the electrode 2 on the insulator film 4 side has a low potential, the ions of the metal element are attracted to the electrode 2 and the insulator It goes into the membrane 4. Then, when the ions reach the electrode 2, the upper and lower electrodes 1 and 2 conduct with each other and the resistance value decreases. On the other hand, when a voltage is applied between the upper and lower electrodes 1 and 2 of the variable resistance element R so that the electrode 1 on the conductor film 3 side has a low potential, the metal element is ionized and attracted to the electrode 1 to be an insulator. As it escapes from the film 4, the insulation between the upper and lower electrodes 1 and 2 increases, and the resistance value rises. By repeating such a change, the resistance value of the variable resistance element R can be reversibly changed between the high resistance state and the low resistance state.

The variable resistance element R having such a film structure has a feature that it is strong in scaling because it does not depend on the size of the element and can obtain a large signal. Further, it has an advantage that the data writing speed due to the resistance change can be increased to, for example, about 5 nanoseconds, and it can be operated at a low voltage (for example, about 1 V) and a low current (for example, about 20 μA).

In FIG. 1, the variable resistance element R is indicated by the same circuit symbol as in FIG. 2B, and is arranged so that the arrow points downward. That is, when a voltage is applied so that a current flows from the terminal Z1 to the terminal Z2, the variable resistance element R becomes low resistance, and when a voltage is applied so that a current flows from the terminal Z2 to the terminal Z1, the variable resistance element R becomes high. Become a resistance. Further, here, the resistance value when the variable resistance element R is high resistance is 100 kΩ, and the resistance value when the variable resistance element R is low resistance is 100 Ω. Furthermore, for the sake of simplicity, the on-resistance of the MOS transistor is set to 100Ω. These are not necessarily the same values, but they are generally reasonable values.

Then, as the stored data S, as shown in FIG. 1, the state in which the variable resistance element R has a low resistance (100Ω) is defined as S = 1 state, and the variable resistance element R has a high resistance (100kΩ). A state is defined as "S = 0 state".

Also, when the data write threshold of the variable resistance element R is defined as Vwr and the data erasure threshold is defined as Ver, 0.3V &lt;Ver &lt;1.0V, 0.3V &lt;Vwr &lt;1.0V (1) Is assumed to hold. The numbers used here are not always correct, but they are generally reasonable.

Further, the signal given to each terminal is defined as follows. The external input Y1 has a terminal voltage Vy1 = 0V when Y1 = 0 and a terminal voltage Vy1 = 1V when Y1 = 1. The external input Y2 has a terminal voltage Vy2 = 0V when Y2 = 0 and a terminal voltage Vy2 = 1V when Y2 = 1. The clock CKX has a voltage Vckx = 0V when CKX = 0 and a voltage Vckx = 1V when CKX = 1. The clock CKY has a voltage Vcky = 0V when CKY = 0 and a voltage Vcky = 1V when CKY = 1. The clock CKW is a reset input, and the voltage Vckw = 0V is set when CKW = 0, and the voltage Vckw = 1V is set when CKW = 1. The external input X has a terminal voltage of Vx = 0.0V when X = 0 and Vx = 0.3V when X = 1. The external input W has a terminal voltage of Vw = 0.0V when W = 0 and Vw = 0.3V when X = 1.

The basic operation of the arithmetic circuit of the present embodiment is that the variable resistance element R stores the stored data S via the MOS transistor, and then the external data and the stored data S input via any of the MOS transistors. A logical calculation is performed between and, and the result is output from one of the terminals Z1 and Z2 (terminal voltages Vz1 and Vz2) at both ends of the variable resistance element R.

There are two types of operation modes in the arithmetic circuit of the present embodiment: a non-destructive operation in which the stored data S is retained even after the operation, and a destructive operation in which the stored data S is changed by the operation.

First, a case where a non-destructive operation is performed between the external input W or the external input X and the stored data S will be described.

The operation procedure in this case is as follows. Prior to the calculation, the stored data S is written in the variable resistance element R. Specifically, after setting (Vy1, Vy2) = (1V, 0V) or (0V, 1V), set CKY = 1, CKX = CKW = 0. As a result, the transistors MW1 and MW2 are turned on and the transistors MRD and MRS are turned off, so that R = 100Ω or 100kΩ and S = 1 or S = 0 is written as the stored data S.

Next, the calculation with the external input is performed. Specifically, after setting one of the voltage Vx and the voltage Vw to 0.3V and the other to 0.0V according to the value (1 or 0) of the external input W or the external input X, CKY = 0. , CKX = CKW = 1. As a result, the transistors MW1 and MW2 are turned off and the transistors MRD and MRS are turned on. Therefore, there are four voltage 0V, 0.1V, 0.2 for Vz1 and Vz2 depending on the combination of W, X and S values. V, 0.3V appears. Then, by binarizing 0.05V or 0.25V with the threshold value Vth, the result of the logical operation of the external input X and the stored data S or the logical operation of the external input W and the stored data S can be obtained.

Table 1 shows the case where the non-destructive logical product is obtained between the external input X and the stored data S by fixing it to W = 0. In this case, by setting the threshold value Vth = 0.25V of Vz1, the calculation result of Z1 = X &amp; ~ S can be obtained, and by setting the threshold value Vth = 0.05V of Vz2, the calculation result of Z2 = X &amp; S can be obtained. Table 2 shows the case where the non-destructive OR is obtained between the external input X and the stored data S by fixing W = 1. In this case, by setting the threshold value Vth = 0.05V of Vz1, the calculation result of Z1 = X | S can be obtained, and by setting the threshold value Vth = 0.25V of Vz2, the calculation result of Z2 = X | ~ S can be obtained. Be done. Table 3 shows the case where the non-destructive logical product is obtained between the external input W and the stored data S by fixing X = 0. In this case, by setting the threshold value Vth = 0.05V of Vz1, the calculation result of Z1 = W &amp; S can be obtained, and by setting the threshold value Vth = 0.25V of Vz2, the calculation result of Z2 = W &amp; ~ S can be obtained. Table 4 shows the case where the non-destructive OR is obtained between the external input W and the stored data S by fixing X = 1. In this case, by setting the threshold value Vth = 0.25V of Vz1, the calculation result of Z1 = W | ~ S can be obtained, and by setting the threshold value Vth = 0.05V of Vz2, the calculation result of Z2 = W | S can be obtained. Be done. In Tables 1 to 4, the values of 299 μV appear in Vz1 and Vz2, but these are treated as 0.0V. It shall be handled in the same manner after this.

<tables num="1"><img file="JP4367281B2_D0001.tif" /></tables><tables num="2"><img file="JP4367281B2_D0002.tif" /></tables><tables num="3"><img file="JP4367281B2_D0003.tif" /></tables><tables num="4"><img file="JP4367281B2_D0004.tif" /></tables>

Next, a case where a destruction operation is performed between the two external inputs Y1 and Y2 and the stored data S will be described.

The operation procedure in this case is as follows. Prior to the calculation, the stored data S is written in the variable resistance element R. Specifically, after setting (Vx, Vw) = (1V, 0V) or (0V, 1V), set CKY = 0, CKX = CKW = 1. As a result, the transistors MW1 and MW2 are turned off, and the transistors MRD and MRS are turned on. Therefore, R = 100Ω or 100kΩ, and S = 1 or S = 0 is written as the stored data S.

Next, the external inputs Y1 and Y2 are calculated. Specifically, after setting the external input Y1 and the external input Y2 to either 1 or 0 (any of the four combinations), CKY = 1, CKX = CKW = 0. As a result, the transistors MW1 and MW2 are turned on and the transistors MRD and MRS are turned off, so that the voltage applied across the variable resistance element R changes according to the combination of the values of Y1 and Y2. Then, the resistance value of the variable resistance element R changes in only one of the four combinations (depending on the content of the stored data S), and the value of the stored data S is rewritten.

Next, the calculation result is read out. Specifically, after setting (Vx, Vw) = (0.0V, 0.3V) or (0.3V, 0.0V), set CKY = 0, CKX = CKW = 1. As a result, the transistors MW1 and MW2 are turned off and the transistors MRD and MRS are turned on. Therefore, there are four voltage 0V, 0.1V, 0.2 for Vz1 and Vz2 depending on the combination of Y1, Y2 and S values. V, 0.3V appears. Then, by binarizing 0.05V or 0.25V with the threshold value Vth, the logical operation between the external inputs Y1 and Y2, the logical operation between the external input Y1 and the stored data S, and the logic between the external input Y2 and the stored data S The result of the operation is obtained.

The four tables in Tables 5 to 8 show various combinations when performing logical operations (destructive operations) between two external inputs Y1 and Y2. Table 5 shows the case where the stored data is set to S = 0, the calculation is performed between the two external inputs Y1 and Y2, and the calculation result is read out at Vw = 0V and Vx = 0.3V. In this case, by setting the threshold value Vth = 0.25V of Vz1, the calculation result of Z1 = ~ Y1 | Y2 can be obtained, and by setting the threshold value Vth = 0.05V of Vz2, the calculation result of Z2 = Y1 &amp; ~ Y2 can be obtained. Be done. Table 6 shows the case where the stored data is set to S = 0, the calculation is performed between the two external inputs Y1 and Y2, and the calculation result is read out at Vw = 0.3V and Vx = 0V. In this case, by setting the threshold value Vth = 0.05V of Vz1, the calculation result of Z1 = Y1 &amp; ~ Y2 can be obtained, and by setting the threshold value Vth = 0.25V of Vz2, the calculation result of Z2 = ~ Y1 | Y2 can be obtained. Be done. Table 7 shows the case where the stored data is set to S = 1, the calculation is performed between the two external inputs Y1 and Y2, and the calculation result is read out at Vw = 0V and Vx = 0.3V. In this case, by setting the threshold value Vth = 0.25V of Vz1, the calculation result of Z1 = ~ Y1 &amp; Y2 can be obtained, and by setting the threshold value Vth = 0.05V of Vz2, the calculation result of Z2 = Y1 | ~ Y2 can be obtained. .. Table 8 shows a case where the stored data is set to S = 1, the calculation is performed between the two external inputs Y1 and Y2, and the calculation result is read out at Vw = 0.3V and Vx = 0V. In this case, by setting the threshold value Vth = 0.05V of Vz1, the calculation result of Z1 = Y1 | ~ Y2 can be obtained, and by setting the threshold value Vth = 0.25V of Vz2, the calculation result of Z2 = ~ Y1 &amp; Y2 can be obtained. ..

<tables num="5"><img file="JP4367281B2_D0005.tif" /></tables><tables num="6"><img file="JP4367281B2_D0006.tif" /></tables><tables num="7"><img file="JP4367281B2_D0007.tif" /></tables><tables num="8"><img file="JP4367281B2_D0008.tif" /></tables>

The four tables in Tables 9 to 12 show various combinations when performing logical operations (destructive operations) between the external input Y2 and the stored data S. Table 9 shows the case where Y1 = 0 is fixed, the external input Y2 and the stored data S are calculated, and the calculation result is read out at Vw = 0V and Vx = 0.3V. In this case, by setting the threshold value Vth = 0.25V of Vz1, the calculation result of Z1 = ~ S | Y2 can be obtained, and by setting the threshold value Vth = 0.05V of Vz2, the calculation result of Z2 = S &amp; ~ Y2 can be obtained. Be done. Table 10 shows a case where Y1 = 0 is fixed, an operation is performed between the external input Y2 and the stored data S, and the operation result is read out at Vw = 0.3V and Vx = 0V. In this case, by setting the threshold value Vth = 0.05V of Vz1, the calculation result of Z1 = S &amp; ~ Y2 can be obtained, and by setting the threshold value Vth = 0.25V of Vz2, the calculation result of Z2 = ~ S | Y2 can be obtained. Be done. Table 11 shows a case where Y1 = 1 is fixed, an operation is performed between the external input Y2 and the stored data S, and the operation result is read out at Vw = 0V and Vx = 0.3V. In this case, by setting the threshold value Vth = 0.25V of Vz1, the calculation result of Z1 = ~ S &amp; Y2 can be obtained, and by setting the threshold value Vth = 0.05V of Vz2, the calculation result of Z2 = S | ~ Y2 can be obtained. .. Table 12 shows a case where Y1 = 1 is fixed, an operation is performed between the external input Y2 and the stored data S, and the operation result is read out at Vw = 0.3V and Vx = 0V. In this case, by setting the threshold value Vth = 0.05V of Vz1, the calculation result of Z1 = S | ~ Y2 can be obtained, and by setting the threshold value Vth = 0.25V of Vz2, the calculation result of Z2 = ~ S &amp; Y2 can be obtained. ..

<tables num="9"><img file="JP4367281B2_D0009.tif" /></tables><tables num="10"><img file="JP4367281B2_D0010.tif" /></tables><tables num="11"><img file="JP4367281B2_D0011.tif" /></tables><tables num="12"><img file="JP4367281B2_D0012.tif" /></tables>

The four tables in Tables 13 to 16 show various combinations when performing a logical operation (destructive operation) of the external input Y1 and the stored data S. Table 13 shows a case where Y2 = 0 is fixed, the external input Y1 and the stored data S are calculated, and the calculation result is read out at Vw = 0V and Vx = 0.3V. In this case, by setting the threshold value Vth = 0.25V of Vz1, the calculation result of Z1 = ~ (Y1 | S) can be obtained, and by setting the threshold value Vth = 0.05V of Vz2, the calculation result of Z2 = Y1 | S. Is obtained. Table 14 shows a case where Y2 = 0 is fixed, an operation is performed between the external input Y1 and the stored data S, and the operation result is read out at Vw = 0.3V and Vx = 0V. In this case, by setting the threshold value Vth = 0.05V of Vz1, the calculation result of Z1 = Y1 | S can be obtained, and by setting the threshold value Vth = 0.25V of Vz2, the calculation result of Z2 = ~ (Y1 | S) can be obtained. Is obtained. Table 15 shows a case where Y2 = 1 is fixed, an operation is performed between the external input Y1 and the stored data S, and the operation result is read out at Vw = 0V and Vx = 0.3V. In this case, by setting the threshold value Vth = 0.25V of Vz1, the calculation result of Z1 = ~ (Y1 &amp; S) can be obtained, and by setting the threshold value Vth = 0.05V of Vz2, the calculation result of Z2 = Y1 &amp; S can be obtained. Table 16 shows a case where Y2 = 1 is fixed, an operation is performed between the external input Y1 and the stored data S, and the operation result is read out at Vw = 0.3V and Vx = 0V. In this case, by setting the threshold value Vth = 0.05V of Vz1, the calculation result of Z1 = Y1 &amp; S can be obtained, and by setting the threshold value Vth = 0.25V of Vz2, the calculation result of Z2 = ~ (Y1 &amp; S) can be obtained.

<tables num="13"><img file="JP4367281B2_D0013.tif" /></tables><tables num="14"><img file="JP4367281B2_D0014.tif" /></tables><tables num="15"><img file="JP4367281B2_D0015.tif" /></tables><tables num="16"><img file="JP4367281B2_D0016.tif" /></tables>

Since Z2 = ~ Z1 in any of the cases shown in Tables 5 to 16, it is possible to obtain an inverted output or a non-inverting output by selecting the output terminals Z1 and Z2 as necessary. it can.

According to the configuration of the arithmetic circuit of the present embodiment, the variable resistance element R is used as the non-volatile device to configure the arithmetic circuit including the arithmetic unit and the memory element, so that the arithmetic circuit operates at high speed and the arithmetic is performed. The circuit can be configured compactly. Then, due to the characteristics of the variable resistance element R, the storage data S can be written by changing the resistance value of the variable resistance element R at a relatively low voltage (for example, about 2V). Furthermore, non-destructive operations, operations between external inputs, and operations between external inputs and stored data are all possible, and AND (logical product) operations and OR (logical sum) operations can be performed, respectively.

In addition, switching between AND operation and OR operation in non-destructive operation changes the read-out voltage (either Vx or Vw) and the threshold voltage Vth of the output terminals Z1 and Z2, for example, as shown in Tables 1 and 2. By doing so, switching is possible. Switching between AND operation and OR operation in the operation between external inputs is performed by changing the read voltage (Vx and Vw) and the threshold voltage Vth of the output terminals Z1 and Z2, for example, as shown in Tables 5 and 6. , Can be switched. Switching between AND operation and OR operation in the operation of external input and stored data also changes the read voltage (Vx and Vw) and the threshold voltage Vth of the output terminals Z1 and Z2, as shown in Tables 9 and 10, for example. By doing so, switching is possible.

Therefore, according to the arithmetic circuit of the present embodiment, it is possible to realize a function considered to be ideal as a logic-in-memory that satisfies all of the following conditions. First, it does not require a high voltage and operates at a voltage similar to the power supply voltage of a CMOS circuit. Secondly, both AND operation and OR operation of external input data and stored data are possible, and these operations can be switched. Third, both AND and OR operations between two external input data are possible, and the AND operation and OR operation can be switched according to the stored data. Fourth, it is possible to switch between the case of calculating without destroying the stored data and the case of leaving the calculation result as stored data, depending on how it is used.

In particular, the variable resistance element R having a film structure shown in FIG. 2A has a feature that it is strong in scaling because it does not depend on the size of the element and can obtain a large signal.

The specific settings of the external input and the clock voltage are not limited to the values described above, and various other settings are possible. Further, each resistance value of the variable resistance element R in the high resistance state and the low resistance state can be arbitrarily set depending on the film configuration, particularly the composition and film thickness of each layer.

By the way, a memory element (so-called phase change memory element) that uses a material such as GeSbTe for the recording layer and changes the resistance value by changing the recording layer between a crystalline state and an amorphous state by a method of applying a current pulse. ). This phase change storage element can obtain a large resistance change and can be used as a non-volatile device. However, this phase change storage element uses temperature change as a recording principle. For example, the temperature at which the transition from the amorphous state to the crystalline state (crystallization temperature) is about 200 ° C. Therefore, the temperature change in the external environment. There is a risk that the operation will become extremely unstable due to temperature changes that accompany the temperature rise during device operation. Further, in order to transition to the crystalline state, it is necessary to keep the temperature above a certain level for a certain long time (at least 50 nanoseconds or more), so that it is not suitable for application to a device for a high-speed logic circuit.

On the other hand, the variable resistance element R having a film structure shown in FIG. 2A has a feature that it is strong in scaling because it does not depend on the size of the element and can obtain a large signal. Further, it has an advantage that the data writing speed due to the resistance change can be increased to, for example, about 5 nanoseconds, and it can be operated at a low voltage (for example, about 1 V) and a low current (for example, about 20 μA).

The arithmetic circuit of the above-described embodiment can realize a function considered to be ideal as a logic-in-memory, which cannot be realized by an arithmetic circuit using a conventional non-volatile device. However, there is still room for improvement in the following three points. First, in the S = 1 state where the variable resistance element R has a low resistance, a large current flows through the arithmetic circuit, so that the power consumption increases. Secondly, since the on-resistance of the MOS transistor and the low resistance value of the variable resistance element R are almost equal, the terminal voltages Vz1 and Vz2 at the time of reading are divided by the voltages Vw and Vz applied to the arithmetic circuit. It becomes a value. Therefore, the difference in voltage level between the case where the calculation result is 0 and the case where the calculation result is 1 becomes small. Third, there are four output voltage values when reading (0V, 0.1V, 0.2V, 0.3V in a specific example), and there are two types of voltage thresholds (0V, 0.1V, 0.2V, 0.3V in a specific example) to distinguish the output between 1 and 0. In a specific example, 0.05V, 0.25V) is required.

Therefore, the configuration of the arithmetic circuit that improves these three points is shown below. As another embodiment of the present invention, a schematic configuration diagram (circuit configuration diagram) of an arithmetic circuit is shown in FIG. This arithmetic circuit constitutes the logic-in-memory described above, and is composed of a non-volatile device and four control MOS transistors.

In the arithmetic circuit of the present embodiment, in particular, as a non-volatile device, two variable resistance elements R1 and R2 are connected in series in a complementary manner. The first variable resistance element 11 (R1) has a downward arrow, and has a low resistance when a voltage is applied so that a current flows downward, and a high resistance when a voltage of the opposite polarity is applied. become. The second variable resistance element 12 (R2) has an arrow pointing upward, and becomes low resistance when a voltage is applied so that current flows upward, and high resistance when a voltage of the opposite polarity is applied. become. Since the first variable resistance element R1 and the second variable resistance element R2 are connected in series, one variable resistance element has a low resistance and the other variable resistance element has a low resistance according to the voltage polarity. It becomes high resistance.

These two variable resistance elements 11 (R1) and 12 (R2) can have the configuration shown in FIG. 4A, for example. The first variable resistance element 11 (R1) and the second variable resistance element 12 (R2) both have a conductor film 3 between the electrodes 1 and 2, similarly to the variable resistance element R shown in FIG. 2A. It has a film structure provided with an insulator film 4. Then, in the two variable resistance elements 11 and 12, the electrodes 2 on the insulator film 4 side are connected to form a common terminal Z, and the electrodes 1 on the conductor film 3 side are connected to the A terminal and the B terminal, respectively. It constitutes a memory element 10 with three terminals. With this configuration, in the circuit symbol, as shown in FIG. 4B, the arrows of the two variable resistance elements 11 and 12 face each other.

Instead of the configuration shown in FIG. 4A, as shown in FIG. 5A, in the two variable resistance elements 11 and 12, the electrodes 1 on the conductor film 3 side are connected to form a common terminal Z, and the insulator film 4 side. By connecting the electrodes 2 to the A terminal and the B terminal, respectively, a configuration in which a complementary 3-terminal memory element 20 may be used may be used. In this case, in the circuit symbol, as shown in FIG. 5B, the arrows of the two variable resistance elements 11 and 12 face each other.

Next, a specific operation in the configuration of the memory element 10 shown in FIG. 4A will be described. Here, the resistance value when the variable resistance elements R1 and R2 are high resistance is 100 kΩ, and the resistance value when the variable resistance elements R1 and R2 are low resistance is 100 Ω. First, the four states that the memory element 10 can take are shown in FIGS. 6A to 6D. Then, as shown in FIG. 6A, the first variable resistance element 11 connected to the terminal A has a low resistance (100Ω), and the second variable resistance element 12 connected to the terminal B has a high resistance (100kΩ). ) Is defined as "S = 1 state", and as shown in FIG. 6B, the first variable resistance element 11 connected to the terminal A has a high resistance (100 kΩ) and is connected to the terminal B. The state in which the second variable resistance element 12 has a low resistance (100Ω) is defined as the S = 0 state. Further, as shown in FIG. 6C, the state in which the two variable resistance elements 11 and 12 are both low resistance is called an "intermediate state", and as shown in FIG. 6D, the two variable resistance elements 11 and 12 are in a low resistance state. The state in which both have high resistance is called the "prohibited state".

Subsequently, FIG. 7 shows a state transition diagram illustrating the operation when the writing voltages Va and Vb are applied to the terminals A and B in order to write data to the memory element. In FIG. 7, the resistance values of the variable resistance elements 11 and 12 (the resistance value of the first variable resistance element 11 / the resistance value of the second variable resistance element 12) are shown in the circle of each state, and each state is described. The transition is indicated by an arrow, and {Va, Vb} / Vz is described as the voltage applied to each terminal A, B, Z of the storage element 10 with respect to this arrow.

First, in the case of "S = 1 state" (100Ω / 100kΩ) on the upper side of FIG. 7, the first variable resistance element 11 connected to the terminal A has a low resistance (100Ω) and is connected to the terminal B. The second variable resistance element 12 has a high resistance (100 kΩ). In this state, when a voltage of Va = 2V, Vb = 0V is applied, a current flows from terminal A to terminal B, which is also a high resistance second variable resistance for the low resistance first variable resistance element 11. Since it is a stable direction for element 12, only Vz = 2.0V. Therefore, as shown by the arrow ({2,0} / 2) above the circle representing the S = 1 state in FIG. 7, the states of the variable resistance elements 11 and 12 do not change.

Next, in the "S = 1 state" (100Ω / 100kΩ), when a voltage of Va = 0V, Vb = 2V is applied, a current flows from terminal B to terminal A, but the second variable resistance element 12 has a high resistance. Since it is (100 kΩ), the potential Vz of terminal Z is 0.0 V. As a result, a voltage of 2V in the writing direction is applied to the second variable resistance element 12 having a high resistance, so that the second variable resistance element 12 changes to a low resistance (100Ω), and S = in the upper middle of FIG. It changes from "1 state" (100Ω / 100kΩ) to the intermediate state (100Ω / 100Ω) on the right side.

In this intermediate state (100Ω / 100Ω), the two variable resistance elements 11 and 12 both have low resistance (100Ω), so the voltage of 2V between AB is divided by half and Vz = 1.0V. Therefore, a voltage of 1 V is applied to the first variable resistance element 11 in the erasing direction. Then, the first variable resistance element 11 changes to a high resistance (100 kΩ), and therefore, from the intermediate state (100 Ω / 100 Ω) on the right side in FIG. 7, the lower S = 0 state (100 kΩ / 100 Ω). It becomes stable and Vz = 0.0V.

Similarly, in the case of "S = 0 state" (100 kΩ / 100 Ω) on the lower side of FIG. 7, the first variable resistance element 11 connected to the terminal A has a high resistance (100 kΩ) and is connected to the terminal B. The second variable resistance element 12 is a low resistance (100Ω). In this state, when a voltage of Va = 0V, Vb = 2V is applied, a current flows from terminal B to terminal A, which is also the first variable resistance with high resistance even for the second variable resistance element 12 with low resistance. Since it is a stable direction for element 11, only Vz = 0V. Therefore, as shown by the arrow ({0,2} / 0) below the circle representing the S = 0 state in FIG. 7, the states of the variable resistance elements 11 and 12 do not change.

Next, in the "S = 0 state" (100kΩ / 100Ω), when a voltage of Va = 2V, Vb = 0V is applied, a current flows from terminal A to terminal B, but the first variable resistance element 11 has a high resistance. Since it is (100 kΩ), the potential Vz of terminal Z is 0.0 V. As a result, a voltage of 2V in the writing direction is applied to the first variable resistance element 11 having a high resistance, so that the first variable resistance element 11 changes to a low resistance (100Ω), and the lower S in FIG. It changes from "= 0 state" (100kΩ / 100Ω) to the intermediate state (100Ω / 100Ω) on the left side.

In this intermediate state (100Ω / 100Ω), the two variable resistance elements 11 and 12 both have low resistance (100Ω), so the voltage of 2V between AB is divided in half and Vz = 1.0V. Therefore, a voltage of 1 V is applied to the second variable resistance element 12 in the erasing direction. Then, the second variable resistance element 12 changes to a high resistance (100 kΩ), and changes from the intermediate state (100 Ω / 100 Ω) on the left side in FIG. 7 to the S = 1 state (100 Ω / 100 kΩ) on the upper side. It becomes stable and Vz = 2.0V.

As described above, in the memory element 10 having the configuration shown in FIG. 4A, the two variable resistance elements 11 and 12 connected to the complementary elements have different resistance values of high resistance and low resistance, and which element has a low resistance. It is characterized in that it distinguishes whether the stored data is 1 or 0 depending on whether it is a resistance. In addition, when the data is rewritten, unlike the operation of one variable resistance element R, it changes to a stable "S = 1 state" or "S = 0 state" after passing through an unstable "intermediate state". It is characterized by the fact that it does.

The "prohibited state" shown in FIG. 6D, that is, the state in which the two variable resistance elements 11 and 12 both have high resistance is the initial state of the memory element 10. In this state, even if a potential difference of 2 V is applied to the terminals A and B on both sides, neither of the variable resistance elements 11 and 12 becomes low resistance. Therefore, by applying a voltage larger than the data write threshold value Vwr between the common terminal Z of the memory element 10 and the terminals A and B on both sides, two or one non-volatile variable resistance elements 11 and 12 are provided. It is necessary to perform an operation (initialization) to reduce the resistance. By performing this operation, the memory element 10 enters the state transition cycle shown in FIG. 7, and data writing and data erasing operations become possible.

Since the memory element 10 described in FIGS. 4 and 6 to 7 is used in the arithmetic circuit of the present embodiment, the first variable resistance element 11 (R1) is used as the stored data S as shown in FIG. ) Is low resistance (100Ω) and the second variable resistance element 12 (R2) is high resistance (100kΩ) is defined as S = 1 state, and the first variable resistance element 11 (R1) is The state in which the resistance is high (100 kΩ) and the second variable resistance element 12 (R2) is low resistance (100 Ω) is defined as the S = 0 state.

Further, when the data writing threshold value of the two variable resistance elements 11 and 12 is defined as Vwr and the data erasure threshold value is defined as Ver, it is different from the above equation (1). 0.4V &lt;Ver &lt;0.5V, 0.4V &lt;Vwr &lt;2.0V (2) Is assumed to hold. Furthermore, for the sake of simplicity, the on-resistance of the MOS transistor is set to 100Ω. The numbers used here are not always correct, but they are generally reasonable.

In the arithmetic circuit of the present embodiment, the output terminals Z are provided between the two variable resistance elements 11 and 12, and the terminals at both ends are not provided with output terminals. The configurations of the MOS transistors MRD, MRS, MW1, MW2 for control, the terminals of the external inputs X, W, Y1, Y2, and the terminals of the clock CKX, CKW, CKY are the same as those of the previous embodiment shown in FIG. It is similar to the arithmetic circuit. Then, the source of the MOS transistor MRD and the source of the MOS transistor MW1 are connected to one end (terminal A in FIG. 4) of the first variable resistance element 11, and the source of the MOS transistor MRS and the source of the MOS transistor MW2 are the second. It is connected to one end (terminal B in FIG. 4) of the variable resistance element 12 of. In this section, it was explained that the drain and the source are connected separately, but since these can be interchanged with the MOS transistor, it does not matter which one is connected to the variable resistance elements 11 and 12. ..

Further, the signal given to each terminal is defined as follows. The external input Y1 has a terminal voltage Vy1 = 0V when Y1 = 0 and a terminal voltage Vy1 = 2V when Y1 = 1. The external input Y2 has a terminal voltage Vy2 = 0V when Y2 = 0 and a terminal voltage Vy2 = 2V when Y2 = 1. The clock CKX has a voltage Vckx = 0V when CKX = 0 and a voltage Vckx = 1V when CKX = 1. The clock CKY has a voltage Vcky = 0V when CKY = 0 and a voltage Vcky = 1V when CKY = 1. The clock CKW is a reset input, and the voltage Vckw = 0V is set when CKW = 0, and the voltage Vckw = 1V is set when CKW = 1. The external input X has a terminal voltage of Vx = 0.3V when X = 0 and Vx = 0.7V when X = 1. The external input W has a terminal voltage of Vw = 0.3V when W = 0 and Vw = 0.7V when X = 1.

The basic operation of the arithmetic circuit of the present embodiment is to store the stored data S in a memory element composed of two variable resistance elements 11 and 12 via a MOS transistor, and then input the stored data S via one of the MOS transistors. A logical calculation is performed between the external data and the stored data S, and the result is output from the terminal Z (terminal voltage Vz) between the two variable resistance elements 11 and 12.

There are two types of operation modes in the arithmetic circuit of the present embodiment: a non-destructive operation in which the stored data S is retained even after the operation, and a destructive operation in which the stored data S is changed by the operation.

First, a case where a non-destructive operation is performed between the external input W or the external input X and the stored data S will be described.

The operation procedure in this case is as follows. Prior to the calculation, the stored data S is written to the variable resistance elements 11 (R1) and 12 (R2). Specifically, after setting (Vy1, Vy2) = (2V, 0V) or (0V, 2V), set CKY = 1, CKX = CKW = 0. As a result, the transistors MW1 and MW2 are turned on and the transistors MRD and MRS are turned off, so that (R1, R2) = (100Ω, 100kΩ) or (100kΩ, 100Ω), and S = 1 as the stored data S. Or S = 0 is written.

Next, the calculation with the external input is performed. Specifically, after setting one of the voltage Vx and the voltage Vw to 0.7V and the other to 0.3V according to the value (1 or 0) of the external input W or the external input X, CKY = 0. , CKX = CKW = 1. As a result, the transistors MW1 and MW2 are turned off, and the transistors MRD and MRS are turned on. Therefore, two voltages of 0.3V and 0.7V appear in Vz according to the combination of the values of W, X and S. Then, by binarizing 0.5 V as the threshold value Vth, the result of the logical operation of the external input X and the stored data S or the logical operation of the external input W and the stored data S can be obtained.

Table 17 shows a case where a logical operation of the external input X and the stored data S or a logical operation of the external input W and the stored data S is performed. In this case, by setting the threshold value Vth = 0.5V of Vz, the calculation result of Z = ~ W &amp; (X &amp; S) | W &amp; (X | ~ S) can be obtained. From this calculation result, if you fix W = 0 and calculate X and S, it becomes an AND operation, if you fix it to W = 1 and calculate X and S, it becomes an OR operation, and if you fix it to X = 0, it becomes W. When S is calculated, it becomes AND operation, and when W and S are calculated by fixing X = 1, it becomes OR operation.

<tables num="17"><img file="JP4367281B2_D0017.tif" /></tables>

In this embodiment, since the memory element 10 having three terminals composed of the two variable resistance elements 11 and 12 is used, there are two values of the output terminal voltage Vz, and each value of W, X, and S is combined. In response to the, Z = ~ W &amp; (X &amp; S) | W &amp; (X | ~ S) Therefore, it is much easier to handle than the arithmetic circuit of the previous embodiment.

Next, a case where a destruction operation is performed between the two external inputs Y1 and Y2 and the stored data S will be described.

The operation procedure in this case is as follows. Prior to the calculation, the stored data S is written to the variable resistance elements 11 (R1) and 12 (R2). Specifically, after setting (Vx, Vw) = (2V, 0V) or (0V, 2V), set CKY = 0, CKX = CKW = 1. As a result, the transistors MW1 and MW2 are turned off and the transistors MRD and MRS are turned on. Therefore, (R1, R2) = (100Ω, 100kΩ) or (100kΩ, 100Ω), and S = 1 as the stored data S. Or S = 0 is written.

Next, the external inputs Y1 and Y2 are calculated. Specifically, after setting the external input Y1 and the external input Y2 to either 1 or 0 (any of the four combinations), CKY = 1, CKX = CKW = 0. As a result, the transistors MW1 and MW2 are turned on and the transistors MRD and MRS are turned off, so that the voltage applied to both ends of the variable resistance elements 11 and 12 changes according to the combination of the values of Y1 and Y2. Then, the resistance values R1 and R2 of the variable resistance elements 11 and 12 change in only one of the four combinations (depending on the content of the stored data S), and the value of the stored data S is rewritten.

Next, the calculation result is read out. Specifically, it is set to (Vx, Vw) = (0.3V, 0.7V) or (0.7V, 0.3V), and CKY = 0, CKX = CKW = 1. As a result, the transistors MW1 and MW2 are turned off and the transistors MRD and MRS are turned on. Therefore, two voltages of 0.3V and 0.7V appear in Vz according to the combination of the values of Y1, Y2 and S. Then, by binarizing 0.5V as the threshold value Vth, the result of the logical operation between the external input Y1 and Y2, the logical operation between the external input Y1 and the stored data S, and the logical operation between the external input Y2 and the stored data S. Is obtained.

The four tables in Tables 18 to 21 show various combinations when performing logical operations (destructive operations) between two external inputs Y1 and Y2. Table 18 shows a case where the stored data is set to S = 0, the calculation is performed between the two external inputs Y1 and Y2, and the calculation result is read out at Vx = 0.7V and Vw = 0.3V. In this case, by setting the threshold value Vth = 0.5V of Vz, the calculation result of Z = Y1 &amp; ~ Y2 can be obtained. Table 19 shows a case where the stored data is set to S = 0, the calculation is performed between the two external inputs Y1 and Y2, and the calculation result is read out at Vx = 0.3V and Vw = 0.7V. In this case, by setting the threshold value Vth = 0.5V of Vz, the calculation result of Z = ~ Y1 | Y2 can be obtained. Table 20 shows a case where the stored data is set to S = 1, the operation is performed between the two external inputs Y1 and Y2, and the operation result is read out at Vx = 0.7V and Vw = 0.3V. In this case, by setting the threshold value Vth = 0.5V of Vz, the calculation result of Z = Y1 | ~ Y2 can be obtained. Table 21 shows a case where the stored data is set to S = 1, the calculation is performed between the two external inputs Y1 and Y2, and the calculation result is read out at Vx = 0.3V and Vw = 0.7V. In this case, by setting the threshold value Vth = 0.5V of Vz, the calculation result of Z = ~ Y1 &amp; Y2 can be obtained.

<tables num="18"><img file="JP4367281B2_D0018.tif" /></tables><tables num="19"><img file="JP4367281B2_D0019.tif" /></tables><tables num="20"><img file="JP4367281B2_D0020.tif" /></tables><tables num="21"><img file="JP4367281B2_D0021.tif" /></tables>

The four tables from Table 22 to Table 25 show various combinations when performing a logical operation (destructive operation) of the external input Y2 and the stored data S. Table 22 shows a case where Y1 = 0 is fixed, an operation is performed between the external input Y2 and the stored data S, and the operation result is read out at Vx = 0.7V and Vw = 0.3V. In this case, by setting the threshold value Vth = 0.5V of Vz, the calculation result of Z = S &amp; ~ Y2 can be obtained. Table 23 shows the case where Y1 = 0 is fixed, the external input Y2 and the stored data S are calculated, and the calculation result is read out at Vx = 0.3V and Vw = 0.7V. In this case, by setting the threshold value Vth = 0.5V of Vz, the calculation result of Z = ~ S | Y2 can be obtained. Table 24 shows a case where Y1 = 1 is fixed, an operation is performed between the external input Y2 and the stored data S, and the operation result is read out at Vx = 0.7V and Vw = 0.3V. In this case, by setting the threshold value Vth = 0.5V of Vz, the calculation result of Z = S | ~ Y2 can be obtained. Table 25 shows a case where Y1 = 1 is fixed, an operation is performed between the external input Y2 and the stored data S, and the operation result is read out at Vx = 0.3V and Vw = 0.7V. In this case, by setting the threshold value Vth = 0.5V of Vz, the calculation result of Z = ~ S &amp; Y2 can be obtained.

<tables num="22"><img file="JP4367281B2_D0022.tif" /></tables><tables num="23"><img file="JP4367281B2_D0023.tif" /></tables><tables num="24"><img file="JP4367281B2_D0024.tif" /></tables><tables num="25"><img file="JP4367281B2_D0025.tif" /></tables>

The four tables from Table 26 to Table 29 show various combinations when performing a logical operation (destructive operation) of the external input Y1 and the stored data S. Table 26 shows a case where Y2 = 1 is fixed, an operation is performed between the external input Y1 and the stored data S, and the operation result is read out at Vx = 0.7V and Vw = 0.3V. In this case, the calculation result of Z = S &amp; Y1 can be obtained by setting the threshold value Vth = 0.5V of Vz. Table 27 shows a case where Y2 = 1 is fixed, an operation is performed between the external input Y1 and the stored data S, and the operation result is read out at Vx = 0.3V and Vw = 0.7V. In this case, by setting the threshold value Vth = 0.5V of Vz, the calculation result of Z = ~ S | ~ Y1 can be obtained. Table 28 shows a case where Y2 = 0 is fixed, calculation is performed between the external input Y1 and the stored data S, and the calculation result is read out at Vx = 0.7V and Vw = 0.3V. In this case, by setting the threshold value Vth = 0.5V of Vz, the calculation result of Z = S | Y1 can be obtained. Table 29 shows the case where Y2 = 0 is fixed, the external input Y1 and the stored data S are calculated, and the calculation result is read out at Vx = 0.3V and Vw = 0.7V. In this case, by setting the threshold value Vth = 0.5V of Vz, the calculation result of Z = ~ S &amp; ~ Y1 can be obtained.

<tables num="26"><img file="JP4367281B2_D0026.tif" /></tables><tables num="27"><img file="JP4367281B2_D0027.tif" /></tables><tables num="28"><img file="JP4367281B2_D0028.tif" /></tables><tables num="29"><img file="JP4367281B2_D0029.tif" /></tables>

According to the configuration of the arithmetic circuit of the present embodiment, the variable resistance elements 11 and 12 are used as the non-volatile device to configure the arithmetic circuit including the arithmetic unit and the memory element, which is shown in FIG. Similar to the arithmetic circuit of the previous embodiment, the arithmetic circuit can be operated at high speed and the arithmetic circuit can be compactly configured. Then, due to the characteristics of the variable resistance elements 11 and 12, the storage data S can be written by changing the resistance value of the variable resistance elements 11 and 12 at a relatively low voltage (for example, about 2V). Furthermore, non-destructive operations, operations between external inputs, and operations between external inputs and stored data are all possible, and AND (logical product) operations and OR (logical sum) operations can be performed, respectively.

Further, switching between the AND operation and the OR operation in the non-destructive operation can be easily performed by changing one of the external inputs (X or W) in Table 17, for example. Switching between AND operation and OR operation in the operation between external inputs can be easily performed by changing the reading voltage (Vx and Vw), for example, as shown in Tables 18 and 19. Switching between the AND operation and the OR operation in the operation of the external input and the stored data can be easily performed by changing the reading voltage (Vx and Vw), for example, as shown in Tables 22 and 23. In the arithmetic circuit of the present embodiment, since it is not necessary to change the threshold voltage Vth of the output Z in order to switch between the AND operation and the OR operation in these operations, the switching can be easily performed.

Therefore, according to the arithmetic circuit of the present embodiment, it is possible to realize a function considered to be ideal as a logic-in-memory that satisfies all of the following conditions. First, it does not require a high voltage and operates at a voltage similar to the power supply voltage of a CMOS circuit. Secondly, both AND operation and OR operation of external input data and stored data are possible, and these operations can be switched. Third, both AND and OR operations between two external input data are possible, and the AND operation and OR operation can be switched according to the stored data. Fourth, it is possible to switch between the case of calculating without destroying the stored data and the case of leaving the calculation result as stored data according to the usage.

Further, according to the arithmetic circuit of the present embodiment, since a three-terminal memory element in which two variable resistance elements 11 and 12 are complementaryly connected is used, the two variables are variable regardless of the contents of the stored data S. Since the combined resistance of the resistance elements 11 and 12 has a high resistance and a constant value, the power consumption can be reduced.

Moreover, since the on-resistance (for example, about 100Ω) of the MOS transistors MRD and MRS is sufficiently smaller than the magnitude of the combined resistance of the two variable resistance elements 11 and 12, the read voltage is divided by the MOS transistors MRD and MRS. There is a large difference in output voltage level between 1 and 0 without being pressed. In addition, there are two values of the output voltage Vz, and only one type of threshold voltage (for example, 0.5V) is required to distinguish between 1 and 0 of the calculation result. Then, even if the threshold voltage is not changed, the AND operation and the OR operation can be easily switched only by changing the voltage at the time of reading, that is, by soft correspondence.

Therefore, the above-mentioned three points can be improved with respect to the arithmetic circuit of the above-described embodiment shown in FIG.

The specific settings of the external input and the clock voltage are not limited to the values described above, and various other settings are possible. Further, each resistance value of the variable resistance element R in the high resistance state and the low resistance state can be arbitrarily set depending on the film configuration, particularly the composition and film thickness of each layer.

In each of the arithmetic circuits of the above-described embodiments, four MOS transistors for control are used to form the arithmetic circuit. On the other hand, the number of MOS transistors for control can be reduced to two to form an arithmetic circuit capable of the same operation. That is, in the arithmetic circuit of each of the above-described embodiments, the two MOS transistors MRD and MRS are turned on and off at the same time, so that the clocks CKX and CKW input to these gates can be shared. Further, since the MOS transistors MRD and MRS and the MOS transistors MW1 and MW2 are exclusively turned on and off, they can be shared. Therefore, it is possible to realize the same operation even if the MOS transistors MRD and MRS are deleted and there are only two MOS transistors MW1 and MW2 and only one input clock to the gate. is there.

FIG. 8 shows a schematic configuration diagram (circuit configuration diagram) of the arithmetic circuit having such a simplified configuration with respect to the arithmetic circuit shown in FIG. In the arithmetic circuit shown in FIG. 8, the MOS transistors MRD, MRS and the terminals of the inputs X, CKX, W, CKW to their gates and drains are deleted from the arithmetic circuit shown in FIG. 1, and the MOS transistor for control is used. Only two MOS transistors MW1 and MW2 are used. Since the other configurations are the same as those in FIG. 1, the same reference numerals are given and duplicate description is omitted. In FIG. 8, the data writing threshold value Vwr of the variable resistance element R and the data erasure threshold value Ver are set. 0.3V &lt;Ver &lt;1.0V, 0.3V &lt;Vwr &lt;1.0V (1) Is assumed to hold.

The calculation circuit shown in FIG. 8 has the same operation mode as the calculation circuit shown in FIG. 1, and the operation procedure is also substantially the same as the calculation circuit shown in FIG.

First, the operation procedure when performing a non-destructive operation between the external input Y1 or the external input Y2 and the stored data S is as follows. Prior to the calculation, the stored data S is written in the variable resistance element R. Specifically, after setting (Vy1, Vy2) = (1V, 0V) or (0V, 1V), set CKY = 1. As a result, the transistors MW1 and MW2 are turned on, so R = 100Ω or 100kΩ, and S = 1 or S = 0 is written as the stored data S.

Next, the calculation with the external input is performed. Specifically, after setting one of the voltage Vy1 and the voltage Vy2 to 0.3V and the other to 0.0V according to the value (1 or 0) of the external input Y1 or the external input Y2, CKY = 1 And. As a result, the transistors MW1 and MW2 are turned on, so four voltages 0V, 0.1V, 0.2V, and 0.3V appear in Vz1 and Vz2 according to the combination of the values of Y1, Y2, and S. Then, by binarizing 0.05V or 0.25V as the threshold value Vth, the result of the logical operation of the external input Y1 and the stored data S or the logical operation of the external input Y2 and the stored data S can be obtained.

When performing this non-destructive operation, X (Vx) was replaced with Y1 (Vy1) and W (Vw) was replaced with Y2 (Vy2) in each of the tables 1 to 4 of the arithmetic circuit in Fig. 1. Similar results are obtained.

Subsequently, the operation procedure when performing the destruction operation between the two external inputs Y1 and Y2 and the stored data S is as follows. Prior to the calculation, the stored data S is written in the variable resistance element R. Specifically, after setting (Vy1, Vy2) = (1V, 0V) or (0V, 1V), set CKY = 1. As a result, the transistors MW1 and MW2 are turned on, so R = 100Ω or 100kΩ, and S = 1 or S = 0 is written as the stored data S.

Next, the external inputs Y1 and Y2 are calculated. Specifically, after setting the external input Y1 and the external input Y2 to either 1 or 0 (any of the four combinations), CKY = 1 is set. As a result, the transistors MW1 and MW2 are turned on, so the voltage applied across the variable resistance element R changes according to the combination of the values of Y1 and Y2. Then, the resistance value of the variable resistance element R changes in only one of the four combinations (depending on the content of the stored data S), and the value of the stored data S is rewritten.

Next, the calculation result is read out. Specifically, after setting (Vy1, Vy2) = (0.0V, 0.3V) or (0.3V, 0.0V), set CKY = 1. As a result, the transistors MW1 and MW2 are turned on, so four voltages 0V, 0.1V, 0.2V, and 0.3V appear in Vz1 and Vz2 according to the combination of the values of Y1, Y2, and S. Then, by binarizing 0.05V or 0.25V with the threshold value Vth, the logical operation between the external inputs Y1 and Y2, the logical operation between the external input Y1 and the stored data S, and the logic between the external input Y2 and the stored data S The result of the operation is obtained.

When performing this destruction operation, it is the same as replacing X (Vx) with Y1 (Vy1) and replacing W (Vw) with Y2 (Vy2) in each of the tables 5 to 16 of the arithmetic circuit in FIG. The result of is obtained.

As described above, since the same calculation result as that of the calculation circuit shown in FIG. 1 can be obtained, the calculation circuit shown in FIG. 8 also satisfies all of the following conditions as in the calculation circuit shown in FIG. , Functions that are considered ideal as logic-in-memory can be realized. First, it does not require a high voltage and operates at a voltage similar to the power supply voltage of a CMOS circuit. Secondly, both AND operation and OR operation of external input data and stored data are possible, and these operations can be switched. Third, both AND and OR operations between two external input data are possible, and the AND operation and OR operation can be switched according to the stored data. Fourth, it is possible to switch between the case of calculating without destroying the stored data and the case of leaving the calculation result as stored data according to the usage.

The area efficiency can be improved by reducing the number of MOS transistors to two.

However, in the configuration shown in Fig. 8, it is necessary to manage the timing of external input. In the configuration shown in Fig. 1, if the clock CKY is inverted and the clocks are CKX and CKW, it is possible to operate two MOS transistors alternately, and the external inputs X, W, Y1 and Y2. The input timing does not have to be exact. On the other hand, in the configuration shown in FIG. 8, the number of control transistors is reduced and the gate clock CKY is common, so that the timing of changing the voltages Vy1 and Vy2 of the external inputs Y1 and Y2 is clocked. It is necessary to control so that it matches well with the 0 period of CKY (the period when MOS transistors MW1 and MW2 are off). Therefore, which configuration should be adopted may be selected depending on whether the simplification of the circuit configuration is prioritized or the ease of control is prioritized.

Subsequently, FIG. 9 shows a schematic configuration diagram (circuit configuration diagram) of the arithmetic circuit having a configuration similarly simplified with respect to the arithmetic circuit shown in FIG. In the arithmetic circuit shown in FIG. 9, the MOS transistors MRD, MRS and the terminals of the inputs X, CKX, W, CKW to their gates and drains are deleted from the arithmetic circuit shown in FIG. 3, and the MOS transistor for control is used. Only two MOS transistors MW1 and MW2 are used. Since the other configurations are the same as those in FIG. 3, the same reference numerals are given and duplicate description is omitted. In FIG. 9, the data writing threshold value Vwr of the variable resistance element R and the data erasure threshold value Ver are set. 0.4V &lt;Ver &lt;0.5V, 0.4V &lt;Vwr &lt;2.0V (2) Is assumed to hold.

The calculation circuit shown in FIG. 9 has the same operation mode as the calculation circuit shown in FIG. 3, and the operation procedure is also substantially the same as the calculation circuit shown in FIG.

First, the operation procedure when performing a non-destructive operation between the external input Y1 or the external input Y2 and the stored data S is as follows. Prior to the calculation, the stored data S is written to the variable resistance elements 11 (R1) and 12 (R2). Specifically, after setting (Vy1, Vy2) = (2V, 0V) or (0V, 2V), set CKY = 1. As a result, the transistors MW1 and MW2 are turned on, so that (R1, R2) = (100Ω, 100kΩ) or (100kΩ, 100Ω), and S = 1 or S = 0 is written as the stored data S.

Next, the calculation with the external input is performed. Specifically, after setting one of the voltage Vy1 and the voltage Vy2 to 0.7V and the other to 0.3V according to the value (1 or 0) of the external input Y1 or the external input Y2, CKY = 1 And. As a result, the transistors MW1 and MW2 are turned on, so two voltages of 0.3V and 0.7V appear in Vz depending on the combination of the values of Y1, Y2, and S. Then, by binarizing 0.5 V as the threshold value Vth, the result of the logical operation of the external input Y1 and the stored data S or the logical operation of the external input Y2 and the stored data S can be obtained.

When this non-destructive operation is performed, the same result as replacing X (Vx) with Y1 (Vy1) and replacing W (Vw) with Y2 (Vy2) can be obtained in Table 17 of the operation circuit of FIG. .. Since the arithmetic circuit shown in FIG. 9 uses a 3-terminal memory element, there are two values of the output terminal voltage Vz, and depending on the combination of each value of Y1, Y2, and S, Z = ~ Y2 &amp; (Y1 &amp; S) | Y2 &amp; (Y1 | ~ S) Therefore, it is much easier to handle than the arithmetic circuit shown in Fig. 8.

Subsequently, the operation procedure when performing the destruction operation between the two external inputs Y1 and Y2 and the stored data S is as follows. Prior to the calculation, the stored data S is written to the variable resistance elements 11 (R1) and 12 (R2). Specifically, after setting (Vy1, Vy2) = (2V, 0V) or (0V, 2V), set CKY = 1. As a result, the transistors MW1 and MW2 are turned on, so that (R1, R2) = (100Ω, 100kΩ) or (100kΩ, 100Ω), and S = 1 or S = 0 is written as the stored data S.

Next, the external inputs Y1 and Y2 are calculated. Specifically, after setting the external input Y1 and the external input Y2 to either 1 or 0 (any of the four combinations), CKY = 1 is set. As a result, the transistors MW1 and MW2 are turned on, so the voltage applied across the variable resistance elements 11 (R1) and 12 (R2) changes according to the combination of the values of Y1 and Y2. Then, the resistance values of the variable resistance elements 11 and 12 change in only one of the four combinations (depending on the content of the stored data S), and the value of the stored data S is rewritten.

Next, the calculation result is read out. Specifically, after setting (Vy1, Vy2) = (0.3V, 0.7V) or (0.7V, 0.3V), set CKY = 1. As a result, the transistors MW1 and MW2 are turned on, so two voltages of 0.3V and 0.7V appear in Vz depending on the combination of the values of Y1, Y2, and S. Then, by binarizing 0.5V as the threshold value Vth, the result of the logical operation between the external input Y1 and Y2, the logical operation between the external input Y1 and the stored data S, and the logical operation between the external input Y2 and the stored data S. Is obtained.

When performing this destruction operation, it is the same as replacing X (Vx) with Y1 (Vy1) and replacing W (Vw) with Y2 (Vy2) in each of the tables 18 to 29 of the arithmetic circuit of FIG. The result of is obtained.

As described above, since the same calculation result as the calculation circuit shown in FIG. 3 can be obtained, the calculation circuit shown in FIG. 9 also satisfies all of the following conditions as in the calculation circuit shown in FIG. , Functions that are considered ideal as logic-in-memory can be realized. First, it does not require a high voltage and operates at a voltage similar to the power supply voltage of a CMOS circuit. Secondly, both AND operation and OR operation of external input data and stored data are possible, and these operations can be switched. Third, both AND and OR operations between two external input data are possible, and the AND operation and OR operation can be switched according to the stored data. Fourth, it is possible to switch between the case of calculating without destroying the stored data and the case of leaving the calculation result as stored data according to the usage.

Furthermore, since a 3-terminal memory element in which two variable resistance elements 11 and 12 are complementaryly connected is used, the combined resistance of the two variable resistance elements 11 and 12 has a high resistance regardless of the content of the stored data S. Since it becomes a constant value, power consumption can be reduced. Moreover, since the on-resistance (for example, about 100Ω) of the MOS transistors MRD and MRS is sufficiently smaller than the magnitude of the combined resistance of the two variable resistance elements 11 and 12, the read voltage is divided by the MOS transistors MRD and MRS. There is a large difference in output voltage level between 1 and 0 without being pressed. In addition, there are two values of the read voltage Vz, and only one type of threshold voltage (for example, 0.5 V) is required to distinguish between 1 and 0 of the calculation result.

The area efficiency can be improved by reducing the number of MOS transistors to two. On the other hand, it is necessary to manage the timing of external input. Therefore, depending on whether the simplification of the circuit configuration is prioritized or the ease of control is prioritized, the configuration shown in FIG. 3 or the configuration shown in FIG. 9 may be selected.

In the arithmetic circuit of each of the above-described embodiments, the operations shown in Tables 1 to 4 and 17 are non-destructive arithmetic in which the stored data S does not change by performing the arithmetic. This non-destructive operation has an advantage that the reset operation of writing back the stored data is unnecessary, but on the other hand, it has a volatility that the operation result is lost when the power supply voltage is lost.

On the other hand, the operations shown in Tables 5 to 16 and 18 to 29 are destructive operations in which the stored data S is changed by performing the operation. This destruction operation has the trouble of requiring a reset operation to write back the stored data every time, but on the other hand, it has the advantage of having non-volatility in which the operation result is saved even when the power supply voltage is lost. is there.

In the calculation circuit of each of the above-described embodiments, the operation for performing the calculation of the input data and the stored data can be performed by either type of non-destructive calculation or destructive calculation. It is possible to select the operation type that suits the purpose by comparing with the gender.

In each of the above-described embodiments, the calculation result can be read out as the voltages Vz1, Vz2, Vz of the terminals Z1, Z2, Z, and how to use the signal is particularly limited. Not done.

First, as a basic usage of the output signal, connect the gate of the MOS transistor to the output terminals Z1, Z2, Z of the calculation result, and connect this MOS transistor to the terminal voltage Vz1, Vz2, Vz of the output terminals Z1, Z2, Z. It is conceivable to form a functional passgate in a dynamic circuit by using it as a passgate transistor that is turned on and off by. Then, two or more functional passgates are connected in series or in parallel to form a precharge transistor and an evaluate transistor in the same manner as the functional passgate using other non-patent devices described in Non-Patent Document 2 and Non-Patent Document 4. By adding, it is possible to perform an arbitrary AND / OR operation between the operation results of the function pass gate and output the result as the voltage of the match line. The operation of this dynamic circuit has already been described and will be omitted.

Another way to use the output signal is to connect the input terminals of an amplifier such as a sense amplifier to the output terminals Z1, Z2, Z of the calculation result, and use this output to drive the logic circuit of the next stage. You can also. In this case, it is possible to use not only a dynamic circuit but also a normal static circuit.

In each of the above-described embodiments, the case where the variable resistance elements R, 11 and 12 constituting the arithmetic circuit have a configuration in which a conductor film and an insulator film are provided between the two electrodes has been described. Other configurations may be used. For example, a semiconductor film may be used instead of the conductor film, a semiconductor film or a conductor film may be used instead of the insulator film, the stacking order may be reversed, or a single layer may be used. In any configuration, the variable resistance element may have a characteristic of changing between a high resistance state and a low resistance state by applying a voltage, and may have a threshold value of the voltage at which the resistance state changes.

The present invention is not limited to the above-described embodiments, and various other configurations may be adopted without departing from the gist of the present invention.

<figref num="1">It is a schematic block diagram (circuit block diagram) of the arithmetic circuit of one Embodiment of this invention.</figref><figref num="2">A It is sectional drawing which shows the film structure of the variable resistance element of FIG. B It is a figure which shows the circuit symbol of the variable resistance element of FIG. 2A.</figref><figref num="3">It is a schematic block diagram (circuit block diagram) of the arithmetic circuit of another embodiment of this invention.</figref><figref num="4">A It is a schematic block diagram of the memory element used in the arithmetic circuit of FIG. B Figure 4A is a circuit configuration diagram of the memory element.</figref><figref num="5">A It is a schematic block diagram of the memory element of other configurations. B It is a circuit block diagram of the memory element of FIG. 5A.</figref><figref num="6">A to D It is a figure which shows the state which a memory element of FIG. 4A can take.</figref><figref num="7">It is a state transition diagram explaining the operation when a write voltage is applied to the memory element of FIG. 4A.</figref><figref num="8">It is the schematic block diagram (circuit block diagram) of the arithmetic circuit which modified the arithmetic circuit of FIG.</figref><figref num="9">It is the schematic block diagram (circuit block diagram) of the arithmetic circuit which modified the arithmetic circuit of FIG.</figref>

Code description

1,2 electrode, 3 conductor film, 4 insulator film, 10,20 memory element, 11 1st variable resistance element, 12 2nd variable resistance element, R variable resistance element, MRD, MRS, MW1, MW2, Tr1 , Tr2 MOS transistor, CKX, CKY, CKW clock