Microprocessor boot-up controller connected to a processor and NAND flash memory for controlling the boot-up of a computer device

<u style="single"> The present invention relates to a microprocessor boot-up control device and an information processing system.</u>

Systems that substitute boot read-only memory (boot ROM) with non-volatile memory (eg, NAND flash memory) typically transfer NAND read data to static random access memory (SRAM) after transfer. A mechanism is adopted in which the host central processing unit (host CPU) accesses SRAM as a boot ROM.

On the other hand, it is necessary to wait for SRAM access of the host CPU and prohibit it until the loading from the NAND non-volatile memory to the SRAM is completed and the SRAM is in the read standby state (read ready). In the prior art, a mechanism is provided in which the boot control unit and the CPU power-on reset signal are independently generated and supplied, and the CPU power-on reset signal is released at the timing when the SRAM access of the boot control unit becomes ready. ..

A boot system using NAND flash memory and a method thereof have already been disclosed (for example, Patent Document 1). Further, in a NAND type flash memory used for a file memory or the like, a non-volatile semiconductor storage device for writing system boot data to an arbitrary address on the memory has already been disclosed (for example, Patent Document 2). Further, the boot code and the NAND flash memory have already been disclosed (for example, Patent Document 3 and Patent Document 4). Further, the configuration of the multi-value NAND cell has already been disclosed (for example, Patent Document 5).

When a multi-value NAND non-volatile memory is used for the boot ROM, the multi-value NAND non-volatile memory is garbled due to minute threshold fluctuations due to aged deterioration of the data holding circuit compared to the binary NAND non-volatile memory. It is easy to use and has low reliability, and it is difficult to realize a highly reliable boot system that is almost error-free.

On the other hand, the problem with the mechanism that independently generates and supplies the power-on reset signal of the boot control unit and the CPU and releases the power-on reset signal of the CPU when the SRAM access of the boot control unit becomes ready is the power. The point is that the on-reset circuit becomes complicated. The SRAM ready timing varies depending on the program capacity to be loaded into the SRAM, retry depending on the presence or absence of an error in the NAND read data, error correction processing, and the like. Therefore, it is necessary to always release the CPU reset at the worst case timing. Therefore, there is a problem that the CPU reset cannot be released in the shortest time according to the SRAM ready timing, and as a result, the average time for system startup cannot be shortened.<patcit num="1"><text>Japanese Unexamined Patent Publication No. 2003-271391</text></patcit><patcit num="2"><text>Japanese Unexamined Patent Publication No. 2003-162453</text></patcit><patcit num="3"><text>Japanese Unexamined Patent Publication No. 2003-114826</text></patcit><patcit num="4"><text>U.S. Pat. No. 5,519,843</text></patcit><patcit num="5"><text>Japanese Patent Application Laid-Open No. 2002-313089</text></patcit>

<p><u style="single"> An object of the present invention is a microprocessor boot-up control device that can allow access to the volatile memory of the CPU according to the ready timing of the volatile memory and can shorten the average system startup time, and a multi-function according to the user's application. It is to provide the information processing system of.</u></p>

<p><u style="single">According to one aspect of the present invention, the microprocessor boot-up control device is connected to a CPU and a non-volatile memory, respectively, and reads a boot-up code stored in the non-volatile memory to control the boot-up of the CPU. Until the volatile memory connected to the non-volatile memory and the boot-up code is loaded from the non-volatile memory and the loading of the boot-up code from the non-volatile memory to the volatile memory are completed. After the boot-up control sequencer that continues to send non-arithmetic instructions to the CPU and the loading of the boot-up code from the non-volatile memory to the volatile memory are completed, the CPU is subjected to the execution routine of the boot-up code. Provided is a microprocessor boot-up control device including a host interface unit that sends a branch instruction to be transferred to the CPU to the CPU.</u></p><p><u style="single">According to another aspect of the present invention, the CPU is connected to the CPU, the non-volatile memory for storing the boot-up code, the CPU, and the non-volatile memory, and the boot-up code is read from the non-volatile memory to read the CPU. A volatile memory including a microprocessor boot-up control device for boot-up control, the microprocessor boot-up control device is connected to the non-volatile memory, and the boot-up code is loaded from the non-volatile memory, and the above. A boot-up control sequencer that continues to send non-arithmetic instructions to the CPU until the loading of the boot-up code from the non-volatile memory to the volatile memory is completed, and the volatile memory from the non-volatile memory. An information processing system including a host interface unit that sends a branch instruction for shifting the CPU to the execution routine of the bootup code to the CPU after the loading of the bootup code into the CPU is completed is provided.</u></p>

<p><u style="single"> According to the present invention, it is possible to provide a microprocessor boot-up control device that can allow access to the volatile memory of the CPU in accordance with the ready timing of the volatile memory and can shorten the average system startup time. It is possible to provide a multifunctional information processing system according to the user's application.</u></p>

Next, the first to fifth embodiments of the present invention will be described with reference to the drawings. In the description of the drawings below, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic and the size ratio of each block is different from the actual one. In addition, it goes without saying that there are parts in which the dimensional relationships and ratios of the blocks are different between the drawings.

Further, the first to fifth embodiments shown below exemplify an apparatus or system for embodying the technical idea of the present invention, and the technical idea of the present invention is a component component. The configuration, structure, arrangement, etc. are not specified as follows.

(First Embodiment) As shown in FIG. 1, the microprocessor boot-up control device according to the first embodiment of the present invention is connected to an external CPU and a non-volatile memory 38, reads data from the non-volatile memory 38, and boots the CPU. It is a microprocessor boot-up controller 12 that controls up. The microprocessor boot-up controller 12 includes a volatile memory (SRAM) 24 connected to the non-volatile memory 38, a selector 36 that transfers the boot-up code from the non-volatile memory 38 to the SRAM 24, and a boot-up code. It is equipped with a boot-up control sequencer 26 that sends CPU read data to the CPU and puts the CPU in a standby state until the transfer is completed.

Here, the CPU read data is a CPU instruction code. The CPU instruction code is one of a non-operation instruction (NOP), an arithmetic logical operation instruction, a data transfer instruction, a branch instruction, or an input / output instruction to a peripheral device. CPU read data can be determined regardless of the CPU output address.

Further, as shown in FIG. 1, the microprocessor boot-up control device 12 according to the first embodiment of the present invention completes the transfer of the boot-up code from the non-volatile memory 38 to the SRAM 24, regardless of the CPU output address. , The host interface unit 10 that causes the CPU to read the branch instruction may be provided. The external memory address signal EMA is supplied from the host interface unit 10 to the boot-up control sequencer 26, and the external memory read data signal EMR is supplied from the boot-up control sequencer 26 to the host interface unit 10.

After the boot-up code is transferred from the non-volatile memory 38 to the SRAM 24, the branch instruction is read by the CPU regardless of the CPU output address, and then the data corresponding to the CPU output address is read by the CPU. The AND gate 32 and the buffer circuit 34 are means for generating the drive clock signal CLK of the means for causing the CPU to read the data corresponding to the CPU output address from the host CPU bus signal HBS.

Since the host bus signal HBS (WE / OE) is supplied to the AND gate 32, there is also an advantage that it is not necessary to provide a clock generation circuit in the boot-up controller 12.

Here, the host bus signal HBS is transferred between the host CPU bus 42 to which the external CPU is connected and the host interface unit 10, and the write enable branched from the host CPU bus signal HBS to the AND gate 32. The signal WE and the output enable signal OE are input. The clock signal CLK, which is the output signal of the buffer circuit 34, is input to the host interface unit 10, the boot-up control sequencer 26, and the error detection / correction processing unit 40, respectively.

Further, as shown in FIG. 1, the microprocessor boot-up control device 12 according to the first embodiment detects the presence or absence of an error in the load data to the SRAM 24, and if there is an error, it is a means for correcting the error. Equipped with a detection / correction processing unit 40, the same bootup program set is stored in multiple blocks of the non-volatile memory 38, and if a data error occurs in the loaded block, error correction processing is performed and error correction is not possible. , Select other sets sequentially, reload the selected set into SRAM24, and perform error detection and error correction.

Furthermore, the CPU instruction code is an arithmetic and logical operation instruction for a device that is not necessary until the bootup code is executed; an arithmetic and logical operation instruction for a device that has no effect until the bootup code is executed; and the bootup code is executed and terminated. Arithmetic and logical operation instructions for memory that are not needed until the bootup code is executed; Arithmetic and logical operation instructions for memory that are not affected until the bootup code is executed, and arithmetic and logical operation instructions for registers that are not necessary until the bootup code is executed; Bootup Arithmetic and logical operation instructions for registers that are not affected by executing the code; data transfer instructions for devices that are not required before executing the bootup code; data transfer instructions for devices that are not affected by executing the bootup code; Data transfer instructions to memory that are not needed until the bootup code is executed; data transfer instructions to memory that are not affected by the time the bootup code is executed; data transfer to registers that are not needed until the bootup code is executed Instructions, data transfer instructions to registers that have no effect until the bootup code is executed; I / O instructions for peripheral devices that are not required until the bootup code is executed and peripheral devices that are not affected until the bootup code is executed It may be any of the input / output instructions for.

Here, the register has a function of executing a meaningless operation in a loop for the registers defined in the instruction set of the CPU and realizing an effective NOP loop execution, for example. , It performs operations such as continuously executing an increment instruction in an accumulator register in which invalid data is stored.

Further, the memory here means a main memory composed of a general-purpose DRAM or a general-purpose SRAM.

Here, peripheral devices, peripheral devices, and memories are all classified as peripheral devices in a broad sense. Here, the peripheral device is supplied in the form of a board. Peripheral devices can be assumed to be large-scale set devices. For example, the device includes a general-purpose memory (DRAM, SRAM), a video card, a USB interface, a PC card interface, and the like. The devices include peripheral terminal devices such as monitors, printers, and keyboards.

Further, in the microprocessor boot-up control device 12 according to the first embodiment, the address indicated by the branch instruction may indicate the start address of the boot-up code, and the address indicated by the branch instruction is on the non-volatile memory 38. A plurality of boot-up program sets may be provided from a part of the non-volatile memory 38, the boot-up program set is selected according to the state of the input pin of the device, and the selected boot-up program is stored in the SRAM 24. You may load it to.

Alternatively, in the microprocessor boot-up control device 12 according to the first embodiment, after the boot-up code is transferred from the non-volatile memory 38 to the SRAM 24, the CPU and the microprocessor boot-up control device 12 other than the CPU and the microprocessor boot-up control device 12 are reset. It may operate and execute the bootup code.

Address signals, data bus signals, write enable signals (WE), output enable signals (OE), and other signals are transferred to the host CPU bus 42 that constitutes the CPU bus interface. The host CPU bus 42 that connects the CPU to the outside is connected to the host interface unit 10 and the AND gate 32 via the data bus that transfers the host CPU bus signal (HBS). A write enable signal (WE) and an output enable signal (OE) are supplied to the AND gate 32.

For example, a boot-up control device 12 having SRAM 24 constituting the main memory and a plurality of other peripheral devices are connected to the host CPU bus 42. The boot-up control device 12 for the non-volatile memory 38 is composed of a host interface unit 10, a boot-up control sequencer 26 which is a control device for the non-volatile memory, SRAM 24, and an error detection / correction processing unit 40. The part excluding the non-volatile memory is formed on the same chip and realized by a one-chip LSI. The SRAM 24 stores the program loaded from the multi-value NAND non-volatile memory 38. After the system is powered on and the NAND data load to the SRAM 24 is complete, the CPU accesses the SRAM 24 and begins the bootup process.

[Bootup process] (a) When the system is powered on, a power-on reset is applied to the host CPU and boot-up controller 12, and the operation starts after the reset is released.

(b) The CPU accesses the SRAM 24 in the boot-up controller 12 as a ROM for the purpose of executing the boot program.

(c) Next, the boot-up controller 12 starts the NAND data loading to the SRAM 24, and in the first phase until the NAND data loading to the SRAM 24 is completed, the CPU is instructed to perform no operation regardless of the CPU output address. Continues to output (NOP) code and puts the CPU in an effective standby state.

(d) Next, the boot-up controller 12 outputs a jump instruction in the second phase when the NAND data loading to the SRAM 24 is completed, regardless of the CPU output address.

(e) Next, the boot-up control device 12 outputs an instruction according to the CPU output address in the third phase after the jump instruction is output. Since the program counter of the CPU is updated in the free run state in the first phase, the CPU output address is an internal value, but the address is confirmed by the jump instruction in the second phase, and the normal program execution routine Can be migrated to.

[NAND read data error handling] Next, error handling of NAND read data will be described.

The multi-value NAND boot code storage page address of the multi-value NAND non-volatile memory 38 applied to the microprocessor boot-up control device 12 according to the first embodiment of the present invention is a NAND page address as shown in FIG. The map has 6 pages (0) to (5), and each page has a capacity of 528 bytes (512 bytes of data storage + 16 bytes of redundant part).

(a) In the boot-up controller 12, page 0 is loaded into SRAM 24 while performing an error check by the error detection / correction processing unit 40. If there is no error, the loading process is completed, and if an error occurs, an error occurs. It is finished. A set of boot codes is stored on page (0), and a copy of this set is also stored redundantly on pages (1) to (5). The boot-up controller 12 shown in FIG. 1 first loads the set 1 on page (0) of the multi-value NAND non-volatile memory 38 into the SRAM 24, but the data from the multi-value NAND non-volatile memory 38 to the SRAM 24. In parallel with loading, the error detection / correction processing unit 40 performs error check processing. If there are no errors, the loading process is completed and the process proceeds to Phases 2 and 3 described above.

(b) When there is an error, the error detection / correction processing unit 40 stores the byte address where the error occurred and the error correction information, and based on this information, the data of the error occurrence address loaded in SRAM 24. Make corrections, complete the load process, and move to Phases 2 and 3 above.

(c) In the case of an uncorrectable error, spare redundant sets 2 to 5 are loaded sequentially, and error detection / correction is performed in the same manner. If it cannot be corrected even after repeating this until the final set 5 (if it is an error that cannot be corrected for all sets), it terminates abnormally as a boot error. The number of redundant sets may be arbitrarily set according to the target boot error avoidance rate, and the set number may be notified to the boot-up control device 12 in advance. Alternatively, a code for identifying the final set may be stored in the redundant set so that the boot-up controller 12 automatically stops reloading with this code. Further, a redundant set can be provided in a plurality of blocks of the erase block (for example, 16 kilobytes) of the non-volatile memory 38, and the boot error avoidance rate can be further increased.

In the microprocessor boot-up control device according to the first embodiment of the present invention, in a system in which the multi-valued NAND non-volatile memory 38 is substituted for the boot ROM, after the NAND read data is transferred to the SRAM 24, the host CPU uses the SRAM 24. Is accessed as a boot ROM and booted. Until the loading from the multi-value NAND non-volatile memory 38 to the SRAM 24 is completed and the SRAM 24 becomes read ready, no calculation is performed as SRAM read data on the host CPU (IDLE). ) It is possible to output an instruction (NOP, etc.) and execute an operation that effectively puts the CPU in the standby (WAIT) state.

As described above, according to the microprocessor boot-up control device according to the first embodiment of the present invention, it is not necessary to independently generate and supply the power-on reset signal of the boot-up control device 12 and the CPU. It is possible to simplify the power-on reset circuit, allow CPU SRAM access in the shortest time according to the SRAM ready timing, and realize a microprocessor boot-up control device that can shorten the average system startup time.

(Second embodiment) As shown in FIG. 2, the configuration of the non-volatile memory control device 26 according to the second embodiment of the present invention relates to the external non-volatile memory 38, the volatile memory SRAM 24, and the host interface unit 10. An address generator 18 that is connected and specifies the address of the non-volatile memory 38, and an address generator memory address signal AGMA that is connected to the address generator 18 and receives an address generator memory address signal AGMA, and supplies an internal memory address signal IMA to the SRAM 24. The first selector 20, the second selector 14, the second selector 14, the second selector 14, which receives the internal memory read data signal IMR from the SRAM 24 and supplies the external memory read data signal EMR to the host interface unit 10. Generates a state machine 16 that supplies the internal control signal SMS to the selector 20 of 1 and supplies the internal control signal SAG to the address generator 18, and a non-arithmetic instruction signal NOP to the second selector 14. It is provided with a non-arithmetic instruction code generation circuit 22.

Further, a non-volatile memory 38 that allocates cell holding data to consecutive page addresses is further provided, and the same data is written to even-numbered pages and odd-numbered pages in which the addresses of the non-volatile memory 38 are continuous, and only one page is accessed. The configuration of the memory control device 26 may be used.

Further, a multi-value NAND non-volatile memory 38 that allocates cell holding data to consecutive page addresses is further provided, and the same data is written to even-numbered pages and odd-numbered pages in which the addresses of the multi-value NAND non-volatile memory 38 are continuous. It may be configured to access only the page of.

The multi-value NAND non-volatile memory 38 can also store data that requires data reliability, such as a boot-up instruction code and parameters necessary for booting the system.

The multi-value NAND boot code storage page address of the multi-value NAND type non-volatile memory 38 applied to the non-volatile memory control device (boot-up control sequencer) 26 according to the second embodiment of the present invention is shown in FIG. As described above, in the NAND page address map, there are 6 pages (0) to (5), and each page has a capacity of 512 bytes, for example. A set of boot codes is stored on page 1, and a copy of this set is also stored on page 2. The boot-up controller 12 loads page 0 into SRAM 24 while performing an error check by the error detection / correction processing unit 40. If there is no error, the loading process is completed, and if an error occurs, the boot-up control device 12 terminates abnormally.

As shown in FIG. 4, the multi-value NAND non-volatile memory 38 applied to the second embodiment of the present invention includes a plurality of memory cell blocks 28, and each memory cell block 28 is, for example, 0. It has 30 page units consisting of ~ 63 pages. Further, the multi-value NAND type non-volatile memory 38 includes a page buffer 31 for inputting / outputting data. The storage capacity of the page buffer is 528 bytes (512 bytes + 16 bytes). When writing data, the page buffer executes data input / output processing in units of one page corresponding to its own storage capacity. Here, the "page" is a unit that can be written or read by the data input / output process of the page buffer.

In the multi-value NAND non-volatile memory 38, each memory cell has a threshold state of 2 to the Nth power (N is an integer of 2 or more). That is, each memory cell can store N-bit information. In the following, for convenience of explanation, a case where each memory cell has four threshold states will be described. As the address generation circuit for each page 30, for example, the address generator 18 shown in FIG. 2 can be used.

In the page unit of the multi-value NAND non-volatile memory 38 applied to the second embodiment of the present invention, the odd-numbered pages and the even-numbered pages are represented by continuous page units as shown in FIG. For example, 1 to 4096 bits, that is, 512 bytes of even pages (0) and odd pages (1) are represented as consecutive page units.

In the multi-valued NAND non-volatile memory applied to the second embodiment of the present invention, the retained data threshold distribution of the 4-valued NAND cell is the lower bit of 2-bit data, as shown in FIG. Is assigned to the 1-bit data of the logically even page viewed from the outside of the NAND device, and the upper bit is assigned to the 1-bit data of the odd page.

Since the same data is written on even-numbered and odd-numbered pages, the cell threshold distribution is only "11" and "00" out of the four ways of "11", "10", "00", and "01".

In the read operation, first, the retained data is identified with reference to the threshold value read 1,0. If this determination is lower than the threshold value, the determination process ends with the retained data "11". If this judgment is higher than the threshold value, the threshold value read 0,1 is used for judgment, and it is confirmed whether or not the judgment is low. Logically, the second judgment result is low. Physically, it is usually impossible for the retained data to change over time by mistake. The reason is that the threshold voltage does not transition to the higher value unless an electric charge is injected into the floating gate of the memory cell from the outside of the memory cell. As a result, read data errors due to aged deterioration such as charge loss of the multi-value NAND non-volatile memory 38 can be significantly reduced.

In the multi-value NAND boot code storage page address of the multi-value NAND non-volatile memory shown in Fig. 3, set 2 and set 3 are preliminary sets when there is an error in set 1, and as a result, the page (1) ) ~ Page (5) contains the same data as page (0).

According to the non-volatile memory control device (boot-up control sequencer) 26 according to the second embodiment of the present invention, a multi-valued NAND non-volatile memory that allocates cell holding data to consecutive page addresses is used. By writing the same data to even and odd pages with consecutive memory addresses and accessing only one page, a minute threshold due to aging of data retention when using multi-valued NAND non-volatile memory for boot ROM It is possible to solve the problems of data garbled due to value fluctuations and deterioration of reliability, and to realize a highly reliable non-volatile memory control device (bootup control sequencer) that is almost error-free.

(Third embodiment) As shown in FIG. 7, the configuration of the information processing system 60 according to the third embodiment of the present invention includes a plurality of word lines and N natural numbers connected to each of the plurality of word lines (N is a natural number greater than 2). A multi-value NAND non-volatile memory 38 having a plurality of memory cells having a threshold state of) and storing program code and user data, and a multi-value NAND non-volatile memory 38 connected to the multi-value NAND type non-volatile memory 38. A boot-up controller 12 having SRAM 24, which is a volatile memory to which the program code is transferred from the NAND-type non-volatile memory 38, and a CPU 50 connected to the boot-up controller 12 and operating based on the program code transferred to the SRAM 24. And. A plurality of memory cells connected to each word line form a plurality of pages, and the program code is stored only in a part of the plurality of pages.

Further, the information processing system 60 according to the third embodiment of the present invention is connected to the multi-value NAND non-volatile memory 38, and has a NAND controller 58 that controls the multi-value NAND non-volatile memory 38, a CPU 50, and a boot. A CPU bus 54 to which the up controller 12 and the NAND controller 58 are commonly connected and a DRAM 52 connected to the CPU bus 54 may be further provided.

Further, the information processing system 60 according to the third embodiment of the present invention includes an address generation circuit composed of an address generator 18 arranged in the boot-up control device 12, and is generated by the address generation circuit. The page is specified based on the address signal.

Further, the multi-value NAND non-volatile memory 38 is divided into two areas, one of which is used with an N value and the other of which is used with an N / 2 value, and the program code may be used with an N / 2 value.

In the case of four values, the information processing system 60 according to the third embodiment of the present invention has a four-value memory for discriminating four threshold states connected to each of a plurality of word lines and the plurality of word lines. A multi-valued NAND non-volatile memory 38 having a plurality of memory cells and storing a program code and user data, and a volatile program code transferred from the multi-valued NAND non-volatile memory 38 at system startup. It includes a boot-up control device 12 having SRAM 24, which is a memory, and a CPU 50, which operates based on the program code transferred to SRAM 24. Of a plurality of word lines, a plurality of memory cells commonly connected to one word line form an odd-numbered page and an even-numbered page that can be addressed, and the program code is either an odd-numbered page or an even-numbered page. It is stored in only one.

The multi-value NAND non-volatile memory 38 is divided into two areas, one is used in four values and the other is used in two values, and the program code is used in two values. User data is stored on both odd and even pages. Further, the multi-value NAND type non-volatile memory 38 and the volatile memory 24 may be contained in the same package.

Furthermore, the information processing system 60 according to the third embodiment of the present invention in the case of four values includes an address generation circuit composed of an address generator 18 arranged in the bootup control device 12. Based on the address signal generated by the address generation circuit, only one of odd-numbered pages and even-numbered pages is addressed at startup.

Furthermore, in the information processing system 60 according to the third embodiment of the present invention, as a simple configuration in the case of four values, a multi-value NAND type non-volatile memory 38 in which the program code is stored and a multi-value A boot-up controller 12 including a multi-valued NAND non-volatile memory controller 26 that accesses only even page addresses or odd page addresses with respect to the continuous page address space of the NAND non-volatile memory 38, and a CPU. It may include a CPU 50 which is connected to the control device 26 of the multi-valued NAND non-volatile memory via the bus 54 and the CPU bus 54 and is boot-up controlled by the program code. Such an information processing system can also be applied to a mobile phone terminal.

Furthermore, the configuration of the multi-value NAND non-volatile memory 38 applied to the information processing system according to the third embodiment of the present invention is composed of a plurality of memory cell blocks 28, for example, as shown in FIG. , A memory cell block 72 for boot code and a multi-valued memory storage unit 70 are provided. The physical memory space of the multi-value NAND non-volatile memory 38 may be divided into first and second areas, and the second area may be accessed by the control device 26 of the non-volatile memory. A program used at boot time is stored in the second area, and user data such as image data and audio data is stored in the first area.

According to the information processing system according to the third embodiment of the present invention, the quadrature NAND non-volatile memory 38 is divided into two areas, one of which is quadrature and the other of which is ternary. It is possible to realize multiple functions according to the user's application. To further generalize, by dividing the N-value NAND non-volatile memory into two areas, one with the N value and the other with the N / 2 value, highly important data such as programs can be N / By using binary values and using user data such as image data and audio data with N values to secure the amount of stored information, it is possible to realize a multifunctional information processing system according to the user's application.

(Fourth Embodiment) As shown in FIG. 8, the information processing system according to the fourth embodiment of the present invention is connected to each of a plurality of word lines and a plurality of word lines, and has N (N is a natural number greater than 2) threshold. A multi-value NAND non-volatile memory 38 having a plurality of memory cells having a value state and storing a program code and user data, and a multi-value NAND non-volatile memory 38 connected to the multi-value NAND non-volatile memory 38. It includes a controller 59 to which a program code is transferred from the memory 38, a CPU bus 54, and a CPU 50 connected to the controller 59 via the CPU bus 54 and operating based on the program code.

A plurality of memory cells connected to each word line form a plurality of pages, and the program code is stored in only a part of the plurality of pages.

In the information processing system according to the fourth embodiment of the present invention, the controller 59 includes a boot-up control device 12 including SRAM 24 which is a volatile memory for storing a program code, and a NAND interface controller 62.

The information processing system according to the fourth embodiment of the present invention further has a configuration including a storage memory 56 and a boot memory 64 connected to the multi-value NAND non-volatile memory 38 and also connected to the controller 59. .. It may further have a DRAM 52 connected to the CPU bus 54.

The multi-value NAND non-volatile memory 38, the storage memory 56, and the boot memory 64 may be configured by using separate semiconductor chips, but most simply, the same chip as the multi-value NAND non-volatile memory 38. Can be placed on top. In this case, the inside of the multi-value NAND non-volatile memory 38 can be divided and configured as the multi-value NAND non-volatile memory 38, the storage memory 56, and the boot memory 64, respectively.

In the information processing system according to the fourth embodiment of the present invention, the controller 59 shows, for example, a portion other than the multi-value NAND non-volatile memory 38 in FIG.

The configuration of the multi-value NAND non-volatile memory 38 applied to the information processing system according to the fourth embodiment of the present invention is composed of a plurality of memory cell blocks 28, for example, as shown in FIG. 9, and is a boot code. A memory cell block 72 for use and a multi-value memory storage unit 70 are provided. The physical memory space of the multi-valued NAND non-volatile memory 38 is, for example, a total of 1 GB and is divided into first and second regions. The second area corresponds to the boot code memory cell block 72, and the first area corresponds to the multi-valued memory storage unit 70. Of course, it is not essential to divide the area into the first area and the second area, and the physical memory space of the multi-value NAND non-volatile memory 38 may be used only as the boot ROM.

The NAND interface controller 62 performs block management, address translation, and the like of the multi-value NAND non-volatile memory 38. The boot-up controller 12, the NAND interface controller 62, and the multi-value NAND non-volatile memory 38 can be arranged on the same chip.

Examples of applications of the information processing system 60 include mobile phone terminals and PDAs. That is, by providing the information processing system 60 with an RF circuit, a display, a key input means, and the like, a mobile phone terminal and a PDA can be realized. The design rule of the NAND non-volatile memory 38 is, for example, less than 0.1 μm.

According to the information processing system according to the fourth embodiment of the present invention, the multi-value NAND type non-volatile memory 38 is divided into the first and second areas, and the first multi-value memory storage unit 70 is formed. This area stores general user data such as image data and audio data, and the second area consisting of the boot code memory cell block 72 stores the program used at boot time of the information processing system 60. By managing the second area with the NAND interface controller 62, it is possible to realize a multifunctional information processing system according to the user's application.

(Fifth Embodiment) As shown in FIG. 10, the information processing system 60 according to the fifth embodiment of the present invention is connected to each of a plurality of word lines and a plurality of word lines, and N (N is a natural number greater than 2). It is connected to a multi-value NAND non-volatile memory 38, a bus 86, and a multi-value NAND non-volatile memory 38, which are provided with a plurality of memory cells having a threshold state and store program code and user data, and are multi-valued. The value includes a controller 59 in which the program code is transferred from the NAND non-volatile memory 38 via the bus 86, and a system memory 88 connected to the bus 86.

The inside of the controller 59 is composed of a CPU 50 connected via the CPU bus 54, a memory controller 82, a boot-up loader 80, and an interface circuit 84 for the memory controller 82 and the boot-up loader 80. Here, the boot uploader 80 has a function of controlling the boot code of the external ROM.

For the multi-value NAND non-volatile memory 38 from the interface circuit 84, various memory controls such as chip enable signal CE bar, clock enable signal CLE, arithmetic operation signal ALE, write enable signal WE bar, read enable signal RE bar, etc. The signal is supplied.

As shown in FIG. 10, the inside of the multi-value NAND non-volatile memory 38 is divided into an area 1 and an area 2. For example, the area 1 stores the binary code in even-numbered pages / odd-numbered pages. Area 2 stores 4-valued user data in even / odd pages.

As shown in FIG. 11, as an operation method of the multi-value NAND non-volatile memory 38 applied to the information processing system 60 according to the fifth embodiment of the present invention, data 1 is always assigned to the lower bits to which even pages are assigned. If you write and store the data in the high-order bits that allocate odd pages, you can use a 4-value memory cell as a 2-value. With this configuration, it is possible to prevent data errors due to threshold fluctuations.

As shown in FIG. 12, the detailed configuration of the multi-value NAND non-volatile memory applied to the information processing system according to the fifth embodiment of the present invention is the area 1 and 4-value user data for storing the binary code. It is composed of the area 2 that stores the information. In area 1, odd-numbered pages are not used, and code information as binary data is stored only in even-numbered pages. On the other hand, in the area 2, the user data is stored in both even-numbered pages and odd-numbered pages as quaternary data.

According to the information processing system according to the fifth embodiment of the present invention, the multi-valued NAND non-volatile memory 38 is divided into the first and second regions as in the fourth embodiment. It is possible to realize a multifunctional information processing system according to the user's application, and further, by using the even-numbered page / odd-numbered page in the storage threshold distribution of binary and quaternary data as shown in FIG. It is possible to prevent data errors due to threshold fluctuations.

(Other embodiments) As mentioned above, the present invention has been described in accordance with the first to fourth embodiments, but the statements and drawings that form part of this disclosure should not be understood to limit the invention. Various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art from this disclosure.

As described above, it goes without saying that the present invention includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention relating to the reasonable claims from the above description.

<figref num="1">The schematic block block diagram of the microprocessor boot-up control device which concerns on 1st Embodiment of this invention.</figref><figref num="2">FIG. 6 is a schematic block configuration diagram of a boot-up control sequencer constituting a control device for a multi-valued non-volatile memory according to a second embodiment of the present invention.</figref><figref num="3">The schematic diagram explaining the multi-value NAND boot code storage page address of the multi-value NAND type non-volatile memory applied to the 1st and 2nd Embodiment of this invention.</figref><figref num="4">The schematic diagram explaining the page unit and the structure of the memory cell block of the multi-value NAND type non-volatile memory applied to the 2nd Embodiment of this invention.</figref><figref num="5">The schematic diagram explaining the odd-numbered page and the even-numbered page in the page unit of the multi-valued NAND type non-volatile memory applied to the 2nd Embodiment of this invention.</figref><figref num="6">The schematic diagram explaining the example of the threshold value distribution of the 4-value NAND cell in the multi-value NAND type non-volatile memory applied to the 2nd Embodiment of this invention.</figref><figref num="7">The schematic block block diagram of the information processing system which concerns on 3rd Embodiment of this invention.</figref><figref num="8">The schematic block block diagram of the information processing system which concerns on 4th Embodiment of this invention.</figref><figref num="9">Schematic diagram illustrating a configuration including both a boot code memory cell block of a multi-valued NAND non-volatile memory and a multi-valued memory storage unit applied to the information processing system according to the third and fourth embodiments of the present invention. ..</figref><figref num="10">The schematic block block diagram of the information processing system which concerns on 5th Embodiment of this invention.</figref><figref num="11">The schematic diagram explaining the example of the threshold value distribution of the 4-value NAND cell in the multi-value NAND type non-volatile memory applied to the 5th Embodiment of this invention.</figref><figref num="12">It is a detailed block diagram of the multi-value NAND type non-volatile memory applied to the information processing system according to the fifth embodiment of the present invention, and is an area 1 for storing a binary code and an area for storing quaternary user data. The schematic diagram explaining the configuration which comprises 2.</figref>

Code description

10 Host interface 12 ... (microprocessor) boot-up controller 14 Second selector 16 ... state machine 18 Address generator (address generation circuit) 20 ... 1st selector 22 Non-arithmetic instruction code generation circuit 24 Volatile memory (SRAM) 26 ... Non-volatile memory control device (boot-up control sequencer) 28 Memory cell block 30 Page unit 31 Page buffer 32 AND gate 34 Buffer circuit 36 Selector 38 (Multi-value NAND type) Non-volatile memory 40 Error detection / correction processing unit 42 Host CPU bus 50 CPU 52 ... DRAM 54 ... CPU bus 56 ... Storage memory 58 ... NAND controller 59 ... controller 60 ... Information processing system 62 ... NAND interface controller 64 ... boot memory 70 ... Multi-valued memory storage section (first area) 72 ... Memory cell block for boot code (second area) 80 ... bootup loader 84 ... Interface circuit 86 ... Bus 88 ... system memory WE ... write enable signal OE ... Output enable signal HBS ... host CPU bus signal CLK ... clock signal EMR ... External memory read data (signal) EMA ... External memory address (signal) IMR ... Internal memory read data (signal) IMA ... Internal memory address (signal) NCS ... NAND control signal NMD ... NAND memory data signal ND ... NAND data signal ECS ... Error detection / correction signal SMS ... Internal control signal SAG ... Internal control signal AGMA ... Address Generator Memory Address (Signal) NOP ... No arithmetic instruction (signal)