Semiconductor device and its manufacturing method

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor chip packaging technique.

In recent years, MCM (Multi Chip Module) has been attracting attention as a new packaging technology. MCM realizes a high-performance module by incorporating a plurality of semiconductor chips in one package. There are many types of MCM depending on how the semiconductor chips are arranged. Among them, the "laminated MCM", which is made by laminating a plurality of semiconductor chips, has recently attracted particular attention.

An example of the structure of this laminated MCM is shown in FIG. This laminated MCM200 is a stack of a plurality of semiconductor chips 204. The via hole 205 penetrating the semiconductor chip 204 is formed by laser processing, and the barrier metal 202 is formed on the side surface of the via hole 205 by a sputtering method or a CVD method. Then, by embedding a conductive material in the via hole 205 by copper plating, wiring for connecting the semiconductor chips 204 and 204 arranged vertically adjacent to each other is formed.

The insulation between the semiconductor chips 204 is maintained by inserting the thermoplastic film 203. By repeating such a manufacturing process, a plurality of semiconductor chips 204 can be laminated. A conductive terminal 206 is attached to the semiconductor chip 204 at the bottom to connect to an external circuit.

The laminated MCM200 can be manufactured by the above manufacturing process. The above-mentioned laminated MCM is disclosed in Patent Document 1.<patcit num="1"><text>Japanese Patent Application Laid-Open No. 9-232503</text></patcit>

<p> In order to manufacture the above-mentioned laminated MCM200, it is necessary to form a via hole having a diameter and depth of about several tens of μm and to embed a conductive material in the via hole. As a result, it is expensive, which has not been used in conventional semiconductor packaging, such as laser machining machines for via hole processing, barrier CVD equipment for barrier metal film formation, and copper plating equipment for embedding via holes. There is a problem that an apparatus is required and the manufacturing cost is high.</p>

<p> The semiconductor device of the present invention includes a first semiconductor device and a second semiconductor device arranged on the first semiconductor device, and the first semiconductor device is on a first semiconductor chip. The first wiring and the second wiring formed through the insulating film 1 and the first semiconductor chip on which the first and second wirings are formed are adhered to the first semiconductor chip via an adhesive. A support substrate having an opening for exposing the second wiring, a second insulating film formed on the side surface portion and the back surface portion of the first semiconductor chip, and the second insulating film formed on the back surface portion and the back surface portion of the first semiconductor chip are connected to the back surface of the first wiring. A third wiring extending from the side surface portion to the back surface portion of the semiconductor chip so as to be in contact with the insulating film of 2, and a protective film formed on the back surface portion of the semiconductor chip so as to cover the third wiring. A conductive terminal formed on the third wiring via the protective film is provided, and the second semiconductor device is formed on the second semiconductor chip and the back surface of the second semiconductor chip. A conductive terminal is provided, and the conductive terminal of the second semiconductor device is connected to the second wiring through an opening of the first semiconductor device. Also,<u style="single">Formed on the conductive terminal formed on the third wiring or on the back surface of the second semiconductor device.</u>The conductive terminal is a protruding electrode terminal. Further, the protruding electrode terminal is a solder bump or a gold bump. Further, the support substrate is a glass substrate, a silicon substrate, or a plastic.<u style="single">Any one of</u>It is characterized by being a plate material made of. Further, in the method for manufacturing a semiconductor device of the present invention, a semiconductor wafer having a plurality of semiconductor chips on which a first wiring and a second wiring are formed via a first insulating film is prepared, and the first and first semiconductor wafers are prepared. A step of adhering a support substrate to the semiconductor wafer on which the wiring of 2 is formed via an adhesive, a step of etching the boundary portion of the plurality of semiconductor chips from the back surface of the semiconductor wafer, and a semiconductor exposed by the etching. The step of forming a second insulating film on the side surface portion and the back surface portion of the chip, and the side surface portion to the back surface portion of the semiconductor chip connected to the back surface of the first wiring and in contact with the second insulating film. A step of forming a third wiring extending to the semiconductor chip, a step of forming a protective film on the back surface of the semiconductor chip so as to cover the third wiring, and a step of forming a protective film on the third wiring via the protective film. A step of forming a conductive terminal, a step of forming an opening for exposing the second wiring in the support substrate, and a step of dividing into a plurality of semiconductor chips along the boundary portion are provided. The second semiconductor chip is laminated on the first semiconductor chip by connecting the conductive terminal of the second semiconductor chip to the second wiring exposed through the opening of the first semiconductor chip. It is characterized by. Further, it is characterized by comprising a step of scraping the surface of the support substrate after the step of forming a conductive terminal on the third wiring and before the step of forming an opening in the support substrate. .. Further, the step of scraping the surface of the support substrate is a step of dropping an etching solution onto the surface of the support substrate and rotating the support substrate. Further, it is characterized by comprising a step of forming a plating layer on the second wiring after the step of forming an opening for exposing the second wiring in the support substrate.</p>

<p> According to the present invention, it is possible to manufacture a laminated MCM at a low manufacturing cost without using an expensive device.</p>

Next, the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention will be described with reference to FIGS. 1 to 13.

First, as shown in FIG. 1, a semiconductor wafer 1a is prepared. The semiconductor wafer 1a is cut and separated into a plurality of semiconductor chips 1 in a step described later. These semiconductor chips 1 are, for example, CCD image sensors and semiconductor memory chips, and are formed by a semiconductor wafer process. A plurality of first wirings 3A and a plurality of second wirings 3B are simultaneously formed on the surface of the semiconductor wafer 1a via the insulating film 2. The first wiring 3A is formed with a predetermined gap on both sides of a boundary S for cutting and separating the semiconductor wafer 1a into a plurality of semiconductor chips 1. The boundary S is called a dicing line or a scribe line.

Here, the first wiring 3A is a pad extended from the normal bonding pad position of the semiconductor chip 1 to the vicinity of the boundary S. Further, the plurality of second wirings 3B are conductive pads that are electrically connected to the conductive terminals of other semiconductor devices laminated on the semiconductor chip 1 in a later process.

Subsequently, the glass substrate 4 as a support is adhered to the surface of the semiconductor wafer 1a on which the first wiring 3A and the second wiring 3B are formed by using the epoxy resin layer 5 as an adhesive. Although a glass substrate is used as the support and an epoxy resin layer is used as the adhesive here, a tape or sheet-like material may be used as the support in addition to the silicon substrate and the plastic plate, and the adhesive may be used. Should select the appropriate adhesive for these supports.

Next, as shown in FIG. 2, the surface of the semiconductor wafer 1a to which the glass substrate 4 is not adhered, that is, the back surface thereof is back-grinded to reduce the thickness of the semiconductor wafer 1a. The back surface of the back-grinded semiconductor wafer 1a is scratched and has irregularities having a width and a depth of about several μm. In order to reduce this, a silicon oxide film (hereinafter referred to as SiO), which is the material of the insulating film 2, is used.₂), Wet etching is performed using a silicon etching solution that has a higher selectivity for silicon (hereinafter referred to as Si), which is the material of the semiconductor wafer 1a. As such a silicon etching solution, for example, a mixed solution of 2.5% hydrofluoric acid, 50% nitric acid, 10% acetic acid and 37.5% water is suitable.

Next, as shown in FIG. 3, isotropic etching is performed on the back surface of the semiconductor wafer 1a using a resist pattern (not shown) provided with an opening along the boundary S as a mask. As a result, a groove is formed at the boundary S portion, and the insulating film 2 is partially exposed. This etching may be performed by either dry etching or wet etching. Although the semiconductor wafer 1a is cut into a plurality of semiconductor chips 1 by this etching, it is supported by the glass substrate 4 and maintains the form of the semiconductor wafer 1a.

Concavities and convexities, residues, and foreign substances are present on the back surface of the etched semiconductor wafer 1a, and corners as shown by the broken line circles a and b in FIG. 3 are formed. Therefore, as shown in FIG. 4, the residue and foreign matter are removed, and wet etching is performed to further round the corners. As a result, the corners as shown by the broken line circles a and b in FIG. 3 have a smooth shape as shown by the broken line circles a and b in FIG.

Next, as shown in FIG. 5, the insulating film 7 is adhered to the back surfaces of the plurality of semiconductor chips 1 and their etched side surfaces. The insulating film 7 is, for example, a silane-based oxide film.

Next, as shown in FIG. 6, a resist (not shown) is applied to the back surface of the semiconductor chip to perform patterning. Using the resist film as a mask, the insulating film 7 and the insulating film 2 are etched to expose the end portion of the first wiring 3A.

Next, the flexible cushioning member 8 is formed at a position overlapping the position where the conductive terminal 11 is formed later. The cushioning member 8 has a function of absorbing a force applied to the conductive terminal 11 and relieving stress at the time of joining the conductive terminal 11, but it is not always necessary. Next, the insulating film 7, the cushioning member 8, and the third wiring 9 covering the exposed portion of the first wiring 3A are formed. As a result, the first wiring 3A and the third wiring 9 are electrically connected.

Next, as shown in FIG. 7, a resist (not shown) is applied to the back surface side of the semiconductor chip 1, and a pattern is formed so as to open a portion along the boundary S of the resist. Then, etching is performed using the resist as a mask to remove the third wiring 9 near the boundary S. Although not shown, the surface of the third wiring 9 may be plated with Ni-Au by electroless plating after the formation of the third wiring 9.

Next, the protective film 10 is formed on the back surface side of the semiconductor chip 1. In order to form the protective film 10, a thermosetting organic resin is dropped from above with the back surface side of the semiconductor chip 1 facing upward to have a plurality of semiconductor chips 1 and the glass substrate 4 is adhered. The semiconductor wafer 1a is rotated. Due to the centrifugal force generated by this rotation, the organic resin spreads on the surface of the semiconductor wafer 1a. As a result, the protective film 10 can be formed on the surface of the third wiring 9.

Next, as shown in FIG. 8, the protective film 10 of the portion forming the conductive terminal 11 is selectively removed by etching using a resist mask to expose the third wiring 9, which is exposed. A conductive terminal 11 that contacts the third wiring 9 is formed. The conductive terminal 11 can be formed of, for example, a protruding electrode terminal such as a solder bump or a gold bump. The thickness of the conductive terminal 11 is 160 μm when solder bumps are used, but can be reduced to several μm to several tens of μm when gold bumps are used. A plurality of conductive terminals 11 have the same structure on the back surface of the semiconductor chip 1, and a ball grid array can be formed.

Next, the surface of the glass substrate 4 is scraped to reduce its thickness. As a result, the processing time for forming the opening in the glass substrate 4, which will be described later, can be shortened. The appropriate thickness of the glass substrate is 50 μm to 100 μm. As a method of thinning the glass substrate 4, (1) a method of grinding the glass substrate 4 with a back grind device, (2) a method of polishing the glass substrate 4 with a CMP device, and (3) a method of polishing the glass substrate 4 such as resist coating. A method in which an etching solution is dropped onto 4 and the semiconductor wafer 1a to which the glass substrate 4 is adhered is rotated to spread the etching solution over the entire glass substrate 4 to etch the glass substrate 4, (4) dry etching. A method of etching the glass substrate 4 using the above can be mentioned. Although the present invention includes a step of thinning the glass substrate 4, it does not limit the use of a support made of a plate material, a tape, or a sheet having a predetermined thickness from the beginning.

Next, as shown in FIG. 10, the glass substrate 4 and the resin layer 5 on a part of the second wiring 3B are removed by etching or the like to form an opening 12 that exposes the surface of the second wiring 3B. .. On the contrary, after the opening 12 is formed, the glass substrate 4 may be shaved to make it thinner, but the processing time for forming the opening 12 becomes longer. Next, the plating layer 13 is formed on the surface of the second wiring 3B exposed by the opening 12. The plating layer 13 constitutes a part of the second wiring 3B. The plating layer 13 is formed by laminating, for example, a Ni plating layer and an Au plating layer.

Next, as shown in FIG. 12, the semiconductor wafer 1a is cut along the boundary S using a dicing apparatus and separated into a plurality of semiconductor chips 1. At this time, the glass substrate 4, the resin layer 5, and the protective film 10 are cut along the boundary S. As a result, the BGA type semiconductor device 100 incorporating the semiconductor chip 1a is completed. According to this BGA type semiconductor device 100, only one glass substrate 4 supporting the semiconductor chip 1 is adhered to the semiconductor chip 1, and the glass substrate 4 is thinly processed, so that the entire package can be made thin. it can. Further, since the glass substrate 4 is formed with an opening 12 that exposes the second wiring 3B of the semiconductor chip 1, the necessary electrical connection with an external electronic circuit can be obtained through the opening 12. Can be done.

FIG. 13 is a cross-sectional view showing the structure of a laminated MCM as an example of such an electrical connection structure. In this laminated MCM, the first semiconductor device 100a and the second semiconductor device 100b are laminated. The first semiconductor device 100a and the second semiconductor device 100b have the same structure as the above-mentioned semiconductor device 100. The conductive terminal 11B of the second semiconductor device 100B is electrically and mechanically connected to the second wiring 3B of the first semiconductor device 100a through the opening 12. If the connection strength is insufficient, an organic adhesive such as underfill may be used as an auxiliary. Further, the number of semiconductor devices to be stacked can be selected as needed.

<figref num="1">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="2">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="3">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="4">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="5">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="6">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="7">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="8">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="9">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="10">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="11">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="12">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="13">It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention.</figref><figref num="14">It is a schematic diagram of the cross section of the conventional MCM type semiconductor device.</figref>