Inverter controller

The present invention relates to an inverter controller, more specifically, to reduce the overall total number of pins and the number of components without reducing the functionality and / or performance of the controller. Inverter controllers that utilize pin multiplexing and / or pin multitasking technology.

The particular utility for the present invention is for a two-switch DC / AC inverter topology for driving CCFLs, but as used herein, other inverter topologies and / or DC / AC converter topologies. Equally consider and / or other loads.

<p> The present invention provides an integrated circuit that includes an inverter controller adapted to generate multiple signals for driving an inverter circuit. The control device further includes one or more input pins configured to receive two or more input signals. Each signal supports an associated function.</p><p> In an exemplary embodiment, the input pin is configured to receive a first signal representing a dim voltage, the first signal having a first voltage range. Further, the input pin is configured to receive a second signal representing a voltage feedback signal, which has a second voltage range.</p><p> In another exemplary embodiment, the input pin is configured to receive a first signal representing a current feedback signal, the first signal being present within the first period. Further, the input pin is configured to receive a second signal representing a soft start signal, which is present within the second period.</p><p> The present invention further provides an inverter control device IC including a multiplexing circuit, the multiplexing circuit for directing one input signal to a first circuit for supporting the first function of the control device. There is, and the other one of the input signals is directed to the second circuit for supporting the second function of the control device.</p><p> The present invention further provides an inverter controller IC that includes input pins configured to receive two or more input signals, each signal supporting a related function of the controller. One of the input signals is present within the first period and the other one of the input signals is present within the second period.</p>

<p> Therefore, according to the present invention, the total number of pins can be significantly reduced. In addition, by selecting which pins can be multifunctional and / or multiplexed, the present invention reduces the need for machine tooling and PCB layout.</p>

Further benefits and benefits of the present invention will become apparent to those skilled in the art relating to the present invention from the description and claims of subsequent preferred embodiments taken up in connection with the accompanying drawings.

FIG. 1 shows a block diagram of an exemplary inverter controller integrated circuit 10 according to the present invention. In this exemplary embodiment, the controller 10 has an 8-pin design (labeled 1-8), in which case pin 2 is adapted to receive two signals. Multiplexed to support two functions, and pin 4 is adapted to receive two signals to support the two functions, depending on the state of some component of the controller. In this example, pin 2 supports both load voltage sensing and dim signal sensing. Pin 4 supports both current comparison under normal operating conditions and soft start (SST) operation during initial turn-on and / or lamp out conditions.

The control device 10 includes an overvoltage protection circuit 100, a dimming circuit 200, a current feedback control circuit 300, and an output circuit 400. The control device 10 further includes a MUX 18 for controlling the switching of the function of pin 2 between the sensing of the load voltage and the input control of the dimming signal based on the load condition. The control device includes an oscillation circuit 12 that generates a sawtooth wave signal 14 by charging / discharging the fixed capacitor CT16, and a reference signal that generates one or more of a reference signal and / or a bias signal used by the control device 10. / Includes a bias signal generator 20 and more. The control device operates to generate two switch drive signals NDR1 and NDR2. The drive control signal can be used to drive two switches, a derived Royer circuit, a push-pull circuit, a half-bridge circuit, or another two-switch inverter circuit known in the prior art. it can.

In other words, the present invention provides an inverter controller that includes one or more multiplexed and / or multifunctional pins, wherein the controller is multiplexed and / or multiple. Adapted to generate one or more control signals based on the signal state of the functional pins. The following description of the overvoltage protection circuit 100, the dimming circuit 200, the current control circuit 300, and the output circuit 400 will be readily understood by those skilled in the art of inverter technology. Each of the components of the control device 10 will be described in more detail later.

The output circuit 400 includes a comparator 42 that compares the signal 52 from the output of the error amplifier 30 with the sawtooth wave signal generated by the oscillator circuit 12. The error signal 52 is generated by the current control circuit 300 and / or by the capacitor 40 (at pin 4) which can also be corrected by the dimming circuit 200. The error signal has a value in the range from the minimum value to the maximum value of the sawtooth wave signal 14 for normal operation. For example, for CCFL loads, the sawtooth signal can have a range of 0V to 3V. As is understood in the prior art, the intersection between the sawtooth wave signal 14 and the error signal 52 is provided by the switch drive logic circuit 44 for setting the pulse width of each of the switch drive signals NDR1 and NDR2. Used. In general, the higher the error signal value, the wider the pulse width (although the circuit can be modified if the opposite is true), thus providing more power to the load.

As described above, the value of the error signal 52 is determined by the current feedback information generated by the current control circuit 300 and corrected by the dimming circuit 200. Generally, the CMP capacitor 40 is charged during the initial power-on state of controller 10. The error amplifier 30 acts as a current source (eg, a mutual conductance amplifier) for adjusting the charge on the CMP capacitor 40. Amplifier 30 sets the load current Isens to maximum power or maximum brightness. Compare against a user-definable reference signal 32 that indicates the maximum load current 32 at brightness). If the value of the load current is less than the signal 32, the amplifier 30 sources the current to charge the capacitor 40 in an attempt to increase the DC value of the error signal 52, thereby the output drive signals NDR1, Increase the pulse width of NDR2. If the load current value is greater than the reference signal 32, the amplifier 30 sinks the charge from the CMP capacitor 40 to reduce the DC value of the error signal 52, thereby pulsing the output drive signals NDR1 and NDR2. Reduce the width. That is, the amplifier 30 represents a closed-loop feedback current control that sources or reduces the load current Isens in an attempt to maintain it approximately equal to the reference signal 32.

The dimming circuit 200 is enabled by the MUX circuit 18 (more on this process later) and the relative dim value is set by VDIM (pin 2). In an exemplary embodiment, VDIM is a DC signal with values V1 to V2. VDIM can be generated by software programmable dimming values or by a user-operable switch (eg, a rotary switch). In this example, the circuit can be modified if the opposite is true, but the higher the Vdim value, the more power is delivered to the load. The dimming circuit 200 is a burst mode dimming circuit that generates a burst mode signal (low frequency PWM signal 50) having a duty cycle proportional to Vdim. The frequency of the burst mode signal 50 is selected so as to be much smaller than the frequencies of the drive signals NDR1 and NDR2. For example, for CCFL applications, the normal operating range of the drive signal may be 35-80kHz, and the burst mode signal may have a frequency of about 200Hz.

In an exemplary embodiment, the dimming circuit 200 comprises a digital dimming circuit that receives Vdim and converts Vdim into a digital signal. Digital signals are weighted to a given bit depth (eg, 8 bits) to represent a given number of dimming values (eg, 256 dim levels). The digital dimming circuit 36 produces a burst mode signal 50 having a duty cycle proportional to the value of Vdim. In this example, the duty cycle of the burst mode signal 50 ranges from 0% (Vdim = V1) to 100% (Vdim = V2).

When the dimming circuit 200 is enabled by MUX18, the PWM enable block 38 operates to reduce the charge from the CMP capacitor 40. The enable block 38 may include a simple switch coupled to the ground with a conduction state controlled by the burst mode signal 50. As mentioned above, the error amplifier 30 produces an output to maintain the DC signal 52 having the maximum value represented by the signal 32. The burst mode signal 50 operates as follows. When the burst mode signal is asserted (high or low), the enable circuit 38 reduces the charge from the capacitor 40. The resulting DC signal 52 is the minimum value (eg, 0 volt). As a result, the signal generated by the comparator 42 represents the intersection of the lowest value of the CT signal 14 with the DC signal 52, which causes the switch drive logic 44 to perform while the burst mode signal is being asserted. , Turn off the drive signals NDR1 and NDR2. When the burst mode signal is deassert, the enable block 38 is essentially open circuit and the error amplifier 30 recharges the capacitor 40 to its original value. The resulting error signal regains a value corresponding to the maximum luminance output as described above, whereby the switch logic circuit driver generates drive signals NDR1 and NDR2 having a duty cycle corresponding to the maximum luminance output. Thus, in this exemplary embodiment, the burst mode step rocks the output from a fully on state to a completely off state at the frequency determined by the burst mode signal 50.

Pin 2 is adapted to receive two signals that represent both the load voltage sensing (Vsens) and the input of the DIM signal. DIM signals (Vdim) are used to support load power control. Load voltage control is used, for example, to detect overvoltage conditions in a load. In this example, the multiplexing device MUX18 is utilized to direct the input on pin 2 (either Vsens or Vdim) to the overvoltage protection circuit 100 or the dimming circuit 200 based on predetermined conditions. In this example, the predetermined condition is a lamp on signal 34, which indicates that a lamp load is present and is operating properly, in which case the signal 34 is an input to the MUX 18. In this exemplary embodiment, the DIM signal is fixed within a predetermined range (ie, V1 &lt;Vdim &lt;V2). Vsens is configured to be outside this range (ie, Vsens&gt; V2 or Vsens &lt;V1).

When the controller is first powered on to drive the load, the controller provides both load voltage and load current feedback to determine if the load is working properly. receive. Current feedback is represented by Isens at pin 3 and voltage feedback is represented by Vsens at pin 2. Assuming a lamp load (eg CCFL), one of ordinary skill in the art can cause a dangerous high voltage situation on the secondary side of the transformer (not shown in Figure 1) by a damaged or lost lamp. Will recognize. Therefore, the present invention first determines the state of the lamp load by checking whether the minimum current is being supplied to the load.

The comparator 28 compares the load current Isens with the lamp threshold signal 46. The ramp threshold signal 46 is a signal indicating the minimum current that should exist under the load when the load is operating properly. If the Isens is greater than or equal to the signal 46, the comparator 28 produces a lamp-on signal 34 indicating that the lamp load is working properly. The lamp-on signal 34 is a control signal generated by the comparator 28 that controls the state of the MUX 18. In this case, the lamp-on signal sets the output state of the MUX in order to connect the dimming circuit 200 to pin 2. The latch circuit 74 is provided to latch the output of the lamp-on signal once Isens exceeds the threshold signal 46. The lamp-on signal remains in this state during normal operation, so that burst mode dimming (discussed below) does not change the state of the lamp-on signal. The Vdim input on pin 2 is then used to set the desired dim luminance value (as described below).

However, during the time the controller to drive the load is first applied power (and, before the latch circuit 74 is set), the current sensing value Isens glass if below the lamp threshold signal 46, The output of the amplifier 28 changes the state of the lamp-on signal 34. This in turn changes the state of the MUX and connects the overvoltage protection circuit 100 to pin 2. As understood in CCFL technology, Vsens is obtained from the secondary side of the transformer used to drive the ramp load. Under normal operating conditions, Vsens does not affect the range of Vdim (ie, V1 &lt;Vdim &lt;V2). However, in the presence of open or damaged lamp conditions, Vsens rises to a value greater than V2. When pin 2 is connected to the overvoltage protection circuit 100, Vsens is compared in the comparator 22 with a predetermined overvoltage threshold signal Vovp (in this case, Vovp&gt; V2). When Vsens exceeds Vovp48, the output of the comparator causes the timing circuit 24 to start a predetermined timeout period.

Since this is a condition of a damaged or lost lamp, Isens has a value smaller than the lamp threshold signal 46. In addition, the error amplifier 30 produces an output signal in an attempt to source the CMP capacitor to increase the power supplied to the load. Thereby, during the timeout period, the protection circuit operates in the same manner as the PWM enable circuit 38. During this period, the OVP signal 60 shuts down the error amplifier 30 to charge / discharge the CMP capacitor 40 to prevent the error amplifier from generating an error signal to drive the switch with higher power. Let me. At the end of the timeout, the protection circuit 26 disables the switch drive logic circuit 44, which controls the output of the overvoltage.

Therefore, in summary, the invention is: 1) An overvoltage protection circuit 100 configured to receive a voltage feedback signal from the load and to generate a protection signal to interrupt power to the load. And 2) the dimming circuit 200 configured to receive the dimming signal and to generate the dimming signal to control the power supplied to the load, and 3) the current feedback from the load. A current control circuit 300 configured to receive a signal and configured to generate an error signal, and 4) a load configured to receive the error signal and the dimming signal. Provided is an inverter control device IC for generating power to a load, including an output circuit 400 configured to generate a drive signal for driving the load. One of the IC pins (eg, pin 2) is configured to receive a voltage feedback signal and a dimming signal. The multiplexing device 18 is connected to a pin and is configured to direct the voltage feedback signal to the overvoltage protection circuit or the dimming signal to the dimming circuit based on the value of the current feedback signal.

Pin 4 and CMP capacitors work further to control the functionality of Soft Start (SST). The soft start essentially operates at the beginning of power-on in order to cause the output circuit to generate a minimum pulse width and gradually increase the pulse width, as is known in the art. At the first power-on, the voltage on the CMP capacitor is zero. Since Isens is also zero, the error amplifier attempts to source the CMP capacitor to a charge that satisfies signal 32. The time required for this process depends on the desired charge on the CMP and the capacitance of the CMP, so this time is used as a soft start. This ensures that the amount of power to the load gradually increases. This continues until the load current value reaches the threshold 32. The error amplifier 30 then takes over control of pin 4, which is the charge on the capacitor, as described herein. For CCFL loads, gradual increases in lamp current are known to help guarantee lamp life.

Therefore, pin 4 is adapted to generate the DC signal CMP52 based on the value of the error signal generated by the current control circuit 300 and / or the value of the dimming signal generated by the dimming circuit 200. Pin 4 is multifunctional as it is also adapted to generate a soft start signal 52 based on the value of the error signal generated by the current control circuit 300.

FIG. 5 shows a typical signal graph for a signal generated by the control device 10 of the present invention. 5A indicates drive signals NDR1 and NDR2. As shown in 5D, the pulse width of these drive signals is determined by the intersection of the DC error signal CMP52 and the sawtooth signal CT. 5B indicates burst mode signal (LPWM) 50, and 5C indicates load current I._LIs shown. If the burst mode signal is deasserted (highed), such as 50A, then there is a drive signal and ramp current. When the burst mode signal is asserted (pulled) like 50B, the drive signal is stopped and the ramp current is almost zero. Note that when the burst mode signal is asserted, the CMP signal drops to its minimum value (nearly zero), as described above.

FIG. 2 shows another exemplary inverter controller 10'according to the present invention. The inverter controller 10'of this exemplary embodiment operates in a manner similar to that described above with reference to FIG. 1, but includes additional circuitry that may be desirable for a given operating environment. For example, the output of the error amplifier 30 has an on / off circuit triggered by an OVP signal. If the overvoltage protection circuit is activated, the OVP signal cuts off the output of the error amplifier 30 regardless of the value of Isens. As a result, when the OVP signal is asserted, the capacitor 40 is discharged by the protection circuit 26, and as a result, the output signals NDR1 and NDR2 operate in the minimum state for supplying the minimum power. Of course, the protection circuit can also be adapted to charge the capacitor 40 to a minimum level, so that the output signal provides a predetermined minimum pulse width to the load during the timeout period.

The controller 10' further includes a minimum / maximum circuit 56, which is the zero DC value as described above during the period during which the burst mode signal is enabled (during these periods). Generate a minimum DC value (instead of 52). As a result, the intersection of the sawtooth wave signal and the minimum DC signal generated by the minimum / maximum circuit 56 generates an output for giving the output signal a predetermined minimum pulse width. This prevents a wide range of voltage fluctuations between the asserted burst mode signal and the deasserted burst mode signal, and / or maintains a continuous function of the drive signal, for example.

The enable comparator 58 is provided to generate an enable control signal for the switch logic circuit 44. If the value on the capacitor 40 is greater than the enable threshold, the comparator will generate an enable signal (which enables the switch logic), otherwise the switch logic will be disabled.

The PWM enable circuit 38'can include a floor value (ie, bias) that is the upper limit that the enable circuit does not decharge from the CMP capacitor 40. Like the min / max circuit, this prevents the burst mode enable signal from completely reducing the charge on the capacitor, so that the output signal is set to a predetermined non-zero minimum. The bias value can be selected according to the operating range of the controller, the desired minimum power delivered to the load during burst mode assertion, and / or other factors apparent to those of skill in the art.

FIG. 6 shows a typical signal graph for a signal generated by the control device 10'of the present invention. 6A indicates drive signals NDR1 and NDR2. As shown in 6D, the pulse width of these drive signals is determined by the intersection of the DC error signal CMP52 and the sawtooth signal CT. 6B indicates burst mode signal (LPWM) 50', and 6C indicates load current I._LIs shown. If the burst mode signal is deasserted (highed), such as 50A', then there is a drive signal and ramp current. When the burst mode signal is asserted (pulled) like 50B', the drive signal is reduced to a predetermined minimum pulse width and the ramp current is significantly reduced. The asserted burst mode signal value 50B'is biased as described above. Note that, as mentioned above, when the burst mode signal is asserted, the CMP signal drops to a minimum (greater than zero).

As a result, the exemplary inverter controller ICs 10, 10'in FIGS. 1 and 2 have a first input signal (eg, Vdim or Vsens) with a first predetermined range and a second with a second predetermined range. Includes pins (eg, pin 2) that are multiplexed to receive the input signal. Inverter controllers IC10,10'are multifunctional pins to operate in the first period (eg, normal operating conditions) and the second period (eg, the first power with soft start loading). For example, it is also adapted to include pin 4).

FIG. 3 is a diagram showing an exemplary application topology for the inverter controller IC 10 or 10'. The inverter controller IC10 or 10'shown in FIG. 3 is used to drive a derived Royer circuit consisting of transistors Q1 and Q2 to power the CCFL load 66. Transistors Q1 and Q2 drive the primary side of the transformer 60 through a resonant tank circuit formed by the capacitor 68 and the primary side inductance of the transformer 60. The operation of this type of circuit is well known to those of skill in the art. Vsen is obtained from a voltage divider (node 62) between capacitors C1 and C2, so that the value of Vsen is the nominal value compared to the voltage on the secondary side of the transformer. Vsen is usually in the range of 1-5 volts. Isen is obtained from the CCFL load through a voltage divider circuit (node 64) consisting of R1 and R2. Isen usually ranges from 0 volts (without lamps) to 1.25 volts (maximum lamp brightness). Of course, these values are only exemplary and can be modified to meet design criteria without departing from the present invention. FIG. 4 shows another exemplary application topology for inverter controller ICs. The controller in this embodiment is used to drive two (or more) CCFL loads 66,70. In this case, the current feedback Isens is obtained from the lamps 66,70 and both the voltage dividers R1, R2 and the voltage dividers R3, R4.

Those skilled in the art will recognize a number of modifications that can be made to the present invention. For example, the controllers IC10,10'in FIGS. 1 and 2 multiplex the Vsen value and the DIM value on pin 2 and combine the functionality of the charged CMP capacitor 40 with the soft start functionality. .. However, these are just examples of pin multiplexing / multitasking that can be achieved by the present invention. Other pins associated with the exemplary IC can be multiplexed and / or multitasked. In addition, other IC designs that require more or less pins than the 8-pin ICs shown in FIGS. 1 and 2 are multitasking and / or multiplexing as provided herein. Can be included as well.

Still other modifications can be made. In the exemplary controller IC of FIGS. 1 and 2, pin 2 is multiplexed to support both load voltage sensing and dim signal input. The dim signal range (V1 &lt;Vdim &lt;V2) as disclosed above and the overvoltage protection threshold Vovp are selected such that Vovp&gt; V2. However, this relationship is not required for the present invention to function properly. In fact, since the Vsens value is used by the overvoltage protection circuit 100 regardless of the dim value, Vovp can be selected within or below the Vsens range. Alternatively, for the multiplexing and / or multifunctional pins disclosed herein, use the multiplexing and / or multifunctional techniques provided herein to support three or more signals. Can be adapted to.

Still other modifications can be made. For example, the exemplary application topologies of FIGS. 3 and 4 show a controller IC10 or 10'that drives a derived Royer circuit formed by Q1 and Q2. However, the controller 10 or 10'can be similarly applied to push-pull inverters, half-bridge inverters, and / or other types of two-switch inverter topologies known in the art. Further, for the controller IC 10 or 10', a second set of drive signals (eg, PDR1, PDR1," for allowing the controller IC 10 or 10'to drive a 4-switch inverter topology (full bridge inverter). It can be modified to include PDR2).

The present invention is not limited to CCFL loads. In fact, the control device 10 or 10'of the present invention can be used to drive other lamp loads such as metal halides or sodium vapor. Still other loads can be used. For example, the controller 10 or 10'of the present invention can be adapted to operate in a frequency range to support the driving of X-ray tubes or other higher frequency loads. The present invention is not limited to the form of the load and should be construed as independent of the load. In addition, a number of lamp topologies as shown in FIG. 4, for example, U.S. Pat. No. 6,104,146, U.S. Patent Application No. 09 / 873,669, U.S. Patent Application No. 09 / 850,692, U.S. Patent Application No. 10 / 035,973. Many other topologies can be used, such as those shown in the issue (all of which are incorporated herein by reference in their entirety).

A detailed discussion of the behavior of the components in Figures 1 and 2 has been omitted. For example, the operation of the oscillator circuit 12 and the operation of the switch logic circuit 44 have been omitted because those skilled in the art would easily recognize both the operation of these features and the means of implementation. Further, the timings of the drive signals NDR1 and NDR2 are not described in detail in the present specification because the operation of these signals is obvious to those skilled in the art. The above-mentioned detailed description of the block diagrams of FIGS. 1 and 2 is mainly directed to the functionality of the components. The components of FIGS. 1 and 2 may be off-the-shelf or custom-made to achieve the functionality described herein, and those skilled in the art can be referred to herein. It will be readily appreciated that many circuit implementations are available to achieve the stated functionality, and all such alternatives are believed to be within the scope of the present invention.

Moreover, voltage and current feedback and dim signals and inverter controller circuits (as described herein) are well known to those of skill in the art. However, prior art integrated circuit inverter controllers have not addressed the long-held need to reduce the total number of pins in an IC package while maintaining the functionality of the inverter IC. The present invention described herein provides an example for addressing this issue, for example by providing multiplexing and / or multifunctional IC pins. Numerous modifications to the subject matter of the invention are apparent to those skilled in the art, and all such modifications are believed to be within the scope of the invention as stated in the claims.

<figref num="1">It is a block diagram of an exemplary inverter control device integrated circuit according to the present invention.</figref><figref num="2">It is a block diagram of another exemplary inverter control device integrated circuit according to the present invention.</figref><figref num="3">It is a figure which shows the circuit topology which becomes an exemplary use about the inverter control device IC of FIG. 1 or FIG.</figref><figref num="4">It is a figure which shows the circuit topology which becomes the other exemplary use about the inverter controller IC of FIG.</figref><figref num="5">It is a figure which shows the typical signal graph about a certain signal generated by the control device of FIG.</figref><figref num="6">It is a figure which shows the typical signal graph about a certain signal generated by the control device of FIG.</figref>

Code description

10,10'Inverter controller 12 Oscillator circuit 16,40 capacitors 18 Multiplexer 20 Reference signal / bias signal generator 24 Timing circuit 26 protection circuit 28 Comparator 30 error amplifier 36 Digital dimming circuit 38 PWM enable circuit 42 Comparator 44 Switch drive logic circuit 56 Minimum / Maximum Circuit 58 Enable Comparator 74 Latch circuit 100 overvoltage protection circuit 200 dimming circuit 300 current control circuit 400 output circuit