Test interface circuit and semiconductor integrated circuit using the same

[0001] [Technical field to which the invention belongs] The present invention relates to a test interface circuit and a semiconductor integrated circuit device using the same, and more particularly to a test interface circuit for directly testing a logic embedded memory from the outside and a semiconductor integrated circuit device including the test interface circuit. [0002] [Conventional technology] In system LSIs such as DRAM with built-in logic in which logic such as a processor or ASIC (IC for specific applications) and dynamic random access memory (DRAM, etc.) with a large storage capacity are integrated on the same semiconductor chip (semiconductor substrate). By interconnecting logic and DRAM with a multi-bit internal data bus of 128 bits to 512 bits, it is possible to realize a high-speed data transfer speed of one or two orders of magnitude or more compared to general-purpose DRAM. In addition, DRAM and logic are connected by internal wiring, and the length of this internal wiring is sufficiently shorter than the wiring on the board, and the parasitic impedance is also small, so that the charge / discharge current of the data bus can be significantly reduced and the speed is high. Signal transfer can be performed. In addition, the logic and DRAM are connected by internal wiring, and the number of external pin terminals of the logic can be reduced as compared with the method of externally attaching a general-purpose DRAM to this logic. For these reasons, DRAM mixed-load system LSIs have greatly contributed to improving the performance of information devices that handle a large amount of data such as 3D graphic processing and image / audio processing. [0003] In such a logic mixed DRAM, only the logic is coupled to the terminal via the pad. Therefore, when testing the functionality of the built-in DRAM, it is necessary to test via logic. However, in this case, the logic controls for performing the test, which increases the load on the logic. In addition, it is necessary to give an instruction for performing a DRAM functional test to the logic from the outside, give a control signal for performing a functional test from this logic to the DRAM again, and read the test result via the logic. is there. For this reason, DRAM functional tests are executed via logic, and tests such as DRAM operation timing merging cannot be performed accurately. Further, from the viewpoint of program capacity, the number of test patterns in which logic is generated is also limited, and sufficient tests cannot be performed, and it is difficult to sufficiently guarantee the reliability of DRAM. Further, as the gate scale increases, the probability of occurrence of a defect in the logic itself increases, so that the reliability of the memory test decreases. [0004] Therefore, it becomes necessary to test the DRAM directly from the outside through a dedicated test device. [0005] FIG. 13 is a diagram schematically showing the configuration of a conventional system LSI with a built-in DRAM. In FIG. 13, the system LSI SLI is coupled to the external pin terminal group LPGA and is coupled between the large-scale logic LG that executes the commanded processing and the large-scale logic LG and the external pin terminal group APG for the analog signal. The analog core ACR that performs processing, the DRAM core MCR that is connected to the large-scale logic LG via internal wiring and stores the data required by this large-scale logic LG, and the large-scale logic LG and DRAM core in test mode. Includes a test interface circuit TIC that disconnects from the MCR and couples an external memory tester to the DRAM core MCR via the pin terminal group TPG. The DRAM core MCR receives the power supply voltage VCC via the power supply pin terminal PST. [0006] The analog core ACR is a phase-locked loop (PLL) that generates an internal clock signal, an analog / digital converter that converts an external analog signal into a digital signal, and a digital signal given by a large-scale logic LG into an analog signal. Includes digital / analog converters that convert and output. [0007] The DRAM core MCR is a clock synchronous memory (SDRAM). Large-scale logic LG includes a memory control unit for performing processing such as image / audio processing and controlling access to the DRAM core MCR. [0008] As shown in FIG. 13, by providing the test interface circuit TIC, the DRAM core MCR can be completely separated from the logic section and directly accessed via the external pin terminal group TPG, and is directly outside the DRAM core MCR. Control and external observation are possible. Such a test method is called a direct memory access test. By providing this test interface circuit TIC, a conventional memory tester can be used, and a test almost the same as that of a general-purpose DRAM (SDRAM) can be performed. [0009] FIG. 14 is a diagram showing the configuration of the test interface circuit TIC shown in FIG. 13 and related parts thereof. In FIG. 14, the pin terminal group TPG specifies a pin terminal that receives the test clock TCLK, a pin terminal that receives the test control signal TCMD that specifies the test operation mode, and a memory cell that should be accessed by the DRAM core MCR in the test mode. It includes a pin terminal that receives the test address TAD, a pin terminal that receives the write data TDin in the test mode, and a pin terminal that receives the output data TDout from the test interface circuit TIC in the test mode. The test write data TDin given to the test interface circuit TIC and the test data TDout output from the test interface circuit TIC are set to, for example, an 8-bit bit width, similar to that of the general-purpose DRAM. [0010] The test interface circuit TIC takes in the test control signal TCMD, the test address TAD, and the test write data TDin given to the pin terminal group TPG in synchronization with the test clock signal TCLK, and issues the test control signal to the DRAM core MCR. It stores information such as the latch / command decoder 1 that decodes to internal commands and expands the 8-bit wide test input data TDin to 256-bit write data, and the column latency of the DRAM core MCR. According to the mode register 2 and the CA shifter 3 that shifts the read data selection signal RD_S given from the latch / command decoder 1 according to the column latency information stored in the mode register 2, and the read data selection signal RD_S from the CA shifter 3. Includes a 256: 8 selection circuit 4 that selects 8-bit data from the 256-bit test read data TIFDout read from the DRAM core MCR. [0011] As this test peripheral circuit, a selector 5 that selectively couples the DRAM core MCR to one of the large-scale logic and the test interface circuit TIC in response to the test mode instruction signal TE and, for example, large-scale logic in the normal operation mode are given. The gate circuit 6 that receives the clock signal CLK and the test clock signal TCLK given in the test mode and gives the clock signal to the DRAM core MCR, and the 256-bit read from the DRAM core MCR when the test mode instruction signal TE is activated. A gate circuit 7 is provided to transmit the read data RD to the test interface circuit TIC. The 256-bit read data RD read from the DRAM core MCR is also given to large-scale logic without going through selector 5. This is to give the read data to the large-scale logic at high speed in the normal operation mode. [0012] The DRAM core MCR is a clock-synchronized DRAM (SDRAM), which takes in the data / signal given from the selector 5 in synchronization with the clock signal and outputs the read data RD. [0013] Next, the operation of the test interface circuit shown in FIG. 14 will be described with reference to the timing chart shown in FIG. [0014] As shown in FIG. 14, the DRAM core MCR transfers the write data INDin and the read data RD via separate buses. As for the test pin terminals, the test input data TDin and the test read data TDout at the time of the test are transferred via separate pin terminals. [0015] Now, decode the test control signal TCMD including the signals / RAS, / CAS and / WE, and set it to read data from the DRAM core MCR (give the read command READ to the DRAM core MCR). The test control signal TCMD given in clock cycle # 1 is decoded in latch / command decoder 1, and this decoding result is delayed by one clock cycle, and in clock cycle # 2, a selector is selected from the test interface circuit TIC as a read command READ. It is given to the DRAM core MCR via 5. Here, in the test mode, the selector 5 separates the large-scale logic from the DRAM core MCR according to the test mode instruction signal TE, and the test interface command TIFCMD, the test interface address TIFAD, and the test interface input output by the test interface circuit TIC output. Select the data TIFDin and transfer it to the DRAM core MCR. The gate circuit 7 transmits the data RD read from the DRAM core MCR according to the test mode instruction signal to the test interface circuit TIC. [0016] The DRAM core MCR takes in the signal / data according to the clock signal given from the gate circuit 6 (generated according to the test clock signal TCLK in the test mode). Now, the given internal command INCMD is the read command READ, and the internal data is read according to the internal address INADD given at that time. When the column latency CL of the DRAM core MCR is 2 clock cycles, effective read data is output at the rising edge of the clock signal TCLK in cycle # 4 according to the internal read command READ (INCMD) given in this cycle # 2. .. [0017] In the test interface circuit TIC, the CA shifter 3 combines the cycle period of the column latency CL according to the selection signal contained in the test address TAD (when the selection signal is generated from the test address TAD, the delay time in this test interface circuit TIC is also added. Include) Shift. Therefore, when the 256-bit read data RD from the DRAM core MCR reaches the selection circuit 4 via the gate circuit 7, the selection signal RD_S from the CA shifter 3 is also in a definite state. The selection circuit 4 selects 8-bit data from the 256-bit data according to the selection signal RD_S and transmits it to the pin terminals as test read data TDout (DO0). [0018] Now, in clock cycle # 2, a write command WRITE indicating data writing is given to the DRAM core MCR from the outside. When a write command is given, test write data TDin (DA) is also given to the test pin terminal at the same time. These write commands WRITE and test input data DA are also sequentially transferred according to the test clock signal TCLK in the test interface circuit TIC, and are given to the DRAM core MCR with a delay of one clock cycle. In the latch / command decoder 1, a bit width extension circuit is provided for the input data TDin, and the 8-bit test input data DA (TDin) is converted into 256-bit internal write data DAin (8). Bit data lines are extended to 256 bit data lines). [0019] From the outside, as a test control signal TCMD, a test control signal to be decoded is given to the read command READ that instructs data reading in clock cycle # 3, and then a write command WRITE that instructs data writing in the next clock cycle # 4 is sent. Gives the test control signal to be decoded. In this case, in clock cycle # 5, internal write data DBin is given to the DRAM core MCR, then in clock cycle # 6, 256-bit data Dout is read from the DRAM core MCR, and then in the test interface circuit TIC. The selection circuit 4 outputs 8-bit read data DO1 as test data TDou in clock cycle # 6. [0020] Data indicating the signal propagation delay (1 clock cycle in the example shown in FIG. 15) and the number of columns of column latency CL in the test interface circuit TIC is stored in this mode register 2, and the CA shifter 3 is stored in this mode register 2. By performing the shift operation for the set period, the data read from the DRAM core MCR can be selected at an accurate timing and the test data can be read. [0021] [0021] By providing the test interface circuit TIC as described above, an external tester can directly access the DRAM core MCR, and the necessary tests of the DRAM core MCR can be performed using a general-purpose SDRAM tester. [0022] [Problems to be Solved by the Invention] In the test interface circuit, the 256-bit read data of the DRAM core MCR data bus width is converted into 8-bit output data. This is realistic because when 256-bit data is directly given to an external memory tester, data processing becomes extremely difficult on the memory tester side, and the number of test data input / output pins also increases to 256.2 = 512. is not it. Therefore, in this test interface circuit, the 8-bit test input data TDin is internally expanded to 256-bit input data, and in the selection circuit, the 256-bit read data TIFDout is converted into 8-bit data TDout. [0023] In this way, although the number of pins required for testing is reduced, the large-scale logic LG in the DRAM embedded system LSI inputs and outputs many signals for the system interface with the outside of the chip. Large-scale logic LG requires a large number of external pin terminals. It is also necessary to assign external pin terminals for testing analog core APGs that include analog circuits such as PLLs and analog-to-digital converters. Therefore, it is conceivable that the number of external pin terminals assigned to the test interface circuit TIC for directly testing the DRAM core from the outside may not be sufficient. [0024] Regarding the test interface circuit TIC, for external addresses that require many external pin terminals, the test address pin terminals are shared by the low address and column address by time division multiplexing of the row address and column address. It is possible to reduce the number. For data pin terminals that require a total of 16 pin terminals, test data pins are provided by arranging bidirectional input / output circuits and using test data input pins and test data output pins as common pin terminals. The number of terminals can be reduced. Further, in this case, there is a secondary effect that the number of wires between the test data input / output pin terminal and the test interface circuit TIC can be reduced. However, when the DRAM core MCR and the test data are transferred via the test interface circuit TIC using such a bidirectional input / output circuit, the test input data and the test output data collide (as described below). Conflicts) cause the problem that DRAM core MCRs cannot be tested at actual operating speeds. This problem will be described in detail below. [0025] FIG. 16 is a diagram schematically showing the configuration of a bidirectional input / output circuit. In FIG. 16, a bidirectional input / output circuit 8 is provided between the test interface circuit TIC and the 8-bit test data terminal group 9. The bidirectional input / output circuit 8 is activated when the output enable signal OE is activated, and the tristate buffer circuit 8a that buffers the 8-bit data transmitted from the test interface circuit TIC and transmits the 8-bit data to the test data terminal group 9 Includes an input buffer circuit 8b that buffers the 8-bit test data TD that is activated when the output enable signal OE is deactivated and is given to the test data terminal group 9 and feeds it to the latch / command decoder 1. Next, the direct memory access test using the bidirectional input / output circuit 8 will be described with reference to the timing chart shown in FIG. [0026] In cycle # 0 of the test clock signal TCLK, the test control signal TCMD to be decoded by the read command READ is given in synchronization with the fall of the test clock signal TCLK. The test control signal TCMD to be decoded is given to the write command WRITE in the next cycle. Since the external tester requires one clock cycle period to switch the activation of the input circuit and the output circuit in the bidirectional input / output circuit 8, the output enable signal OE is lowered to the L level in the clock cycle # 0. (Inactivates). [0027] In the test interface circuit TIC, one clock cycle period is required for signal / data transfer. Therefore, at the fall of the test clock signal TCLK in clock cycle # 1, the internal command INCMD becomes the read command READ, and in the next clock cycle # 2, the internal command INCMD becomes the write command WRITE. At the falling edge of the test clock signal TCLK in clock cycle # 1, test input data Din is given as test data TD at the same time as the write command WRITE. [0028] The delay time of signal transfer in the column latency CL and the test interface circuit TIC by the test control signal TCMD decoded by the read command READ given from the outside in synchronization with the fall of the test clock signal TCLK in clock cycle # 0, that is, After 3 clock cycles have elapsed, test output data Dout is generated as test data TD from the test interface circuit TIC. Therefore, in order to extract the test output data to the outside after giving the test control signal TCMD to be decoded by the write command WRITE from the outside in the cycle # 1, the output enable signal OE sets the test clock signal TCLK of the clock cycle # 2. Synchronized with the descent, it is set to H level. Therefore, when the test output data Dout is output, the bidirectional input / output circuit 8 ensures that the output buffer circuit 8a operates stably and buffers and outputs the test output data Dout. [0029] It is not possible to give a test control signal to be decoded by the write command WRITE from the outside in synchronization with the fall of the test clock signal TCLK in clock cycle # 3. Clock cycle # 0<u style="single">To</u>This is because the data is read to the test data input / output terminal group according to the test control signal TCMD decoded by the read command READ given from the outside. [0030] Even in the next clock cycle # 4, the test control signal TCMD to be decoded by the write command WRITE cannot be given from the outside. The output enable signal OE is set to H level for reading the data Dout in clock cycles # 3 to # 4, and in this clock cycle # 4, the output enable signal OE responds to the fall of the test clock signal TCLK. Even if it is set to the L level, the switching of the input / output circuit is insufficient in this cycle # 4, and the data cannot be stably taken in and given to the test interface circuit TIC. [0031] In clock cycle # 5, clock cycle #<u style="single">2</u>Since the test data Dout is output according to the control signal decoded by the read command READ given from the outside in synchronization with the fall of the test clock signal TCLK, it is not possible to give the write command WRITE even in this cycle # 5. Can not. [0032] At this time, it is necessary to set the output enable signal OE to H level again, and if the output enable signal OE is set to L level in synchronization with the fall of the test clock signal TCLK in the next clock cycle # 6, this In cycle # 6, the input / output switching of the bidirectional input / output circuit 8 is insufficient, and the write command WRITE cannot be given. Therefore, in clock cycles # 3 to # 6, it is necessary to give the no-operation command NOP. [0033] When a test control signal to be decoded is given to the write command WRITE in synchronization with the fall of the test clock signal TCLK of clock cycle # 7, the output enable signal OE falls to the L level one clock cycle before, and both The input buffer circuit 8b of the input / output circuit 8 operates stably, and this test input data Din can be taken in. [0034] When a test control signal to be decoded is given to the write command WRITE, it is necessary to give test input data Din to the test interface circuit TIC at the same time, so one clock cycle period required for input / output switching in the bidirectional I / O circuit 8 In consideration of the signal propagation delay of this bidirectional I / O circuit 8, set the output enable signal OE to L level in the cycle one clock cycle or more before the write command is applied, and set the bidirectional I / O circuit 8 Must be set to input mode. Therefore, in the timing chart shown in FIG. 17, the output enable signal OE is set to the L level in the cycle one clock cycle before the application of the write command WRITE. However, depending on the frequency of this test clock signal TCLK, it may be necessary to set the output enable signal OE to the data input instruction state two to three clock cycles before. [0035] When only the read command or the write command is continuously given to the DRAM core, the problem of the signal confirmation timing of this output enable signal OE does not occur. The output enable signal OE is fixed at H level or L level, and read or write commands are continuously applied. However, as shown in FIG. 17, when the read command READ and the write command WRITE are given alternately, it corresponds to at least the number of clock cycles required for the output enable signal OE to be determined to the L level before applying the write command WRITE. You need to keep entering as many command NOPs (no operations) as you want. In addition, there is a restriction that it is necessary to avoid collision between the test input data and the test output data. In the case shown in FIG. 17, command NOPs are inserted over 4 clock cycles, and as the test clock signal TCLK becomes higher, the number of command NOPs inserted further increases. [0036] Therefore, if the test data output terminal and the test data input terminal are shared in order to reduce the number of test pin terminals, it is not possible to perform tests such as read-write-read-write according to the page mode. However, there is a problem that it is virtually impossible to test the DRAM core at the actual speed. [0037] Therefore, an object of the present invention is to provide a test interface circuit capable of testing a logic embedded memory without increasing the number of test pin terminals and without being restricted by a test pattern. [0038] Another object of the present invention is to provide a semiconductor integrated circuit device that can sufficiently perform a test of this DRAM in a semiconductor integrated circuit device including a logic-embedded DRAM without being restricted by a test pattern from the outside. is there. [0039] Another object of the present invention is to perform a test from the outside of a logic integrated DRAM without being restricted by a test pattern even if the test data output terminal and the test data input terminal are shared. It is an object of the present invention to provide a test interface circuit capable of the present invention and a semiconductor integrated circuit device including the same. [0046] [Means for solving problems] The semiconductor integrated circuit device according to claim 1 includes logic, a memory for storing data for this logic, and the like.<u style="single">A bidirectional I / O circuit that is coupled to a common test data pad and transfers data to and from the test data pad in both directions.</u>It is equipped with a test interface circuit to make the memory directly accessible from the outside in the test operation mode. This test interface circuit is a first-in / first-out circuit that sequentially stores the data read from the memory, reads the stored data in the same order as the sequential storage order, and gives the read data to the bidirectional input / output circuit, and an input. It is equipped with a control circuit for controlling the writing / reading of data in the first-in / first-out circuit and controlling the data transfer from the bidirectional input / output circuit to the memory in response to the operation mode instruction signal indicating / reading. .. This control circuit counts the number of data read instructions to the memory when the operation mode instruction signal indicates the data input mode, and writes the number of data corresponding to the count value to the first-in / first-out circuit.<u style="single">And from the first-in / first-out circuit</u>Control the operation of the first-in / first-out circuit to read. [0047] Claim<u style="single">2</u>The semiconductor integrated circuit device according to claim<u style="single">1</u>In this device, the memory has a plurality of memory cells arranged in a matrix, and at one row access, one page memory cell of size M bit is selected, and the bit width of the input / output data is m. This first-in / first-out circuit includes an M / m stage register circuit. [0048] Claim<u style="single">3</u>The semiconductor integrated circuit device according to claim<u style="single">1</u>In this device, the memory contains N banks that are driven into active states independently of each other. Each bank has a plurality of memory cells arranged in a matrix, one page of memory cells of size M bits is selected by one row access, and the memory outputs data having a bit width of m. The first-in / first-out circuit includes an N / M / m stage register circuit. [0049] Claim<u style="single">4</u>The semiconductor integrated circuit device according to claim<u style="single">1</u>In the device, the control circuit counts the number of data read from the memory in response to the data read instruction to the memory when the operation mode instruction signal indicates the data input mode, and first-in-first according to the count value. The first counter that generates a write pointer indicating the position of data writing to the out circuit, and the first counter in response to the change from the data input mode instruction to the data output mode instruction of the operation mode instruction signal. It includes a second counter that generates a read pointer that indicates the position to read data from the first-in / first-out circuit according to the count value. The read pointer and write pointer initially indicate the same position. [0050] Claim<u style="single">5</u>The semiconductor integrated circuit device according to claim<u style="single">1</u>Outfit<u style="single">Place</u>In the bidirectional input / output circuit, the data transfer path is determined in response to the operation mode instruction signal. [0051] Claim<u style="single">6</u>The semiconductor integrated circuit device according to claim<u style="single">4</u>In the device of<u style="single">Te</u>The test data is input and output in synchronization with the strike clock signal, and the second counter counts in response to the rise and fall of the test clock signal to generate a read pointer. [0052] Claim<u style="single">7</u>The semiconductor integrated circuit device according to claim<u style="single">1</u>The device further comprises a selector for connecting the memory to the test interface circuit and separating the logic from the memory in response to the test mode instruction signal.<u style="single">The semiconductor integrated circuit device according to claim 8 further includes a write data bus and a read data bus that are separately provided for the memory. The write data bus transfers the write data from the test interface circuit and logic to the memory, and the read data bus transfers the data read from the memory to at least the first-in / first-out circuit.</u>[0053] The data read from the embedded memory is stored in the first-in / first-out circuit according to the read command, and the data output latency from the test interface circuit can be changed by adjusting the read timing. Therefore, even if the test data input / output pins are shared, a continuous write / read operation test can be performed without causing data collision. [0054] BEST MODE FOR CARRYING OUT THE INVENTION [Embodiment 1] FIG. 1 is a diagram schematically showing a configuration of a test interface circuit according to the first embodiment of the present invention. In the configuration shown in FIG. 1, the test interface circuit TIC is coupled to the test data input / output terminal 9 via the bidirectional input / output circuit 8. The bidirectional input / output circuit 8 includes an output buffer circuit 8a and an input buffer circuit 8b, and its data transfer direction is determined by the output enable signal OE. [0055] The test interface circuit TIC takes in the test control signal TCMD and the test address TAD given via the test pin terminal group TPG according to the test clock signal TCLK, decodes the test control signal TCMD, and is from the bidirectional input / output circuit 8. According to the latch / command decoder 1 that captures the test input data according to the test clock signal TCLK and expands the bit width, the mode register 2 that stores the column latency information of the DRAM core MCR, and the column latency information stored in the mode register 2. , Signal transfer delay and column latency period in this test interface circuit TIC It is given via the CA shifter 3 which shifts the read selection signal given by the latch / command decoder 1 according to the test clock signal TCLK, and the CA shifter 3 and the gate circuit 7. Includes a 256: 8 selection circuit 4 that selects 8-bit data according to the read selection signal RD_S from the 256-bit read data TIFDout from the DRAM core MCR. These components are the same as the configuration of the test interface circuit TIC shown in FIG. 14 above. [0056] The test interface circuit TIC also includes a first-in first-out (FIFO) circuit 10 that sequentially stores 8-bit data from the 256: 8 selection circuit 4 and outputs the stored data in that storage order, and an output enable signal OE. It includes a FIFO control circuit 15 that controls a data write / read operation of the first-in / first-out circuit 10 according to a read instruction signal (read command) from the latch / command decoder 1. [0057] The FIFO control circuit 15 counts the read instruction signal from the latch / command decoder 1 when the output enable signal OE indicates the data input mode (at the L level), and the test should be stored in the first-in / first-out circuit 10. The number of read data is counted to control the data writing operation to the first-in / first-out circuit 10. Further, when the output enable signal OE changes from the input mode instruction state (L level) to the output mode instruction state (H level), the FIFO control circuit 15 sequentially reads the stored data according to the test clock signal TCLK and bidirectionally. It is given to the output buffer circuit 8a included in the input / output circuit 8. [0058] [0058] Therefore, in the data input mode of the bidirectional input / output circuit 8, the first-in / first-out circuit 10 performs only the data storage operation and does not perform the data read operation. When this data input mode is completed and there is no test input data at the test data input / output terminal 9, data is read from the first-in / first-out circuit 10 and the test data is input / output via the output buffer circuit 8a. Read the test data to terminal 9. Therefore, even when the write command and the read command are given alternately, the test data is sequentially read from the first-in / first-out circuit 10 after the application of the test control signal decoded by the write command is completed, so that the data conflicts. Does not occur. [0059] By adaptively changing the latency of the test data output by the first-in / first-out circuit 10, even if the read command and the write command are continuously applied, the test input data and the test output data are connected to the test data input / output terminal. The read / write continuous operation test can be performed during the direct memory access test of the DRAM core using the common input / output pin terminals. Next, the operation of the test interface circuit according to the first embodiment of the present invention will be described with reference to the timing chart shown in FIG. [0060] When performing a read / write continuous operation test, first, the test control signal TCMD to be decoded is given to the active command ACT, and the memory cell of page 1 is selected in the DRAM core MCR. Here, page 1 shows a memory cell row that is driven to the selected state by being given this active command ACT and instructing low access to the DRAM core MCR, performing a row selection operation in the DRAM core MCR. [0061] After giving the test control signal corresponding to this active command ACT, the output enable signal OE is then set to L level and the bidirectional I / O circuit 8 is set to data input mode. In FIG. 2, the test control signal TCMD decoded by the read command READ is externally given to the falling edge of the test clock signal TCLK in cycle # 0 of the test clock signal TCLK, and the control decoded by this read command READ is given. The output enable signal OE is lowered from H level to L level in parallel with the application of the signal. [0062] The bidirectional input / output circuit 8 requires a clock cycle period for switching between its input and output, and also considers the delay time when the write data is given to the latch / command decoder 1 via the bidirectional input / output circuit 8. Then you need to give the write command WRITE and the test input data Din. In FIG. 2, it is considered that the signal propagation delay in the bidirectional input / output circuit 8 can be ignored. [0063] The output enable signal OE is lowered to the L level in response to the fall of the test clock signal TCLK in cycle # 0, and is decoded by the write command WRITE at the fall of the test clock signal TCLK in the next cycle # 1. Even if the test input data Din is given at the same time as the test control signal, the input buffer circuit 8b of this bidirectional input / output circuit 8 is already set to the operating state, and the test data input / output terminal group 9 is surely set. The given 8-bit test input data Din is buffered and given to latch / command decoder 1. [0064] Next, a control signal that becomes a read command READ and a write command WRITE is given from the outside in synchronization with the fall of the test clock signal TCLK of each of cycle # 2 and cycle # 3. These test control signals TCMD are input to the DRAM core MCR with a delay of one cycle as an internal command INCMD via the test interface circuit TIC and selector 5. The DRAM core MCR writes / reads data according to this given internal command INCMD. [0065] When the read command READ is given, the DRAM core MCR outputs valid data Dout after the column latency CL has elapsed. In FIG. 2, the operation when the column latency CL is 2 is shown as an example. The DRAM core MCR has a separate bus for transmitting the internal write data INDin and a bus for transmitting the read data RD, and therefore, considering the column latency CL of the DRAM core MCR, on these buses. It is not necessary to consider the collision between the write data and the read data. However, it is necessary to consider when the internal data transfer path in the DRAM core MCR is a common IO data line and the internal write data and the internal read data are transmitted via the common IO data bus. However, in a mixed DRAM, a write data bus and a read data bus are usually provided separately as internal data buses, and in particular, it is necessary to consider the collision between the write data and the read data of the internal data bus. Absent. [0066] The 256-bit read data RD read from the DRAM core MCR is given to the selection circuit 4 of the test interface circuit TIC via the gate circuit 7. The selection circuit 4 takes into account the delay time of one cycle in the test interface circuit TIC and the column latency CL in the DRAM core MCR, and 8 from this 256-bit read data TIFDout according to the read selection signal RD_S timed by the CA shifter 3. Bit data is selected and given to the first-in / first-out circuit 10. The FIFO control circuit 15 counts the number of read command READs given from the outside when the output enable signal OE is L level according to the read operation instruction signal from the latch / command decoder 1, and first-in-first according to the count value. A write pointer is generated for the out circuit 10, and the 8-bit data Dout given by the selection circuit 4 is stored in the first-in / first-out circuit 10. [0067] In clock cycle # 3, the data Dout read from the DRAM core MCR is temporarily stored in the first-in / first-out circuit 10, so that the input / output pins are combined with the test control signal TCMD, which is a write command WRITE from the outside in this cycle. Even if the test input data Din is given to the terminal group 9, the data read from the DRAM core MCR does not collide with the test input data. [0068] When the continuous test operation is completed in the clock cycle # 4, the output enable signal OE is then raised to the H level, the bidirectional I / O circuit 8 is set to the data output mode, that is, the output buffer circuit 8a is activated. Set. Further, when the output enable signal OE rises from the L level to the H level, the FIFO control circuit 15 sequentially reads the stored data from the first-in / first-out circuit 10 after one clock cycle elapses, and outputs the buffer circuit 8a. Give to. Here, it is bidirectional input that the data is read from the first-in / first-out circuit 10 after one clock cycle period has elapsed since the output enable signal OE rises from the L level to the H level and is set to the data output mode. This is because one clock cycle is required for input / output switching in the output circuit 8. [0069] The FIFO control circuit 15 changes the read pointer of the first-in / first-out circuit 10 by the number of read commands input when the output enable signal OE is L level, and sequentially outputs the data stored at that time. .. Therefore, as shown in FIG. 2, from the falling edge of the test clock TCLK in clock cycle # 5, the read command given from the outside synchronizes with the falling edge of the test clock signal TCLK in cycles # 0 and # 2. The read data is output for each clock cycle. [0070] By using this first-in / first-out circuit as a so-called buffer circuit and changing the latency when reading data from the DRAM core MCR, the data input terminal and data output terminal are shared and read / write operations are continuously performed. Even if it is done, data collision does not occur and the test operation can be performed accurately. [0071] FIG. 3 is a diagram schematically showing the configuration of the latch / command decoder 1 shown in FIG. In FIG. 3, the latch / command decoder 1 has a latch circuit 20 that latches the test input data TDin, the test control signal TCMD, and the test address TAD in response to the test clock signal TCLK, and an 8-bit test input from the latch circuit 20. A bit width expansion circuit 21 that converts data into 256-bit test input data, a command decoder 22 that decodes the test control signal given by the latch circuit 20, and 256-bit test input data and commands from the bit width expansion circuit 21. The test command from the decoder 22 and the test address from the latch circuit 20 are latched in response to the test clock signal TCLK to generate the test input data TIFDin, the test command TIFCMD, and the test address TIFAD, and the selector 5 shown in FIG. Includes a latch circuit 23 to give to. [0072] The latch circuit 20 captures the signal / data given when the test clock signal TCLK is at the L level, and outputs and latches the captured signal when the test clock signal TCLK is at the H level. The latch circuit 23 captures the signal / data given when the test clock signal TCLK is at the H level, and outputs and latches the captured signal when the test clock signal TCLK is at the L level. Even if the signal / data processing timing of the bit width extension circuit 21 and the command decoder 22 is asynchronous with the test clock signal TCLK, the latch circuits 20 and 23 ensure that the test input data TDin, test control signal TCMD, and test address TAD. Is output from the latch circuit 23 as input data TIFDin, test command TIFCMD, and test address TIFAD after one clock cycle period has elapsed. [0073] The command decoder 22 receives the test control signal TCMD and the specified bits of the test address, and according to the specified operating mode, internal commands such as mode register set command MRS, no operation command NOP, active command ACT, precharge command PRE, read. Generate command READ, write command WRITE, etc. The command decoder 22 also generates a read instruction signal φr when a read command READ is given, and a reset signal φrst when a test completion command is given. Further, among the test address TAD output from the latch circuit 20, the upper 5 bits of the column address are given to the CA shifter 3 as a read selection signal RD-SF. The 5-bit selection signal RD-SF is used because it is necessary to perform 32: 1 selection in order to select 8-bit data from 256-bit data. By giving the 5-bit read selection signal RD_SF to the CA shifter 3, the circuit configuration is simplified as compared with the configuration in which the 32-bit read selection signal is shifted. Therefore, the 256: 8 selection circuit 4 has a function of decoding this read selection signal RD_S. [0074] The bit width expansion circuit 21 is composed of wiring, and the 8-bit data is expanded to 256-bit data by the wiring connection. At the time of this data expansion, 32 8-bit data may be duplicated as they are, or bits of the same digit may be created as 8-bit data. The selection mode of the selection circuit 4 is determined according to the bit width expansion mode. [0075] FIG. 4 is a diagram schematically showing the configuration of a first-in first-out circuit (FIFO) 10. FIG. 4 also schematically shows the array configuration of the DRAM core MCR. [0076] In the DRAM core MCR, memory cells are arranged in a matrix in the memory array MA. At low access, that is, when the active command ACT is given, one page is selected according to the internal address INAD given at the same time. Here one page, the inner represent memory cell row selected by the unit address INAD. One page has an M-bit memory cell. [0077] From this 1-page M-bit memory cell, m-bit data is read by column access (read command or write command). Therefore, in the present embodiment, when the M bit on one page is, for example, 2K bits, a 256-bit memory cell is selected from the 2K bits and data is written or read to the selected memory cell. In the case of read data RD, further 8 bits of data are selected from the m-bit read data RD by the read selection signal RD_S in the selection circuit 4. The data selected by this selection circuit is sequentially stored in the first-in first-out circuit (FIFO) 10. [0078] In the first-in / first-out circuit, a register circuit REG # 0-REG # k is provided. Where k = (M / m) -1. That is, when accessing each DRAM core MCR, column access is continuously performed in the page mode. In page mode, the maximum number of data RDs read is when full page access is performed, that is, M / m data can be read in page mode. Therefore, for example, when the read data RD is 256 bits, if the size of one page is 2 K bits, 2K / 256 = 8, and an 8-stage register circuit of register circuits REG # 0-REG # 7 is provided. As a result, all the maximum number of data at the time of continuous access can be stored in the first-in / first-out circuit 10. After accessing the full page, it is necessary to temporarily return the memory array MA to the precharge state for page switching, during which column access cannot be executed, and during this time, from the first-in / first-out circuit 10 Data can be read. Therefore, the first-in / first-out circuit 10 only needs to have a capacity for storing read data when accessing a full page in this page mode at a minimum. [0079] FIG. 5 is a diagram schematically showing the configuration of the FIFO control circuit 15 shown in FIG. In FIG. 5, the FIFO control circuit 15 includes a gate circuit 15a that receives a read instruction signal φr and an output enable signal OE, and a first counter 15b that counts the rise of the output signal of the gate circuit 15a and generates a write pointer WPF. It includes a write control circuit 15c that generates a write pointer WP for the first-in / first-out circuit and a write instruction signal φWE according to the output signal of the gate circuit 15a and the write pointer WPF output by the first counter 15b. This write control circuit 15c performs a shift operation for the same period as the CA shifter, and adjusts the timing so that the data is written to the first-in / first-out circuit 10 when the data read from the DRAM core MCR arrives. .. Therefore, the write control circuit 15c delays the given signal for a delay period (half a clock cycle due to the presence of the latch circuit) in the column latency CL and the test interface circuit TIC. [0080] [0080] The FIFO control circuit 15 further responds to the output signals of the one-shot pulse generation circuit 15d that generates a one-shot pulse having a pulse width for a predetermined period in response to the rise of the output enable signal OE and the one-shot pulse generation circuit 15d. Responds to the set / reset flip-flop 15e, the AND circuit 15f that receives the output signal from the output Q from the set / reset flip-flop 15e, and the test clock signal TCLK, and the output signal fall of the AND circuit 15f. The second counter 15g that generates the read pointer RPF by performing the counting operation, the read pointer RPF output by the second counter 15g, and the signal from the output Q of the set / reset flip-flop 15e are received and first-in. -Includes a read control circuit 15h that generates a read pointer RP for the first-out circuit and a read instruction signal φRE. This read control circuit 15h reads data to the first-in / first-out circuit after one clock cycle period elapses after the output enable signal OE rises to the H level (clock cycle period required for I / O switching). To do. [0081] The FIFO control circuit 15 further compares the write pointer WPF from the first counter 15b with the read pointer RPF from the second counter 15g, and sets / resets the flip-flop 15e when they match. Including 15i. The count values of the first counter 15b and the second counter 15g are set to the initial values (pointers that specify the register circuit REG # k) according to the reset signal φrst. [0082] Next, the operation of the FIFO control circuit 15 shown in FIG. 5 will be described with reference to FIG. [0083] The test control signal TCMD is given in synchronization with the fall of the test clock signal TCLK in clock cycle # 0. In the latch / command decoder 5, as shown in FIG. 3, a latch circuit 20 is provided in the first stage, and the internal signal changes with a delay of half a clock cycle. Therefore, in this clock cycle # 1, the read instruction signal φr from the command decoder 22 shown in FIG. 3 becomes H level in synchronization with the rise of the test clock signal TCLK, and the FIFO is given a command to instruct data read. Notify control circuit 15. This read instruction signal φr becomes H level for one clock cycle period T. When this read instruction signal φr becomes H level, the output enable signal OE becomes L level, the output signal of the gate circuit 15a becomes H level, and the first counter 15b raises the output signal of this gate circuit 15a. The count operation is performed in synchronization with, and the count value is incremented by 1. Since the write control circuit 15c delays the signal propagation in the column latency CL and the test interface circuit TIC, that is, the half clock cycle period by the latch circuit 23 shown in FIG. 3, when the column latency CL is 2, 2.5 clock cycles and a read instruction are given. The signal φr is delayed to generate a write instruction signal φWE and give it to the first-in / first-out circuit. [0084] Also, in clock cycle # 2, again<u style="single">Outside</u>When the control signal to be decoded is given to the read command from the unit, the read instruction signal φr becomes H level again in synchronization with the rise of the test clock signal TCLK in clock cycle # 3, and the first counter 15b sets this read instruction. A count operation is performed in response to the rise of the signal φr, and the count value is incremented by one. The count value output by the first counter 15b, that is, the write pointer WPF, is given to the first-in / first-out circuit as a write pointer WP with a delay of 2.5 clock cycles by the write control circuit 15c. [0085] The data Dout read from the DRAM core MCR in clock cycle # 3 is given to the first-in / first-out circuit according to this read command. At this time, the write instruction signal φWE is in the H level active state, and the first-in / first-out circuit writes data according to the write pointer WP at that time. [0086] Further, the data read in the clock cycle # 5 is sent to the corresponding register circuit of the first-in / first-out circuit according to the write instruction signal φWE activated at this time and the write pointer WP (WP = 2) at that time. Written. [0087] On the other hand, when the read / write continuous operation test is completed and the output enable signal OE rises from the L level to the H level, the one-shot pulse generation circuit 15d generates a one-shot pulse, and the set / reset flip-flop 15e responds accordingly. Is set, and the output signal becomes H level. The control signal of the AND circuit 15f changes accordingly according to the test clock signal TCLK. The second counter, 15g, performs a counting operation in synchronization with the rise of the test clock signal TCLK. Therefore, the flip-flop 15 is set in response to the falling edge of the test clock signal TCLK of the clock cycle # 4, and the AND circuit 15f passes the test clock signal TCLK. Therefore, the second counter 15g has this clock cycle. The count operation is performed in synchronization with the rise of the test clock signal TCLK in # 5 and clock cycle # 6, and the count value (read pointer) RPF is updated. [0088] The read control circuit 15h delays the output count value of the second counter 15g by 0.5 clock cycle (0.5T) to generate a read pointer RP. The read pointer RP changes in synchronization with the fall of the test clock signal TCLK from the next cycle when the output enable signal OE reaches the H level. The read control circuit 15h delays the output signal from the output Q of the flip-flop 15 by one clock cycle period (1T), so that the read instruction signal φRE from the read control circuit 15h is a test clock signal from clock cycle # 5. It rises to H level in synchronization with the fall of TCLK. Therefore, after one clock cycle period (1T) has elapsed after the output enable signal OE rises to the H level and the output buffer of the bidirectional I / O circuit becomes stable, the read instruction signal φRE from the first-in / first-out circuit. Data is read according to the read pointer RP, and data Dout is given to the input / output pin terminal group 9 via the bidirectional input / output circuit. [0089] As a result, data can be read from the first-in / first-out circuit at an accurate timing in consideration of the delay of the read data in the DRAM core MCR, that is, the signal propagation delay in the column latency CL and the test interface circuit TIC. [0090] When the read read pointer RPF from the second counter 15g becomes the same value (= 2) as the write pointer WPF from the first counter 15b, the output signal of the comparator 15i is activated and the set / reset flip-flop 15e Is reset. Therefore, when the count value of the second counter 15g, that is, the read pointer RPF becomes equal to the value of the write pointer WPF output by the first counter 15b in the clock cycle # 6, the clock signal TCLK is set in the clock cycle # 6. In synchronization with the decline, the flip-flop 15 is reset and its output signal drops to the L level. Accordingly, the read instruction signal φRE from the read control circuit 15h is also reset after the lapse of one clock cycle period. Therefore, even if a read command is given when the output enable signal OE is at L level, continuous read / write operations can be performed accurately. No collision occurs in the data input / output pin terminal group 9. [0091] The configuration for resetting the flip-flop 15e in synchronization with the falling edge of the test clock signal TCLK is realized by providing the comparator 15i with a configuration in which the output signal is output when the test clock signal TCLK is at the L level. Will be done. For example, a latch circuit that operates in synchronization with the test clock signal TCLK may be provided in the output stage of the comparator 15i, and the inversion signal of the test clock signal TCLK may be displayed on the output stage of the comparator 15i as pointers WPF and RPF. A gate circuit that receives a signal indicating the comparison result of the above may be provided. [0092] The read operation instruction signal φr from the command decoder 22 is maintained in the active state for one clock cycle period T. However, this read operation instruction signal φr may be generated in the form of a one-shot pulse having a predetermined time width. [0093] Further, the write control circuit 15c and the read control circuit 15h are realized by using a well-known latch circuit that transfers a signal according to the test clock signal TCLK. For example, by using the latch circuit 20 as shown in FIG. 3, a delay of half a clock cycle can be realized. [0094] Further, when a latch circuit is provided at the output of the first-in / first-out circuit and the data read from the first-in / first-out circuit is delayed by half a clock cycle and given to the bidirectional input / output circuit, this second The read pointer RPF from the counter 15g of the above may be given to the first-in / first-out circuit. In this case, the read instruction signal φRE is composed of a delay circuit that delays the output signal of the flip-flop 15 by half a clock cycle. Further, the first and second counters 15b and 15g may be configured to count at the falling edge of the clock signal. The count value before counting can be used as a pointer. [0095] FIG. 7 is a diagram schematically showing the configuration of the first-in / first-out circuit 10 shown in FIG. In FIG. 7, the first-in / first-out circuit 10 has an input buffer 10a that receives 8-bit data DIN from the gate circuit 7 shown in FIG. 1, a register file 10b having a k + 1-stage register circuit, and a register file. Data buffer from the selected register circuit of 10b Output buffer 10c that generates output data DOUT, and data of the register circuit specified by the read pointer RP of this register file 10b according to the read instruction signal φRE and read pointer RP. 8-bit data from the input buffer 10a is written to the read control circuit 10d that controls to read the data, and the register circuit output by the write pointer WP of the register file 10b according to the write instruction signal φWE and the write pointer RP. Includes a write control circuit 10e for control. [0096] The internal configuration of the read control circuit 10d and the write control circuit 10e is appropriately determined according to the configuration of the register file 10b. When the register file 10b is composed of, for example, SRAM having word lines and bit lines, these write control circuits 10e and read control circuits 10d include an address decoding circuit and a word line selection circuit, respectively. No bit line pair selection is made. Only an 8-bit bit line pair is provided. [0097] FIG. 8 is a diagram showing a modified example of the first-in / first-out circuit 10. Figure<u style="single">8</u>In, a write selection gate WSG0-WSGk and a read selection gate RSG0-RSGk are provided corresponding to each of the register circuits REG # 0-REG # k. The register circuit REG # 0-REG # k is coupled to the write data input line WL via the write selection gate WSG0-WSGk and to the read data line RL via the read selection gate RSG0-RSGk. The write data line WL and the read data line RL are 8-bit signal lines, respectively. [0098] A read selection control gate RSCi that receives a read instruction signal φRE and a register selection signal RPi (i = 0-k) is provided corresponding to the read selection gate RSG0-RSGk. Further, a write selection control gate WSCi that receives a write instruction signal φWE and a write register selection signal WPi is provided corresponding to the write selection gate WSGi (i = 0-k). The read selection control signal RP0-RPk may be each bit of the second counter 15g shown in FIG. 5 or the read pointer RP from the read control circuit 15h, and this read pointer RP is decoded by a decoding circuit (not shown). May be generated. Further, the write selection signal WP0-WPk may also be each bit of the first counter 15b or the write control circuit 15c count value shown in FIG. 5, and the write pointer WP is decoded by a decoding circuit (not shown). May be generated. When the output count bits of the first counter 15b and the second counter 15g shown in FIG. 5 are used as the read selection signal RP0-RPk and the write selection signal WP0-WPk, the first counter 15b and the second counter 15b The counter 15g is composed of a shift register, and the bit position in the active state is shifted according to each count value. In this case, the shift register is composed of a ring-shaped shift register. [0099] In the case of the first-in / first-out circuit configuration shown in FIG. 8, the register circuits REG # 0-REG # k are selected by the write selection gate WSG0-WSGk or the read selection gate RSG0-RSGk, respectively, and the write data line WL And it is only connected to the read data line RL, which simplifies the circuit configuration. [0100] As described above, according to the first embodiment of the present invention, when the output enable signal OE is at the L level and indicates the data input mode, the number of read commands applied in this input mode is counted and the count is counted. The data of the first-in / first-out circuit is input and output according to the value, the latency of the data read from the DRAM core can be changed, and even if the common test data input / output pin terminal is used accordingly, There is no collision between the test input data and the test output data, and continuous read / write operation tests can be performed. [0101] [Embodiment 2] FIG. 9 is a diagram schematically showing the configuration of a test interface circuit according to the second embodiment of the present invention. In FIG. 9, the first-in / first-out circuit 10 is provided with a switch circuit 30 that bypasses the register circuits REG # 0-REG # k when conducting. In order to indicate the continuity / non-conduction of the switch circuit 30, in the FIFO control circuit 15, the AND circuit 15s that receives the output enable signal OE and the read operation instruction signal φr, and the output signal of the AND circuit 15s are column latency CL. A delay circuit (15t) that is delayed for the sum of 0.5 clock cycles (CL + 0.5) is provided. This (CL + 0.5) delay circuit 15t transfers the output signal of the AND circuit 15s according to the test clock signal TCLK to give a delay equal to the column latency CL + 0.5 clock cycle of the test clock signal TCLK. This (CL + 0.5) delay circuit 15t generates a complementary output signal to control the continuity / non-conduction of the switch circuit 30. [0102] FIG. 10 is a timing chart showing the operation of the test interface circuit shown in FIG. With the output enable signal OE set to H level, the control signal decoded by the read command READ is continuously given from the outside. When this read command READ is given, the read operation instruction signal φr is driven from the command decoder 22 shown in FIG. 3 to the active state of the H level for a predetermined time. Here, the read operation instruction signal φr is generated in the form of a one-shot pulse. This is to perform a continuous read operation. [0103] When this read operation instruction signal φr is activated, the output signal of the AND circuit 15s becomes an H level active state, and the signal in this active state is transmitted according to the column latency CL + 0.5 clock cycle period test clock signal TCLK. Therefore, according to the read operation instruction signal φr activated in response to the rise of this test clock signal TCLK, the bypass control signal SH from the (CL + 0.5) delay circuit 15t becomes H level after 2.5 clock cycles, and the switch. Circuit 30 conducts. Therefore, the read data given from the gate circuit 7 is given to the bidirectional input / output circuit 8 via the switch circuit 30 by bypassing the register circuits REG # 0-REG # k. Thereby, the continuous read mode can be realized. [0104] Here, in the first embodiment, only the read / write continuous operation is a problem. However, in the write / read operation as well, the write control circuit 15c and the read control circuit 15h can read data from the first-in / first-out circuit at an accurate timing. [0105] As described above, according to the second embodiment of the present invention, when the read command is given when the output enable signal OE is H level, the register circuit of the first-in / first-out circuit is bypassed. Therefore, the continuous read operation test can be surely performed. As a result, even if the first-in / first-out circuit is provided, the test items are not limited. [0106] [Embodiment 3] FIG. 11A is a diagram schematically showing the configuration of a test interface circuit according to the third embodiment of the present invention. FIG. 11A shows the configuration of the FIFO control circuit 15. In the FIFO control circuit 15 shown in FIG. 11 (A), in addition to the configuration shown in FIG. 5, the frequency divider 15 that further divides the test clock signal TCLK by two.<u style="single">j</u>Is provided. Divider 15<u style="single">j</u>The frequency dividing signal BCLK from is given to the AND circuit 15f that receives the output signal of the set / reset flip-flop 15e. The read control circuit 15h is given the test clock signal TCLK. The second counter 15g executes a counting operation in response to the rise of the output signal of the AND circuit 15f. Next, the operation of the FIFO control circuit shown in FIG. 11 (B) will be described with reference to the timing chart diagram shown in FIG. 11 (B). [0107] When the output enable signal OE rises to the H level, the set / reset flip-flop 15e is set, and accordingly, the read control circuit 15h sends the read instruction signal φRE after one clock cycle (T) of the test clock signal TCLK has elapsed. It is driven to the active H level. The second counter 15g executes the counting operation according to the AND circuit 15f. In this case, the rise of the divided clock signal BCLK at the rise of the output enable signal OE is not counted because of the possibility of racing. The second counter 15e performs a counting operation in response to the rising edge of the divided clock signal BCLK from the AND circuit 15f in the next clock cycle, and sequentially updates the count value in synchronization with the rising edge of the divided clock signal BCLK. .. [0108] The output count value RPF of the second counter 15g is transmitted via the read control circuit 15h after a half clock cycle (T / 2) of the test clock signal TCLK has elapsed. Therefore, in the first-in / first-out circuit, when the read instruction signal φRE is in the active state, the read pointer RP is given in synchronization with the frequency division clock signal BCLK, and the stored data is sequentially read out to the data. It is given to the bidirectional input / output circuit as Dout. [0109] The writing of data to the first-in / first-out circuit is performed under the control of the first counter 15b and the write control circuit 15c, and therefore, in synchronization with the test clock signal TCLK, the DRAM core MCR. The data is written to the first-in / first-out circuit according to the reading speed of the data read from. By using the frequency-divided clock signal BCLK, stored data is read from the test interface circuit TIC at twice the speed of the test clock signal TCLK. Therefore, the time required for reading data during the test can be shortened, and the test cycle can be shortened. [0110] [Embodiment 4] FIG. 12 is a diagram showing a configuration of a main part of a mixed-load DRAM according to the fourth embodiment of the present invention. In FIG. 12, the DRAM core MCR contains N banks B # 1-B # N. Banks B # 1-B # N have the same configuration, and the size of one page is M bits. Banks B # 1-B # N can each be driven into an active state independently of each other, and each can hold a page in a selected state. The m-bit data read from the banks B # 1-B # N is converted into 8-bit data via the selection circuit 7 and given to the first-in / first-out circuit 10. In the first-in / first-out circuit 10, register circuits REG # 1-REG # P are provided. Here, P = N · M / m. [0111] When data is read from banks B # 1-B # N of the DRAM core MCR by page mode access, data of maximum N · M / m can be read continuously. The m-bit (256-bit) data read from the DRAM core MCR is converted into 8-bit data by the selection circuit 7. Therefore, it is necessary to store the maximum N · M / m data in the first-in / first-out circuit. By providing the register circuit REG # 1-REG # P, when the number of banks is N, the data read continuously when all the banks are accessed according to the page mode is stored in the first-in / first-out circuit 10. be able to. [0112] In the register circuit REG # 1-REG # P, the data of banks B # 1-B # N are stored in the order read from the DRAM core. It is not necessary to monitor which bank of data is stored in which register circuit. Since the correspondence between the data and the bank is determined by the test program, the tester can know the correspondence between the data and the bank. Therefore, in the first-in / first-out circuit 10, the register circuits REG # 1-REG # P are provided in common with the banks B # 1-B # N. It is not necessary to distribute the data for each bank and store it in the first-in / first-out circuit, which simplifies the circuit configuration. [0113] [Other application examples] The size M bits per page of the mixed DRAM may be bits other than 2K bits. Further, the bit width m of the input / output data of the DRAM core may be another bit width such as 128 bits or 512 bits. [0114] Further, the column latency CL is not limited to 2, and may be another value. When the delay of the input data in the bidirectional input / output circuit cannot be ignored, the data writing timing to the first-in / first-out circuit is adjusted in consideration of this delay. [0115] Further, the memory is not limited to DRAM, and may be other memory such as burst SRAM (static random access memory) or flash memory that operates in synchronization with the clock signal, and is on the same semiconductor substrate as the logic. The present invention is applicable as long as the memory is integrated in the memory. [0116] [Effect of the invention] As described above, according to the present invention, even if the input / output pins of the test data for the mixed memory are shared, sufficient tests can be performed on the mixed memory without being restricted by the test pattern due to the test data input / output switching timing. You can get a test interface circuit that you can do. [0123] Claim<u style="single">1</u>According to the invention according to the present invention, in a semiconductor integrated circuit device in which logic and memory are integrated on the same substrate, a first-in / first-out circuit for sequentially storing and reading data read from memory in a test interface circuit and this A control circuit that controls the operation of the first-in / first-out circuit according to the operation mode instruction signal is provided, and the test data input / output terminals can be shared to reduce the number of pin terminals required for testing. It is possible to realize a system LSI that can be used.<u style="single">In addition, the bidirectional input / output circuit makes it possible to realize a system LSI in which the test data input / output pads are shared and the number of test pin terminals is reduced.</u>[0124] Claim<u style="single">2</u>According to the invention according to the above invention, the first-in / first-out circuit is provided with a register circuit having the number of ratios of the page size of the memory and the data output bit width, so that the test data can be reliably first-in even when the page mode is accessed. It can be transferred in a first-out manner. [0125] Claim<u style="single">3</u>According to the invention according to the invention, the first-in / first-out circuit is provided with a number of register circuits given by the ratio of the product of the number of memory banks and the page size to the output data bit width, and all banks are set in page mode. Even if it is accessed, the test data can be reliably transferred in the first-in / first-out manner. [0126] Claim<u style="single">4</u>According to the invention according to the invention, the number of data read instructions is counted by a counter according to the operation mode instruction signal, and the read pointer and the write pointer are generated according to the count values. Can be stored / read. [0127] Claim<u style="single">5</u>According to the invention according to<u style="single">The data transfer path of the bidirectional input / output circuit is set according to the operation mode instruction signal, accurately preventing input / output data collisions.</u>can do. [0128] Claim<u style="single">6</u>According to the invention according to the invention, the read pointer is changed in response to the rise and fall of the test clock signal, so that the test data read cycle can be shortened, and the test cycle can be shortened accordingly. [0129] Claim<u style="single">7</u>According to the invention according to the above, the logic and the test interface circuit are selectively coupled to the memory, and the memory can be tested by surely eliminating the influence of the logic during the test operation.<u style="single">According to the invention of claim 8, the memory data bus is provided with a write data bus and a read data bus separately, and it is possible to prevent data collision with the memory.</u>[Simple explanation of drawings] FIG. 1 is a diagram schematically showing a configuration of a test interface circuit according to the first embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the test interface circuit shown in FIG. FIG. 3 is a diagram schematically showing the configuration of the latch / command decoder shown in FIG. FIG. 4 is a diagram schematically showing a configuration of a first-in / first-out circuit shown in FIG. FIG. 5 is a diagram schematically showing a configuration of a FIFO control circuit shown in FIG. FIG. 6 is a timing chart showing the operation of the FIFO control circuit shown in FIG. FIG. 7 is a diagram schematically showing a configuration of a first-in / first-out circuit shown in FIG. FIG. 8 is a diagram showing a modified example of the first-in / first-out circuit shown in FIG. FIG. 9 is a diagram schematically showing a configuration of a test interface circuit according to the second embodiment of the present invention. FIG. 10 is a timing chart showing the operation of the test interface circuit shown in FIG. [Fig. 11] (A) is a diagram schematically showing the configuration of a FIFO control circuit according to the third embodiment of the present invention, and (B) is a timing chart diagram showing the operation of the FIFO control circuit shown in (A). FIG. 12 is a diagram schematically showing a configuration of a first-in / first-out circuit according to a fourth embodiment of the present invention. FIG. 13 is a diagram schematically showing a configuration of a conventional system LSI. FIG. 14 is a diagram schematically showing a configuration of a test interface circuit of the system LSI shown in FIG. FIG. 15 is a timing chart showing the operation of the test interface circuit shown in FIG. FIG. 16 is a diagram showing a configuration when the test interface circuit shown in FIG. 14 is applied to the configuration of a common test data input / output terminal. FIG. 17 is a timing chart showing the circuit operation shown in FIG. [Explanation of symbols] SLI system LSI, LG large-scale logic, MCR DRAM core, TIC test interface circuit, 1 latch / command decoder, 2 mode register, 3 CA shifter, 4 256: 8 selection circuit, 5 selector, 6 gate circuit, 7 Gate circuit, 8 bidirectional input / output circuit, 9 test data input / output terminal, 10 first-in / first-out circuit, 15 FIFO control circuit, REG # 0-REG # k, REG # P register circuit, 15b first counter, 15g second counter, 15c write control circuit, 15h read control circuit, 15t (CL + 0.5) delay circuit, 30 switch circuit, 15j divider.