Self-configuring processors in an asynchronous transfer mode switch

[0001] [Field of Invention] The present invention relates to a multiprocessor configuration and, more particularly, to a multiprocessor configuration within an asynchronous transfer mode (ATM) switch. [0002] Outline and Background of the Invention In the architecture of the present invention, a plurality of function module boards (FMB) Board) is connected to the Asynchronous Transfer Mode (ATM) switch core. Each functional module board includes software containing one or more data processors, a distributed operating system and one or more application programs, and in particular hardware circuits including ATM switch ports. The ATM switch core contains multiple matrix units (RCUs: Row-Column-Units), and each ATM switch port is logically connected to one of the RCUs. When the FMB is connected to the ATM switch core slot, its logical connection is established. A distributed operating system is performed by one or more board processors BP within each functional module to coordinate the tasks performed in each functional module. Signal and traffic information is path-designated between various functional modules through the ATM switch core. In order to carry out such asynchronous communication, each functional module needs to know the ID and position of other functional modules connected to the ATM switch core. In particular, internal connections or paths through the ATM switch core need to be established in order to carry out selective processor-to-processor communication. [0003] Such location and identity information, as well as the internal control path (ICP) between processors, can be manually established by a human operator (eg, using the DIP switch included on each functional module board). If these configuration tasks could be performed automatically, the effort and cost would be significantly reduced. Therefore, in the present invention, the board processor is capable of performing self-configuration at initial startup and when a new or replacement functional module board is connected to the ATM switch core. [0004] That is, an object of the present invention is to provide an automatic configuration of a plurality of processors associated with an ATM switch. [0005] Another object of the present invention is to automatically establish an internal control path between processors associated with an ATM switch. [0006] Another object of the present invention is to automatically configure new processors when they are associated with ATM switches. [0007] Another object of the present invention is to automatically configure an array of processors associated with two or more ATM switches. [0008] Another object of the present invention is to automatically establish an internal control path between processors associated with different connected ATM switches. [0009] The autoconfigured node contains multiple functional module boards, each functional module board containing one or more board processors and a corresponding ATM switch port, connected to an available slot in an asynchronous transfer mode (ATM) switch. Will be done. When a node enters service, each board processor automatically broadcasts an initial message to all ATM switch port locations. The initial message includes the ID of each board processor and the location of the ATM switch port. [0010] One of the board processors acts as the main processor. When the main processor receives the broadcast initial message from the board processor, it stores the board processor ID and ATM switch port location in the database, and the initial message is clearly addressed to the broadcast board processor. Send a cognitive response. This acknowledged gment signal causes the board processor to recognize the ID of the main processor and the location of the ATM switch port. [0011] The stored ID and location information for each board processor is then used to establish an internal control path (ICP) between the processors through an ATM switch. In a preferred embodiment, the ICP is mutually established between the main processor and the board processor by the main processor establishing half of the ICP and the board processor establishing the other half of the ICP. Internal control paths are used by various board processors to selectively communicate control messages and other information. As an example of the latter, the main processor can download software to one or more board processors using an established internal control path. [0012] Thus, in the first exemplary embodiment of the invention, a multiprocessor, ATM switch based node is automated without the need for polling the board processor by the main processor or the intervention of a human operator in the node configuration. Can be configured as a target. The basic configuration information stored for each board processor includes the board processor ID and the ATM switch port location. Other configuration information can also be stored. [0013] In a second exemplary embodiment of the invention, a new functional module board is connected to an empty slot in the ATM switch core, for example to add capacity and / or functionality to the node. When a new feature module board is added, the board processor automatically broadcasts an initial message containing its ID and ATM switch port location. The main board processor receives this initial broadcast message, stores the ID and ATM exchange port location contained in the message, and sends a cognitive response. The main board processor and the new board processor first establish an internal control path through the ATM switch core between the new board processor and the main processor. The addition of newly added board processors and automatic configuration do not interrupt the operation of already configured board processors. [0014] In a third exemplary embodiment of the invention, the board processor is configured within a functional module connected to two or more ATM switch cores. For example, a physical link is established between the first and second ATM exchanges via the first and second exchange terminal boards (ETBs) connected to the first and second ATM exchange cores, respectively. That is, the ETB connects to physical lines such as twisted wire, coaxial cable, and optical fiber. The operation of each replacement terminal board is controlled by the corresponding board processor. One of the array of board processors connected to the first and second ATM switches is designated as the main processor. For example, the main processor is connected to the port of the first ATM switch. [0015] The main processor constitutes the board processor in both the first and second ATM switches. When each of the second board processors broadcasts an initial message to all ports of the second ATM switch, the second ETB, which acts as a pseudo-main processor, transfers information to the first ETB over a physical link. Relay. The first ETB "translates" that information and provides it to the main processor. [0016] The main processor stores the converted information and recognizes and responds to the initial message from the broadcast processor connected to the second ATM switch via the first and second ETBs and physical links. By doing so, the main and board processors mutually establish internal control paths through the first and second ATM switches. Some internal control paths are path-designated on the physical link through the first and second ETBs. Therefore, by using the physical link and the first and second ETBs, the board processors connected to the first and second ATM switch cores are automatically configured and all processors connect to the same ATM switch core. It is effectively manipulated as if it were done. [0017] The above and other objects and advantages of the present invention will be described in detail below, along with drawings and a detailed description of the invention. [0018] The present invention will be described by way of example in the accompanying drawings, and is not limited thereto. In the attached drawings, similar elements are indicated by similar reference numbers. [0019] [Simple explanation of drawings] In the following description, in order to fully understand the present invention, specific details such as a specific architecture, application, interface, technique, etc. are described for the purpose of exemplification rather than limitation. However, it will be apparent to those skilled in the art that the present invention can be implemented in other embodiments that deviate from these particular details. In addition, detailed description of well-known methods, protocols, devices and circuits will be omitted so as not to be obscured by unnecessarily detailed description of the present invention. [0020] The present invention is particularly advantageously applied to mobile wireless communication networks having multiple stations or nodes built on an ATM-based platform. For such mobile wireless communication networks, a related US provisional patent application filed on December 19, 1997 and filed as a formal US patent application on March 16, 1998 (Agent Dockett 2380-12). , Named "Asynchronous Transfer Mode Platform for Mobile Communications," US Patent Application No. 60 / 068,097, which is incorporated herein by reference. [0021] [0021] For example, in the Public Land Mobile Network (PLMN) 10 shown in Figure 1, three stations, nodes 12 and 20, are shown and built on an ATM-based platform. The mobile exchange controller (MSC) 12 connects the public land mobile network 10 to other fixed networks such as the public switched telephone network (PSTN) and integrated services digital network (ISDN). Two base stations 20 connect the MSC 12 to individual mobile stations 30 via a wireless aerial interface 28. [0022] The mobile exchange controller 12 includes an ATM exchange core 14. Multiple functional module boards (FMBs) connected to slots in the ATM switch core 14 include a main processor board (MPB) 16 and several board processors (BP) 18. Each board processor includes a program and data, and a data processing circuit for processing the data and executing the program. The board processors communicate with each other and use asynchronous transfer procedures on the ATM interface 15 to set up a connection through the ATM switch core 14. In general, the mobile exchange controller 12 performs setup and control of all connections to and from the mobile station 30 and also provides supplementary services. For the mobility of mobile station 30, MSC12 updates mobile subscriber data and mobile subscriber location using an appropriate database (not shown). The MSC12 also handles the continuity of the mobile subscriber's voice path, sometimes referred to as a "handover" or "handover". [0023] The mobile exchange controller 12 is connected to a plurality of base stations 20 (only two are shown for illustration) via the traffic and signal interface 19. Each base station 20 includes an ATM switch core 22. A plurality of functional module boards (FMBs) 26 are connected to the ATM switchboard core 22 via the ATM interface 25. The functional module main processor board 24 is also connected to one of the slots in each ATM switch core. [0024] With reference to Figure 2, each functional module board (FMB) contains a data processor or group of data processors, memory, and dedicated hardware circuitry. Each FMB is connected to a slot in the ATM switch core. Each ATM switch core consists of a matrix unit (RCU) associated with a slot, and the ATM switch "port" is logically associated with the corresponding RCU / slot. Therefore, when a board processor is described as being connected to or associated with an ATM switch port, the connection / association is understood to be a logical connection / association. It is the FMB that physically connects to the ATM switch core slot. [0025] The ATM switch core is added to a part of each functional module board to form the ATM switch itself (indicated by the dotted line). The parts of each functional module board included in the ATM switch can be shown as ATM switch ports, but buffering ATM cell inputs and outputs, encapsulating data, adding ATM headers and routing tags, VPI / VCI. It preferably includes dedicated data processing and storage hardware resources to perform ATM switch port functions such as cell analysis and conversion. Such buffering, analysis, and conversion are necessary to establish a path through the ATM switch core. [0026] The ATM switch ports associated with each functional module board are connected by a transmission path or link. Each link contains a link circuit that performs cell packaging according to the particular protocol used by that link. Each link can carry multiple connection cells. The path inside the ATM switch core is selectively controlled and specific ports in the core are connected to allow messages to move from the ATM switch inlet side to the ATM switch exit side. The queue or buffer found on each functional module board for each ATM switch port stores cells prior to exchange through the ATM switch core. An exchange core with a matrix unit essentially acts like a cross-connection between ATM exchange ports. [0027] In situations where a cell may have one of multiple priority classes to provide different quality services, each processor board should have as many queues or buffers as there are priority classes. Can be done. The cell is put into the appropriate buffer by the input queue selector and read from the buffer at the appropriate time by the output queue selector. Of course, the particular details of the ATM switch cores and protocols used in the present invention are not limited to any particular ATM architecture or protocol. [0028] Returning to FIG. 1, the base station 20 processes the radio interface to the mobile radio station 30 and includes radio equipment such as transmitters and receivers and antennas required for the service of one or more cells within the mobile radio network 10. Such functions include radio transmission, reception of radio signals from mobile stations including homogenization and versatility functions to compensate for fading effects, and signals on uplink and downlink connections between base stations and mobile stations. Quality measurements to measure strength and quality, timing and alignment measurements, base station radio transmitter power control and mobile station power control, multiplexing on radio paths, channel coding of system information and paging messages, interleaving, broadcasting, And the reception of radio channel requests from mobile stations. It is preferred that these functions be distributed and performed by various members of the functional module board 26. [0029] The public land mobile radio 10 will be built on an ATM platform and will use a fixed-length cell-based connected ATM transmission protocol. The ATM protocol is asynchronous in that cells containing information from individual network users do not need to be repeated periodically. Each ATM cell contains 53 bytes, 5 bytes from the ATM cell header, and 48 bytes carrying the actual information provided for transmission, sometimes referred to as the "payload". .. Each ATM cell is associated with a given "virtual channel", the connection supported by the physical link. Each connection is identified by two subfields in the header: the virtual channel identifier (VCI) and the virtual path identifier (VPI). Together, these fields are used to multiplex, demultiplex, and exchange cells over the mobile wireless network 10 for a particular connection. VCI and VPI are not addresses. Rather, they are explicitly specified within each ATM segment or link when the connection is established and are maintained for the duration of the connection. [0030] When an ATM exchange receives an input cell on an input port, it must determine the output port to path this cell based on the VPI, VCI, and input port physical identifier of the input cell. The cell is correctly pathed to the next ATM networking segment because the ATM switch determines the new VPI and VCI values to assign to the cell header. ATM exchanges generally look up this connection information in the VP / VC connection table based on the VPI and VCI information in the cell header as well as the "physical layer" information that identifies the input ATM exchange port. [0031] Specific applications running on the board processor are separated by the ATM adaptive layer (AAL) from the characteristics inherent in the ATM protocol layer. The present invention is not limited to a particular ATM adaptive layer category or type, but one preferred implementation is AAL-5 for ATM connections between board protocol modules connected to a single ATM switch core. use. The AAL-5 is specifically adapted for the transmission of data traffic commonly found on local area networks (LANs), so it is well applicable for local processor-to-processor communication. Any satisfactory ATM switch core and protocol topology can be used to implement ATM platforms within mobile network nodes such as MSC12 and base station 20. [0032] The present invention is advantageously applied to the mobile communication network 10 shown in FIG. 1, but is generally applied as described in detail in the general first embodiment shown in FIG. Figure 3 includes a single main processor board (MPB) 52 and multiple functional module boards (FMB) 54 connected to individual slots in the ATM switch core 50. The main processor board 52 and FMB 54 connect to the ATM switch core 50 via an appropriate AAL interface such as AAL-5. [0033] Communication between the main processor and the board processor is based on an internal control path (ICP) through the ATM switch core 50. An example of internal control path 58 is shown by the dotted line through the ATM switch core 50. The internal control path is a processor control signal connection from a typical processor. In an exemplary embodiment, the ICP is provided to establish the first minimal topology, called the "star" topology. Here, a single ICP connects the main processor to one of the board processors, just as each board processor has its own ICP to the main processor. Of course ICP can be automatically established between all processors. Once the appropriate application software is loaded on the processor, additional ICPs can be established between any board processor at the request of the application. [0034] In a preferred exemplary embodiment, each ICP is mutually established by a main processor and each board processor. The main processor establishes the main processor side half of the ICP, and the board processor establishes the other half of the ICP. [0035] To establish an internal control path, the main processor must know the ID of the board processor and the location of the ATM switch port to which the board processor is connected. Such an internal control path through the ATM switch core allows interprocessor communication without the need for a separate bus structure or other signal lines connected to the board processor. Moreover, the present invention can advantageously establish these internal control paths through the ATM switch core automatically and without the intervention of a human operator or the polling of the board processor by the main processor. [0036] Next, the procedure for establishing an internal control path (ICP) for configuring various board processors for communication will be described with reference to the ICP routine (block 60) shown in the flowchart of FIG. At system startup, such as after power-on or reset, each board processor 54 broadcasts an initialization message (block 62). The initialization procedure involves broadcasting an initialization message to all ATM exchange ports stored in the PROM of each FMB and connected to the same ATM exchange core. Initialization messages are sent periodically until a cognitive response from the main processor is received. [0037] Each initialization message contains configuration information for the board processor being broadcast, including the board processor ID and ATM switch port location. Other configuration information includes FMB type, special version of FMB type, ATM switch port speed, number of addressable devices on FMB, device type on FMB, PROMized and loaded software. Includes ID and version, ATM address that can specify the path, etc. For example, the initialization message should include a virtual path identifier (VPI) and a virtual connection identifier (VCI) that correspond to a coded ATM switch port location that explicitly identifies the board processor that is broadcasting. Can be done. [0038] The main processor (MP) stores each board processor identifier and ATM switch port location in a database or other memory table based on the broadcast message (block 64). Alternatively, the main processor can determine which board processor sent the initialization message by explicitly identifying the ATM switch port ID in the ATM cell payload. Only the main processor acknowledges and responds to each board processor's initialization message (block 66). Initialization messages are ignored by other board processors. The cognitive response message establishes half of the ICP on the main processor side and also contains information that identifies the main processor and its ATM switch port location. Therefore, when the cognitive response message is received by the board processor, half of the ICP on the board processor side is established (block 68). The board processor sends a message confirming the ID of the main processor and the location of the ATM switch port directly to the main processor via the newly established ICP (block 70). Transmission of signals and other types of control information between the various processors connected to the ATM switch core is carried out through these internal control paths. For example, the main processor can download software to the board processor via an established internal control path (block 72). [0039] According to the method of the present invention, the processor connected to the ATM switch core is automatically configured for selective interprocessor communication via the ATM switch without the main processor polling the board processor. Further, in order to carry out such a configuration or inter-processor communication, an external signal via an external bus structure is not required. [0040] A second exemplary embodiment of the invention does not require the hassle of reconfiguring all preconfigured processors in which the functional module board (FMB) is already connected to the ATM functional module switch core. Related to carrying out FMB module replacement or addition at. Refer to the exchange / addition routine (block 80) shown in the flowchart of FIG. When a new or exchange function module is installed in the ATM switch core (block 82), the processor on the new or exchange function module automatically broadcasts an initialization message (block 84). As described above, the initialization message includes the processor ID and ATM switch port location. After this, the internal control path procedure after system startup described in FIG. 4, ie blocks 64-72, is implemented, an appropriate internal control path with a new or exchange function module is configured and established, and the ATM switch is reconfigured. Be done (block 86). [0041] Advantageously, the replacement or addition of a new functional module processor board does not interrupt the operation of the already configured board processor. In general, taking the device offline for maintenance or other services is unacceptable in information communication systems. In addition, if the operator first installs a node capable of handling 200 concurrent calls, an additional board will be added without interfering with the running call, for example to upgrade the node to handle 400 concurrent calls. It is advantageous to add "during operation". In this second exemplary embodiment of the invention, growth and expansion are expected and can be readily addressed without having to take the entire node offline for repair, service, upgrade, or expansion. [0042] Next, a third exemplary embodiment of the present invention will be described with reference to the functional block diagram of FIG. Two or more ATM exchanges may be connected together. In FIG. 6, for example, three ATM switches 90, 100 and 110 are labeled ATM-A, ATM-B, and ATM-C, respectively. It will be understood that the FMB is physically connected to the ATM switch core slot, but the following description describes that the board processor (BP) is associated with the ATM switch port for simplicity. Therefore, multiple board processors are associated with each exchange port of the three ATM exchanges. In particular, ATM switch A includes a main processor 92 associated with a switch port. In addition to the other board processors 94, ATM switch A also includes exchange terminal board (ETB) processors 96 and 98. The ATM switch B includes a board processor 102 and a switch terminal board processor 104. The ATM switch C includes a board processor 112 and a switch terminal board processor 114. [0043] Neither ATM exchanges B nor C are equipped with a main processor board. All processors shown in FIG. 6 are displayed and configured as an extended but unified processor network monitored and maintained by the main processor associated with ATM switch A. [0044] The initial configuration of the processor network and the establishment of the internal control path between the board processors of ATM switches B and C are carried out using the switch terminal board processor. A direct ATM communication link 106 is established between the ATM-A switchboard board 96 and the ATM switchboard B switchboard 104. Similarly, an ATM communication link 116 is established between the exchange terminal board 98 of ATM switch A and the exchange terminal board 114 of ATM switch C. A third level of ATM switch is established at ATM switch D (not shown) over ATM communication link 116, for example via ETB114. Further, hierarchy levels can be added in the same way. The internal control path is established through ATM switch A between the main processor and the other "A" ATM switch board processors according to the procedure described in Figures 3-5 (indicated by the dotted line). [0045] Regarding the procedure for establishing an ICP for BP in other ATM switches "B" and "C" for configuring the board processor of ATM switch B and ATM switch C in the extended board processor network shown in FIG. This will be described next. Similar procedures are performed for the configuration of additional tier ATM exchanges. At system startup, the board processor associated with ATM switches B and C broadcasts an initialization message to all ports on each ATM switch. These initialization messages include the processor ID and the ATM switch port location. Since ATM switches B and C do not have a main processor, these initialization messages are not yet cognitively responsive. Since the main processor associated with the ATM switch A already constitutes the processor board associated with the ATM switch A, the main processor recognizes the switch terminals 96 and 98 and loads the VPI conversion software. [0046] When the "near-end" ETB 96 and 98 (as seen by the main processor) are recognized and the associated software, including the VPI conversion software, is loaded, the main processor 92 sends a predefined message near. It sends via the end ETBs 96 and 98 through the corresponding direct ATM communication links 106 and 116 to the "far-end" ETBs 104 and 114 (also seen from the main processor). The predefined message temporarily designates ETB 104 and 114 of ATM switches 100 and 110 as pseudo-main processors. Specifically, when a far-end ETB receives a predefined message directly through an ATM communication link, the ETB is configured to recognize itself as the pseudo-main processor of the corresponding ATM switch (eg, in a PROM). .. Upon this recognition, each pseudo-main ETB relays all initialization messages from the board processor connected to its respective ATM switch to the main processor's ATM switch through its ATM communication link. [0047] When these initialization messages are received by the near-end ETBs 96 and 98, the VPI of each initialization message is translated into a new VPI uniquely associated with the corresponding near-end ETB in the first ATM switch 90. Remapped. The VPI conversion allows the main processor to recognize that these initialization messages are coming from an ATM switch connected to a particular far-end ETB. As a result, each initialization message from the second level (or other additional level) ATM switch will have a unique VPI / VCI combination when it reaches the main processor. The VPI indicates a specific ATM switch ID. [0048] Since the main processor knows from the VPI where a particular initialization message originated, the first half of the internal control path (ICP) is established. A cognitive response message is sent from the main processor to the appropriate near-end ETB using the newly established ICP. This near-end ETB relays the cognitive response message to the far-end ETB through the corresponding ATM communication link. The far-end ETB sends a cognitive response message to the correct board processor. Thus, the second half of ICP is established. The board processor sends a confirmation message to the main processor that it has received information about the ID of the main processor and the location of the ATM switch port. The confirmation message is sent to the main processor using the established ICP, so the far-end ETB no longer functions as a pseudo-main processor. During the initialization process, the board processors in the second and other levels of ATM switches are unaware that the established ICP contained a pseudo-main processor. [0049] After this, the main processor can download the software to various board processors at different levels of ATM via an established internal control path. When a new or exchanged FMB is connected to any of the ATM exchanges, the new or exchanged board processor broadcasts an initialization message and the board processor configuration and ICP setup procedure described above is performed. [0050] Thus, the present invention greatly increases the flexibility and scalability of a single ATM switch base node and a multi-level network of ATM switch base nodes. Initialization and configuration procedures for establishing inter-processor communication occur automatically and are self-launched on a processor basis. As a result, these procedures replace multiple ATM exchanges, each with multiple board processors, from a very small system that uses only a single ATM exchange with only a few board processors connected. It can be applied to a wide range of networks connected via modules. [0051] Although the present invention has been described in the context of what is considered to be the most useful and preferred embodiment at this time, it will be appreciated that the invention is not limited to the disclosed embodiments. The present invention is intended to embrace the various modifications and equivalent sequences contained within the spirit and scope of the appended claims. [Simple explanation of drawings] FIG. 1 is a diagram showing a mobile wireless communication network to which the present invention can be advantageously applied. FIG. 2 is a functional block diagram showing an ATM switch consisting of an ATM switch core and a part of each connected functional module board. FIG. 3 is a functional block portion of the first exemplary embodiment of the present invention. FIG. 4 is a flowchart showing an outline of an example of a self-construction method according to the first exemplary embodiment. FIG. 5 is a flowchart showing an outline of a method example according to a second exemplary embodiment of the present invention. FIG. 6 is a functional block diagram showing a third exemplary embodiment of the present invention.