Dual gate field-effect transistor

[0001] [Technical field to which the invention belongs] The present invention relates to threshold voltage control of a double gate field effect transistor. [0002] [Conventional technology] In order to realize an insulated gate field effect transistor having a minute channel length, it is essential to prevent the so-called short channel effect (a sharp drop in the threshold voltage when the channel length is shortened). [0003] As one element structure for that purpose, there is a double gate field effect transistor shown in FIG. 1 (see [Patent Document 1] below). In the figure, 1 is a substrate, 2 is a second gate insulating film, and although not shown as a whole, it is an insulating layer that separates the semiconductor crystal layer formed on the substrate from the substrate, and is 3, 4, and 5. Are the source region, drain region, and channel region formed in a part of the semiconductor crystal layer, where 6 is the first gate insulating film, 7 is the insulating film, 8 is the source electrode, 9 is the drain electrode, and 10 is the first. The one-gate electrode and 11 are the second gate electrodes. [0004] This structure is considered to be the most effective method for suppressing the short-channel effect. That is, the channel region 5 is shielded by the upper and lower first gate electrodes 10 and the second gate electrode 11, and the influence of the drain electric field on the potential distribution at the source and channel region interfaces is suppressed, so that the source and channel can be shortened even if the channel is shortened. The potential distribution at the region interface can be stably controlled only by the gate electrode, and a sudden drop in the threshold voltage is prevented. [0005] An important issue in such an element is how to control the threshold voltage. Normally, the concentration of impurities in the channel region is controlled, but the upper limit of the concentration is 10 due to the limitation of the withstand voltage of the semiconductor itself.¹⁸cm^-3Limited to a degree. In that case, when the device size becomes fine, the number of impurity atoms in the channel region becomes extremely small, and statistical fluctuations in the number of impurity atoms for each device appear prominently as fluctuations in the threshold voltage of the device. This point becomes a problem as a decrease in yield in an integrated circuit using an extremely large number of elements. [0006] In the double-gate field-effect transistor, this problem can be avoided because an extremely low-concentration channel region close to that of an intrinsic semiconductor can be used without impairing the suppression of the short-channel effect. However, for that reason, in order to realize an appropriate threshold voltage, it is necessary to use a metal or the like having an appropriate work function as the gate electrode material, but since the work function value is an discrete value, fine control is possible. There wasn't. There is also a method of appropriately selecting the ratio of Si and Ge using SiGe or the like and setting the work function to an appropriate value, but it has a drawback that the process becomes complicated. [0007] In the above description, the two gates of the double-gate field effect transistor are electrically connected, but as shown in Fig. 2 (d), one gate electrode is used for signal input. , A predetermined constant potential (the value of the constant potential changes at any time, but at least the constant potential is maintained for a period sufficiently longer than the input signal cycle) is applied to the other gate electrode, and the signal is viewed from the signal input gate. A method of controlling the threshold voltage to the optimum value is also known. However, in this case, since the current flows only through the channel on the signal input gate side, the current is about half that when the two gate electrodes are electrically connected, which is a drawback that causes deterioration of the load drive capability during transient response operation. There is. Further, below the threshold voltage, there is a drawback that the so-called gate amplitude (also called S factor, in units of mV / digit), which is how much the gate voltage change is required to change the drain current by an order of magnitude, becomes large. By the way, when two gate electrodes are electrically connected, a small value of about 60 mV / digit at room temperature, which is close to the theoretical limit, is realized. [0008] [Patent Document 1] Patent No. 2021931 [0009] [Problems to be Solved by the Invention] The subject of the present invention is a gate signal of a double gate field effect transistor that can eliminate the above-mentioned drawbacks and control the threshold voltage arbitrarily and accurately.<u style="single">Apply</u>To provide a method. [0010] [Means for solving problems] During the transient response operation, an input signal for performing normal logic operation is applied to one gate electrode of the double gate field effect transistor, and the signal level changes with time with respect to the signal to the other gate electrode. Signals that are the same (hereinafter referred to as "in-phase") and that have at least one of the low and high levels of the signal shifted by a predetermined value, or a signal that has a predetermined time difference (may be progress or delay). Alternatively, a signal whose time change of the signal is made faster or slower is applied. [0011] FIG. 2 schematically illustrates the time relationship between the waveform of the input signal Vg1 of the gate electrode 1 and the waveform of the input signal Vg2 to the gate electrode 2. FIG. 2A illustrates the first method of the present application in which the input signal Vg1 shifted to the negative side or the positive side is used as Vg2. FIG. 3B illustrates the second method of the present application in which Vg2 uses a waveform that rises and falls slower than Vg1, or a waveform that both rises and falls faster. In some cases, a waveform with a fast rise and a slow fall, or vice versa, is used, and the threshold voltage is reduced at the time of rising and increased at the time of falling. Or vice versa to improve circuit performance. FIG. 3C illustrates the third method of the present application using a waveform in which Vg1 is delayed or advanced as Vg2. Further, FIG. 3D illustrates a case where a constant potential is applied to Vg2, which is a conventional threshold voltage control method. [0012] [Action] The case of an n-type field effect transistor will be described as an example. As in the conventional case, the input signal Vg1 is applied to one gate electrode of the double gate field effect transistor, for example, the first gate electrode, and both gate electrodes are connected to the other gate electrode, for example, the second gate electrode. A voltage lower than the threshold voltage VT0, for example, -0.5V or -1.0V, constant voltage Vg2 is input at the same time. Then, as shown in Fig. 3, the threshold voltage can be shifted in the positive direction when both gates are electrically connected and the input signal is applied (Vg2 = Vg1), respectively. VT2 is obtained. [0013] However, as can be seen in FIG. 3, when the constant voltage Vg2 is applied, the slope of the characteristic curve becomes small in the voltage range lower than the threshold voltage, showing the drawback that the gate amplitude becomes large. .. Ivt is a drain current value that defines the threshold voltage. For these characteristics, a two-dimensional device simulator atlas (Silvaco, USA) was used, and the gate length was 100 nm, the first and second gate oxide film thicknesses were 2 nm, the silicon channel layer thickness was 5 nm, and the first and second gate electrodes were used. , Calculated under the condition of aluminum gate electrode. The same applies to the following characteristic diagram. By the way, in this case VT0 is about -0.2V. [0014] On the other hand, in the first method of the present invention, as seen in FIG. 2A, an input signal Vg1 is applied to one gate electrode of the double gate field effect transistor, for example, the first gate electrode. The other gate electrode, for example, the second gate electrode, has a voltage lower than the threshold voltage VT0 when both gate electrodes are connected and operated, for example, -0.5V (Vg1-Vg2 = 0.5V) or -1.0V. The input signal Vg2 with at least the low level of Vg1 shifted by (Vg1-Vg2 = 1.0V) is input at the same time. Then, as shown in Fig. 4, when both gates are electrically connected and an input signal is applied (Vg2 = Vg1), the threshold voltage seen from the first gate electrode is set to the respective level shift amount. A larger value can be shifted in the positive direction accordingly, and threshold voltages of VT1 and VT2 can be obtained, respectively. [0015] In this case, as seen in FIG. 4, almost the same gate amplitude is obtained in each case, and there is no significant deterioration as in the case where only a constant potential is applied. In the case of FIG. 4, the signal amplitude of Vg2 is the same as that of Vg1. The horizontal axis is the gate voltage Vg1, but the time response inside the transistor is usually sufficiently fast with respect to the input signal, so it can be read as the time axis. [0016] Therefore, in this case, it is shown that the rise time response and the fall time response of the signal follow the same curve, and the threshold voltage values in both time responses are the same in principle. Further, if the input signal Vg2 whose level is shifted in the positive direction from VT0 is applied to the second gate electrode at the same time, the threshold voltage can be shifted in the negative direction. However, the leakage current at low levels increases slightly. [0017] In the second method of the present invention, as seen in FIG. 2 (b), the rise time of the signal Vg2 applied to the second gate electrode is faster than that of the input signal Vg1 applied to the first gate electrode. It's a way to slow it down. [0018] In the former case, the gate amplitude seen from the first gate electrode is apparently smaller than the theoretical value, and the threshold voltage shifts in the negative direction. In the latter case, the gate amplitude becomes large, but a smaller value can be realized as compared with the conventional case where a constant potential is applied to the second gate electrode, and the threshold voltage can be shifted in the positive direction. In the case of the fall time, the same applies to the gate amplitude, but the opposite action and effect can be obtained for the threshold voltage. [0019] Therefore, the threshold voltage at the rising edge and the falling threshold voltage look different, and a hysteresis characteristic can be obtained. As a method of generating a signal having a short fall time and a fast rise time, a signal faster than the input signal can be generated by using a trigger circuit or the like. There is an integrator circuit etc. as a method of slowing down. [0020] In the third method of the present invention, as seen in FIG. 2 (c), the signal applied to the first gate electrode is applied to the second gate electrode with a predetermined delay. [0021] [0021] Then, in the case of the rise time response, a constant voltage is applied to the second gate during the delay time, in this case, the same voltage as the low level is applied, but after that time, within the delay time. A signal whose level is shifted in the negative direction by the equivalent voltage difference generated between the two signals is applied to the second gate electrode. [0022] On the contrary, in the case of the fall time response, the same voltage as the high level is applied within the delay time, so that the signal whose level is shifted in the positive direction is transmitted to the second gate electrode. Will be applied to. [0023] Therefore, as shown in FIG. 5, at the time of rising, the current response is the same as when a constant voltage is applied to the second gate electrode within the delay time, but after that, the signals level-shifted in the negative direction are simultaneously generated. As in the case of application, there is no deterioration of the gate amplitude, and the response is that the threshold voltage is shifted in the positive direction. [0024] At the time of falling, the response is shifted in the negative direction of the threshold voltage, and similarly, there is no deterioration of the gate amplitude. In this case, when the low level (-0.5V) is reached, the drain current is lowered because the second gate voltage is delayed and reaches the low level. [0025] In this method, the threshold voltage is large at the rising edge and the threshold voltage is low at the falling edge, which is a hysteresis characteristic, as compared with the case where the same signal is input to the first and second gate electrodes. Since a large noise margin can be obtained and the same voltage is applied to both gate electrodes in the steady state, there is no deterioration of the on-current and the low-level leak current. [0026] In the above description of the present invention, the second gate oxide film thickness has been described as being the same as the first gate oxide film thickness, but for example, the action and effect even when the second gate oxide film thickness is thicker than the first gate oxide film thickness. Is similar. [0027] In this case, the threshold voltage seen from the second gate electrode is larger than the threshold voltage seen from the first gate electrode, and the on-current and leakage current can be reduced. [0028] Furthermore, the transient response can be made faster by the smaller the gate electrode capacitance. Further, the roles of the first gate electrode and the second gate electrode may be exchanged, the gate electrode may be composed of electrode materials having different work functions, respectively, and further, the first method of the present invention, the second. The above method and the third method can be arbitrarily mixed and used, and it goes without saying that the same actions and effects can be obtained in both cases. [0029] [Example] First, FIG. 6 shows a graphic symbol of the double gate field effect transistor used in the circuit diagram. FIG. 6 (a) shows an n-channel element, and FIG. 6 (b) shows a p-channel element. Further, 100 indicates a first gate electrode, 200 indicates a second gate electrode, 300 indicates a drain electrode, and 400 indicates a source electrode. [0030] FIG. 7 is an example of an inverter using the first method of the present invention. In the figure, 20 is an input terminal, 21 is an output terminal, 22 is a drain power supply terminal, and 23 is a source power supply terminal. The signal input to the input terminal 20 is applied to the first gate electrode, the potential level is further shifted by the level shift circuit, and the signal is applied to the second gate electrode. As the load element, a resistor, an n-channel field-effect transistor, a p-channel field-effect transistor, or the like is used. A specific example of the level shift circuit is a source follower circuit. [0031] FIG. 8 shows another embodiment, in which diodes 24 and 25 connected in antiparallel are used as the level shift circuit, and the input signal is level-shifted in the negative direction at the rising edge by the forward voltage and in the positive direction at the falling edge. Level shift to. In the steady state, the potentials of both gate electrodes are almost equal, so the drive current in the on state and the leak current in the off state are the same as when both gates are electrically connected. There is no deterioration like the law. As the diode, a short key diode having no accumulation time effect is desirable. [0032] FIG. 9 shows another embodiment according to the second method of the present invention. The input signal of the first gate electrode is applied to the second gate electrode through a voltage dividing circuit or an integrating circuit. Therefore, an in-phase signal with a slow rise or fall is applied to the second gate electrode. [0033] FIG. 10 is an example in which the voltage dividing circuit is specifically shown. Both gate electrodes are connected by a capacitance of 26. Ideally, a signal divided by the capacitance 26 and the capacitance of the second gate electrode is applied to the second gate electrode, and therefore a signal whose rising and falling ends are delayed by the division ratio is applied. The resistance shown in the figure is not necessary, but in some cases, it becomes equal to the potential of the source electrode in the steady state, the threshold voltage seen from the first gate electrode becomes larger, and only the channel on the first electrode side Since it operates, leakage current and on-current are reduced, resulting in low power consumption. The connection destination of the resistor does not have to be the source electrode, and may be connected to another constant potential point. [0034] FIG. 11 is an example showing a concrete integrator circuit. A resistor R of 27 is connected between the first gate electrode and the second gate electrode, and this and the capacitance of the second gate electrode form an approximate integrator circuit. In this case, the potentials of both electrodes are equal in the steady state. [0035] FIG. 12 shows another embodiment according to the third method of the present invention. X1 and X2 are double-gate field effect transistors, and the second gate electrodes of X1 and X2 are cross-coupled to the drain electrodes of X2 and X1, respectively. 28 and 29 are signal input terminals, and 30 and 31 are output terminals, which output values that are complementary to each other as logical values. 32 is the drain power supply VDD terminal, and 33 is the source power supply VSS end. This circuit operates as an inverter circuit of a so-called double rail logic circuit. [0036] The outline of the operation is shown below. First, if the input terminals 28 and 29 are at a low level, the logical state of the output terminals 30 and 31 is maintained. That is, one remains at a high level and the other remains at a low level. If the input terminals 28 and 29 are at high level at the same time, X1 and X2 are turned on at the same time, so the output terminals 30 and 31 are at low level at the same time. If a low level is input to the input terminals 28 and 29 at the same time from this state, one of the output terminals 30 and 31 will be at a high level and the other will be at a low level, but it is uncertain which one will be. [0037] To change the state at the output terminal, input a high level to the input terminal of the higher level transistor and input a lower level to the input terminal of the other transistor. For example, when the output terminal 30 is a high level and 31 is a low level, a high level is input to the input terminal 28 and a low level is input to the input terminal 29. Then, X1 changes from off to on, X2 changes from off to on, output terminal 30 changes to a low level, and 31 changes to a high level. [0038] At this time, since the second gate electrode of X1 is connected to the output terminal 31, a signal that changes from a low level to a high level and is in phase with the input signal of the input terminal 28 is input, but about two stages of transistors. It will be input with a delay of minutes. Further, a signal having the same phase as the input signal of the input terminal 29 having a delay of one stage of the transistor is input to the second gate of X2. [0039] In this circuit, both channels of transistors X1 and X2 are in the operating state only when the state changes, and in the steady state, only one channel of the transistor in the low level output state is in the on state. Power consumption can be reduced even when an n-channel element is used. [0040] This circuit can also be used as a SRAM cell circuit. In that case, the cell selection transistor is connected to the input terminals 28 and 29, respectively, and is also connected to the output terminals 30 and 31, respectively. Then, since the input to the cell and the output from the cell can be taken out from separate bit lines, the collision between reading and reading can be avoided. Further, it can be read from the output bit line if necessary, and has a variety of operations as a memory. [0041] [Effect of the invention] In the present invention, the threshold voltage of the double-gate field-effect transistor can be arbitrarily and accurately controlled by devising the gate signal input method of the double-gate field-effect transistor. [Simple explanation of drawings] FIG. 1 shows a structural example of a conventional double-gate field effect transistor. FIG. 2 is an input waveform diagram to a gate electrode. FIG. 3 is an example of gate characteristics of a double gate field effect transistor by a conventional gate input application method. FIG. 4 shows gate characteristics according to the method of the present invention. FIG. 5: Gate characteristics according to the method of the present invention. FIG. 6 is an explanatory diagram of a circuit symbol used for a double gate field effect transistor. FIG. 7 is an example in which the present invention is used for an inverter. FIG. 8 is an example of embodying the level shift circuit in the inverter of FIG. FIG. 9 is an example of another inverter. FIG. 10 is an example of embodying the voltage dividing circuit in the inverter of FIG. FIG. 11 is another example of embodying the voltage divider circuit in the inverter of FIG. FIG. 12 is an example in which the present invention is used in an inverter circuit of a double rail logic circuit. [Explanation of symbols] 1 ... Substrate 2 ... Second gate insulating film 3 Source area 4 Drain area 5 ... Channel area 6 First gate insulating film 7 Insulating film 8 Source electrode 9 Drain electrode 10 ... 1st gate electrode 11 ... Second gate electrode 20 ... Input terminal 21 ... Output terminal 22 ... Drain power supply terminal 23 ... Source power terminal 24 ... diode 25 ... diode 26 ... Capacity 27 ... Resistance 28 ... Signal input terminal 29 ... Signal input terminal 30 ... Output terminal 31 ... Output terminal 32 ... Drain power supply VDD terminal 33 ... Source power VSS terminal 100 First gate electrode 200 Second gate electrode 300 Drain electrode 400 Source electrode X1 ... Double gate field effect transistor X2 ... Double gate field effect transistor