Physical layer processing for a wireless communication system using code division multiple access background

The present invention generally relates to radio time division bidirectional transmission (TDD) communication systems that use code division multiple access (CDMA). In particular, the present invention relates to the processing of data in the physical layer of such a system.

In CDMA communication systems, communications are transmitted in the same frequency spectrum via a wireless air interface, which is distinguished by a channelization code. To further enhance the use of the spectrum, the CDMA / TDD communication system time-divides the spectrum into repeating frames with a fixed number of time slots, such as 15 time slots per frame. In TDD, each time slot is used exclusively for uplinks or downlinks.

Prior to transmission, the data to be transferred over the air interface is processed by the Universal Mobile Telecommunication System (UMTS) Terrestrial Radio Access Network (UTRAN). A simplified wireless communication system is shown in Figure 1. Wireless user (user equipment; UE) 38₁~38_N(38) is base station 36₁~36_NCommunicate with (36). Usually node-B 34₁~34_N(34) controls a group of base stations 36. Wireless Network Controller (RNC) 32₁~32_N(32) controls the group of node-B 34. RNC 32, Node-B 34 and other related components are part of UTRAN 30. UTRAN30 communicates with other users through the core network 40.

Data processing within UTRAN30 is standardized by the Third Generation Partnership Project (3GPP), UMTS's Terrestrial Radio Access (UTRA) TDD system, and more. The UTRAN30 handles transport channels for transport on the air interface. FIG. 2 is a block diagram of this UTRAN processing.

The transport block arrives and the air interface transports. Transport blocks arrive in units of sets (transport block sets). These sets are received at the specified time interval (Transmission Time Interval (TTI)). For 3GPP UTRA TDD, the possible TTI lengths are 10ms, 20ms, 40ms, and 80ms, which correspond to 1, 2, 4, and 8 radio frames, respectively.

The Cyclic Redundancy Check (CRC) attachment block 42 adds a CRC bit to each transport block. The CRC bit is used for error detection on the receiver side. The CRC bit length is sent as a signal from the upper layer.

The transport blocks (TrBKs) are sequentially concatenated by the TrBK concatenation / code block segmentation block 44. If the number of bits in the concatenated block exceeds the maximum permissible size of the code block, the concatenated block is divided into multiple segments. The size of the code block is based on the type of error correction coding used, such as convolutional coding (up to 504 bits), turbo coding (up to 5114 bits), or no coding (unlimited). The concatenated blocks are divided into the smallest number of segments (code blocks) of equal size. If the original number of concatenated bits is not an even multiple of the minimum number of segments, fill bits are used to ensure that the segments are of equal size.

An error correction of the channel coding block 46 encodes the code block by convolutional coding, turbo coding, no coding, or the like. After coding, the code blocks are concatenated into one. If the concatenated code blocks cannot be divided into the minimum number of segments (frames) of equal size, radio frame equalization is performed by concatenating any number of additional bits.

The first interleaver 48 interleaves all concatenated data. The wireless frame segmentation block 50 then segments the interleaved data into wireless frames. The rate matching block 52 punctures the bits, that is, it repeats the bits. Due to puncturing and repetition, the data transmitted on each physical channel (resource unit) is equal to the maximum bit rate of that channel. The rate matching attribute of each transport channel (TrCH) is sent as a signal by the upper layer.

The TrCH multiplexing block 54 receives one frame of data for each transport channel. The data received for each TrCH is sequentially multiplexed and sent out on the composite transport channel (CCTrCH). The bit scrambling block 56 scrambles the CCTrCH bits.

The physical channel block 58 maps the scrambled data onto the physical channel. The second interleaver 60 interleaves the scrambled data over the entire radio frame or over each time slot. The upper layer dictates the type of interleaving to use. After the second interleaving, the interleaved data is segmented into a plurality of physical channels so that it can be transferred over the air interface by the physical channel mapping block 62. After that, the physical channel data is transmitted from the base station 36, UE38, or the like. On the receiver side, such as UE38 or base station 36, the same process is performed in reverse order to restore the transmitted data.

Various after the first interleaver 48, rate matching block 52, transport channel multiplexing block 68, bit scrambling block 56, second interleaver 60, etc. to process the data as shown in Figure 2. Requires a high level of buffering (buffers 64, 66, 70, 72). Such extensive buffering is not desirable. It is necessary to use a large amount of memory and add memory space for application specific integrated circuits (ASICs) to support such buffering.

<p> Therefore, it is desirable to prepare another data processing method.</p>

<p> The present invention includes various embodiments used in physical layer treatment. In one embodiment, the address mapping of the bits in the physical channel buffer is determined from the addresses of the bits in the first interleaver buffer. The address of the physical channel buffer is determined corresponding to the address of the bit after rate matching, bit scrambling, second interleaving, and physical channel mapping. These bits are read directly from the first interleaver buffer and written to the physical channel buffer using the determined physical channel buffer address. In another embodiment, the address mapping of the bits in the first interleaver buffer is determined from the addresses of the bits in the physical channel buffer. The address of the first interleaver buffer is determined corresponding to the address of the bit after reverse rate matching, reverse bit scrambling, reverse second interleaving, and reverse physical channel mapping. These bits are read directly from the determined first interleaver buffer and written to the address of the physical channel buffer.</p><p> Preferred embodiments are described in the context of preferred applications of 3GPP UTRA TDD communication systems, but these embodiments are Code Division Multiple Access 2000 (CDMA2000), Time Division Synchronous Code Division Multiple Access (TDSCDMA), and Frequency. It can also be applied to other standards such as Time Division Bidirectional Code Division Multiple Access (FDD / CDMA), and applications. Preferred embodiments are described in three common approaches: "push", "pull", and "simplified first interleaver buffering". However, engine embodiments for each approach can be modified for use in other approaches or applications.</p>

One approach to physical channel processing is called the "push" approach, as shown in the flow diagram of Figure 3 and the block diagram of Figure 4. If the sender takes a "push" approach, the bits output from the first interleaved output buffer 82 are mapped (step 74) and written to one bit in the physical channel buffer 84 (step 76). The data in the physical channel buffer 84 is sent to chip rate processing and transmitted over the air interface. For illustration purposes, a given bit in first interleaved buffer 82 is not mapped to any location in physical channel buffer 84, mapped to one location, or multiple locations, as shown in FIG. Either map to a location. After being mapped, the bits are inserted at the corresponding positions in the physical channel buffer 84. On the receiving side, the bits are read from the physical channel buffer 84 and written to the first interleaved buffer 82. As a result, the sender's "push" approach is executed in the reverse order of the receiver's "push" approach. Below, the "push" approach is primarily described from the sender. The receiving side is executed in the same reverse order.

FIG. 4 is a block diagram of an embodiment of the push approach. For the bits in the first interleaver buffer 82, the push address generation engine 86 determines its destination address in the resource unit of the physical channel buffer 84. One frame of bits is processed at a time. If the TTI exceeds 10 milliseconds, the other frame bits are sequentially fetched after the first frame, for example, from frame 1 to frame 2 and frame 3. These bits can be retrieved one at a time, or in groups such as 8-bit, 16-bit, or 32-bit. The push address generation engine 86 determines one or more addresses as the write-to address of each bit in the physical channel buffer 84, or does not determine anything. The push address generation engine 86 uses standardized or signaled control parameters to determine the appropriate address.

The push address generation engine 86 sends the control signal to the read / write controller 78. The read / write controller 78 reads one or more bits from the corresponding address in the first interleaver buffer 82 and one or more bits at one or more addresses as directed by the push address generation engine 86. To write. All of these operations are controlled by the physical mapping controller 104, which also uses control parameters to monitor physical layer processing operations.

The push address generation engine 86 includes four primary subengines: a rate matching engine 88, a bit scrambling engine 90, a second interleaving engine 92, and a physical channel mapping engine 94.

The other three sub-engines feed the four primary engines: the wireless frame segmentation compute engine 96, the TrCH multiplexing (MUX) compute engine 98, and the physical channel segmentation compute engine 100. These three sub-engines do not functionally change the bit order during physical layer processing. These engines actually mark the bits.

The wireless frame segmentation engine 96 determines the bit address of the first interleaver buffer 82 to be transmitted within each frame. The TrCH MUX engine 98 determines which of the frames to send to which CCTrCH. The physical channel segmentation engine 100 determines which CCTrCH is transmitted on which physical channel (resource unit). These three engines 96, 98, 100 are shown in Figure 1 as being executed and functioning just before the step that requires information, but in reality they can be executed before that, In some cases, it can be run before any of the primary engines 88, 90, 92, 94 are up and running.

The four primary engines 88, 90, 92, 94 operate on the transmitting side in the order shown in Figure 3. Rate matching is performed first. This is followed by bit scrambling, followed by a second interleaving. Finally, physical channel mapping is performed.

Rate matching performs bit puncturing and iteration, not only reducing the number of channels required, but also ensuring that each channel is fully utilized. For the sake of explanation, assume that a channel has 110 bits in the first interleaver buffer, but that channel must have 100 bits to allocate a physical channel. 10-bit puncture is performed. In contrast, if there are only 90 bits on that same channel in the buffer, it would be necessary to repeat 10 bits. Due to puncturing and repetition, some bits of the first interleaver buffer are not written to any address, are written to one address, or are written to multiple addresses.

The rate matching engine 88 determines the address where each bit of the first interleaver buffer is inserted after the rate matching, which will be described with reference to FIG. Rate matching mainly uses three variables: e-ini, e-plus, and e-minus. e-ini is the initial value for e used in the rate matching algorithm. e-plus is an incremental value for e used in the rate matching algorithm. e-minus is the decrement value for e used in the rate matching algorithm.

The rate matching engine 88 chooses step 108 or step 110 depending on whether the particular channel is convolutional coded or turbo coded (step 106). This selection is signaled by control information. If the channel is non-turbo-encoded, the bits are treated as a single column (step 110). In turbo coding, each bit is tagged with one of three types of systematic (S), parity 1 (P1), and parity 2 (P2). Puncturing is not performed on systematic bits. The rate matching engine treats each of these types of bits as a separate column (step 108). Treating these bits separately eliminates the need for explicit bit separation and bit collection, as described in the standard.

The preferred rate matching algorithm for push address mapping is as follows (step 112).

Parameter definition: e_ini Initial error between current puncturing and desired puncturing ratio e_minus Decreased value of variable e e_plus Incremental value of variable e Number of bits before X rate matching (from a transmission point of view) p Address to which bits are mapped after puncturing or repetition u Address of the bit before rate matching (from a transmission point of view) e Temporary variable that holds the "error" as specified in the standard i-column identifier (that is, S, P1, or P2) f A function that further resolves the address p and represents the rest of the push processing engine that writes bit u to the corresponding physical channel. When puncturing is performed, the following algorithm is used.

e_i= e_{ini, i} p = 0 u = 0 while u &lt;X e_i= e_i--e_{minus, i} if e_i &gt; 0 then --Usually no puncture bit Execute function f (u, p) u = u + 1 p = p + 1 else Perform a puncture bit otherwise u = u + 1 e_i= e_i+ e_{plus, i} end if end while

If the iteration is performed, the following algorithm is used.

e_i= e_{ini, i} p = 0 u = 0 while u &lt;X e_i= e_i--e_{minus, i} if e_i &gt; 0 then --Usually no repeating bits Execute function f (u, p) u = u + 1 p = p + 1 else Otherwise this is a repeating bit Execute function f (u, p) p = p + 1 e_i= e_i+ e_{plus, i} end if end while

"Push" rate matching is described in the context of preferred TDD / CDMA communication systems, such as UE, base station, or node-B along with TDD / CDMA, FDD / CDMA, and TDSCDMA systems. It can be used in various applications.

The next step in this process is bit scrambling. In bit scrambling, the order of the bits is changed to eliminate the DC bias. The bit scrambling engine determines the bit scrambled address for the address output by the rate matching engine.

In bit scrambling, the scramble code is used to scramble the bits. Bit scrambling is used to remove DC bias. Bits prior to bit scrambling are h₁, H₂, H₃, ..., h_sIt is represented by. S is the number of bits in CCTrCH, otherwise it is called a scrambling block. The kth bit of the S bits is defined by Equations 1 and 2.

<maths num="1"><img file="JP4246751B2_D0001.tif" /></maths>

p_kIs the kth bit of the scrambled code. g_iIs the i-th bit of g.

The bit scrambling process is illustrated in the flow diagram of Figure 6. Scramble code p using bit position k in CCTrCH_kDetermine the corresponding bit of (step 300). Bit h_kIs p_kScramble by executing exclusive OR with (step 302).

As shown in FIG. 7, in the other embodiment described in the flow diagram of FIG. 8, the bit scrambling engine 90 is the other engine 88, 92, 94 (rate matching, second interleaving, and Placed after physical channel mapping). This embodiment allows all address mapping to be performed before manipulating bit values. The bit scrambling engine determines the address of the specified bit after rate matching (step 304). Scramble a bit using the address of the specified bit after rate matching p_k(Step 306). Determined p_kThe specified bits are scrambled, for example by performing an exclusive OR using. (Step 308).

"Push" bit scrambling is described in connection with the preferred TDD / CDMA communication system, which is preferably in various applications such as UE, base station, or node-B in TDD / CDMA systems. Can be used.

The second interleaver engine 92 is used for rate matching to later interleave the bits. Initially, the second interleaver engine 92 needs to know whether to perform the second interleave on the entire CCTrCH or in a single time slot on the CCTrCH. This information is signalized from the upper layer. In the second interleaving, the bits are read row by row, such as more than 30 columns. After being read into the array, column replacement is performed. These bits are then read from the replaced column.

The second interleaving is illustrated in Figures 9 and 10. The address u of the bit before the second interleaving (after bit scrambling) is used to determine the address p after the second interleaving. Use a known number of columns in the array, for example 30 columns, to determine the columns and rows of bits in the array (step 114). To illustrate FIG. 10, we analyze the bit at address 58 after bit scrambling. By dividing the address and truncating it, the row of bits is obtained (line 1: 58/30 = 1 ... remainder 29). The column is derived from the remainder of this division. In this illustration, the column is determined to be column 28 by subtracting 1 from the remainder (29-1). Use the known permutation of columns to determine the new column for a bit (step 116). In this illustration, column 28 is replaced by column 11. The number of bits in the CCTrCH or CCTrcH time slot and the column offset determine the address p of the bits after the second interleaving (step 118). In this illustration, the seven columns before column 11 contain 3 bits and the four columns contain 2 bits. Therefore, the bit is at address 30 after the second interleaving.

The "push" second interleaving is described in connection with the preferred TDD / CDMA communication system, which, along with TDD / CDMA, FDD / CDMA, and TDSCDMA systems, is UE, base station, or node-B. It can be used in various applications such as.

After the second interleaving, the bits of each CCTrCH are mapped to physical channels / resource units. Physical channel mapping will be described with reference to FIG. Physical channel mapping uses different mapping approaches for four different cases. In the first case, the time slot has only one resource unit for CCTrCH. In the second case, multiple resource units are used in the time slot due to the downlink. In the third case, multiple resource units are used in the uplink, and the diffusion coefficient of the data in the first resource unit is greater than or equal to the diffusion coefficient of the second resource unit. In the fourth case, multiple resource units are used in the uplink, and the diffusion coefficient of the first resource unit is smaller than the diffusion coefficient of the second resource unit. On the uplink, only two resource units can be used for CCTrCH in the time slot. The physical channel mapping engine 100 classifies the address u of the input bit into one of four categories (step 120).

In the first case (there is a single resource unit in the time slot), the bits are sequentially assigned to the resource units. Therefore, the address u of the bit after the second interleaving directly corresponds to the address p in the resource unit (step 122).

In the second case (downlink to multiple resource units), bits are assigned to each resource unit in turn. This operation is repeated until the last resource unit is reached, such as assigning the first bit to resource unit 1, assigning the second bit to resource unit 2, and so on. When the last resource unit is reached, the next bit is assigned to resource unit 1.

The operations assigned to each resource unit can be considered as modulo counting. In the description of Figure 12, there are three resource units. The operation to fill a resource unit is modulo 3 counting. In general, if there are N resource units, those resource units are filled with modulo N counts.

Odd resource units are filled from left to right, and even resource units are filled from right to left in reverse order. As shown in FIG. 12, resource units 1 and 3 are filled from left to right, and resource unit 2 is filled from right to left.

Bits are filled in this way until one of the resource units is filled. This point is called a switch point. At the switching point, the number of modulus is reduced by the number of buried resource units. Using FIG. 12 as an explanatory diagram, resource unit 1 is filled with bits 681. After the remaining resource units are filled, resource units 2 and 3 are filled using modulo 2 counting, starting at bit 684 (switching point).

The physical channel mapping engine puts the bits in the forward direction (F) before the switching point, in the reverse direction (R) before the switching point, in the forward direction (F) after the switching point, and in the reverse direction (R) after the switching point. ) In one of four categories (step 124). In the forward direction, the bits are filled from left to right, and in the reverse direction, the bits are filled from right to left. The address of the bit is determined based on that category (step 126).

The switching point is obtained by obtaining the length of the shortest resource unit and multiplying the length by the number of resource units. In Figure 12, the first resource unit is 228 bits long. The switching points are 228 x 3 or 684 resource units. After the switching point is determined, it is determined whether the bit is forward (F) or reverse (R). For the bit before the switching point, the address is determined by the remainder of the bit address divided by the number of its modulus. Using address 682, dividing 682 by modulus 3 yields 227 remainder 1. The resource units are numbered from 1 to 3 instead of 0 to 2, so 1 is added too much and the bits go into resource unit 2. With respect to classification, the bits in the odd resource unit are in the forward direction and the bits in the even resource unit are in the reverse direction.

After the switching point, use a similar approach. The switching point is subtracted from the bit address, and the result is divided by the new modulus, and the remainder is used to find the resource unit of the bit.

After classifying the bits, one of four formulas is used to determine its address. For the forward direction in front of the switching point, use Equation 3.

p = Start + u / mod Expression 3

Start is the first address within that resource unit, such as bit 0. u is the address of the bit after the physical channel mapping. p is the address of the determined resource unit. mod is the number of modulus before the switching point, which is 3 in the example.

For the opposite direction in front of the switching point, use Equation 4.

p = End-u / mod Expression 4

End is the last address in the resource unit.

For the forward direction after the switching point, use Equation 5.

p = Start + SP / mod + (u-SP) / mod_sp Equation 5

SP is a switching point, mod_spIs the modulus after the switching point.

For the reverse direction after the switching point, use Equation 6.

p = End-SP / mod-(u-SP) / mod_sp-1 Equation 6

In case 3 (uplink where the first resource unit contains a higher diffusion coefficient than the second resource unit), the bits are filled using a modulus based on the diffusion coefficient of the two resource units. Find the modulus using Equation 7.

mod = 1 + max ((SF1, SF2) / min (SF1, SF2)) Equation 7

SF1 is the diffusion coefficient of the resource unit 1, and SF2 is the diffusion coefficient of the resource unit 2.

For explanation using FIG. 13, let the diffusion coefficient of resource unit 1 be 16 and the diffusion coefficient of resource unit 1 be 4. As a result, the resource unit is filled with modulo 5 counts. Therefore, the resource unit 1 has bits 0 and 5, and the resource unit 2 has bits 1 to 4. After resource unit 1 is filled, the remaining bits are sequentially filled in resource unit 2. The switching point is the position where the resource unit 1 is filled. Resource unit 1 is always filled from left to right, and resource unit 2 is filled vice versa.

The physical channel mapping engine classifies the bits into one of three categories: forward before the switching point, reverse before the switching point, and reverse after the switching point (step 128). The address of the bit is determined based on that category (step 130).

The switching point is derived from the length of the first resource unit according to Equation 8.

SP = mod * (length of first resource unit) Equation 8

After the switching point is determined, it is determined whether the bits are forward or reverse. For the bit before the switching point, if there is a remainder after dividing the bit address by its modulus, the bit is in the second resource unit. To explain bit 4, dividing 4 by modulus 5 yields a remainder of 4. As shown in Figure 10, bit 4 is in resource unit 2 as expected. If there is not enough, the bits are in the first resource unit. After the switching point, all bits are in the second resource unit.

After classifying the bits, one of three formulas is used to determine its address. For the forward direction in front of the switching point, use Equation 9.

p = Start + u / mod Expression 9

For the opposite direction in front of the switching point, use Equation 10.

p = End-((mod-1) * (u / mod)-BN% mod Equation 10

BN% mod is the number of bits modulo the value for mod. For mod = 5, BN% mod is mod₅(Number of bits).

For the reverse direction after the switching point, use Equation 11.

p = End-mod * SP / (mod + 1)-(u-SP) Equation 11

In case 4 (uplink where the first resource unit contains a lower diffusion coefficient than the second resource unit), the bits are filled using a modulus based on the diffusion coefficient of the two resource units. Equation 7 is also used to find the modulus.

For explanation using FIG. 14, let the diffusion coefficient of resource unit 2 be 16 and the diffusion coefficient of resource unit 1 be 4. As a result, the resource unit is filled with modulo 5 counts. Therefore, the resource unit 1 has bits 0 to 3, and the resource unit 2 has bits 4. After resource unit 1 is filled, the remaining bits are sequentially filled in resource unit 2. The switching point is the position where the resource unit 1 is filled. Resource unit 1 is always filled from left to right, and resource unit 2 is filled vice versa.

The physical channel mapping engine classifies the bits into one of three categories: forward before the switching point, reverse before the switching point, and reverse after the switching point (step 132). The address of the bit is determined based on that category (step 134).

The switching point is derived from the length of the first resource unit according to Equation 12.

SP = mod * (length of first resource unit) / (mod-1) Equation 12

After the switching point is determined, it is determined whether the bits are forward or reverse. For the bit before the switching point, if there is a remainder of adding 1 to the bit address and dividing it by its modulus, the bit is in the first resource unit. If not, it is in the second resource unit. After the switching point, all bits are in the second resource unit.

After classifying the bits, one of three formulas is used to determine its address. Equation 13 is used for the forward direction in front of the switching point.

p = Start + ((mod-1) * (u / mod)) + BN% mod Equation 13

For the opposite direction in front of the switching point, use Equation 14.

p = End-u / mod Expression 14

For the reverse direction after the switching point, use Equation 15.

p = End-SP / (mod + 1)-(u-SP) Equation 15

Using these equations for these four cases, the physical channel mapping engine 94 determines the address p of the resource unit for a particular address u prior to physical channel mapping.

"Push" channel mapping is described in connection with the preferred TDD / CDMA communication system, which is preferably used in various applications such as UE, base station, or node-B in TDD / CDMA systems. can do.

As shown in Figure 15, another approach to physical channel processing is called the "pull" approach. If the sender takes a "pull" approach, each bit entered into physical channel buffer 146 is mapped to one or more bits in first interleaver buffer 144 (step 136). For illustration purposes, the address in physical channel buffer 146 is mapped to the address in first interleaver buffer 144. After being mapped, the bits are inserted into the physical channel buffer 146 by also reading the corresponding location in the first interleaver buffer 144 (step 138). The data in the physical channel buffer 146 is sent to the chip rate processing unit and transmitted on the air interface. On the receiving side, the bits are read from the physical channel buffer 146 and written to the first interleaved buffer 144. As a result, the "pull" approach on the receiving side is the opposite of that on the transmitting side. Below, the "pull" approach is primarily described from the sender. The receiver is also executed in a similar reverse order.

FIG. 16 is a block diagram of an embodiment of the "pull" approach. The pull address engine 148 determines the bits to write to the physical channel buffer 146. The advantage of the "pull" approach is that resource units can be filled as needed, eliminating the need to buffer physical channel data across multiple time slots. For illustration purposes, if you want to send only one resource unit within the first time slot of the frame, the "pull" approach allows you to "pull" only the bits for that resource unit. As a result, the pull approach can be used to reduce the number of physical channels buffered in only a single time slot.

In the "pull" approach, these bits can be retrieved one at a time, or in groups such as 8-bit, 16-bit, or 32-bit. These bits are preferably extracted in order from the first bit to the last bit of the resource unit, but the bits can be extracted in other orders. The pull address generation engine 148 determines the address to read the bit from the first interleaver buffer 144. The pull address generation engine 148 uses standardized or signaled control parameters to determine the appropriate address.

The pull address generation engine 148 sends the control signal to the read / write controller 140. The read / write controller 140 reads one bit from the determined address in the first interleaver buffer 144 and writes that bit to the physical channel buffer 146. These operations are controlled by the physical mapping controller 166, which also uses control parameters to monitor physical layer processing operations.

Similar to the "push" approach, the pull address generation engine 148 comprises four primary subengines: a rate matching engine 150, a bit scrambling engine 152, a second interleaving engine 154, and a physical channel mapping engine 156.

The other three sub-engines also supply information to the four primary engines: the wireless frame segmentation calculation engine 158, the TrCH multiplexing (MUX) calculation engine 158, and the physical channel segmentation calculation engine 162.

In contrast to the "push" approach, the four primary engines 150, 152, 154, 156 operate on the transmitting side in the order shown in Figure 16. Physical channel reverse mapping is performed first. After that, reverse second interleaving is performed, followed by reverse bit scrambling. Finally, reverse rate matching is performed.

The physical channel mapping engine 156 performs inverse physical channel mapping. For each bit address in the resource unit, the corresponding address before the next channel mapping is determined.

Physical channel mapping uses different mapping approaches for four different cases. Physical channel mapping will be described with reference to FIG. In the first case, the time slot has only one resource unit for CCTrCH. In the second case, multiple resource units are used in the time slot due to the downlink. In the third case, multiple resource units are used in the uplink, and the diffusion coefficient of the data in the first resource unit is greater than or equal to the diffusion coefficient of the second resource unit. In the fourth case, multiple resource units are used in the uplink, and the diffusion coefficient of the first resource unit is smaller than the diffusion coefficient of the second resource unit.

The physical mapping engine 156 determines the case that applies to the bit address of each resource unit (step 168). In the first case (there is a single resource unit in the time slot), the bits are sequentially assigned to the resource units. Therefore, the address p of the bits in the resource unit corresponds directly to the address u before the physical channel mapping (step 170). In the second case (downlink of multiple resource units). The physical channel mapping engine 156 puts the bits in one of four categories: forward before the switching point, reverse before the switching point, forward after the switching point, and reverse after the switching point. Classify (step 172). In the forward direction, the bits are filled from left to right, and in the reverse direction, the bits are filled from right to left. The address of the bit is determined based on that category (step 174).

The switching point of the odd resource unit is the shortest resource unit length. Using the example in Figure 18, the switching point is 228 (the shortest resource unit length). For even resource units, the switching point is the last address in the resource unit minus the length of the shortest number of resource units. After the switching point is determined, the bit is determined to be forward or reverse based on the resource unit. Odd resource units are in the forward direction and even resource units are in the reverse direction.

After classifying the bits, one of four formulas is used to determine its address. Equation 16 is used for the forward direction in front of the switching point.

u = p * mod + ru% mod Expression 16

u is the address of the bit as a mapped inverse physical channel. p is the address of the resource unit. mod is the counting modulus before the switching point. ru% mod is the number of bits of the resource unit whose mod value is modulo.

For the opposite direction in front of the switching point, use Equation 17.

u = End-p * mod + 1 Equation 17

End is the last address in the resource unit.

For the forward direction after the switching point, use Equation 18.

u = SP * mod + (p-SP) * (mod_sp) Equation 18

SP is a switching point, mod_spIs the modulus after the switching point.

For the reverse direction after the switching point, use Equation 19.

u = SP * mod-(End-SP-p) * (mod_sp-1) + RU-2 Equation 19

RU is the number of resource units in the bit.

In case 3 (uplink where the first resource unit contains a higher diffusion coefficient than the second resource unit), as mentioned above, the bits are filled using a modulus based on the diffusion coefficient of the two resource units.

The physical channel mapping engine 156 classifies the bits into one of three categories: forward before the switching point, reverse before the switching point, and reverse after the switching point (step 176). The address of the bit is determined based on that category (step 178).

Two switching points, a forward switching point (SPF) and a reverse switching point (SPR), are used for the physical channel mapping in Case 3. The forward switching point is the switching point of the first resource unit, which is equal to its length, such as 228 in FIG. The reverse switching point is the switching point of the second resource unit determined by Equation 20.

SPR = End- (mod-1) * SPF Equation 20

End is the last address in resource unit 2.

After classifying the bits, one of three formulas is used to determine its address. Equation 21 is used for the forward direction in front of the switching point.

u = mod * p expression 21

For the opposite direction in front of the switching point, use Equation 22.

u = mod * INT ((LP2-ruPOS) / (mod-1) + MOD (LP2-ruPOS, (mod-1)) +1 Equation 22

INT is an integer operator. MOD is a modulo operator. LP2 is the last position in resource unit 2. ruPOS is the bit position number of the bit in the resource unit.

For the reverse direction after the switching point, use Equation 23.

u = mod + SPF + SPR-p-1 Equation 23

In case 4 (uplink where the first resource unit contains a lower diffusion coefficient than the second resource unit), as mentioned above, the bits are also filled using a modulus based on the diffusion coefficient of the two resource units.

The physical channel mapping engine 156 classifies the bits into one of three categories: forward before the switching point, reverse before the switching point, and reverse after the switching point (step 180). The address of the bit is determined based on that category (step 182).

Only the reverse switch point (SPR) is used for physical channel mapping in Case 4. The reverse switching point is the switching point of the second resource unit determined by Equation 24.

SPR = End- (length of resource unit 1) / (mod-1) Equation 24

End is the last address in resource unit 2.

After classifying the bits, one of three formulas is used to determine its address. For the forward direction in front of the switching point, use Equation 25.

u = mod * INT (p / (mod-1)) + ruPOS% (mod-1) Equation 25

ruPOS% (mod-1) is the bit position in the resource unit modulo the value of (mod-1).

For the opposite direction in front of the switching point, use Equation 26.

u = mod * (LP2-p) + (mod-1) Equation 26

For the reverse direction after the switching point, use Equation 27.

u = mod * (LP2-SPR + 1) + (LP2-p)% modMinus1 Equation 27

Using these equations for these four cases, the physical channel mapping engine 156 determines the address p of the resource unit for the bit address u of a particular second interleaver.

"Pull" physical channel mapping is described in connection with the preferred TDD / CDMA communication system, which is used in various applications such as UE, base station, or node-B in TDD / CDMA systems. be able to.

The second interleaving engine 154 is used to deinterleave the bits after physical channel mapping. First, the second interleaving engine 154 needs to know whether it runs across CCTrCH or for a single time slot in CCTrCH. This information is signalized from the upper layer.

The second interleaving is illustrated in FIG. The specific address p of the bits after the physical channel mapping is used to determine the address u after the inverse second interleaving. The total number of bits in the CCTrCH or CCTrcH time slot and the column offset are used to determine the number of bits in each column. The address p is used to determine the columns and rows of bits in the reordered array (step 184). To illustrate the use of the example in Figure 22, analyze the bits at address p = 61 in the physical channel buffer. Using the total number of bits and the column offset, we can see that column 0 has 5 bits and the other columns have 4 bits. The number of bits known for each column is used to determine the columns and rows for the bits (column 12, row 1).

Determine the non-offset columns using the known permutation of columns (step 186). In the above description, the offset column 12 corresponds to the non-offset column 1. The columns and rows of the bits in the non-offset array are used to determine the address of the bits (step 188). In the above description, the address of the bit is address 6.

The "pull" second interleaving is described in connection with the preferred TDD / CDMA communication system, which, along with TDD / CDMA, FDD / CDMA, and TDSCDMA systems, is UE, base station, or node-B. It can be used in various applications such as.

As mentioned earlier, rate matching performs bit puncturing and iteration, not only reducing the number of channels required, but also ensuring that each channel is fully utilized. The rate matching engine 150 determines the address where each bit of the first interleaver buffer is inserted after the reverse rate matching. Rate matching mainly uses three variables: e-ini, e-plus, and e-minus. e-ini is the initial value for e used in the rate matching algorithm. e-plus is an incremental value for e used in the rate matching algorithm. e-minus is the decrement value for e used in the rate matching algorithm.

Rate matching is described in the flow charts of FIGS. 23-25. The rate matching engine 150 determines whether the data for a particular channel is non-turbo-encoded, such as convolutional-encoded, or turbo-encoded. If the channel is non-turbo encoded, the bits are treated as a single column.

Turbo coding uses one of three types of bits: systematic (S), parity 1 (P1), and parity 2 (P2). Puncturing is not performed on systematic bits. The rate matching engine 150 treats each of these types of bits as a separate column (step 190). Treating these bits as separate columns eliminates the need for explicit bit separation and bit collection, as described in the standard. This feature is handled by treating each column separately.

Unless turbo-coded puncturing (step 192) is required, addressing of these columns is performed by Equation 28 for puncturing and by Equation 28 for iteration and works well (step 194).

<maths num="2"><img file="JP4246751B2_D0002.tif" /></maths>

u is the address obtained by calculating the bits in the first interleaver buffer. p is the address of the bit before reverse rate matching.

Puncturing of turbo coded sequences is treated differently. As shown in Figures 24 and 25, two common approaches can be used to determine the address for these bits. In the first approach, as shown in Figure 24, the columns S, P1, and P2 are treated independently. Therefore, a large system of first-order indeterminate equations can be obtained. It is possible to solve these equations by imposing certain constraints on unknown variables, primarily limiting the addresses u and p to integer values (step 198). These constraints are used to narrow the solution space so that there is only one solution u for any given p. To implement this approach, approximate the number of punctures before the u address (step 200). Perform the search with sufficient space around the approximate value so that a valid solution can be found. Imposing known constraints on intermediate variables to find a valid solution (step 202).

The preferred method for applying the first approach is shown below. Systematic bits (S) are never punctured. Equation 30 describes the state of the "e" variable at the address u arbitrarily given in the puncturing operation on the P1 bit.

<maths num="3"><img file="JP4246751B2_D0003.tif" /></maths>

e₁Is the variable e for P1. Similarly

<maths num="4"><img file="JP4246751B2_D0004.tif" /></maths>

and

<maths num="5"><img file="JP4246751B2_D0005.tif" /></maths>

Is e for P1 respectivelyⁱⁿⁱ, E^-, And e⁺Is. u₁Is the number of bits in the P1 column before determining the address u. n₁Is u in the P1 column₁The number of punctured bits before the current value of.

Equation 31 describes the state of the "e" variable at the address u arbitrarily given in the puncturing operation on the P2 bit.

<maths num="6"><img file="JP4246751B2_D0006.tif" /></maths>

e₂Is the variable e for P2. Similarly

<maths num="7"><img file="JP4246751B2_D0007.tif" /></maths>and

<maths num="8"><img file="JP4246751B2_D0008.tif" /></maths>

Is e for P2 respectivelyⁱⁿⁱ, E^-, And e⁺Is. u₂Is the number of bits in the P2 column before determining the address u. n₂Is u in the P2 column₂The number of punctured bits before the current value of.

For a given p, use Equation 32.

up = n₁+ n₂ Equation 32

Equations 33 and 34 have been found to be true by examining the standard rate matching algorithm.

<maths num="9"><img file="JP4246751B2_D0009.tif" /></maths>

The above linear inequality group consists of 3 equations and 5 unknowns (u, e).₁, E₂, N₁, N₂). To get the solutions of these equations, n₁And n₂Find the approximate value of. Search for a sufficient spatial range centered on this approximation. This solution is determined based on the constraints of equations 33 and 34.

n₁And n₂To get an approximation of, replace u in Equation 32 with Equation 35.

<maths num="10"><img file="JP4246751B2_D0010.tif" /></maths>

Equation 36 is obtained.

<maths num="11"><img file="JP4246751B2_D0011.tif" /></maths>

γ is the puncturing ratio. This is determined by Equation 37.

<maths num="12"><img file="JP4246751B2_D0012.tif" /></maths>

The rate matching parameters determine the algorithm according to standard distribution puncturing of the P1 and P2 bits, unless an odd number of punctures are required. If an odd number of punctures are requested, P1 gets one extra puncture. The rate matching algorithm also allows you to have at most two P1 punctures in a row without P2 punctures. In addition, at most two P2 punctures can occur with the P1 puncture. Therefore, equations 38 and 39 are obtained.

n₁-n₂3 formula 38

n₂-n₁2 Equation 39

Equations 38, 39, and 36 are used to obtain equations 40 and 41.

<maths num="13"><img file="JP4246751B2_D0013.tif" /></maths>

Use these equations to find a small subspace containing the solution.

For any p for which the corresponding write address u is determined, the bit at that address position is not punctured (or never ends in the physical channel mapping buffer). Therefore, the value of e is e^-Must be greater than, giving equation 42.

<maths num="14"><img file="JP4246751B2_D0014.tif" /></maths>

Since this inequality is true for both x = 1 or 2 (for P1 or P2), we use the subscript x in general. Equations 30 and 31 are used to obtain Equation 43.

<maths num="15"><img file="JP4246751B2_D0015.tif" /></maths>

In equation 43, u is P_xTrue only for bits. u is P_xIf not a bit, Equation 44 applies.

<maths num="16"><img file="JP4246751B2_D0016.tif" /></maths>

Equations 45 and 46 are used to identify valid solutions.

<maths num="17"><img file="JP4246751B2_D0017.tif" /></maths>

Then perform a range check. If u is the P1 bit, use equation 47.

<maths num="18"><img file="JP4246751B2_D0018.tif" /></maths>

If u is a P2 bit, use equation 48.

<maths num="19"><img file="JP4246751B2_D0019.tif" /></maths>

If u is an S bit, use equation 49.

<maths num="20"><img file="JP4246751B2_D0020.tif" /></maths>

The second approach is shown below, as shown in Figure 25. Determine the rate matching input bit position p based on the position of u. Find the systematic ratio (step 204). The systematic ratio is based on the puncture ratio for the P1 and P2 columns. Systematic bit S by equation 50, etc._bitsEstimate the number of (step 206).

<maths num="21"><img file="JP4246751B2_D0021.tif" /></maths>

<maths num="22"><img file="JP4246751B2_D0022.tif" /></maths>

Is the estimated number of systematic bits. P1_PRIs the puncture ratio in the P1 row, P2_PRIs the puncture ratio of the P2 row.

Assume four cases, depending on the bit order (S, P1, P2 are forward, S, P2, P1 are reverse). S is

<maths num="23"><img file="JP4246751B2_D0023.tif" /></maths>Is the initial estimate of. The values for these cases are summarized in Table 1 below.

<tables num="1"><img file="JP4246751B2_D0024.tif" /></tables>

Select the four applicable rows in Table 1 based on the type of bit you want to analyze (top of column). To describe the P2 bits, select the last four rows (for the column most significant P2). If this bit is forward, the leftmost column is used. If this bit is in the opposite direction, the rightmost column is used. Find the output index for each row, using the appropriate four rows and the appropriate three columns in that row. To describe the forward P2 bits, four cases (Case 1-S, S, S, Case 2-S, S, S + 1, Case 3-S + 1, S, S + 1, Case 4- Use S + 1, S + 1, S + 1).

Using these four cases, we calculate four candidate output positions (step 208). Find the number of punctured bits for each candidate shown in Table 2. Table 2 below also shows the calculation results for the candidate output bit positions.

<tables num="2"><img file="JP4246751B2_D0025.tif" /></tables>

p1_PbitsIs the number of punctured P1 bits. p2_PbitsIs the number of punctured P2 bits. p1_Pbits_sin_iIs the number of initial P1 bits. p2_Pbits_sin_iIs the number of initial P2 bits.

The first candidate output bit position that matches the actual output bit position represents the number of S, P1, and P2 bits. Use this information to find the input bit position p (step 210).

"Pull" rate matching is described in the context of preferred TDD / CDMA communication systems, such as UE, base station, or node-B along with TDD / CDMA, FDD / CDMA, and TDSCDMA systems. It can be used in various applications.

The next step in this process is reverse bit scrambling. The bit scramble engine determines the bit scrambled address for the address output by the second interleaver.

The process of reverse bit scrambling is illustrated in the flow diagram of FIG. Scramble code p using bit position k in CCTrCH_kDetermine the corresponding bit of (step 400). Bit h_kScrambles, for example, by performing an exclusive OR with pk (step 402).

Although bit scrambling can be performed before reverse rate matching, it is preferably performed after reverse rate matching, as shown in FIG. 27 and illustrated in the flow diagram of FIG. 28. This embodiment allows all address mapping to be performed before manipulating bit values. For the bits specified after the reverse rate matching, the address after the reverse second interleaving (before the reverse rate matching) is determined (step 404). After the inverse second interleaving, the address of the specified bit is used to scramble the bit._k(Step 406). The specified bit is p_kP determined by executing exclusive OR with_kScramble using (step 408).

"Pull" bit scrambling is described in connection with the preferred TDD / CDMA communication system, which is used in various applications such as UE, base station, or node-B in TDD / CDMA systems. be able to.

Another approach can reduce buffering of the first interleaver, which is called "simplified first interleaver buffering". FIG. 29 is a block diagram of simplified first interleaver buffering.

As shown in FIG. 29, the output of the first interleaver 212 is not sent directly to the interleaver buffer. All physical layer buffering is shown in FIG. 29 as being performed by a single common memory 220. Transport channel data blocks are provided in one or more frames. This attribute is indicated by the TTI parameter. TTI is one of four possible values 10, 20, 40, and 80 ms. A TTI of 10 indicates that the data is for one frame, a TTI of 20 indicates two frames, a TTI of 40 indicates four frames, and an 80 indicates eight frames. The data for the first frame of TTI can be sent directly to the physical channel processor 218. Other frames in the TTI are buffered for later processing. Therefore, the entire first interleaver buffering is reduced by one frame. For the sake of explanation, assuming that the TTI is 10 ms, the single frame is stored directly in the physical channel buffer, and the first interleaver buffering is unnecessary. If the TTI is 80ms, you only need 7 frames of data instead of 8.

It is preferable to apply "simplified first interleaver buffering" to the "push" approach for physical layer processing. As a result, when the data is output from the first interleaver 212, it is written to the corresponding address in the physical channel mapping buffer, but other physical layer processing approaches can be used. Simplified first interleaver buffering can also be used when intermediate buffering, such as after rate matching and second interleaving, uses the physical layer processing approach used in physical channel processing. The data in the first frame is sent directly to the physical layer processing and stored in the intermediate buffer.

As shown in FIG. 23, the bits of all frames are input to the first MUX214. The first MUX214 sends the bits of the first frame to the second MUX216 by the physical channel processing block 218 for physical channel processing. Bits of other frames are sent to memory 220 (first interleaver buffer) via the first MUX 214 if the TTI is greater than 10 ms. The bits of the first frame are sent to the chip rate processing unit and transmitted on the air interface. Extract the bits of the subsequent frame from memory 230 via the second MUX216 for physical channel processing. All of these operations are monitored by physical channel controller 222.

Figures 30 and 31 show the "reduced first interleaver buffering" data flow for a 10 ms TTI (1 frame) transport channel databook. The transport channel bits are sent directly to the physical channel processor 218 and then to the physical channel buffer for subsequent chip rate processing without using the first interleaver buffer. As shown in FIG. 30, frame N is sent directly to the physical channel physical processor 218. As shown in FIG. 31, the next frame (Frame N + 1) is also sent directly to the physical channel physical processor 218.

Figures 32 and 33 show the "reduced first interleaver buffering" data flow for the 80ms TTI transport channel databook. The transport channel data of the first frame (Frame N) is sent to the physical layer processing and stored in the physical channel buffer (memory 220). The other frames (Frame N + 1 to N + 7) are stored in the physical channel buffer and high-pass the physical layer channel. In the next frame, as shown in Figure 33, (Frame N + 1) is sent to physical layer processing and stored in the physical channel buffer. The other frames (Frame N + 2 to N + 7) are sequentially processed by the same method in the next 6 frames. The chip rate processor reads one frame of data bits behind the current frame from the physical channel buffer. For example, if the physical layer processor is processing (Frame N + 1), the chip rate processor will be Frame. Read N. The processing approach applied to pairs with data with TTIs of 20 and 40 ms is the same as the 80 ms approach described above. The only difference is the number of frames buffered before physical channel buffering.

<figref num="1">It is a figure of a wireless TDD / CDMA communication system.</figref><figref num="2">It is a figure of a physical layer processing.</figref><figref num="3">It is a flow chart of the "push" approach.</figref><figref num="4">It is a simplified diagram of one embodiment of the "push" approach.</figref><figref num="5">It is a flow chart of "push" rate matching.</figref><figref num="6">It is a flow diagram of "push" bit scrambling.</figref><figref num="7">FIG. 3 is a simplified diagram of another embodiment of the "push" approach.</figref><figref num="8">FIG. 5 is a flow diagram of another embodiment of push bit scrambling.</figref><figref num="9">It is a flow chart of "push" second interleaving.</figref><figref num="10">This is an example of "push" second interleaving.</figref><figref num="11">It is a flow chart of "push" physical channel mapping.</figref><figref num="12">It is explanatory drawing which shows an example of the "push" physical channel mapping of case 2.</figref><figref num="13">It is explanatory drawing which shows an example of the "push" physical channel mapping of case 3.</figref><figref num="14">It is explanatory drawing which shows an example of the "push" physical channel mapping of case 4.</figref><figref num="15">It is a flow chart of the "pull" approach.</figref><figref num="16">It is a simplified diagram of one embodiment of the "pull" approach.</figref><figref num="17">It is a flow chart of "pull" inverse physical channel mapping.</figref><figref num="18">It is explanatory drawing which shows an example of the "pull" inverse physical channel mapping of case 2.</figref><figref num="19">It is explanatory drawing which shows an example of the "pull" inverse physical channel mapping of case 3.</figref><figref num="20">It is explanatory drawing which shows an example of the "pull" inverse physical channel mapping of case 4.</figref><figref num="21">It is a flow chart of the "pull" reverse second interleaving.</figref><figref num="22">It is explanatory drawing which shows an example of "pull" reverse 2nd interleaving.</figref><figref num="23">It is a flow chart of "pull" reverse rate matching.</figref><figref num="24">A flow diagram of one of two approaches to "pull" reverse rate matching of punctured turbo code sequences.</figref><figref num="25">A flow diagram of one of two approaches to "pull" reverse rate matching of punctured turbo code sequences.</figref><figref num="26">It is a flow chart of one Embodiment of "pull" reverse bit scrambling.</figref><figref num="27">It is a simplified diagram of another embodiment of the "pull" approach.</figref><figref num="28">FIG. 5 is a flow diagram of another embodiment of pull bit scrambling.</figref><figref num="29">It is a figure of "reduced first interleaver buffering".</figref><figref num="30">It is a block diagram showing an example of "reduced first interleaver buffering" for TTI of 10 milliseconds.</figref><figref num="31">It is a block diagram showing an example of "reduced first interleaver buffering" for TTI of 10 milliseconds.</figref><figref num="32">It is a block diagram which shows an example of "reduction 1st interleaver buffering" for TTI of 80 milliseconds.</figref><figref num="33">It is a block diagram which shows an example of "reduction 1st interleaver buffering" for TTI of 80 milliseconds.</figref>

Code description

78 Read / Write Controller 82 1st interleaver buffer 84 Physical channel buffer 86 Push address generation engine 88 rate matching engine 90-bit scrambling engine 92 Second interleaving engine 94 Physical channel mapping engine 96 Wireless Frame Segmentation Computation Engine 98 TrCH Multiplexer (MUX) Computational Engine 100 Physics Channel Segmentation Computation Engine 104 Physical mapping controller