Programming method of nonvolatile semiconductor memory device

The present invention is a non-volatile semiconductor including a memory cell array formed by arranging a plurality of memory cells having a charge storage region formed between a channel region and a control gate via an insulating film in the row direction and the column direction, respectively. The present invention relates to a storage device and a method for writing the memory cell array thereof, and more particularly to a non-volatile semiconductor storage device in which each memory cell can store data having three or more values.

Conventionally, as the most common flash memory as a non-volatile semiconductor storage device of this type, for example, there is an ETOX (EPROM Thin Oxide, a registered trademark of Intel Corporation in the United States) type flash memory.

FIG. 12 is a schematic cross-sectional view of a memory cell transistor constituting a memory cell of the ETOX type flash memory and an equivalent circuit thereof. As shown in FIG. 12, a floating gate 40 serving as a charge storage region is formed on the channel region 41 between the source 45 and the drain 46 via the tunnel oxide film 43, and is further controlled via the interlayer insulating film 44. A gate 42 is formed.

The operating principle of this ETOX type flash memory cell will be described. When writing to a memory cell, Vpp (for example, 9V) is applied to the control gate, the reference voltage Vss (for example, 0V) is applied to the source, and Vdp (for example, 5V) is applied to the drain. As a result, a large amount of current flows in the channel region between the source and the drain, hot electrons are generated in the portion where the electric field is high near the drain, electrons are injected into the floating gate, and the threshold voltage rises. That is, as shown in FIG. 13 (b), many electrons are injected into the floating gate.

When erasing a written memory cell, Vnn (for example, -9V) is applied to the control gate and Vpe (for example, 6V) is applied to the source, and electrons are drawn out in the vicinity of the source to lower the threshold voltage. That is, as shown in FIG. 13A, there are fewer electrons in the floating gate than in the writing state.

In an actual flash memory, the memory cells are not a single unit, but as shown in FIG. 2, a plurality of memory cells are arranged in an array to form a memory cell array. Multiple (n + 1) flash memory cell control gates are connected to the word line (WL0 to WLn), and multiple (m + 1 in Fig. 2) are connected to the bit line (BL0 to BLm). The drain of the flash memory cell is connected. In the case of FIG. 2, the memory cell array is composed of (n + 1) × (m + 1) flash memory cells.

In the memory cell array composed of a plurality of memory cells as described above, since a plurality of memory cells having different threshold voltages can coexist, these threshold voltages have a distribution corresponding to the number of memory cells.

These threshold voltage states are shown in FIG. FIG. 14 shows the distribution of the threshold voltage of each memory cell with respect to the memory cell array in which a plurality of the above-mentioned flash memory cells are arranged. The horizontal axis is the threshold voltage of the memory cell, and the vertical axis is the threshold voltage shown by the horizontal axis. Indicates the number of memory cells in the memory cell array with. In FIG. 14, the distribution of 4.5 V or more (threshold voltage range) with a high threshold voltage represents the memory cell in the write state (program state), and the distribution of 3 V or less (threshold voltage range) with a low threshold voltage is the erased state (erase). Represents a memory cell in the state). If the threshold voltage of the flash memory cell belongs to any of the two threshold voltage ranges shown in FIG. 14, it can be seen that two states (storage states) can be identified by one flash memory cell.

To read the storage state of such a memory cell, Vdr (for example, 1V) is applied to the drain, and Vgr (for example, 5V) is applied to the control gate. For example, when the threshold voltage is in the low threshold voltage range in the erased state, a current flows through the memory cell, and it is determined that the data is 1. On the other hand, when the threshold voltage is in the high threshold voltage range in the programmed state, no current flows in the memory cell, and it is determined that the data is 0.

In the write operation sequence of the ETOX type flash memory, Vgv (for example, 5 V) is set to the control gate as a read step for verifying whether or not the threshold voltage has changed within the desired threshold voltage range, that is, whether or not the write has been performed normally. Vdv (for example, 1V) is applied to the drain to read the data, and write verification is performed to compare it with a predetermined reference voltage.

In the ETOX type flash memory, by providing three or more threshold voltage ranges shown in FIG. 14, it is possible to realize multi-value storage larger than one bit (two values) in one memory cell. As a multi-valued method for setting data of three or more values, a writing method is generally used as needed, in which writing and verification are repeatedly executed from a low threshold voltage range to a high threshold voltage range. This is described in, for example, Non-Patent Documents 1 to 3 below.

FIG. 4 shows an example of the threshold voltage distribution when four threshold voltage ranges are provided. As shown in FIG. 4, the 2-bit storage states 11, 10, 01, and 00 are assigned in order from the state where the threshold voltage is low. Further, FIG. 15 shows the relationship between the four threshold voltage ranges shown in FIG. 4 and the number of electrons injected into the floating gate of the flash memory cell.

As the number of electrons in the floating gate increases, the threshold voltage of the flash memory cell also increases. That is, the state where there are no (small) electrons in the floating gate is the state where the threshold voltage is the lowest (here, the storage state 11 (Data 11 in FIG. 4)), and the threshold voltage range of the memory cell is 3.0V. It is as follows. The state in which electrons are injected into the floating gate rather than the storage state 11 and the threshold voltage range of the flash memory cell becomes 3.7V to 4.2V is defined as the storage state 10 (Data 10 in FIG. 4). The state in which electrons are injected into the floating gate rather than the storage state 10 and the threshold voltage range of the flash memory cell becomes 4.7V to 5.2V is defined as the storage state 01 (Data 01 in FIG. 4). The state in which more electrons than the storage state 01 are injected into the floating gate and the threshold voltage range becomes 5.7V or more is defined as the storage state 00 (Data 00 in FIG. 4).

FIG. 16 is a flow diagram showing a conventional as-needed write sequence in the case where four values are stored in one memory cell in this way. Further, FIG. 17 shows the operation according to the writing sequence shown in FIG. 16 in chronological order by the word line voltage and the bit line voltage. The waveform of each rectangle in FIG. 17 represents the word line voltage and the bit line voltage in both the write and verify operations, and the corresponding operation steps are assigned the same step numbers in FIGS. 16 and 17.

It is assumed that the threshold voltage in the initial state of the memory cell is in the threshold voltage range corresponding to the storage state 11. The word line voltage that sets this memory cell in the threshold voltage range corresponding to the storage state "10" is Vg10, the word line voltage that sets the threshold voltage range in the storage state "01" is Vg01, and the threshold voltage in the storage state "00". The word line voltage set in the range is Vg00. Here, the mutual relationship of each word line voltage is Vg10 <Vg01 <Vg00. As described in Non-Patent Document 3, if the threshold voltage after writing to the control gate of the memory cell with Vgp is Vt, the voltage given to the control gate is increased by ΔVgp and writing is performed. The threshold voltage of the memory cell rises from Vt by ΔVgp. That is, in order to increase the threshold voltage of the memory cell, it is necessary to increase the voltage applied to the control gate by the amount of increase in the threshold voltage.

A conventional as-needed write sequence will be described with reference to FIG. When writing to the storage state 00 with the storage state 11 as the initial state of the memory cell (ST1), first set the word line voltage to Vg10 and wait until the voltage stabilizes, and then set the bit line to the amplitude Vdp (for example, 5V). A voltage pulse with a pulse width of Wp (for example, 1 μsec) is applied as a voltage to write to the storage state 10 (ST2), the word line voltage is set to the verify voltage Vgv, and the bit line voltage is set to the verify voltage. After switching to Vdv and stabilizing each voltage, verify the storage state "10" by reading operation (ST3). As a result of verification, it is determined whether the threshold voltage has reached the threshold voltage range corresponding to the storage state "10" for all the written memory cells (ST4), and for the memory cells that have not reached the threshold voltage, the word at the time of writing is used. Increase the line voltage Vg10 by ΔVg10 (ST5), write (ST2) and verify (ST3) to apply the word line voltage and bit line voltage pulse again, and all memory cells correspond to the storage state 10. Repeat steps 2 to 5 until the threshold voltage reaches the threshold voltage range (ST4). In FIG. 17, this corresponds to the 10 writing period.

After the threshold voltage of all the memory cells to be written reaches the threshold voltage range corresponding to the storage state "10", the word line voltage is switched to Vg01, and after the word line voltage stabilizes, the pulse width Wp swings to the bit line. The voltage pulse of is applied to write to the storage state "01" (ST6). Subsequently, the word line voltage is switched to the verification voltage Vgv, the bit line voltage is switched to the verification voltage Vdv, and after each voltage stabilizes, the storage state 01 is verified by the read operation (ST7). Similar to writing to the storage state 10, the word line voltage is increased by ΔVg01 (ST9) until all the memory cells to be written reach the threshold voltage range corresponding to the storage state 01 (determined by ST8). , Repeat writing (ST6) and verifying (ST7) to apply the word line voltage and bit line voltage pulse. In FIG. 17, this corresponds to the 01 writing period.

After the threshold voltage of all the memory cells to be written reaches the threshold voltage range corresponding to the storage state 01, the word line voltage is switched to Vg00, and after the word line voltage stabilizes, the procedure is the same as in step ST6. Write to the storage state 00 (ST10). Subsequently, the voltage for verification is switched to Vgv, the bit line voltage is switched to the voltage for verification Vdv, and after each voltage is stabilized, the storage state 00 is verified by the read operation (ST11). Write by increasing the word line voltage by ΔVg00 (ST13) and applying the word line voltage and bit line voltage pulse until all the memory cells to be written reach the threshold voltage range corresponding to the storage state 00 (ST12). When ST10) and verify (ST11) are repeated and the threshold voltages of all the memory cells to be written reach the threshold voltage range corresponding to the storage state 00 (ST13), the writing is completed. In FIG. 17, this corresponds to the 00 writing period.

As described above, in the conventional occasional writing sequence, the writing process of the storage state 10 (ST2 to 5) and the writing process of the storage state 01 (ST6 to 9) are completed before the writing to the storage state 00 is completed. ), Each writing process (ST10 to 13) of the storage state 00 exists, and in each writing process, the threshold voltage of all the memory cells to be written reaches the threshold voltage range corresponding to each storage state 10. Does not complete and does not move to the next writing process. If a part of the memory cell to be written is not written to the storage state "00" but is written to the storage state "10" or the storage state "01", the memory cell is stored. Only the writing process of the state 10 or the writing process of the storage states 10 and 01 will be executed, but the time required for writing is the maximum when writing to the storage state 00. ..<nplcit num="1"><text>A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories IEEE Journal Of Solid-State Circuits, Vol.31, No.4, April 1996</text></nplcit><nplcit num="2"><text>A 117-mm2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications IEEE Journal Of Solid-State Circuits, Vol.31, No.11, November 1996</text></nplcit><nplcit num="3"><text>40-mm2 3-V-Only 50-MHz 64-Mb 2-b / Cell CHE NOR Flash Memory IEEE Journal Of Solid-State Circuits, Vol.35, No.11, November 2000</text></nplcit>

<p> When the above-mentioned conventional occasional write sequence is adopted as the multi-value writing method of the ETOX type flash memory cell, when writing from a certain initial state to another storage state, there is another storage state in the middle. In addition, since the writing to the intermediate storage state is completed step by step, the verification step is also required for the writing to the intermediate storage state. As a result, it is necessary to switch between the word line voltage and the bit line voltage for the intermediate verification process, the waiting time until these voltages stabilize becomes long, and the write time until the write operation is completed becomes long. The inconvenience of becoming longer occurs. Further, since the number of verifications until the final writing is completed increases, the writing time becomes longer.</p><p> For a memory cell array composed of a plurality of memory cells, it is necessary to narrow the threshold voltage range corresponding to each storage state in order to secure a margin at the time of reading, so that the threshold voltage change at the time of writing is highly accurate. If measures such as setting a low word line voltage at the time of writing or narrowing the write pulse width in order to control with are taken, the number of writes and verifications increases, and the write time becomes longer. There is.</p><p> The present invention has been made in view of the above problems, and an object of the present invention is to provide a writing method capable of writing multi-valued data at high speed in a non-volatile semiconductor storage device in which a memory cell can store data having three or more values. There is.</p>

<p> The writing method of the non-volatile semiconductor storage device according to the present invention for achieving the above object has a transistor in which a charge storage region is formed between a channel region and a control gate via an insulating film, and the charge storage region has a transistor. A plurality of memory cells capable of having three or more storage states including two or more write states according to the level of the threshold voltage determined according to the amount of charge are arranged in the row direction and the column direction, respectively, and the memory cells in the same row are arranged. A non-volatile semiconductor storage device comprising a memory cell array configured by connecting the control gates of the above to each other to form a common word line and connecting the drains of the memory cells in the same row to each other to form a common bit line. In the writing method, a plurality of write gate voltages corresponding to each of the two or more write states are set in advance, and a threshold voltage range corresponding to the storage state before writing and a threshold voltage range after writing are set in the memory cell to be written. When there is at least one threshold voltage range corresponding to another storage state between the threshold voltage range corresponding to the storage state, at least one other of the word line connected to the write target memory cell. A first write step of applying at least one first write gate voltage corresponding to each of the storage states of the above, and applying a predetermined write / drain voltage to the bit line connected to the write target memory cell, and the write A second write gate voltage corresponding to the write state after writing is applied to the word line connected to the target memory cell, and a predetermined write drain voltage is applied to the bit line connected to the write target memory cell. The first feature is to execute a verification step for verifying whether or not the write target memory cell has been written after each of the second write steps has been executed.</p><p> The writing method of the non-volatile semiconductor storage device according to the present invention having the first feature described above is a method of writing multivalued data to a multivalued memory cell in which the memory cell can take three or more storage states including two or more write states. In the writing method, the threshold voltage of the transistor constituting the memory cell is applied to the control gate in relation to the word line, and the writing gate voltage corresponding to the storage state after writing is applied to the control gate to obtain the threshold voltage of the memory cell to be written. It can be contained in the threshold voltage range corresponding to the target storage state. Here, when the threshold voltage before writing of the memory cell to be written is low and the threshold voltage after writing is high, the write gate voltage to be applied also becomes high, so that an excessive drain current flows through the memory cell and consumption during writing. Since there is a problem that the current, especially the peak current, increases, in order to avoid this, between the threshold voltage range corresponding to the storage state before writing and the threshold voltage range corresponding to the storage state after writing, etc. If there is at least one threshold voltage range corresponding to the storage state of, write to the other storage state and then perform stepwise writing to finally reach the desired write state. To do. By the way, according to the writing method of this feature, even if writing to another storage state is executed, the writing operation to the final target writing state is continuously performed without performing the verify operation. , The delay time associated with the intermediate verification operation can be avoided, and the writing time until the writing is finally completed can be significantly shortened. Furthermore, even if the intermediate verification operation is omitted, the corresponding write gate voltage is applied to the writing to the other storage states existing in the middle, regardless of whether the writing is complete or incomplete, and thus the memory cell. Since the threshold voltage of is surely high, the effect of suppressing the current consumption is sufficiently achieved, and the verification operation for the final writing state is surely executed. Therefore, the threshold voltage after writing is the purpose. It can be kept within the threshold voltage range corresponding to the storage state.</p><p> Here, when the threshold voltage before writing of the memory cell to be written is in the lowest threshold voltage range, the worst condition is in terms of current consumption, but even if the threshold voltage before writing is in the lowest threshold voltage range. If the other storage states in the middle increase by that amount, the first write gate voltage in the first write process increases, and the threshold voltage of the memory cell to be written gradually increases, which is excessive. The problem of drain current flowing is solved. Further, as the number of possible storage states of one memory cell increases, the number of other storage states in the middle increases, and the number of times the first write gate voltage is applied in one first write process increases, but it is verified. Since the process is fixed to one for a series of first write process and second write process regardless of the number of storage states, that is, the multi-value level, the larger the multi-value level, the longer the write time. However, the effect of shortening the writing time is also increased.</p><p> In addition to the first feature, the writing method further includes, in the first writing step and the second writing step, when it is determined in the verification step that the memory cell to be written is not written. The second feature is that at least the second writing step is executed again.</p><p> According to the writing method having the second feature, the threshold voltage of the memory cell to be written can be finally set within the threshold voltage range corresponding to the target storage state. That is, in the verification step, among the first write step and the second write step, until it is confirmed that the memory cell to be written is written (the threshold voltage falls within the threshold voltage range corresponding to the target storage state). By repeatedly executing at least the second writing step, the threshold voltage of the memory cell to be written is finally kept within the threshold voltage range corresponding to the target storage state unless the memory cell is a completely defective cell. be able to. Here, since the threshold voltage before writing is high in the first writing step of the first time, the effect of suppressing the current consumption can be sufficiently expected even if the first writing step is omitted in the second and subsequent times.</p><p> When there are a plurality of memory cells to be written on the same word line, it is determined that writing has not been performed in the verification process, so that there are a plurality of memory cells, and the final write state of one of them is the final of the other memory cells. Since it is naturally possible that the other memory state is in the middle of the specific write state, at least the first write gate voltage is applied to the other memory cells in the first write step, so that the first write In some cases, both the process and the second writing process may be performed. However, assuming a flash memory cell, the first write gate voltage is lower than the second write gate voltage, so that the execution of the first write step does not significantly affect the change in the threshold voltage.</p><p> In addition to the second feature, the writing method further executes the first writing gate voltage or the first writing gate voltage applied in at least one of the first writing step and the second writing step to be executed again. 2 The third feature is that the write gate voltage is set higher than the respective voltage values in the first write step or the second write step applied for the first time.</p><p> According to the same writing method having the third feature, the write gate voltage is set high in the second and subsequent first write steps or the second write steps to be executed again, so that the memory cell is difficult to write. On the other hand, writing can be promoted, the number of repetitions of the first writing process or the second writing process can be suppressed to a small number, and the worst writing time, which is rate-determined by a memory cell that is difficult to write, can be shortened.</p><p> In the writing method, in addition to the second or third feature, the first writing gate voltage applied in at least one of the first writing step and the second writing step after the second execution is executed again. Alternatively, the fourth feature is that the write period in which the second write gate voltage is applied to the write target memory cell at the same time as the write drain voltage is set to be longer than the first write period.</p><p> According to the same writing method having the fourth feature, the gate in one writing step is performed in the second and subsequent first writing steps or the second writing steps to be executed again, as in the third feature. Since the effective application period of the voltage is set to be long, it is possible to promote writing to a memory cell that is difficult to write, and to reduce the number of repetitions of the first writing process or the second writing process, which makes it difficult to write. The worst write time, which is rate-determined by the memory cell, can be shortened in total.</p><p> The writing method has a transistor in which a charge storage region is formed between a channel region and a control gate via an insulating film, and depends on the level of the threshold voltage determined according to the amount of charge in the charge storage region 2 A plurality of memory cells capable of having three or more storage states including the above write states are arranged in the row direction and the column direction, respectively, and the control gates of the memory cells in the same row are connected to each other to form a common word line. It is a writing method of a non-volatile semiconductor storage device including a memory cell array configured as a common bit line by connecting the drains of the memory cells in the same row to each other, and corresponds to each of the two or more writing states. When writing to two or more write target memory cells connected to the same word line at the same time by setting a plurality of write gate voltages to be performed simultaneously, the word line connected to the two or more write target memory cells may be used. Two or more write gate voltages corresponding to two or more write states including the write state after writing are sequentially applied in ascending order of voltage value, and are connected to the write target memory cell at the same time as each application of the write gate voltage. After executing a write step of applying a predetermined write / drain voltage to at least one of the bit lines, it is the first to execute a verification step of verifying whether or not the two or more write target memory cells have been written respectively. It has 5 features.</p><p> The writing method having the fifth feature is a method of writing multi-valued data to a multi-valued memory cell in which the memory cell can have three or more storage states including two or more writing states, and the memory cell is used. By applying the threshold voltage of the constituent transistors to the control gate in relation to the word line, the write gate voltage corresponding to the storage state after writing is applied to the threshold voltage of two or more write target memory cells connected to the same word line. The voltage can be contained in the threshold voltage range corresponding to each target storage state. Here, the memory cell having the higher threshold voltage range corresponding to the target storage state has a longer write time in memory cell units, but at least the other memory cell is written after writing. The application of the write gate voltage corresponding to the state becomes the first write step in the write method of the first feature, and the same effect of shortening the write time and reducing the current consumption as the write method of the first feature. Is exhibited at the same time. As a result, the writing time can be shortened for all the memory cells to be written at the same time.</p><p> Further, even when all of the two or more write target memory cells are in the write state after the same write, the write gate voltage of two or more is applied sequentially in ascending order of the voltage value, so that the write gate voltage having the lower voltage value is used. If the write gate voltage is set lower than the write gate voltage corresponding to the write state after writing, the write gate voltage applied first becomes the first write step in the write method of the first feature, and the write gate voltage of the first feature is described. The same effect as the writing method, that is, the effect of shortening the writing time and the effect of reducing the current consumption are exhibited at the same time.</p><p> In addition to the fifth feature, the writing method further applies to the writing gate having a voltage value lower than the writing gate voltage corresponding to the writing state after writing to the two or more writing gate voltages applied in the writing step. The sixth feature is that voltage is included.</p><p> According to the same writing method having the sixth feature, the writing state after writing is also applied to the memory cell having the lower threshold voltage range corresponding to the target storage state among the two or more memory cells to be written. Since a write gate voltage having a voltage value lower than the write gate voltage corresponding to the above is applied, the application becomes the first write step in the write method of the first feature, and is the same as the write method of the first feature. , The effect of reducing current consumption is exhibited. Further, the application also exerts the effect of reducing the current consumption of the memory cell having the higher threshold voltage range corresponding to the target storage state.</p><p> In the writing method, in addition to the fifth or sixth feature, in the writing step, the bit line to which the predetermined write drain voltage is applied is the write target memory cell connected to the bit line. The threshold voltage range corresponding to the storage state before the predetermined write-drain voltage is applied is lower than the threshold voltage range corresponding to the write state that determines the write gate voltage applied when the predetermined write-drain voltage is applied. It has 7 features.</p><p> According to the writing method having the seventh feature, the predetermined write-drain voltage is applied only when the threshold voltage of the memory cell to be written becomes high, so that the threshold voltage already corresponds to the target storage state. It is possible to prevent the write gate voltage and the write drain voltage from being applied to the write target memory cell within the threshold voltage range to be overwritten and excessively written beyond the appropriate threshold voltage range.</p><p> In addition to the above-mentioned fifth to seventh features, the writing method further repeats the writing step when it is determined in the verification step that at least one of the writing target memory cells has not been written. The eighth feature is to execute.</p><p> According to the writing method having the eighth feature, finally, all the threshold voltages of the two or more write target memory cells can be kept within the threshold voltage range corresponding to the target storage state.</p><p> Further, in the same writing method, in addition to the eighth feature, the written memory cell determined to be written in the verification step from the write target memory cell in the second and subsequent write steps to be executed again. The ninth feature is to exclude.</p><p> According to the same writing method having the ninth feature described above, the bit line connected to the written write target memory cell by executing the second and subsequent write steps only on the unwritten write target memory cell. Is not unnecessarily charged and discharged, the current consumption can be reduced, and the above-mentioned excessive writing can be prevented.</p><p> In addition to the eighth feature, the writing method applies to two or more write gate voltages applied in at least the first writing step among the first and second and subsequent writing steps to be executed again. The tenth feature is that the write gate voltage having a voltage value lower than the write gate voltage corresponding to the write state after writing is included.</p><p> According to the writing method having the tenth feature, the write gate voltage corresponding to the write state is applied stepwise to all of two or more write target memory cells at least once. , Excessive drain current flows through the memory cell, and it is possible to prevent the current consumption during writing, particularly the peak current, from increasing. Further, in the second and subsequent writing steps, the writing time can be shortened by arbitrarily stopping the application of the writing gate voltage having a voltage value lower than the writing gate voltage corresponding to the writing state after writing.</p><p> The non-volatile semiconductor storage device according to the present invention has a transistor in which a charge storage region is formed between a channel region and a control gate via an insulating film, and a threshold voltage determined according to the amount of charge in the charge storage region. A plurality of memory cells capable of having three or more storage states including two or more write states are arranged in the row direction and the column direction, respectively, and the control gates of the memory cells in the same row are connected to each other. A memory cell array configured as a common bit line by connecting the drains of the memory cells in the same column to each other as a common word line, and the word line connected to the memory cell to be written are in the writing state of two or more. A writing means that selectively applies a plurality of preset write gate voltages corresponding to each and applies a predetermined write / drain voltage to the bit line connected to the write target memory cell, and the write target memory cell. A non-volatile semiconductor storage device including a verification means for verifying whether or not has been written, in which a threshold voltage range corresponding to a storage state before writing and a storage state after writing are stored in the memory cell to be written. When there is at least one threshold voltage range corresponding to another storage state between the threshold voltage range corresponding to, the writing means has at least one on the word line connected to the writing target memory cell. A first write step in which at least one first write gate voltage corresponding to each of the other storage states is applied, and a predetermined write / drain voltage is applied to the bit line connected to the write target memory cell. A second write gate voltage corresponding to the write data is applied to the word line connected to the write target memory cell, and a predetermined write drain voltage is applied to the bit line connected to the write target memory cell. The first feature is that after each of the second write steps is executed, the verify means executes a verify step for verifying whether or not the write data has been written to the write target memory cell.</p><p> According to the non-volatile semiconductor storage device according to the present invention having the first feature, the writing means is the first writing in the writing method of the non-volatile semiconductor storage device according to the present invention having the first to fourth features. Since the step and the second writing step are executed and the verifying means executes the verifying step after executing the first writing step and the second writing step, the non-volatile semiconductor storage device according to the present invention having the first to fourth features described above is executed. The effect of the writing method can be achieved, and the writing time can be significantly reduced.</p><p> The non-volatile semiconductor storage device further has a transistor in which a charge storage region is formed between a channel region and a control gate via an insulating film, and has a threshold voltage determined according to the amount of charge in the charge storage region. A plurality of memory cells capable of having three or more storage states including two or more write states depending on the level are arranged in the row direction and the column direction, respectively, and the control gates of the memory cells in the same row are connected to each other and are common. A memory cell array configured as a common bit line by connecting the drains of the memory cells in the same column to each other and the word line connected to the memory cell to be written to each of the two or more write states. A writing means that selectively applies a plurality of preset write gate voltages and applies a predetermined write / drain voltage to the bit line connected to the write target memory cell, and the write target memory cell In a non-volatile semiconductor storage device including a verification means for verifying whether or not writing has been performed, the writing means is used when writing to two or more write target memory cells connected to the same word line at the same time. , Two or more write gate voltages corresponding to two or more write states including the write state after writing are sequentially applied to the word lines connected to the two or more write target memory cells in ascending order of voltage value. After executing a write step of applying a predetermined write drain voltage to at least one of the bit lines connected to the write target memory cell at the same time as each application of the write gate voltage, the verify means has two or more of the above. The second feature is to execute a verification process for verifying whether or not each memory cell to be written has been written.</p><p> According to the non-volatile semiconductor storage device according to the present invention having the second feature, the writing means performs the writing step in the writing method of the non-volatile semiconductor storage device according to the present invention having the first to fourth features. Since the verifying means executes the verifying step after executing the writing step, the effect of the writing method of the non-volatile semiconductor storage device according to the present invention of the fifth to tenth features can be exhibited, and the writing time can be achieved. Can be significantly shortened.</p><p> In the non-volatile semiconductor storage device, in addition to the first or second feature, the write state that the memory cell can take for each verification target memory cell that the verify means simultaneously executes the verification step. A third feature is that a plurality of sense amplifiers corresponding to the number of the above-mentioned sense amplifiers are provided, and reference voltages having different unique voltage values are used for each of the plurality of sense amplifiers.</p><p> In addition to the first or second feature, the non-volatile semiconductor storage device further comprises one sense amplifier for each verification target memory cell in which the verification means simultaneously executes the verification step. A fourth feature is that a plurality of reference voltages having different voltage values depending on the number of write states that the memory cell can take are selectively used in the sense amplifier via the switch circuit.</p><p> According to the non-volatile semiconductor storage device according to the present invention having the third or fourth feature, writing is performed by setting the lower limit of the threshold voltage range corresponding to the target storage state as the reference voltage of the sense amplifier. It can be determined that the threshold voltage of the target memory cell has increased due to the application of the write gate voltage and the write drain voltage and has entered the threshold voltage range, and the verifying means verifies whether or not the write target memory cell has been written. be able to.</p>

An embodiment of a non-volatile semiconductor storage device (hereinafter, appropriately referred to as the device of the present invention) and a writing method thereof (hereinafter, appropriately referred to as the method of the present invention) according to the present invention will be described with reference to the drawings. ..

&lt;First Embodiment&gt; FIG. 1 is a block configuration diagram showing a functional schematic configuration of an embodiment of the apparatus 10 of the present invention. In FIG. 1, input circuits such as a plurality of address input signals (ADD in the figure), a plurality of data input signals (DI in the figure), a plurality of control signals (CTRL in the figure), and a plurality of data output signals (in the figure). Since the details of the output circuit such as DO) and the peripheral circuits such as the decoder circuit of the address input signal are the same as those of a known non-volatile semiconductor storage device such as a flash memory, the description thereof is omitted. FIG. 1 mainly describes the circuit portion related to the writing operation of the main memory array 11 (hereinafter, simply referred to as the memory array 11) of the apparatus 10 of the present invention.

As shown in FIG. 1, the apparatus 10 of the present invention includes a memory array 11, a reference memory array 12, a word line voltage supply circuit 13 for supplying a word line voltage to the word lines of the memory array 11 and the reference memory array 12, and a memory array 11. And the bit line voltage supply circuit 14 that supplies the bit line voltage to the bit line of the reference memory array 12, the read voltage read from the selected bit line of the memory array 11, and the selected bit line of the reference memory array 12. A sense amplifier array 15 composed of a plurality of sense amplifiers that verifies the write status of a plurality of selected memory cells of the memory array 11 by comparing with the reference voltage read from, word during the write process. Write gate voltage supplied as line voltage and write voltage generation circuit that generates write drain voltage supplied as bit line voltage 16, verify gate voltage supplied as word line voltage and supply as bit line voltage during verification process It is configured to include a read-out voltage generating circuit 17 that generates a verified drain voltage, and a control circuit 18 that controls the operation of each of the above circuits 13 to 17.

As shown in FIG. 2, the memory array 11 arranges a plurality of memory cells 100 in the row direction and the column direction, respectively, and connects a plurality of control gates of the memory cells 100 in the same row to each other to connect a plurality of common word lines WL0 to. As WLn, a plurality of drains of memory cells 100 in the same column are connected to each other to form a common bit line BL0 to BLm, and the sources of each memory cell 100 are connected to each other to form a common source line SL. User data is stored in memory array 11. As shown in FIG. 12, the memory cell 100 has a transistor structure similar to that of a floating gate type flash memory cell such as a conventional ETOX type flash memory, and insulating films 43 and 44 are provided between the channel area 41 and the control gate 42. It is composed of transistors formed by a floating gate (floating gate) 40 that functions as a charge storage region through the floating gate 40, and is in a writing state of 2 or more depending on the threshold voltage level of the transistor determined according to the amount of charge of the floating gate 40. Can have 3 or more memory states including.

Similar to the memory array 11, the reference memory array 12 is also configured by arranging the flash memory cells 100 in an array as shown in FIG. A reference voltage is supplied to the sense amplifier in the verification of the write operation and the normal array read operation. By using the same word line as the memory array 11, deterioration of the read margin is prevented. Here, the memory cells 100 in each column of the reference memory array 12 are set (programmed) in advance to a predetermined threshold voltage specifically for array read, write verification, and erase verification.

The word line voltage supply circuit 13 selects the write gate voltage generated by the write voltage generation circuit 16 in the writing process under the control of the control circuit 18 according to the writing procedure described later, and sets the word line selected by the address input signal. In the supply and verification step, the verify gate voltage generated by the read voltage generation circuit 17 is supplied to the same selection word line. Under the control of the control circuit 18, the bit line voltage supply circuit 14 sets the write drain voltage generated by the write voltage generation circuit 16 as a voltage pulse having a predetermined pulse width on the bit line selected by the address input signal in the writing process. In the supply and verification step, the verify drain voltage generated by the read voltage generation circuit 17 is supplied to the same selection bit line.

In the verification process, the verify gate voltage and the verify drain voltage generated by the read voltage generation circuit 17 are selected by the word line voltage supply circuit 13 and the bit line voltage supply circuit 14, respectively, in the memory array 11 and the reference memory array 12. Applied to the cell, the read voltage of the memory array 11 and the read voltage (reference voltage) of the reference memory array 12 are connected to each sense amplifier of the sense amplifier array 15, and the output of each sense amplifier is output to the control circuit 18. Then, the control circuit 18 makes a verification determination (determination of whether or not writing has been performed), and the determination result is used for controlling the writing sequence of the method of the present invention. The details will be described later. On the other hand, at the time of normal reading, the output of each sense amplifier is connected to an output buffer circuit (included in the control circuit 18 in FIG. 1) and output to an external output terminal as data output.

The control circuit 18 receives a write signal from the outside (a control signal input or a write instruction by a command input by a data input signal), controls the write sequence of the method of the present invention (switching between a write process and a verify process), and a word. Set the line voltage and bit line voltage, and adjust the application time. In addition, a memory cell to which a write pulse (bit line voltage) is applied is also selected based on the data to be written or the verification result.

The method of the present invention relates to a method of writing multi-valued data to a memory cell or a memory cell array, and is controlled by a control circuit 18 in FIG. Hereinafter, for the sake of simplicity, the method of the present invention that realizes a reduction in the writing time assuming the case where the multi-value level is four values will be described with reference to the flowchart shown in FIG.

As shown in FIG. 4, the storage states of the memory cells are stored in four values (2 bits) in order from the state with the lowest threshold voltage range, 11 (for example, the threshold voltage range of 1.0 V or more and 3.0 V or less), 10. "(For example, a threshold voltage range of 3.7V or more and 4.2V or less)," 01 "(for example, a threshold voltage range of 4.7V or more and 5.2V or less)," 00 "(for example, a threshold voltage range of 5.7V or more and 6.2V or less) It shall be. In addition, FIG. 5 shows the voltage pulse waveforms of the word line voltage and the bit line voltage applied to the control gate and drain of each memory cell. In Fig. 5, the thick solid line shows the word line voltage and the broken line shows the bit line voltage. The source (common source line) of each memory cell is grounded during the writing and verifying steps.

Hereinafter, the writing sequence to the memory cell and the memory cell array by the method of the present invention will be described with reference to FIGS. 3 and 5. First, an embodiment of the method of the present invention will be described by focusing on one memory cell. Consider a case where writing is performed so that the threshold voltage of the memory cell falls within the threshold voltage range corresponding to the storage state 00. Here, the threshold voltage in the initial state of the memory cell may correspond to any of the storage states of "11", "10", "01", and "00", but here, the storage state "11" It is assumed that the threshold voltage corresponds to. As the initial state of each voltage, for example, it is assumed that the word line voltage is 0V, the bit line voltage is 0V, and the source voltage is 0V (the source voltage is fixed at 0V during the writing period) (ST20). The reading of the write data (corresponding to the target storage state) (00 in this embodiment) and the reading of the current (before writing) storage state of the memory cell to be written (11 in this embodiment) are , Executed in the preprocessing stage (ST20).

From this initial state, the voltage is set to Vg10 [n] (for example, 6V. The period of t_0-Vgp in Fig. 5) for the word line, the amplitude is set to Vdp10 [n] (for example, 5V) for the bit line, and the pulse width is Wp10 [n] (for example, 1 μsec). Apply a write voltage pulse (during Wp10 in Figure 5) (ST21). Here, n is 0 or a natural number and represents the number of series of rewrite cycles described later. Here, n = 0 is set in order to explain the writing from the initial state. After applying this write pulse, the threshold voltage of the memory cell rises from 3.0 V or less to around 3.7 V. Note that n indicating the number of rewrites is irrelevant to the number n of word lines WL of the memory array 11 shown in FIG.

Next, the word line voltage is switched to Vg01 [0] (for example, 7V) (the period of t_Vgp-Vgp in FIG. 5), and the pulse width Wp01 [0] (for example, 1 μsec) is applied to the bit line with the amplitude Vdp01 [0] (for example, 5V). Apply a write pulse (during Wp01 in Figure 5) (ST22). Due to this write pulse, the threshold voltage of the memory cell rises to around 4.7V. Furthermore, the word line voltage is changed to Vg00 [0]. Switch to (for example, 8V) (t_Vgp-Vgp period in Fig. 5), and write pulse with pulse width Wp00 [n] (for example, 1μsec, period of Wp00 in Fig. 5) with amplitude Vdp00 [0] (for example, 5V) on the bit line. Apply (ST23). At this time, the threshold voltage of the memory cell to be written reaches about 5.7V. Here, the word line voltage at the time of writing to each storage state has a relationship of Vg10 [n] &lt;Vg01 [n] &lt;Vg00 [n] as in the conventional writing sequence, but the method of the present invention is different from the conventional one. The verify operation is not performed every time a write pulse is applied. As described above, steps ST21 to ST23 are the writing steps of the method of the present invention, and in particular, steps ST21 and ST22 are referred to as a first writing step, and steps ST23 are referred to as a second writing step.

Next, after completing all the writing steps of steps ST21 to ST23, the verifying steps (ST24, ST25) are executed. First, for verification, the word line voltage is switched to Vgv (for example, 5.5V) and the bit line voltage is switched to Vdv (for example, 1V), and the write state 00 to the memory cell is verified (read) (ST24).

This verification (ST24) is performed, for example, by a readout circuit 21 (corresponding to a part of the sense amplifier array 15 of FIG. 1) having a plurality of sense amplifiers 20 as shown in FIG. In the example of FIG. 6, the bit line connected to the memory cell 100a to be written in the memory array 11 is connected to a plurality of sense amplifiers 20, and three write states 00, 01, and 10 are simultaneously connected. Can be verified. In this read circuit 21, the bit line is connected to a plurality of sense amplifiers 20 to one input, and the sense amplifier 20 is compared with the output voltage (reference voltage) of the verification reference cells 101a to 101c connected to the other input. Output the verified result. Here, the verification reference cell 101a is for the write state 10 and outputs a reference voltage of 3.7 V, and the verify reference cell 101b is for the write state 01 and outputs a reference voltage of 4.7 V. Cell 101c is for the write state "00" and outputs a reference voltage of 5.7V. If the reference voltage input to all the sense amplifiers 20 is the same, it will be verified to judge only one data, and if the reference voltage input to each sense amplifier 20 is a different voltage, a plurality of different data will be output. Judgment verification can be performed at the same time. In the figure, the circuit block 22 is a bit line selection circuit for selecting bit lines to be connected to the memory cell 100a to be written and the reference cells 101a to 101c for verification, respectively, and is composed of an NOTES transfer gate or the like. ..

Further, in the verify (ST24), instead of the read circuit 21 shown in FIG. 6, for example, the read circuit 23 provided with one sense amplifier 20 for each write target memory cell 100a as shown in FIG. 7 (FIG. 1). A part of the sense amplifier array 15) may be used. In the example of FIG. 7, each bit line connected to the memory cell 100a to be written in the memory array 11 is connected to one input of one sense amplifier 20 and is connected to the other input for verification reference. By sequentially switching and comparing the output voltages (reference voltages) of cells 101a to 101c by the switch circuit 24, verification of different storage states written in a plurality of memory cells 100a to be written on the same word line can be performed at the same time.

The verification result of the read circuit 21 or 23 is output to the control circuit 18, and if the verification result is a pass (in this embodiment, the threshold voltage of the memory cell 100a to be written is 5.7 V or more), it is controlled by the control circuit 18. , The word line voltage and the bit line voltage are returned to the initial state, and the write sequence is completed (ST25, the period of t_Vgv-0 in FIG. 5).

If the verification result fails in step ST25 (in this embodiment, the threshold voltage of the memory cell 100a to be written is less than 5.7V), the control circuit 18 controls the process to return to step ST21, and steps ST21 to ST24 of the write sequence. Is repeated. In the embodiment shown in FIG. 3, the word line voltages Vg10 [n], Vg01 [n], and Vg00 [n] (n = 1,2,3 ...) Applied after the second time are respectively. , The same as the first word line voltage Vg10 [0], Vg01 [0], Vg00 [0].

Next, consider a case where the memory cell to be written is written so as to be in the storage state 01. The initial (before writing) storage state is assumed to be "11" or "10". That is, writing from the initial storage state 00 to 01 is prohibited, and writing from the initial storage state 01 to 01 is practically not executed in order to prevent excessive writing. In this embodiment, the case where the initial storage state is 10 will be described.

As in the case of writing to the storage state 00 described above, first, the word line voltage is set to Vg10 [0] (for example, 6V), the amplitude Vdp10 [0] (for example, 5V) is applied to the bit line, and the pulse width Wp10 [0] ( For example, a write pulse of 1 μsec is applied (ST21), then the word line voltage is switched to Vg01 [0] (for example, 7V), and the pulse width Wp01 [0] (for example, 5V) is applied to the bit line with the amplitude Vdp01 [0] (for example, 5V). For example, a write pulse of 1 μsec) is applied (ST22). Next, the word line voltage is set to Vg00 [0] (for example, 8V) for other memory cells to be written connected to the same word line to be written to the storage state 00, but to this storage state 01. No write pulse with amplitude Vdp00 [0] (eg 5V) is applied to the bit line connected to the memory cell to be written (ST23). Regarding the memory cell to be written to the storage state 01, step ST21 is the first writing step, step ST22 is the second writing step, and step ST23 is not substantially a writing step.

Next, after completing all the writing steps of steps ST21 to ST23, the verifying steps (ST24, ST25) are executed. First, for verification, the word line voltage is switched to Vgv (for example, 5.5V) and the bit line voltage is switched to Vdv (for example, 1V), and the write state 01 to the memory cell is verified (ST24). Similar to the verification of the storage state 00 described above, when the read circuit 21 shown in FIG. 6 is used, one of the plurality of sense amplifiers 20 executes the verification of the storage state 01. When the read circuit 23 shown in FIG. 7 is used, the reference voltage for verification in the storage state 01 is switched by the switch circuit 24 for execution.

The verification result of the read circuit 21 or 23 is output to the control circuit 18, and if the verification result is a pass (in this embodiment, the threshold voltage of the memory cell 100a to be written is 4.7 V or more), it is controlled by the control circuit 18. , The word line voltage and the bit line voltage are returned to the initial state, and the write sequence is completed (ST25, the period of t_Vgv-0 in FIG. 5).

Next, consider a case where the memory cell to be written is written so as to be in the storage state 10. The initial (before writing) storage state is assumed to be "11". In other words, writing from the initial storage state "00" or "01" to "10" is prohibited, and writing from the initial storage state "10" to "10" is practically done to prevent overwriting. Does not run. In this embodiment, the case where the initial storage state is 11 will be described.

As in the case of writing to the storage state 00 or 01 described above, first, the word line voltage is set to Vg10 [0] (for example, 6V), the amplitude Vdp10 [0] (for example, 5V) is applied to the bit line, and the pulse width is Wp10. Apply a write pulse of [0] (eg 1 μsec) (ST21). Next, the word line voltage is set to Vg01 [0] (for example, 7V) for other memory cells to be written connected to the same word line to be written to the storage state 01, but to this storage state 10. No write pulse with amplitude Vdp01 [0] (eg 5V) is applied to the bit line connected to the memory cell to be written (ST22). Next, the word line voltage is set to Vg00 [0] (for example, 8V) for other memory cells to be written connected to the same word line to be written to the storage state 00, but to this storage state 10. No write pulse with amplitude Vdp00 [0] (eg 5V) is applied to the bit line connected to the memory cell to be written (ST23). For the memory cell to be written to the storage state 10, step ST21 is the second writing step, and steps ST22 and ST23 are not substantially writing steps.

Next, after completing all the writing steps of steps ST21 to ST23, the verifying steps (ST24, ST25) are executed. First, for verification, the word line voltage is switched to Vgv (for example, 5.5V) and the bit line voltage is switched to Vdv (for example, 1V), and the write state 10 to the memory cell is verified (ST24). Similar to the verification of the storage state 00 or 01 described above, when the read circuit 21 shown in FIG. 6 is used, one of the plurality of sense amplifiers 20 executes the verification of the storage state 10. .. When the read circuit 23 shown in FIG. 7 is used, the reference voltage for verification in the storage state 10 is switched by the switch circuit 24 for execution.

The verification result of the read circuit 21 or 23 is output to the control circuit 18, and if the verification result is a pass (in this embodiment, the threshold voltage of the memory cell 100a to be written is 3.7 V or more), it is controlled by the control circuit 18. , Return the word line voltage and bit line voltage to the initial state and end the write sequence (ST25, period t_Vgv-0 in Fig. 5).

&lt;Second embodiment&gt; Next, the case where there are a plurality of memory cells to be written on the same word line and the target storage states (threshold voltage) are different has been slightly mentioned in the description of the first embodiment, but will be described in detail with reference to FIG. To do. In the following description, the set of memory cells to be written to the storage state 10 is A0, the set of memory cells to be written to the storage state 01 is B0, and the set of memory cells to be written to the storage state 00 is C0. The method of the present invention according to the second embodiment is executed by the apparatus 10 of the present invention shown in FIGS. 1 and 2 as in the first embodiment.

First, from the initial state (ST20), the word line voltage is charged to Vg10 [0], and the bit line voltage Vdp10 [0] is applied to all the memory cells included in A0, B0, and C0 with the pulse width Wp10 [0]. Then, the threshold voltage of all the memory cells to be written is raised to around 3.7V (ST21). Next, the word line voltage Vg01 [0] is applied to the word line, and the bit line voltage Vdp01 [0] is applied only to all the memory cells included in B0 and C0 with the pulse width Wp01 [0], and B0, Raise the threshold voltage of all memory cells contained in C0 to around 4.7V (ST22). Further, subsequently, the word line voltage is set to Vg00 [0], the bit line voltage Vdp00 [0] is applied to all the memory cells contained in C0 with the pulse width Wp00 [0], and all the memory cells contained in C0 Raise the threshold voltage to around 5.7V (ST23). Here, steps ST21 to ST23 are writing steps.

Next, after completing the writing process of the first steps ST21 to ST23, the word line voltage for verification is switched to Vgv, the bit line voltage for verification is set to Vdv, and verification is performed. Returns the bit line voltage to the initial state. When the threshold voltages of all the memory cells included in A0, B0, and C0 have reached the target value (verify path) (YES in ST25), the writing is completed. Here, the verification process of step ST24 is executed for all the memory cells to be written at the same time or divided into a plurality of times, but the verification for each memory cell is performed, for example, as shown in FIG. This is performed using the circuit 21 or the reading circuit 23 shown in FIG. When verifying all the memory cells to be written at the same time, one read circuit 22 or 23 is assigned to each memory cell. The verification process for each memory cell is the same as in the case of the first embodiment, and duplicate explanations are omitted.

Next, as a result of verification, for example, one or more memory cells A1 contained in A0, one or more memory cells B1 contained in B0, and one or more memory cells C1 contained in C0 are the objectives, respectively. The case where it is determined that the threshold voltage of is not reached (when ST25 is NO) will be described. From the initial state, the word line connected to the memory cells A1, B1, C1 is charged to the word line voltage Vg10 [1], and the bit line voltage Vdp10 [1] is applied only to the bit line connected to the memory cells A1, B1, C1. Apply with a pulse width of Wp10 [1] to raise the threshold voltage of memory cell A1 to around 3.7V (ST21) (however, the threshold voltages of memory cells B1 and C1 hardly change, and are less than 4.7V and 5.7V, respectively. Remains).

Next, the word line voltage Vg01 [1] is applied to the word line, and the bit line voltage Vdp01 [1] is applied only to the bit lines connected to the memory cells B1 and C1 with the pulse width Wp01 [1], and the memory cell B1 (ST22) (however, the threshold voltage of memory cell C1 hardly changes and remains less than 5.7V). Further, subsequently, the word line voltage Vg00 [1] is applied to the word line, and the bit line voltage Vdp00 [1] is applied only to the bit line connected to the memory cell C1 with the pulse width Wp00 [1], and the threshold voltage of the memory cell C1 is applied. Raise the voltage to around 5.7V (ST23).

Next, after completing the writing process of the first step ST21 to ST23, switch to the word line voltage Vgv for verification, set the bit line voltage Vdv for verification, and perform the verification in the same manner as the first time. , Returns the word line voltage and bit line voltage to the initial state. When the threshold voltages of all the memory cells included in the memory cells A1, B1 and C1 have reached the target value (verify pass. If YES in ST25), the writing is completed. Since the memory cells other than the memory cells A1, B1 and C1 among A0, B0 and C0 have passed in the first verification, the second verification result is omitted as a matter of course. If the verify does not pass (verify fail. If NO in ST25), return to step ST21, repeat steps ST21 to ST24, and in step ST25, the purpose of verification fail until all the cells to be written become YES. The write pulse is repeatedly applied to the memory cell to be written that has not reached the threshold voltage.

&lt;Third embodiment&gt; Next, another embodiment in the case where there are a plurality of memory cells to be written on the same word line and the target storage states (threshold voltage) are different will be described with reference to the flowchart of FIG. Here, as in the second embodiment, the set of memory cells to be written to the storage state 10 is A0, the set of memory cells to be written to the storage state 01 is B0, and the set of memory cells to be written to the storage state 00 is set. Let C0. Since the flow of steps ST30 to ST35 in the writing sequence shown in FIG. 8 is the same as that of steps ST20 to ST25 (see FIG. 3) in the second embodiment, the description thereof will be omitted.

In the first step ST35, the word line voltage Vg10 [1] (= Vg10 [0] + ΔVg10 [1]) (ΔVg10 [1]) is applied to the sets A1, B1, and C1 of the memory cells to be written that the verification does not pass. Is a voltage greater than 0V) (ST36), applies the word line voltage Vg10 [1] to the word line, and sends a write pulse of Vdp [1] to the bit lines connected to the memory cells A1, B1, C1 Wp10. [1] Apply with a pulse width of (= Wp10 [0]) (ST31), then the word line voltage Vg01 [1] (= Vg01 [0] + ΔVg01 [1]) (ΔVg01 [1] is from 0V High voltage) (ST36) is reset, the word line voltage Vg01 [1] is applied to the word line, and the pulse width of Wp01 [1] (= Wp01 [0]) is applied to the bit lines connected to the memory cells B1 and C1. Apply the voltage of Vdp01 [1] at (ST32), and then continue with the word line voltage Vg00 [1] (= Vg00 [0] + ΔVg00 [1]) (ΔVg00 [1] is a voltage greater than 0V) (ST36). Is reset, the word line voltage Vg00 [1] is applied to the word line, and Wp00 [1] (=) is applied to the bit line connected to the memory cell C1. Apply the voltage of Vdp00 [1] with the pulse width of Wp00 [0]) (ST33).

Next, apply the word line voltage Vgv for verification to the word line and the bit line voltage Vdv for verification to the bit lines connected to each memory cell A1, B1, C1, and perform the same verification as the first time (ST34). ), Determine whether the threshold voltage of the memory cells verified and failed in the previous verification included in A0, B0, and C0 has reached the target value (ST35), and the threshold voltages of all memory cells become the target value. Steps ST36 and ST31 to ST35 are repeated for the memory cells that need to be rewritten until they are reached. Here, in ST31 to ST33, which are repeated again, the word line voltages Vg10 [n], Vg01 [n], and Vg00 [n] are sequentially applied to the bit lines as in the second time, respectively, and the amplitude Vdp10 [n], Vdp01 [n] and Vdp00 [n] are sequentially applied with pulse widths Wp10 [n], Wp01 [n] and Wp00 [n], and verification processing of the verify fail memory cell is executed in step ST34. Also, in the second and subsequent steps, in step ST36, the word line voltages Vg10 [n], Vg01 [n], and Vg00 [n] are gradually increased in order to promote writing to a memory cell that is difficult to write. ..

&lt;Fourth Embodiment&gt; Next, another embodiment in the case where there are a plurality of memory cells to be written on the same word line and the target storage states (threshold voltage) are different will be described with reference to the flowchart of FIG. Here, since the flow of steps ST40 to ST45 in the writing sequence shown in FIG. 9 is the same as that of steps ST30 to ST35 (see FIG. 8) in the third embodiment, the description thereof will be omitted.

In step ST36 of the third embodiment (see FIG. 8), only the word line voltage setting was changed in step 36 until the verification passed, but in the fourth embodiment, in addition to that, in step ST46, The write pulse width setting is increased each time the verify fails. That is, at the jth rewrite, Wp10 [j] = Wp10 [j-1] + ΔWp10 [j], Wp01 [j] = Wp01 [j-1] + ΔWp01 [j], Wp00 [j] = Wp00 The pulse width is gradually increased and rewritten as in [j-1] + ΔWp00 [j] (however, ΔWp10 [j], ΔWp01 [j], and ΔWp00 [j] are values of 0 or more). In this way, for memory cells that need to be rewritten, the word line voltages Vg10 [n], Vg01 [n], Vg00 [n] and the corresponding pulse widths Wp10 [n], Wp01 [n], Wp00, respectively. At the same time as [n], verification is performed after applying a write pulse while sequentially changing the memory cells, and steps ST46 and ST41 ~ are applied to the memory cells that need to be rewritten until the threshold voltage of all the memory cells reaches the target value. Repeat ST45.

&lt;Fifth Embodiment&gt; When rewriting to a memory cell determined to have not reached a predetermined threshold voltage at the time of verification, in the first and second embodiments, a bit line voltage (write pulse) having the same pulse width as the word line voltage having the same amplitude as the previous time. In the third embodiment, only the amplitude of the word line voltage is gradually increased according to the number of rewrites, and in the fourth embodiment, both the amplitude of the word line voltage and the pulse width of the bit line voltage are rewritten. It was gradually increased according to the number of times. On the other hand, in the fifth embodiment, while using the word line voltage having the same amplitude as the previous time, only the pulse width of the bit line voltage may be gradually increased according to the number of rewrites to perform rewrite. Absent.

In the description of the prior art, referring to Non-Patent Document 3, it has been explained that in order to increase the threshold voltage of the memory cell, the voltage applied to the control gate (word line in the memory array) of the memory cell is increased. , The same effect can be obtained by increasing the pulse width. That is, when rewriting is performed using a word line voltage having the same amplitude as the previous time and a bit line voltage (write pulse) having the same pulse width as in the first and second embodiments, the change in the threshold voltage of the memory cell is small. Therefore, there is a high possibility that the number of rewrites will increase before reaching a predetermined threshold voltage, but the controllability of the threshold voltage will be improved. Therefore, it is effective when it is necessary to narrow the distribution of the threshold voltage corresponding to each storage state, such as when one memory cell has four or more storage states. On the contrary, when shortening the writing time is prioritized over the controllability of the threshold voltage, if rewriting is performed by increasing the amplitude and pulse width of the word line voltage, the amount of change in the threshold voltage due to the rewriting increases, which is the purpose. It is possible to reduce the number of rewrites until the threshold voltage is reached.

That is, the writing method described in the first to fifth embodiments aims at shortening the writing time as compared with the conventional case, and further provides controllability of the threshold voltage distribution in the range of the first to fifth embodiments. It can be selected in consideration of the trade-off with the effect of shortening the writing time.

&lt;Sixth Embodiment&gt; In the second to fifth embodiments, the case where there are a plurality of memory cells to be written on the same word line and the target storage states (threshold voltage) are different has been described, but the memory cells to be written are on the same word line. There may be a plurality of them, and there may be one target storage state (threshold voltage), or all write states may not be included. For example, when the set of memory cells to be written to the storage state 10 is A0, the set of memory cells to be written to the storage state 01 is B0, and the set of memory cells to be written to the storage state 00 is C0, the write target is set. Memory cells may not be included in A0, B0 or A0 and B0 of A0, B0, C0. In such a case, a writing sequence capable of further shortening the writing time will be described with reference to the flowchart of FIG. In FIG. 10, steps ST50, ST52, ST54, St56, ST57, ST58, ST59 correspond to steps ST40, ST41, ST42, ST43, ST44, ST45, ST46 (see FIG. 9) of the fourth embodiment, respectively. The contents of each process are basically the same.

In the sixth embodiment, after the preprocessing (ST50), first, it is determined whether or not the memory cell included in the memory cell A0 to be written in the storage state 10 is substantially present (ST51). This means that, for example, the writing to the storage state 10 is completed before the writing to the storage states 01 and 00 is completed, and the storage state is stored in the memory cell to be written. When the memory cell included in the memory cell A0 to be written to 10 does not substantially exist, the writing to the storage state 10 is omitted, so that step ST52 is omitted to shorten the writing time. Because. Here, as a case where the memory cell included in the memory cell A0 does not substantially exist, a case where the memory cell is formally included in A0 but the initial state before writing is 10 is applicable. If the memory cell included in the memory cell A0 does not substantially exist in step ST51, the process proceeds to the next step ST53 without writing to the storage state 10, and the memory included in the memory cell A0 is included. If the cell substantially exists, the writing in step ST52 is performed, and then the process proceeds to step ST53. Further, in step ST53, after determining whether or not the memory cell included in the memory cell B0 to be written to the storage state 01 substantially exists, the memory cell included in the memory cell B0 substantially exists. If not, the process proceeds to the next step ST55 without writing to the storage state 01, and if the memory cell included in the memory cell B0 actually exists, the writing in step ST54 is performed. Proceed to step ST55. Further, in step ST55, after determining whether or not the memory cell included in the memory cell C0 to be written to the storage state 00 substantially exists, the memory cell included in the memory cell C0 substantially exists. If not, the process proceeds to the verification process of the next step ST57 without writing to the storage state 00, and if the memory cell included in the memory cell C0 actually exists, the writing in step ST56 is performed. Go

Since the verification steps of steps ST57 and ST58 and the process of resetting the word line voltage and pulse width in step ST59 are the same as those in the fourth embodiment, the description thereof will be omitted.

Thus, in steps ST51, ST53, and ST55, whether or not the memory cells included in the memory cells A0, B0, or C0 to be written to the storage states 10, 01, or 00 are substantially present. If the memory cell to be written is not included in at least one set of memory cells A0, B0, and C0, one of the corresponding write steps ST52, ST54, and ST56 can be omitted. , The total writing time can be shortened.

By the way, in the case of the sixth embodiment, for example, there are a plurality of memory cells to be written on the same word line, the initial state of all the memory cells to be written is the storage state "11", and only the target storage state "00" is set. Assuming the case of writing, in the first writing process, the writing of steps ST52 and ST54 is omitted, that is, the word line voltages Vg10 [0] and Vg01 [0] are not applied respectively, and the storage state 11 ( A word line voltage Vg00 [0] (for example, 8V) is applied to a memory cell having a threshold voltage of 3V or less), and an excessive drain current may flow in a plurality of memory cells at the same time. Therefore, the sixth embodiment is practically used as the seventh or eighth embodiment in order to avoid the above risk.

&lt;7th Embodiment&gt; In the seventh embodiment, in a series of writing steps up to the first time or the nth time including the first time in the sixth embodiment, step ST52 and ST54 (see FIG. 10) are performed without determining steps ST51 and ST53 (see FIG. 10). By forcibly executing the writing (see 10), the above problem (the problem that a high gate voltage is applied to a memory cell having a low threshold voltage and an excessive drain current flows) can be solved. That is, by performing steps ST51 and ST53 at the time of rewriting after the (n + 1) th time, the sixth embodiment is implemented, and the writing time related to the rewriting can be shortened.

&lt;8th Embodiment&gt; In the seventh embodiment, it is necessary to determine whether or not to carry out steps ST51 and ST53 in each writing step. In order to avoid this complexity, a writing sequence as shown in FIG. 11 may be performed. That is, in a series of writing steps up to the first time or the nth time including the first time, the writing of steps ST62 and ST63 (corresponding to steps ST52 and ST54 in FIG. 10) is performed by another route.

Steps ST60 and ST64 to ST72 in the eighth embodiment are basically the same as steps ST50 and ST51 to ST59 in the sixth embodiment, respectively. However, in the writing of ST65, ST67, and ST69, only the memory cells whose target writing states are "10", "01", and "00", respectively, may be the target of writing.

The number n of the writing steps is set to an initial value of 0 in the preprocessing step ST60, and is counted up by 1 in the step ST73 each time the verification fails in the step ST71. Here, assuming that the number of times that the determination of steps ST51 and ST53 (see FIG. 10) of the sixth embodiment is not performed is m, the magnitude determination of n&gt; (m-1) is performed in step ST61. For example, when m = 2, the determination of n&gt; 1 is performed in step ST61. Since the first and second times are n = 0 and 1, the judgment is NO in both cases, and the writing process of steps ST62 and ST63 corresponding to the writing to the storage states 10 and 01 is executed. All the cells to be written gradually increase to the threshold voltages around 3.7V and 4.7V. After all, the first and second steps are the same as those of the second to fifth embodiments because the steps are changed to steps ST62, ST63, ST69, ST70, and ST71. From the third time onward, since n = 2 or more, the determination in step ST61 is YES, the transition from ST64 to ST71, and the same as in the sixth embodiment. As a result, as in the seventh embodiment, the threshold voltage and the word to be applied to the memory cell to be written to the target storage state 00 when the initial state is the storage state 11 in at least the first writing, for example. By increasing the line voltage stepwise, it is possible to avoid the flow of an excessive drain current and shorten the writing time in the (m + 1) and subsequent rewriting steps.

Although step ST73 is provided after step ST72, it may be provided in another place. However, the value "n" indicating the number of rewrites needs to be compared with the maximum value in order to prevent the rewrite process from being repeated indefinitely for the bad write memory cell. It is preferable that the count of the number of writes is in the main routine, that is, in the path of ST70-ST71-ST72-ST61. Further, the number of times m is usually preferably set in the range of 1 to 3 times. Further, the number of times m is irrelevant to the number m of bit lines BL of the memory array 11 shown in FIG. 2, like n indicating the number of times of rewriting.

&lt;9th embodiment&gt; In the above 1st to 8th embodiments, the case where the possible storage state (threshold voltage state) of the memory cell is 4 values has been described, but the method of the present invention exemplified in the 1st to 8th embodiments has a multi-value level. It is not limited to 4 values. The technical idea of the method of the present invention has the same effect even when applied to the writing of an N value (N is a natural number of 3 or more) memory cell. Assuming that the storage state of the N value is from the state where the threshold voltage is low to the level "1" to the level "N", the level "2" or higher becomes the writing state when associated with the case of the four values. Here, when the write state level is M (M is a natural number of 2 or more and N or less), the write process corresponding to each write state exists (N-1) times, and each write process M (write state level). If the word line voltage (write gate voltage at the memory cell level) of (write to M) is VgM [n] (n represents the number of rewrites, 0 at the first write), Vg (M-) is a general formula. 1) The relationship of [n] &lt;VgM [n] is established (in the case of four values, it is expressed as Vg10 [n] &lt;Vg01 [n] &lt;Vg00 [n] as shown in the first embodiment). .. Bit line voltage of write process M VdpM [n] (Write-drain voltage at the memory cell level) and pulse width WpM [n] are constant regardless of the value of M, as in the first to eighth embodiments. The write process M executes sequentially for M = 2 to N, and then performs a verify process corresponding to the target storage state of the memory cell to be written, and returns the voltage of the word line and the bit line to the initial state. In the verify process, the write process M (M = 2 to N) is repeated until the target storage state of all the memory cells to be written is reached.

Next, taking the first embodiment as an example, the effect of shortening the writing time in the method of the present invention will be described with reference to specific examples. For example, as shown in FIG. 19, the time until the word line changes from 0V to the word line voltage Vgp at the time of writing and the bit line voltage changes from 0V to the bit line voltage Vdp at the time of writing is t_0-Vgp (for example). , 2 μsec), the period during which a write pulse with an amplitude Vdp is applied to the bit line (pulse width) is Wp (for example, 4 μsec), and the next write from the word line voltage Vgp in the write state (M-1) with the word line. The time for the state (M) to change to the word line voltage Vgp is t_Vgp-Vgp (for example, 1 μsec), and the time for the word line to change from the last write state word line voltage Vgp to 0 V is t_Vgp-0 (for example, 0.3 μsec). , Time when the word line changes from 0V to the word line voltage Vgv for verification t_0-Vgv (for example, 8 μsec), Time when the bit line voltage Vdv for verification is applied to the bit line (verification period) is Wv (for example) , 0.5 μsec), assuming that the time required to change the word line voltage from Vdv for verification to 0 V is t_Vgv-0 (for example, 0.8 μsec), the conventional writing illustrated in the flowchart of FIG. If each memory cell is written once in the sequence, the write time is 25.8 μsec. FIG. 18 shows the transition of the word line voltage and the bit line voltage at this time. On the other hand, the write time in the method of the present invention shown in the flowchart of FIG. 3 is 18.6 μsec when each memory cell is written once, which is about 30% faster than the conventional write method. .. The transition of the word line voltage and the bit line voltage at this time is as shown in FIG. Further, since the voltage switching between the verification process and the writing process is small, the current consumption required for charging / discharging the word line and the bit line can be reduced, and the current consumption during writing can be reduced.

As described above, in the apparatus 10 of the present invention, when writing to a multi-value level writing state, the word line voltage and the bit line corresponding to each writing state up to the target writing state by switching the word line voltage By performing verification after applying the voltage to the memory cell to be written, it is possible to omit the charge / discharge time of the word line and the bit line and the unnecessary time until the word line voltage and the bit line voltage stabilize. Value writing can be performed at high speed.

Next, another embodiment of the apparatus 10 of the present invention will be described.

&lt;1&gt; In the above embodiment, the memory cell transistor structure constituting the memory cell is assumed to be a floating gate type transistor structure as shown in FIG. 12, but the memory cell transistor structure or the structure of the charge storage region is this. It is not limited. For example, even if the charge storage region is a charge storage region formed in an ONO film (a laminated structure of an oxide film, a nitride film, and an oxide film) other than the floating gate, if multi-value writing is possible, the method of the present invention Can be applied.

&lt;2&gt; In the above embodiment, the configuration shown in FIG. 2 is illustrated as the configuration of the memory array 11, but the memory array configuration is not limited to the configuration illustrated in FIG. In the configuration shown in FIG. 2, all the sources in the same block are shared and connected to the common source line. For example, the source lines in the same row are connected in common and a plurality of sources are connected in parallel with the bit line. It may be a virtual ground line type memory array structure to be arranged.

<figref num="1">The block block diagram which shows the functional block structure of one Embodiment of the non-volatile semiconductor storage device which concerns on this invention.</figref><figref num="2">The circuit diagram which shows the structure of the memory cell and the memory cell array in one Embodiment of the non-volatile semiconductor storage device which concerns on this invention.</figref><figref num="3">The flowchart which shows the writing sequence of 1st and 2nd Embodiment of the writing method of the non-volatile semiconductor storage device which concerns on this invention.</figref><figref num="4">The figure which shows the distribution of the threshold voltage of the memory cell transistor in the 4-value flash memory as a non-volatile semiconductor storage device.</figref><figref num="5">The figure which shows the voltage transition of a word line and a bit line in the writing process and the verification process of the 1st and 2nd embodiments of the writing method of the non-volatile semiconductor storage device which concerns on this invention.</figref><figref num="6">The circuit diagram which shows an example of the read circuit of the non-volatile semiconductor storage device which concerns on this invention.</figref><figref num="7">The circuit diagram which shows another example of the read circuit of the non-volatile semiconductor storage device which concerns on this invention.</figref><figref num="8">The flowchart which shows the writing sequence of 3rd Embodiment of the writing method of the non-volatile semiconductor storage device which concerns on this invention.</figref><figref num="9">The flowchart which shows the writing sequence of 4th Embodiment of the writing method of the non-volatile semiconductor storage device which concerns on this invention.</figref><figref num="10">The flowchart which shows the writing sequence of 6th Embodiment of the writing method of the non-volatile semiconductor storage device which concerns on this invention.</figref><figref num="11">The flowchart which shows the writing sequence of 8th Embodiment of the writing method of the non-volatile semiconductor storage device which concerns on this invention.</figref><figref num="12">A cross-sectional view schematically showing a memory cell transistor structure in a flash memory as a non-volatile semiconductor storage device and an equivalent circuit diagram thereof.</figref><figref num="13">The figure which shows the state of the electron in the floating gate of the memory cell in the binary flash memory as a non-volatile semiconductor storage device.</figref><figref num="14">The figure which shows the distribution of the threshold voltage of the memory cell transistor in the binary flash memory as a non-volatile semiconductor storage device.</figref><figref num="15">The figure which shows the state of the electron in the floating gate of the memory cell in the quaternary flash memory as a non-volatile semiconductor storage device.</figref><figref num="16">The flowchart which shows an example of the multi-value writing method of the conventional non-volatile semiconductor storage device.</figref><figref num="17">The figure which shows the voltage transition of a word line and a bit line in the multi-value writing method of the conventional non-volatile semiconductor storage device.</figref><figref num="18">The figure which shows the voltage transition of a word line and a bit line at the time of writing in the multi-value writing method of the conventional non-volatile semiconductor storage device.</figref><figref num="19">A list of elapsed times in which the writing time in the writing method of the non-volatile semiconductor storage device according to the present invention is distributed according to the voltage levels of the word line voltage and the bit line voltage, and the writing time of the method of the present invention and the writing of the conventional writing method. A table showing time comparisons.</figref>

Code description

10: Non-volatile semiconductor storage device according to the present invention 11: Memory array (main memory array) 12: Reference memory array 13: Word line voltage supply circuit 14: Bit line voltage supply circuit 15: Sense amp array 16: Write voltage generation circuit 17: Read voltage generation circuit 18: Control circuit 20: Sense amplifier 21: Read circuit 22: Bit line selection circuit 23: Read circuit 24: Switch circuit 40: Floating gate (floating gate) 41: Channel area 42: Control gate 43: Oxidized film (insulating film) 44: Interlayer insulating film 45: Source area 46: Drain area 100: Memory cell 100a: Memory cell to be written 101a ~ 101c: Reference cell for verification SL: Common source line WL0 ~ WLn: word line BL0 ~ BLm: Bit line