Output circuit

The present invention relates to an output circuit, and more particularly to an output circuit having an overcurrent protection function.

[0002] An output circuit includes a switching element and controls on / off of power supplied to a load based on an input control signal. For the switching element, for example, a transistor such as a power MOS is used. When an excessive current flows through such a switching element, the switching element is destroyed due to heat generation or the like. Usually, the output circuit is provided with an overcurrent protection function for protecting the switching element from destruction.

[0003] As a technique relating to an overcurrent protection function of a switching element, there are techniques described in Japanese Patent Application Laid-Open No. 7-114351 (Patent Document 1) and Japanese Patent Application Laid-Open No. 10-107605 (Patent Document 2). For example, in the technique described in Patent Document 1, a resistance element is arranged as a current detection element on the emitter side of the output transistor constituting the switching element, and an overcurrent is flowing through the output transistor by the current detection element. Is detected. The capacitor connects the base of another transistor for turning off the output transistor and the base of the output transistor, and the capacitor is charged and discharged when an overcurrent is detected by the current detection element, and the output is output. The transistor is intermittently interrupted to protect the switching element.

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 7-114351 [Patent Document 2] Japanese Patent Application Laid-Open No. 10-107605 [0005] [Problems to be Solved by the Invention] Generally, a patent is provided for overcurrent protection of a switching element. Including the techniques described in Documents 1 and 2, the time from the detection of overcurrent to the turning off of the switching element (shutdown time) is the charging / discharging time of the capacitor, that is, the capacitance value of the capacitor or the capacitor. It is set by the resistance value that determines the charge / discharge current value of. The shutdown time set in this way is constant regardless of the degree of abnormality that has occurred in the load.

[0006] By the way, the heat generated by the switching element depends on the value of the current flowing through the switching element and the time. Therefore, when the degree of abnormality generated in the load is high and a large current flows through the switching element, the shutdown time is shortened so that the switching element is not destroyed before it is forcibly turned off. Must be set to. However, when the shutdown time is set short and the threshold current for overcurrent detection (minimum value of abnormal current) is set low, it is turned on even if there is no abnormality in the load. There is a problem that the switching element is forcibly turned off by the rush current immediately after the above.

[0007] The above problem can be avoided by increasing the threshold current for overcurrent detection. However, if the threshold current value for overcurrent detection is set high so that the switching element is not forcibly turned off by the rush current, as described above, the heat generated by the switching element is caused by the switching element. Since it depends on the value and time of the current flowing through the load, the degree of abnormality generated in the load is low, and a current that is larger than the steady current of the load but not as large as the threshold current of the overcurrent detection circuit flows for a long time. If continued, the switching element cannot be effectively protected from destruction due to heat generation.

[0008] The present invention solves the above problems, can change the shutdown time according to the degree of abnormality generated in the load, and can effectively protect the switching element from destruction caused by the abnormal current. The purpose is to provide a circuit.

[Means for Solving the Problems] In order to achieve the above object, the output circuit of the present invention includes an output transistor connected in series with a load to supply a load current, and protection for protecting the output transistor. In the output circuit including the circuit, the protection circuit detects whether or not the load current exceeds the threshold value, and the current detection circuit indicates that the load current exceeds the threshold value. It is provided with an off signal generation circuit that generates an off signal that turns off the output transistor after an elapsed time depending on the voltage drop of the output transistor from the detected time.<u style="single">The off-signal generation circuit includes a current generator that generates a current depending on the voltage drop and a capacitor that is charged by the current generated by the current generator, and the terminal voltage of the capacitor is a predetermined voltage. When the value is exceeded, the off signal is generated, the current generator includes a current mirror, and the current mirror is connected in series with the reference side transistor through which a current depending on the voltage drop of the output transistor flows. Equipped with an output side transistor</u>It is characterized by that.<u style="single"> Further, the output circuit of the present invention is an output circuit including an output transistor connected in series with a load to supply a load current and a protection circuit for protecting the output transistor. From the time when the current detection circuit that detects whether or not the value is exceeded and the time when the current detection circuit detects that the load current exceeds the threshold value, after the elapsed time depending on the voltage drop of the output transistor. The off-current generation circuit includes an off-signal generation circuit that generates an off-signal that turns off the output transistor, and the off-current generation circuit includes a clock generation circuit that generates a clock signal having a period depending on the voltage drop and the clock signal. It is characterized by including a counter that generates the off signal when counting and counting a predetermined number of clocks.</u>[0010] In the output circuit of the present invention, the protection circuit detects that the load current flowing through the output transistor exceeds the threshold value by the current detection circuit, that is, an abnormality has occurred in the load. From time, the off-signal generation circuit generates a signal to turn off the output transistor after an elapsed time that depends on the voltage drop of the output transistor. Therefore, the time during which the abnormal current flows through the output transistor can be changed according to the degree (degree) of the abnormality generated in the load. For example, when the degree of abnormality generated in the load is high, the output transistor is immediately turned off. When the degree of abnormality is low, the output transistor is turned off after a relatively long time has passed, and both when the degree of abnormality generated in the load is high and when the degree of abnormality is low, the output transistor is effectively turned off from destruction due to heat generation. Can be protected.

[0011] In the output circuit of the present invention, the off-signal generation circuit can adopt a configuration in which the off-signal is released after a certain elapsed time from the generation time of the off-signal, or the off-signal can be released. A configuration can be adopted in which the off signal is released after another elapsed time depending on the voltage drop from the generation time. When adopting a configuration that releases the off signal generated by the off signal generation circuit after the output transistor is turned off by the protection circuit, it is said that the abnormality that occurred in the load by the time the off signal is released is eliminated. The output circuit can return to normal operation.

[0012] In the output circuit of the present invention, the current detection circuit is configured to detect whether or not the load current exceeds the threshold value depending on whether or not the voltage drop of the output transistor exceeds the threshold value. Can be adopted. In this case, the current detection circuit detects the magnitude of the load current in a pseudo manner based on the magnitude of the voltage drop of the output transistor.

[0013] In the output circuit of the present invention, the off-signal generation circuit includes a current generation unit that generates a current depending on the voltage drop, and a capacitor that is charged by the current generated by the current generation unit. A configuration that generates the off signal when the terminal voltage of the capacitor exceeds a predetermined voltage value can be adopted. In this case, a predetermined elapsed time until the off signal is generated can be determined by the charging time of the capacitor.

[0014] In the output circuit of the present invention, the current generating unit includes a current mirror, and the current mirror is connected in series with a reference side transistor through which a current depending on the voltage drop of the output transistor flows. It can be provided with an output side transistor. In this case, the capacitor is charged by the output transistor. The reference side transistor of the current mirror and the output side transistor can be connected to different power supply systems.

[0015] In the output circuit of the present invention, instead of the above configuration, the off-signal generation circuit counts the clock signal and the clock generation circuit that generates a clock signal having a period depending on the voltage drop, and determines. It is possible to adopt a configuration including a counter that generates the off signal when the number of clocks is counted. In this case, the off-signal generation circuit determines a predetermined elapsed time until the off-signal is generated by the time required to count a predetermined number of clock pulses of the clock signal having a period depending on the voltage drop of the output transistor. Can be made to.

[0016] In the output circuit of the present invention, the clock signal generation circuit includes a current generation unit that generates a current depending on the voltage drop, and a capacitor that is charged by the current generated by the current generation unit. Therefore, it is possible to adopt a configuration in which the clock signal has a period depending on the charging time of the capacitor. By changing the cycle of the clock signal depending on the degree of abnormality that has occurred in the load, the predetermined elapsed time until the off signal is generated can be set as the time that depends on the degree of abnormality that has occurred in the load. it can.

[0017] In the output circuit of the present invention, the current generating unit includes a current mirror, and the current mirror is connected in series with a reference side transistor through which a current depending on the voltage drop of the output transistor flows. A configuration including an output side transistor can be adopted. In this case, the capacitor is charged by a charge / discharge current that depends on the current flowing through the output transistor. The reference side transistor of the current mirror and the output side transistor can be connected to different power supply systems.

[0018] In the output circuit of the present invention, a load element including a MOS transistor in which a gate and a source are interconnected and at least one Zener diode connected in series with the MOS transistor is a reference of the current mirror. A configuration connected in series with the side transistor can be adopted. In the output circuit, the current-voltage characteristic of the reference side transistor of the current mirror determines the time from when the voltage drop of the output transistor exceeds the threshold value until the off signal generation circuit generates an off signal. By connecting the Zener diode in series with a MOS transistor or resistor in which the gate and source are interconnected, the voltage-current characteristics of the reference-side transistor of the current mirror can be changed. The number of connected Zener diodes can be appropriately designed so that the current-voltage characteristic of the reference side transistor of the current mirror becomes a desired characteristic.

[0019] In the output circuit of the present invention, it is possible to adopt a configuration in which a plurality of the load elements are connected in parallel and connected to the reference side transistor. In this case, by connecting a plurality of load elements having different current-voltage characteristics in parallel, the current-voltage characteristics of the reference side transistor of the current mirror can be made into a desired characteristic.

[0020] In the output circuit of the present invention, it is also possible to adopt a configuration in which another MOS transistor in which the gate and the source are interconnected is connected in parallel with the load element.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in more detail below with reference to the drawings, based on examples of embodiments of the present invention. FIG. 1 shows the configuration of the output circuit according to the first embodiment of the present invention. The output circuit 10 includes an output switch 11, a gate control circuit 12, a current limit circuit 13, an AND circuit 14, a counter 15, an overcurrent detection circuit 16, current generation circuits 17, 18 and a clock generator 19. In the output circuit 10 of the present embodiment, the clock pulse width (clock signal cycle) of the clock signal C generated by the clock generator 19 is set to the potential difference V between the power supply terminal Vbb and the output terminal OUT._onAdopt a circuit configuration that can be changed depending on.

[0022] The output switch 11 is composed of, for example, a semiconductor switching element such as a power MOS, and has a power supply terminal Vbb to which a power source such as a battery is connected and an output terminal OUT to which a load such as a lamp or a solenoid coil is connected. Placed in between. The gate control circuit 12 controls the switching of the output switch 11. The current limiting circuit 13 prevents a large current such as a short-circuit current from flowing through the output switch 11. The AND circuit 14 inputs the AND signal F of the control signal E input from the input terminal IN and the output signal D of the counter 15 to the gate control circuit 12.

The counter 15, the overcurrent detection circuit 16, the current generation circuits 17, 18 and the clock generator 19 constitute a protection circuit. The overcurrent detection circuit 16 detects whether or not an abnormal current exceeding the threshold value is flowing through the output switch 11. The first current generation circuit 17 has a current I that depends on the potential difference between the power supply terminal Vbb and the output terminal OUT.₁To generate. The second current generation circuit 18 is the current I generated by the first current generation circuit 17.₁Current I based on₂To generate. The clock generator 19 is a current I generated by the second current generation circuit 17.₂Generates a clock signal C with a period based on. The counter 15 counts the clock pulse of the clock signal C and outputs the H level or L level signal D.

FIG. 2 shows a configuration example of the gate control circuit 12. The gate control circuit 12 includes an inverter 121, a charge pump circuit 122, pMOS21, nMOS22 and 23, and resistors R21 and R22. The charge pump circuit 122 includes inverters 123 and 124, diodes D21 to D23, capacitors C21 and C22, and a charge pump clock generator 125. The gate control circuit 12 outputs a gate control signal G based on the input logical product signal F to control the switching of the output switch 11.

In the gate control circuit 12, the charge pump clock generator 125 is activated in response to the H-level logical product signal F input via the inverter 121, and the charge pump circuit 122 uses the power supply. The voltage Vbat is boosted to, for example, Vbat + 10V to generate a voltage. At this time, pMOS21 is turned on, nMOS22 and nMOS23 are turned off, and the gate control circuit 12 outputs a gate control signal G whose H level is the voltage boosted by the charge pump circuit 122, and outputs a switch. Turn on 11. The gate control circuit 12 turns on nMOS22 and nMOS23 and turns off pMOS21 in response to the L-level AND signal F input via the inverter 121. At this time, the gate control circuit 12 shorts the signal line connecting the gate control circuit 12 and the output switch 11 with the output terminal OUT, and turns off the output switch 11.

Returning to FIG. 1, the AND circuit 14 transmits the AND signal F of the control signal E input from the input terminal IN and the output signal D of the counter 15 to the gate control circuit 12. input. The counter 15 normally outputs an H level signal D when the overcurrent detection circuit 16 does not detect that an abnormal current is flowing through the output switch 11, and the overcurrent detection circuit 16 causes an abnormal current to flow. When it is detected that the signal "D" is detected, the L level signal "D" is output under the predetermined conditions described later. When the counter 15 outputs the H level signal D, the AND circuit 14 outputs the AND signal F based on the control signal E.

[0027] The current limiting circuit 13 includes nMOS2 and diodes D1 to D4. The nMOS2 and the diodes D1 to D4 are inserted in series between the signal line connecting the gate control circuit 12 and the output switch 11 and the output terminal OUT, and the gate of the nMOS2 is connected to the power supply terminal Vbb. The current limiting circuit 13 operates as described below to lower the level (potential) of the gate control signal G and limit the current flowing through the output switch to a predetermined value when an abnormality occurs in the load. However, it prevents a large current such as a short-circuit current exceeding 600 A from flowing through the output switch 11.

[0028] When the output switch 11 is on, if no abnormality has occurred in the load, the voltage (output voltage) Vout between the output terminal OUT and the ground is almost equal to the power supply voltage Vbat, nMOS2 is turned off, and the diode D1 No current flows through ~ D4. When an abnormality occurs in the load and, for example, the output terminal OUT is equivalently grounded as shown by the dotted line in FIG. 1, the output voltage Vout becomes almost the ground potential. In this case, nMOS2 is turned on, and a current flows from the signal line connecting the gate control circuit 12 and the output switch 11 toward the output terminal OUT via the diodes D1 to D4. As a result, the level of the gate control signal G is lowered, and the current flowing through the output switch 11 can be suppressed. The current value limited by the current limiting circuit 13 is set to about 200A, which is about twice that, assuming that the maximum value of the rush current immediately after the output switch 11 is turned on is 100A.

[0029] The first current generation circuit 17 includes pMOS1 and a resistor R0. The pMOS1 and the resistor R0 are inserted in series between the power supply terminal Vbat and the output terminal OUT, and the gate of the pMOS1 is connected to the drain. The first current generation circuit 17 has a potential difference V between the power supply terminal Vbb and the output terminal OUT._onCurrent I that changes depending on (= Vbat-Vout)₁To generate.

The second current generation circuit 18 includes pMOS3 and nMOS4. pMOS3 and nMOS4 are inserted between the power supply lines of both power supply V1. In the second current generation circuit 18, the gate of nMOS4 is connected to the drain of pMOS3, and the gate of pMOS3 is connected to the gate of pMOS1 of the first current generation circuit 17. That is, pMOS3 of the second current generation circuit 18 and pMOS1 of the first current generation circuit form a current mirror, and the second current generation circuit 18 is the current I generated by the first current generation circuit 17.₁Depends on current I₂To generate.

As will be described later, the second current generation circuit 18 determines the period of the clock signal C generated by the clock generator 19 in the clock generator 19.₃And discharge current I₄To decide. Current I generated by the second current generation circuit 18₂Is the current I generated by the first current generation circuit 17₁Since the current is proportional to, the period of the clock signal C generated by the clock generator 19 depends on the magnitude of the potential difference between the power supply terminal Vbb and the output terminal OUT.

The overcurrent detection circuit 16 includes an operational amplifier OP1 and a switch SW1 and detects whether or not an abnormal current is flowing through the output switch 11. In the operational amplifier OP1, the inverting input terminal is connected to the switch SW1, and the non-inverting input terminal determines the threshold voltage._refIt is connected to the power supply terminal Vbb via. The switch SW1 connects the power supply terminal Vbb and the inverting input terminal of the operational amplifier OP1 based on the control signal E input from the input terminal IN, or connects the output terminal OUT and the inverting input terminal of the operational amplifier OP1. .. In the overcurrent detection circuit 16, the potential input to the inverting input terminal of the operational amplifier OP1 is the potential input to the non-inverting input terminal (Vbat-V)._ref), An H-level overcurrent detection signal is output.

When the control signal E is at the L level, that is, when the output switch 11 should be turned off, the switch SW1 connects the inverting input terminal of the operational amplifier and the power supply terminal Vbb. At this time, the overcurrent detection circuit 16 outputs an L-level overcurrent detection signal because the potential input to the inverting input terminal is higher than the potential input to the non-inverting input terminal. When the control signal E is at H level, that is, when the output switch 11 should be turned on, the switch SW1 connects the inverting input terminal of the operational amplifier OP1 and the output terminal OUT. At this time, in the overcurrent detection circuit 16, if the potential of the output terminal OUT input to the inverting input terminal is lower than the potential input to the non-inverting input terminal, that is, the potential of the output terminal OUT is (Vbat-). V_refIf it is lower than), an H level overcurrent detection signal is output.

By the above operation, the overcurrent detection circuit 16 has a potential difference V between the power supply terminal Vbb and the output terminal OUT when the output switch 11 should be turned on._onIs the threshold V_refWhen it exceeds, it detects that an abnormal current has flowed through the output switch 11 and outputs an H level overcurrent detection signal. For example, when the on-resistance of the output switch 11 is 10 mΩ and it is detected that a current of 20 A or more has flowed through the output switch 11 as an abnormal current, the threshold value V_refShould be set to 0.2V.

[0035] The counter 15 counts the clock pulse of the clock signal C generated by the clock generator 19 in response to the H level overcurrent detection signal. The counter 15 outputs an L level signal D (off signal) when the count number of the clock pulse of the clock signal C reaches a predetermined value. Further, when the counter 15 counts the clock pulse of the clock signal C by another predetermined number after the count number reaches a predetermined number, the off signal is released and the signal D is returned to the H level. When the counter 15 starts counting and then counts the clock pulse of the clock signal C by, for example, 50, it outputs an L level signal D, and then further counts the clock pulse of the clock signal C by, for example, 100. Then, the H level signal "D" is output.

[0036] The clock generator 19 includes a charging pMOS5, a discharging nMOS6, a bypass pMOS7, an operational amplifier OP2, a capacitor CP1, resistors R1 to R3, a switch SW2, an AND circuit 20, and an inverter 21. To be equipped. The clock generator 19 generates a clock signal C to be H level or L level based on the potential difference between the inverting input terminal and the non-inverting input terminal of the operational amplifier OP2, and sends the clock signal C to the counter 15. input.

The resistors R1 to R3 are inserted in series between both power supply lines of the power supply V1, and the bypass pMOS7 is connected in parallel with the resistor R1. A clock signal C is input to the gate of the bypass pMOS 7 via the inverter 21. The bypass pMOS7 is turned on when the clock signal C is at H level, and turned off when the clock signal C is at L level. The node B that connects the resistor R2 and the resistor R3 is connected to the non-inverting input terminal of the operational amplifier OP2. One terminal of the capacitor CP1 is connected to the inverting input terminal (node A) of the operational amplifier OP2, and the other terminal is connected to the power supply line on the low potential side of the power supply V1.

[0038] The AND circuit 20 outputs the logical product of the overcurrent detection signal output by the overcurrent detection circuit 16 and the clock signal C. The switch SW2 is controlled based on the output of the AND circuit 20 and controls the charging / discharging of the capacitor CP1. When the switch SW2 inputs the H level signal from the AND circuit 20, it connects the node A and the drain of the charging pMOS5 to charge the capacitor CP1, and when inputting the L level signal from the AND circuit 20, the switch SW2 charges the capacitor CP1. Connect the node A and the drain of the discharge nMOS6 to discharge the capacitor CP1. When the L-level overcurrent detection signal is output from the overcurrent detection circuit 16, the switch SW2 connects the node A and the drain of the discharge nMOS6, and the potential of the node A is higher than the potential of the node B. As it becomes lower, the clock signal C, which is the output of the operational amplifier OP1, maintains the H level.

[0039] The charging pMOS5 is inserted between the power supply line on the high potential side of the power supply V1 and the switch SW2. The gate of the charging pMOS 5 is connected to the gate of the pMOS 3 of the second current generation circuit 18, and the charging pMOS 5 and the pMOS 3 of the second current generation circuit 18 form a current mirror. When the switch SW2 connects the node A and the drain of the charging pMOS5, the capacitor CP1 receives the current I generated by the second current generation circuit 18 via the charging pMOS5.₂Based on current I₃It is charged with.

[0040] The discharge nMOS6 is inserted between the power supply line on the low potential side of the power supply V1 and the switch SW2. The gate of the discharge nMOS 6 is connected to the gate of the nMOS 4 of the second current generation circuit 18, and the discharge nMOS 6 and the nMOS 4 of the second current generation circuit 18 form a current mirror. When the switch SW2 connects the node A and the drain of the discharge nMOS6, the capacitor CP1 passes the current I generated by the second current generation circuit 18 via the discharge nMOS6.₂Based on current I₄Is discharged at.

FIG. 3 shows a state of generation of the clock signal C in the clock generator 19 as a waveform diagram. In the figure, the short circuit state of the load progresses, and the time t₃₀An example is shown in which the output voltage Vout decreases with the passage of time after the output switch 11 is turned on. The overcurrent detection circuit 16 has a potential difference V between the power supply terminal Vbb and the output terminal OUT._onIs the threshold V_refWhen it is detected that the value exceeds, in the clock generator 19, the switch SW2 charges the node A based on the logical product of the H level clock signal C and the H level overcurrent detection signal. By connecting the drain of the pMOS5 for use, charging / discharging of the capacitor CP1 is started.

[0042] Time t₃₀~ Time t₃₁Then, the clock signal "C" is at H level, and the bypass pMOS7 is on. Assuming that the potential of the non-inverting input terminal (node B) of the operational amplifier OP2 at this time is VB1, VB1 = V1 × (R3 / (R2 + R3)). Further, the switch SW2 selects the charging pMOS5 side based on the signal from the AND circuit 20 that outputs the H level, and in the clock generator 19, the first current generation circuit 17 and the second current mirror are configured. Current I generated by the current generation circuit 18₂Charging current based on I₃Then, charging of the capacitor CP1 is started.

[0043] By charging the capacitor CP1, the potential of the inverting input terminal (node A) of the operational amplifier OP2 rises. Time t₃₁Then, when the potential of the inverting input terminal of the operational amplifier OP2 exceeds the potential VB1 of the non-inverting input terminal, the output of the operational amplifier OP2 is inverted and the clock signal C is inverted to the L level. When the clock signal C reaches the L level, the bypass pMOS7 is turned off. At this time, the potential VB2 of the non-inverting input terminal of the operational amplifier OP2 is VB2 = V1 × (R3 / (R1 + R2 + R3)) (&lt;VB1). Further, the AND circuit 20 outputs an L level signal based on the L level clock signal C, and the switch SW2 switches the selection to select the discharge nMOS6 side. In the clock generator 19, the current I generated by the first current generation circuit 17 and the second current generation circuit 18 constituting the current mirror.₂Discharge current I based on₄Then, the discharge of the capacitor CP1 is started.

[0044] Due to the discharge of the capacitor CP1, the potential of the inverting input terminal of the operational amplifier OP2 drops, and the time t₃₂Then, when the potential of the inverting input terminal of the operational amplifier OP2 falls below the potential VB2 of the non-inverting input terminal, the output of the operational amplifier OP2 is inverted again and the clock signal C is inverted to the H level. When the clock signal C reaches the H level, the bypass pMOS7 is turned on again, and the potential of the non-inverting input terminal of the operational amplifier OP2 becomes VB1. Further, the switch SW2 switches the selected state again to select the charging pMOS5 side, and the clock generator 19 starts charging the capacitor CP1. In the clock generator 19, the capacitor CP1 is repeatedly charged and discharged in this way, and the clock signal C is generated.

[0045] Charging current I of capacitor CP1₃And discharge current I₄Is the current I generated by the second current generation circuit 18.₂However, the potential difference V between the power supply terminal Vbb and the output terminal OUT_onCurrent generated by the first current generation circuit 17, which changes depending on₁Since it is determined based on, the potential difference V between the power supply terminal Vbb and the output terminal OUT_onThe value of the current depends on. Since the H level period and L level period of each clock pulse of the clock signal C are determined by the charge / discharge current of the capacitor CP1, the period of the clock signal C is the potential difference V between the power supply terminal Vbb and the output terminal OUT._onDepends on.

In the example of FIG. 3, a short-circuit state progresses with the passage of time, and the potential difference V between the power supply terminal Vbb and the output terminal OUT_onIs getting bigger, so the charging current I₃And discharge current I₄Increases over time. Therefore, time t₃₁~ t₃₂L level period between T₁And time t₃₃~ t₃₄L level period between T₃And time t₃₅~ t₃₆L level period between T₅Comparing with each other, T₁&gt; T₃&gt; T₅Will be. Also, time t₃₂~ t₃₃H level period between T₂And time t₃₄~ t₃₅H level period between T₄Compared to T₂&gt; T₄Therefore, the period of the clock signal C becomes shorter with the passage of time.

FIG. 4 shows the potential difference V between the power supply terminal Vbb and the output terminal OUT._onThe relationship between the clock signal C and the period of the clock signal C is shown as a graph. When the first current generation circuit 17 is composed of a series circuit of pMOS1 and a resistor R0 as shown in FIG. 1, the period of the clock signal C is the potential difference V between the power supply terminal Vbb and the output terminal OUT._onBased on, it changes as shown in FIG. In this case, the period of the clock signal C is the potential difference V between the power supply terminal Vbb and the output terminal OUT._onHowever, the threshold voltage V in the overcurrent detection circuit 16_refIn the range slightly exceeding, the voltage shortens sharply, and the potential difference V between the power supply terminal Vbb and the output terminal OUT_onIn the range where is high to some extent, it gradually shortens.

[0048] As described above, the period of the clock signal C is the potential difference V between the power supply terminal Vbb and the output terminal OUT._onTherefore, the time required for the counter 15 to count the clock pulses of the clock signal C by a predetermined number is the potential difference V between the power supply terminal Vbb and the output terminal OUT._onIt will be decided based on. Time t₃₇In (FIG. 3), when the counter 15 counts a predetermined number of clock pulses of the clock signal C, the counter 15 outputs an L level signal D. By such an action, the output switch 11 is forcibly turned off and protected from destruction.

[0049] Normally, when a short circuit occurs in the load, whether the apparent load resistance becomes 50% or 0% due to the short circuit is determined between the power supply terminal Vbb and the output terminal OUT. Potential difference V_onObserved as. In other words, the potential difference V between the power supply terminal Vbb and the output terminal OUT_onIt is possible to judge the degree of abnormality that has occurred in the load. In this embodiment, the period of the clock signal C is set to the potential difference V between the power supply terminal Vbb and the output terminal OUT._onSince a configuration that can be changed based on It can be changed accordingly.

[0050] When the shutdown time is constant regardless of the magnitude of the potential difference between the power supply terminal Vbb and the output terminal OUT as in the conventional output circuit, when the degree of abnormality generated in the load is high and low. Neither can effectively protect the output switch from destruction. In the output circuit 10 of the present embodiment, for example, the degree of abnormality generated in the load is high, and the potential difference V between the power supply terminal Vbb and the output terminal OUT is high._onWhen is large, the output switch 11 can be forcibly turned off immediately, and when the degree of abnormality is low, the output switch 11 can be forcibly turned off after a certain period of time. Depending on the degree of anomaly, the output switch 11 can be effectively protected from destruction.

In the output circuit 10, the counter 15 counts the clock pulse of the clock signal C by a predetermined number for forcibly turning off the output switch 11, and the output switch 11 is forcibly turned off. Later, if the control signal "E" input from the input terminal IN is H level, the potential difference between the power supply terminal Vbb and the output terminal OUT becomes Vbat, and the overcurrent detection circuit 16 continues to H. The level overcurrent detection signal is output, and the clock generator 19 continuously generates the clock signal C. The period of the clock signal C at this time is the current I generated by the first current generation circuit 17, which depends on the potential difference between the power supply voltage Vbat and the ground potential.₁It is determined based on, and has a constant cycle.

[0052] The counter 15 starts counting the clock pulse of the clock signal C, and after the count has reached a predetermined number, in other words, the output switch 11 is forcibly turned off, and then the clock signal When the clock pulse of "C" is counted by another predetermined number, the output signal "D" is returned to the H level. When the signal D output by the counter 15 returns to the H level, the output switch 11 is turned on again based on the control signal E input from the input terminal IN. When the output switch 11 is turned on again, the output switch 11 keeps the on state and supplies the power supply Vbat to the load if the abnormality of the load is resolved. When the load abnormality continues even after the output switch 11 is turned on again, the counter 15 counts the clock pulses of the clock signal C again by a predetermined number by the above-mentioned operation, and the output switch 11 Is forced off again.

[0053] FIG. 5 shows a state of change in the shutdown time as a timing chart. Time t₅₀Then, when the control signal E rises to the H level, the H level AND signal F is input to the gate control circuit 12, and the output switch 11 is turned on. At this time, if an abnormality has occurred in the load and the output voltage Vout is about half the value of the voltage Vbat supplied to the power supply terminal Vbb, in the output circuit 10, the counter 15 is the power supply terminal Vbb and the output terminal OUT. Potential difference between_on1Counts the clock pulse of the clock signal "C" whose period is determined by. Time t₅₁Then, when the count number reaches a predetermined value, the counter 15 inputs the L level signal D to the AND circuit 14, and the AND signal F input to the gate control circuit 12 drops to the L level. The output switch 11 is forcibly turned off.

The counter 15 is set to the time t.₅₁After outputting the L level signal "D", it takes a predetermined time (T) to count another predetermined number of clock signals "C" with a fixed cycle._{OFF OFF}) After the lapse of time t₅₂Then, the signal "D" is raised to the H level. As a result, the logical product signal F input to the gate control circuit 12 rises to the H level, and the output switch 11 is turned on again. After the output switch 11 is turned on, when the abnormality that occurred in the load is not resolved, the time t in the example of FIG.₅₃Then, the output switch 11 is forcibly turned off again. Time t₅₂~ t₅₃At the time t, the abnormality that occurred in the load₅₀~ t₅₁When the output voltage Vout is about 1/4 of the voltage Vbat supplied to the power supply terminal Vbb, the potential difference V between the power supply terminal Vbb and the output terminal OUT_on2Is V_on1The period of the clock signal C is higher than that of the time t.₅₀~ t₅₁It becomes shorter than when, and the shutdown time becomes shorter.

[0055] Time t₅₄Then, when the counter 15 outputs the H level signal D, the output switch 11 is turned on. At this time, if the abnormality generated in the load is further progressing, the potential difference V between the power supply terminal Vbb and the output terminal OUT_on3Is V_on2Higher than the output switch 11 at time t₅₅And it is forcibly turned off. Time t₅₀Time t after the output switch 11 was turned on₅₁Time to be forcibly turned off by T_ON1And time t₅₂Time t after the output switch 11 was turned on₅₃Time to be forcibly turned off by T_ON2And time t₅₄Time t after the output switch 11 was turned on₅₅Time to be forcibly turned off by T_ON2Comparing with each other, T is based on the degree (progress) of the abnormality that occurred in the load._ON1&gt; T_ON2&gt; T_ON3Will be. As described above, in the present embodiment, the shutdown time can be shortened according to the progress of the abnormality generated in the load, and the output switch 11 can be effectively protected from destruction.

FIG. 6 shows the configuration of the output circuit according to the second embodiment of the present invention. In this embodiment, the circuit configuration is simplified as compared with the output circuit 10 of the first embodiment shown in FIG. The output circuit 10a includes an output switch 11, a gate control circuit 12a, an overcurrent detection circuit 16, a current generation circuit 17, and a shutdown signal generation circuit 22. In addition to the functions of the gate control circuit 12 (FIG. 1) in the first embodiment, the gate control circuit 12a has a function of forcibly turning off the output switch 11 when receiving a predetermined shutdown signal, and an output switch. It has a function of controlling the level of the signal input to the output switch 11 so that the current flowing through the 11 does not exceed a predetermined value.

[0057] The shutdown signal generation circuit 22 includes a charging pMOS8, a capacitor CP2, a switch SW3, and an operational amplifier OP3. The charging pMOS8 and the capacitor CP2 are inserted in series between the power supply lines of both the power supply V1, and the switch SW3 is inserted between the charging pMOS8 and the capacitor CP2. The gate of the charging pMOS8 is connected to the gate of the pMOS1 of the current generation circuit 17, and the charging pMOS8 and the pMOS1 of the current generation circuit 17 form a current mirror. The inverting input terminal of the operational amplifier OP3 is the power supply V._ref2It is connected to the power supply line on the low potential side of the power supply V1 via the capacitor CP2, and the non-inverting input terminal is connected to the power supply line on the low potential side of the power supply V1 via the capacitor CP2. The switch SW3 is switched based on the signal from the overcurrent detection circuit 16.

When the output switch 11 is on, an abnormality occurs in the load, and the overcurrent detection circuit 16 causes a potential difference V between the power supply terminal Vbb and the output terminal OUT._onIs the threshold V_refWhen it is detected that the value exceeds, the switch SW3 is closed in the shutdown signal generation circuit 22. At this time, the current generation circuit 17 has a current I that depends on the potential difference between the power supply terminal Vbb and the output terminal OUT.₁Is being generated. Capacitor CP2 has current I via charging pMOS8₁Charging current I determined based on₅The potential of the non-inverting input terminal of the operational amplifier OP3 is gradually increased by charging the capacitor CP2. When the potential of the non-inverting input terminal of the operational amplifier OP3 exceeds the potential of the inverting input terminal, the shutdown signal generation circuit 22 sends a predetermined shutdown signal to the gate control circuit 12a to forcibly turn off the output switch 11. Send.

[0059] In the present embodiment, although a simpler circuit configuration is adopted as compared with the first embodiment, the shutdown time is set according to the degree of abnormality generated in the load as in the first embodiment. Can be changed. Therefore, for example, the degree of abnormality generated in the load is high, and the potential difference V between the power supply terminal Vbb and the output terminal OUT_onWhen is large, the output switch 11 can be forcibly turned off immediately, and when the degree of abnormality is low, the output switch 11 can be forcibly turned off after a certain period of time. The output switch 11 can be effectively protected from destruction.

[0060] The current generation circuit 17 is not limited to the circuit configuration described above, and other circuit configurations may be adopted. In the output circuit of the present invention, the circuit configuration of the current generation circuit 17 is changed, and the potential difference V between the power supply terminal Vbb and the output terminal OUT is changed according to the load connected to the output terminal OUT._onAnd the current I generated by the current generation circuit 17₁By properly setting the characteristics of and, the potential difference V between the power supply terminal Vbb and the output terminal OUT_onThe relationship between and the shutdown time can be adjusted. 7 to 9 (a) show different examples of the circuit configuration of the current generation circuit 17, respectively, and FIGS. 7 to 9 (b) show the current generation circuit 17 in the output circuit 10 from FIG. 7 to 7, respectively. Potential difference V between power supply terminal Vbb and output terminal OUT when configured as shown in Fig. 9 (a)_onThe relationship between the clock signal C and the period of the clock signal C is shown as a graph.

[0061] For example, in the current generation circuit 17 (FIG. 1), the current generation circuit 17a (FIG. 7 (a)) in which the resistor R0, which is the load element of pMOS1, is replaced with the depletion type nMOS9 whose source is connected to the gate. ), The potential difference V between the power supply terminal Vbb and the output terminal OUT_onDepending on, the period of the clock signal C changes as shown in FIG. 7 (b). Fig. 7 (b) and the potential difference V between the power supply terminal Vbb and the output terminal OUT in the current generation circuit 17_onComparing the relationship between the clock signal C and the clock signal C (Fig. 4), in Fig. 7 (b), the potential difference V between the power supply terminal Vbb and the output terminal OUT_onThe change in the period of the clock signal "C" is small in the region where is larger than a certain level.

[0062] As a load element of pMOS1, a current generation circuit 17b having a circuit configuration in which a Zener diode D5 is inserted between pMOS1 and nMOS9 of the current generation circuit 17a having the circuit configuration shown in FIG. 7 (a) (FIG. 8 (FIG. 8). In a)), the potential difference V between the power supply terminal Vbb and the output terminal OUT_onDepending on, the period of the clock signal C changes as shown in FIG. 8 (b). Comparing FIG. 8 (b) and FIG. 7 (b), in FIG. 8 (b), due to the Zener diode D5, the graph shown in FIG. 7 (b) shows the potential difference V between the power supply terminal Vbb and the output terminal OUT._onIs shifting to the high potential side of.

[0063] The current generation circuit may adopt a configuration in which a plurality of load elements having different current-voltage characteristics are connected in parallel. For example, in the current generation circuit 17c (FIG. 9 (a)), the load of nMOS9a, which is the load element of pMOS1 in the current generation circuit 17a (FIG. 7 (a)), and the load of pMOS1 in the current generation circuit 17b (FIG. 8 (a)). The nMOS9b and the Zener diode D5, which are elements connected in series, are connected in parallel. In this current generation circuit 17c, as shown in FIG. 9B, the potential difference V between the power supply terminal Vbb and the output terminal OUT_onThe relationship between the clock signal C and the period of the clock signal C is similar to that of Fig. 7 (b) and Fig. 8 (b), and the period of the clock signal C changes significantly in two stages.

[0064] In FIG. 5, the off time (T) from when the counter 15 outputs the L level signal D to when the signal D is raised to the H level._{OFF OFF}) Was constant regardless of the previous shutdown time, but instead, the off time T_{OFF OFF}May be changed according to the immediately preceding shutdown time. For example, the output circuit 10 is further arranged with a timer circuit that generates an off time with reference to the immediately preceding shutdown time, and the timer circuit raises the output signal D of the counter 15 to the H level. It may be adopted. In this case, the timer circuit has an off time T when the previous shutdown time is short._{OFF OFF}Is set long, and when the previous shutdown time is long, the off time T_{OFF OFF}It is possible to adopt a configuration in which is set short.

[0065] Although the present invention has been described above based on the preferred embodiment, the output circuit of the present invention is not limited to the above embodiment, and may vary from the configuration of the above embodiment. Modified and modified output circuits are also included within the scope of the present invention.

[Effect of the Invention] As described above, in the output circuit of the present invention, the time when the protection circuit detects that the load current flowing through the output transistor exceeds the threshold value by the current detection circuit, that is, , To adopt a configuration in which the off signal generation circuit generates a signal to turn off the output transistor after an elapsed time that depends on the voltage drop of the output transistor from the time when an abnormality has occurred in the load. , The time during which an abnormal current flows through the output transistor can be changed according to the degree (degree) of the abnormality that has occurred in the load. Therefore, for example, when the degree of abnormality generated in the load is high, the output transistor is turned off immediately, and when the degree of abnormality is low, the output transistor is turned off after a relatively long time has elapsed, and the degree of abnormality generated in the load is turned off. The output transistor can be effectively protected from destruction due to abnormal current both when the value is high and when the value is low.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of an output circuit according to an example of the first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a gate control circuit 12.

FIG. 3 is a timing chart showing a state of generation of a clock signal C.

FIG. 4: Potential difference V_onA graph showing the relationship between the clock signal C and the period of the clock signal C.

FIG. 5 is a timing chart showing a change in shutdown time.

FIG. 6 is a block diagram showing a configuration of an output circuit according to a second embodiment of the present invention.

7 (a) is a circuit diagram showing another example of the circuit configuration of the current generation circuit 17, and FIG. 7 (b) is a potential difference V._onA graph showing the relationship between the clock signal C and the period of the clock signal C.

8 (a) is a circuit diagram showing another example of the circuit configuration of the current generation circuit 17, and FIG. 8 (b) is a potential difference V._onA graph showing the relationship between the clock signal C and the period of the clock signal C.

9 (a) is a circuit diagram showing another example of the circuit configuration of the current generation circuit 17, and FIG. 9 (b) is a potential difference V._onA graph showing the relationship between the clock signal C and the period of the clock signal C.

[Description of Code] 10: Output circuit 11: Output switch 12: Gate control circuit 13: Current limiting circuit 14: AND circuit 15: Counter 16: Overcurrent detection circuit 17, 18: Current generation circuit 19: Clock generator 20: AND circuit 21: Inverter 22: Shutdown signal generation circuit OP1, OP2: Optics CP1, CP2: Capacitor D1 ~ D5: Diode R0 ~ R3, R21, R22: Resistance SW1, SW2: Changeover switch