Memory system and memory apparatus

The present invention relates to a memory system, and more particularly to a memory system including a memory device having a dual voltage port.

[0002] In general, a memory system inputs an external power supply voltage (hereinafter referred to as "Vext voltage") to a voltage lower than Vext (hereinafter referred to as "VCC voltage") or a voltage higher than Vext. It is used as an operating power source by generating (hereinafter referred to as "VPP voltage"). The VCC voltage is used to satisfy low power consumption, and as shown in FIG. 1, the voltage regulator 110 in the memory system 100 receives a Vext voltage, eg 5V, and drops it by a predetermined voltage. Generates a VCC voltage of 3.3V. The VCC voltage is used as the operating power source for the controller 120 and DRAM 130.

[0003] The VPP voltage is used to compensate for the threshold voltage (hereinafter referred to as Vt) loss of a transistor. In particular, the VPP voltage is used in DRAM wordline driver circuits, bitline isolation circuits, data output buffers, and the like. The wordline driver circuit provides the VPP voltage to the wordline voltage. As a result, even if there is a Vt loss of the MEMS transistor of the DRAM cell, the data "high (H)" can be written to the DRAM cell during the write operation, and the DRAM cell data "H" can be sufficiently written during the read operation. It can be transmitted to the bit line. The bitline isolation circuit uses an NMOS transistor to connect the shared sense amplifier and the memory block when the DRAM has a shared sense amplifier structure. Using the VPP voltage as the gate voltage for this NMOS transistor, the H data in the data line is fully VCC (Full) into the memory cell of the selected memory block. VCC) Voltage can be transmitted. In the data output buffer, if the VCC voltage is lowered from 5V to 3.3V, for example, and if an NMOS circuit is used instead of the CMOS circuit to prevent latch-up, the charging speed of the load will increase due to the Vt loss of the NMOS transistor. It decreases and the VOH level becomes insufficient. Therefore, by applying the VPP voltage to the gate voltage of the NMOS transistor, it is driven at high speed to a sufficient VOH level.

[0004] A technique for providing VPP voltage is disclosed in US Pat. No. 6,320,457. According to the 6,320,457 patent, the VPP voltage is generated through the first and second high voltage pump parts. The high voltage pump unit obtains the VPP level by performing a pumping operation according to the pulse signal of the oscillation unit. Normally, the pumping operation is performed through the charge pump circuit, and in particular, the charge pumping operation consumes a large amount of current. Furthermore, in order to generate a higher VPP voltage, more current must be consumed, and the pumping efficiency of the charge pumping operation for the higher voltage is relatively lower than the pumping efficiency of the VPP voltage.

[0005] Therefore, if a voltage generating unit including a high voltage pump unit as in the 6,320,457 patent is adopted in the low voltage system, the ratio of the charge pumping current to the operating current of the entire low voltage system becomes large. This becomes a problem of deteriorating the performance of a low voltage system for the purpose of low power consumption.

[0006] Therefore, a memory system that satisfies the demand for low power consumption and can selectively use the VCC voltage and the VPP voltage is required.

[0007] [Patent Document 1] US Pat. No. 6,320,457 [0008] [Problems to be Solved by the Invention] An object of the present invention is a memory that satisfies the demand for low power consumption and uses VCC voltage and VPP voltage. To provide the system.

[0009] Another object of the present invention is to provide a semiconductor memory device that inputs a VCC voltage and a VPP voltage into the memory system.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the memory system according to the first embodiment of the present invention receives a first power supply voltage and generates a second power supply voltage with a voltage regulator. Includes a memory controller that is connected to a second power supply voltage and generates a control signal, and a memory device that is connected to a second power supply voltage and determines whether or not to be connected to a first power supply voltage in response to a control signal. .. The control signal can be the mode register information of the memory device.

[0011] In order to achieve the above-mentioned object, the memory system according to the second embodiment of the present invention receives a first voltage regulator that receives a first power supply voltage and generates a second power supply voltage, and receives a first power supply voltage. The second voltage regulator that generates the third power supply voltage, the memory controller that is connected to the second power supply voltage and generates the control signal, and the third power supply voltage that is connected to the second power supply voltage and responds to the control signal. Includes a memory device that determines whether or not to be connected with.

[0012] In order to achieve the other object described above, the memory device according to the first embodiment of the present invention has a first voltage generating unit that receives a first power supply voltage and generates a first internal voltage, and a first power supply. A second voltage generator that receives a voltage and generates a second internal voltage, a third voltage generator that receives a second power supply voltage and generates a second internal voltage, a second voltage generator that receives a control signal, and It includes a switching unit that selectively operates the third voltage generating unit. The control signal is, for example, a signal given by a mode register in the memory device.

[0013] In order to achieve the other object described above, the memory device according to the second embodiment of the present invention has a first voltage generating unit that receives a first power supply voltage and generates a first internal voltage, and a first power supply. Connect the first power supply voltage to the input of the second voltage generator that receives the voltage and the second power supply voltage and generate the second internal voltage, and the input of the second voltage generator that receives the control signal, or connect the second power supply voltage. Includes a switching unit that determines whether to connect.

[0014] In order to achieve the other object described above, the memory device according to the third embodiment of the present invention has a voltage generating unit that receives a first power supply voltage and generates a high voltage, and responds to a control signal. The voltage generating unit includes a switching unit that determines whether to select the generated high voltage or the second power supply voltage. To give a specific example, examples of the switching unit include, for example, an inverter that inputs a control signal and enables the voltage generating unit by its output, and a switch that connects a second power supply voltage to a high voltage in response to the control signal. Can include. Other examples of the switching unit are an inverter that inputs a control signal and enables the voltage generator by its output, a level shift that inputs a control signal, and a boosted voltage of the second power supply voltage in response to the output of the level shift. Can include transistors connected to.

[0015] Therefore, the present invention does not generate a boosted voltage inside the memory device, and either lowers the external power supply by a predetermined voltage or uses the external power supply as it is as the boosted voltage. Since the memory device of the present invention and the memory system including the memory device do not require a charge pumping operation for generating a boosted voltage, it is possible to reduce the power consumption.

[Embodiments of the Invention] Hereinafter, a memory device for inputting a dual voltage and a memory system including the memory device will be described. Here, the dual voltage is shown as VCC1 and VCC2, and VCC2 is a voltage (high voltage) higher than VCC1 and means a kind of VPP voltage.

FIG. 2 is a drawing showing a memory system according to an embodiment of the present invention. In FIG. 2, the memory system 200 shows a voltage regulator 210, a controller 220, and a memory device 230. The voltage regulator 210 receives a first power supply voltage Vext, which is an external power supply, for example, a voltage of 5V, drops it by a predetermined voltage, and generates a second power supply voltage VCC1 of 3.3V. The memory controller 220 is driven by the second power supply voltage VCC1 and controls the operation of the memory system 200. The control signal CNTL generated from the memory controller 220 is applied to the memory device 230 to select the operating power source of the memory device 230. The memory device 230 is connected to the second power supply voltage VCC1 of 3.3V, and is also configured to be able to be connected to the first power supply voltage Vext of 5V, and is connected to the first power supply voltage Vext in response to the control signal CNTL. Decide whether or not to use it. When the memory device 230 is connected to the first power supply voltage Vext, the first power supply voltage Vext of 5V is used as a voltage source for generating a high voltage in the voltage generator in the memory device 230. This voltage generator is configured to drop the input voltage by a predetermined voltage, and receives a 5V first power supply voltage Vext to generate a high voltage of about 4.5V. The details will be described later with reference to FIG.

[0018] The control signal CNTL is an external signal provided from the memory controller 220 to the memory device 230, the control signal CNTL is a signal indicating that the power mode is low, and the information corresponding to this signal is the memory device 230. It can be set in the inner mode register MRS. As a result, the memory device 230 is connected to the first power supply voltage Vext according to the information stored in the mode register MRS. Therefore, since the memory device 200 of the present embodiment uses the 5V first power supply voltage Vext as a power supply for generating a high voltage of 4.5V, the charge pumping operation for generating the boosted voltage as in the conventional case is unnecessary. Yes, it is possible to reduce power consumption.

FIG. 3 is a drawing showing a memory system 300 according to a second embodiment of the present invention. In FIG. 3, the memory system 300 includes a first voltage regulator 310, a second voltage regulator 320, a controller 330, and a memory device 340. The first voltage regulator 310 receives the 5V first supply voltage Vext and generates the 3.3V second supply voltage VCC1. The second voltage regulator 320 receives the first power supply voltage Vext of 5V and generates the third power supply voltage VCC2 of 4V. The memory controller 330 is connected to a second power supply voltage VCC1 of 3.3V and generates a control signal CNTL to control the operation of the memory system 300. The memory device 340 is connected to the 3.3V second power supply voltage VCC1 and determines whether or not it is connected to the 4V third power supply voltage VCC2 in response to the control signal CNTL. The information corresponding to the control signal CNTL can be set in the mode register MRS in the memory device 340.

Therefore, when the memory device 340 of the present embodiment requires a high voltage of about 4V, which is lower than the first power supply voltage Vext of 5V, the high voltage required by the memory device 340 in response to the control signal CNTL. Since the third power supply voltage VCC2 is used as the voltage booster, no charge pumping operation is required to generate a boosted voltage. Therefore, the power consumption of the memory device 340 is reduced, and the demand for lower power consumption of the memory system 300 is satisfied.

[0021] FIGS. 4 to 7 are drawings showing a memory device having a dual voltage port. The memory device 400 according to the first embodiment of FIG. 4 includes first to third voltage generation units 410, 420, 430 and a switching unit 440. The first voltage generator 410 receives the 3.3V first power supply voltage VCC1 and drops it by a predetermined voltage to generate the 2.4V first internal voltage Vint1. The second voltage generation unit 420 receives the first power supply voltage VCC1 of 3.3V, boosts it by a predetermined voltage, and generates the second internal voltage Vint2 of 4.5V. The third voltage generation unit 430 receives the second power supply voltage VCC2 of 5V, drops it by a predetermined voltage, and generates the second internal voltage Vint2 of 4.5V. Therefore, the third voltage generator 430 does not need a charge pumping operation.

On the other hand, if the second power supply voltage VCC2 is about 4V, the third voltage generator 430 boosts the 4V second power supply voltage VCC2 by a predetermined voltage to generate a 4.5V second internal power supply voltage Vint2. .. Here, since the third voltage generating unit 430 boosts the voltage difference of 0.5V, which is smaller than the voltage difference of 1.2V boosted by the second voltage generating unit 420, the charge pumping amount may be small. The switching unit 440 receives the control signal CNTL or the mode register information and selectively operates the second voltage generation unit 420 and the third voltage generation unit 430. The switching unit 440 incorporates an inverter 442 that is linked to the control signal CNTL or mode register information. The second voltage generator 420 is enabled by the inverted control signal CNTL or the inverted mode register information which is the inverter 442 output, and the third voltage generator 430 is enabled by the control signal CNTL or the mode register information which is the inverter 442 input. Will be done.

Therefore, the memory device 400 of the present embodiment selectively operates the second voltage generation unit 420 or the third voltage generation unit 430 according to the power mode specification. In the low power mode, the memory device does not require the charge pumping operation from the second power supply voltage VCC2 level by the third voltage generator 430, or even if the charge pumping operation is performed, the pumping amount is small. Therefore, the demand for low power consumption is satisfied.

[0024] FIG. 5 is a drawing showing a memory device according to the second embodiment. In FIG. 5, the memory device 500 includes a first voltage generating unit 510, a second voltage generating unit 520, and a switching unit 530. The first voltage generator 510 receives the 3.3V first power supply voltage VCC1 and drops it by a predetermined voltage to generate the 2.4V first internal voltage Vint1. The second voltage generating unit 520 is selectively connected to the first power supply voltage VCC1 or the second power supply voltage VCC2 to generate the second internal voltage Vint2. The switching unit 530 determines whether to connect the input of the second voltage generating unit 520 to the first power supply voltage VCC1 or the second power supply voltage VCC2 in response to the control signal CNTL or the mode register MRS information. When the second voltage generator 520 is connected to the 3.3V first power supply voltage VCC1, the 3.3V first power supply voltage VCC1 is boosted by a predetermined voltage in order to generate the 4.5V second internal voltage Vint2.

On the other hand, when the second voltage generating unit 520 is connected to the second power supply voltage VCC2 of 5V, the second voltage generating unit 520 generates the second internal voltage Vint2 of 3V, so that the second voltage generating unit 520 is the second power supply of 5V. The voltage VCC2 is lowered by a predetermined voltage. In this case, the second voltage generating unit 520 does not need a charge pumping operation. If the second power supply voltage VCC2 is about 4V, the second voltage generator 520 boosts about 0.5V to generate the second internal voltage Vint2 of 4.5V. In this case, the charge pumping amount is smaller than that of boosting the first power supply voltage VCC1 of 3.3V to 4.5V.

Therefore, when the memory device 500 of the present embodiment is in the normal power mode, the first power supply voltage VCC1 is connected to the second voltage generation unit 520. Then, in the low power mode, the second power supply voltage VCC2 is connected to the second voltage generation unit 520 to eliminate the need for the charge pumping operation from the second power supply voltage VCC2 level, or the charge pumping operation is performed. Even so, the amount of pumping is small, so the demand for low power consumption is satisfied.

[0027] FIG. 6 is a drawing showing a memory device according to a third embodiment. In FIG. 6, the memory device 600 includes a boosted voltage generating unit 610 and a switching unit 620. The step-up voltage generator 610 receives the first power supply voltage VCC1 of 3.3V and generates a step-up voltage VPP of 4V. The switching unit 620 determines whether to select the boosted voltage generated from the boosted voltage generating unit 610 or the second power supply voltage VCC2 as the boosted voltage VPP in response to the control signal CNTL or the mode register MRS information. The switching unit 620 inputs the control signal CNTL or mode register MRS information and uses the output to enable the boosted voltage generator 610, and the switching unit 620 boosts the second power supply voltage VCC2 by the control signal CNTL or mode register MRS information VPP. Includes switch 624 to be connected to.

Therefore, when the memory device 600 according to the present embodiment uses the second power supply voltage VCC2 as the boosted voltage VPP, the boosted voltage generator 610 is not operated and the second power supply voltage VCC2 is connected to the boosted voltage VPP. Let me. As a result, power consumption due to the charge pumping operation does not occur, so that there is an advantage that the power consumption of the memory device 600 can be reduced.

[0029] FIG. 7 is a drawing showing a memory device according to a fourth embodiment. In FIG. 7, the memory device 700 includes a boosted voltage generating unit 710 and a switching unit 720. The switching unit 720 differs from the switching unit 620 of FIG. 6 in that it includes a level shift 724 and a transistor 726. In order to avoid duplication of description, the description of the step-up voltage generating unit 710 and the inverter 722 in the switching unit 720 will be omitted. The level shift 724 inputs the control signal CNTL or the mode register MRS information and outputs it at a predetermined voltage level, for example, a voltage level of about the second power supply voltage (VCC2) + Vth. Transistor 726 is turned on in response to the output of level shift 724, and the second supply voltage VCC2 is connected to the boost voltage VPP. At this time, the second power supply voltage VCC2 is transmitted to the boosted voltage VPP without loss of the threshold voltage Vth of the transistor 726.

[0030] Although the present invention has been described above with reference to some embodiments, this is merely an exemplary description and is not intended to limit or limit the technical idea and scope of the present invention. .. For example, the voltage generating unit in the memory device according to the first to fourth embodiments of the present invention may be configured to lower the input voltage by a predetermined voltage in order to satisfy the demand for low power consumption. , The input voltage may be configured to be boosted by a predetermined voltage. In this way, various changes and changes can be made without departing from the technical idea and scope of the present invention.

[Effect of the Invention] As described above, in the memory device of the present invention and the memory system including the memory device, the external power supply is lowered by a predetermined voltage or charged without generating a boosted voltage inside the memory device. Since the voltage is boosted by a predetermined voltage in a range where the pumping amount is small, the demand for low power consumption is satisfied. Alternatively, by using the external power supply as the boosted voltage as it is, the charge pumping operation for generating the boosted voltage is not required, so that the power consumption can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS [FIG. 1] FIG. 1 is a drawing showing a conventional memory system.

FIG. 2 is a drawing showing a memory system according to the first embodiment of the present invention.

FIG. 3 is a drawing showing a memory system according to a second embodiment of the present invention.

FIG. 4 is a drawing showing a memory device according to the first embodiment of the present invention.

FIG. 5 is a drawing showing a memory device according to a second embodiment of the present invention.

FIG. 6 is a drawing showing a memory device according to a third embodiment of the present invention.

FIG. 7 is a drawing showing a memory device according to a fourth embodiment of the present invention.

[Code description] 210 Voltage regulator 220 Controller 230 Memory device