Data processing device and method of computing the cosine transform of a matrix

Technical Field The present invention relates to the data processing apparatus described in the feature description portion of claim 1. Background Techniques Such data processing devices are known from PCT Patent Application No. 97/31308. This data processing device is SIMD (Single Instruction Multiple) Allows parallel processing under the control of parallel instructions such as Data) instructions. The SIMD instruction applies the same operation many times in parallel. In general, SIMD instructions usually define two operands by register address. The contents of each of these operands are treated as multiple segments of packed data. For example, the contents of a 64-bit register can be treated as four 16-bit numbers at bit positions 0-15, 16-31, 32-47, and 48-63 in this register. When the data processor encounters a SIMD instruction, the same operation is applied in parallel to several different pairs of numbers in the operand. For example, the contents of bit positions 0-15 in the first operand register are added to the contents of bit positions 0-15 in the second operand register, and the contents of bit positions 16-31 in the first operand register are the first. 2 Operand Added to the contents of bit positions 16-31 in the register. SIMD instructions can be used to reduce the number of instructions that must be executed to perform a single function. For example, consider the ability to perform a Discrete Cosine Transform (IDCT) on individual columns of blocks of pixel values. Pixel values in different rows of blocks are stored in different operands. In each operand, the pixel value is determined by the pixel value column of the positions in the segment.It is stored in the full position. For example, in the case of the first register, the pixel values in the first row and the first column are stored in the bit positions 0-15, and the pixel values in the first row and the second column are stored in the bit positions 16-32. In the second register, the pixel values from the second row are stored, and similarly, the pixel values in each row are stored at the positions determined by the respective columns. As a result, if you execute a series of instructions coded for an operation that applies IDCT to one column, IDCT will automatically execute in parallel for many columns if all arithmetic operations are performed using SIMD instructions. Will be done. This reduces the number of instructions that need to be executed. For separable 2D IDCTs, 1D IDCTs need to be applied to individual columns and individual rows of blocks. In this case, the number of instructions can be reduced in the same way by exchanging the roles of rows and columns between column conversions. Row and column roles can be exchanged by replacing blocks. This replacement stores the different pixel values in one column in the same register instead of the different pixel values in one row. That is, the replacement moves the contents of the corresponding positions (in the same column) of different registers to different positions in another register. However, the execution of the replacement itself requires the addition of a significant number of instructions. For this reason, two-dimensional conversion requires more than twice the number of instructions required for one-dimensional conversion. This constraint on the benefits of SIMD is generally even greater when you have to program features that require you to combine data in non-corresponding positions in the packed data. In this case, SIMD parallel instructions that handle the contents of the operands cannot be used as a packed format containing numbers that are independent of each other, and at least additional operations are required to sort the data so that SIMD operations can be used. .. Disclosure of the Invention An object of the present invention is to provide the processing apparatus described in the description, which can further reduce the number of instructions that need to be executed. Data processing of the present invention The physical device is characterized by the feature description portion of claim 1. This allows you to program parallel operations that combine segments that are not identical to each other in the operands, or use different operations to create different combinations of operand segments. This is in contrast to the prior art SIMD instructions, which apply the same operation to a pair of segments at the same location each time. In the case of the instruction of the present invention, for example, the numerical value stored in the bit positions 0-15 of the operand register is added to the numerical value stored in the bit positions 16-31, and in parallel with the numerical value stored in the bit positions 32-47. The stored number is added to the number stored at bit positions 48-63. Instructions can be provided for both operations that combine segments in the same operand register and operations that combine segments in different operand registers. Any one or more segments can be used in more than one operation. All operations performed in parallel can be of the same type (eg, all additions) or different operations (eg, all add). Addition and subtraction) is also acceptable. In general, other than SIMD instructions, application-specific instructions that combine segments will provide only a very limited instruction set. For example, when instructions are available that perform operations such as addition between specific segments at different positions, it is not necessary to have an instruction set to program the operations between all possible segment pairs. Similarly, when instructions are available that combine some segment pair (at least one of the operations differs from the other) into its own operation, instructions for all possible combinations of operations applied to those segments. There is no need to prepare a set. For any application, only a small portion of all possible operations or all possible combinations of operations and / or a small portion of all possible combinations of segments are required. For separable two-dimensional transformations of blocks, the present invention makes it possible to reduce the number of instructions required without block replacement. Each register may contain different pixel values from one row, and another register may store pixel values from the same column in the same segment. Column conversions will be performed using SIMD instructions, but row conversions will be performed by parallel computing that combines pixel values from the same row in different segments. For example, it is possible to provide an IDCT instruction that calculates the IDCT of the entire row from the pixel values of the row stored in different segments of the operand register referenced in the IDCT instruction. You can also use an operation to calculate the sum and difference of the contents of pairs of different segments in a register. This operation is a type of operation that is generally required for IDCT transformations and similar transformations. As will be done, the row transformation is performed by parallel computing that combines pixel values from the same row in different segments. For example, it is possible to provide an IDCT instruction that calculates the IDCT of the entire row from the pixel values of the row stored in different segments of the operand register referenced in the IDCT instruction. You can also use an operation to calculate the sum and difference of the contents of pairs of different segments in a register. This operation is a type of operation that is generally required for IDCT transformations and similar transformations. The row transformation, as it will be, is performed by parallel computing that combines pixel values from the same row in different segments. For example, it is possible to provide an IDCT instruction that calculates the IDCT of the entire row from the pixel values of the row stored in different segments of the operand register referenced in the IDCT instruction. You can also use an operation to calculate the sum and difference of the contents of pairs of different segments in a register. This operation is a type of operation that is generally required for IDCT transformations and similar transformations.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and other advantages of the present invention described above will be exemplified by way of using the following figures. FIG. 1 shows a data processing device. Figure 2 shows an example of a data flow diagram of the execution of an 8-point one-dimensional IDCT. FIG. 3 shows a data flow diagram of an instruction according to the present invention. 4a and 4b show functional units for executing instructions according to the present invention. The best form for carrying out the invention Fig. 1 shows VLIW (Very Long Instruction). Indicates a Word) type data processor. The present invention has been illustrated using VLIW type devices, but is not limited to this type of device. This device has an instruction issuing unit 10, a large number of functional units 12a-c, and a register file 14. The instruction issuing unit 10 has an instruction output terminal combined with the functional unit 12a-c and the register file 14. The register file 14 has a read / write port coupled to the operand input / output end of the functional unit 12a-c. One functional unit 12a is illustrated in detail. This functional unit 12a has an instruction decoder 120, a large number of ALUs (arithmetic logic units) 122a to 122d, a first input register 124a and a second input register 124b, and an output register 126. The instruction decoder is coupled to ALU122a ~ 122d. The input registers 124a and 124b are divided into a large number of segments. The segments of the first input register 124a and the second input register 124b are ALUs. It is connected to 122a-d. During operation, the instruction issuing unit 10 accesses consecutive instructions in the program and issues those instructions to the functional unit 12a-c. Instructions issued in functional units 12a-c typically have one arithmetic code, two source register addresses, and one result register address (these elements of the instruction do not necessarily have to be issued at the same time). ). The operation code must be executed by the functional unit 12a-c.<u style="single">Re</u>Define one or more operations that must be done. The source register address refers to a register in the register file 14 that contains the operand for which one or more operations are to be performed. The instruction issuing unit 10 applies these addresses to the register file 14. The result register address refers to a register in the register file 14 that stores the results of one or more operations. The instruction issuing unit 10 applies the result register address to the register file 14. Most of the functional units 12a-c treat the contents of each register as one numerical value. For example, if the register length is 64-bit, its contents are treated as a 64-bit number that can be added to another 64-bit number, or can be arithmetically or logically shifted. However, at least some of the functional units 12a-c can (or can) treat the contents of a register as a series of numbers stored in each segment of the register. The following dedicated operations can be performed in parallel on these numbers independently of each other. That is, the carry bit does not carry from one segment to another, the shift does not carry the bit from one segment to another, clipping is performed independently for each segment, and so on. The functional unit 12a is a functional unit that treats the contents of each register as a plurality of segments in which individual numerical values are stored. For this purpose, all registers are virtually segmented in the same way. When the instruction is executed, the contents of each segment of the source register referenced in the instruction are applied to each of the ALU 122a-d. For SIMD instructions, the contents of the same segment in the two source operands are the same ALU Supplied to 122a-d. For example, suppose the operant is 64-bit and bit positions 0-15, 16-31, 32-47, 48-63 constitute four segments S0, S1, S2, S3, respectively. At this time, the contents of bit positions 0-15 of both operands are supplied to the first ALU 122a, and the contents of bit positions 16-31 are supplied to the second ALU 122b (the same applies hereinafter). In the case of SIMD instructions, the instruction decoder 120 applies the same control code to all of the ALU 122a-d. Therefore, the ALU 122a-d performs all the same types of operations (eg addition) on different segments. The SIMD instruction is, for example, the numerical value B._ijIt can be applied to the calculation of one-dimensional transformation of many columns of block B (eg 8 × 8 blocks (n = 7, m = 7)) of (i = 0..n, j = 0..m). Therefore, the numbers in the same row of blocks are loaded into each segment of one register. For example, the number B_0,0, B_0,1, B_0,2, B_0,3Is loaded into segments S0, S1, S2, S3 of the first register R1, respectively, and the numerical value B_0,4, B_0,5, B_0,6, B_0,7Is loaded into segments S0, S1, S2, S3 of the second register R2, respectively, and the numerical value B_1,0, B_1,1, B_1,2, B_1,3Is loaded into segments S0, S1, S2, S3 of the third register R3, respectively, and the numerical value B_1,4, B_1,5, B_1,6, B_1,7Is loaded into segments S0, S1, S2, and S3 of the fourth register R4, respectively. Here, there is a program that performs a one-column conversion, and this program is a one-column number B_ijSuppose that (i = 0..n) is represented by an instruction containing arithmetic instructions such as addition, subtraction, and multiplication applied to the register in which it is stored. If SIMD instructions are used for all of these arithmetic instructions, the program will automatically calculate the transformations in parallel for many columns j = 0.3. Therefore, in the case of a block with N columns and P numbers stored in each segment of each register, this program only needs to be executed N / P times to convert N columns. In the case of a separable 2D transformation, all columns can be transformed as described above. Then you need to convert all the rows of the converted block. An example of such a two-dimensional transformation is a two-dimensional IDCT. In this case, block A after conversion_ijIs expressed as follows. A_ij= 2 / N Σ_uΣ_vC_uC_vB_{u, v}cos ((2i + 1) uπ / 2N) cos ((2j + 1) vπ / 2N) Where u = 0 C_u= 1 / sqrt (2), otherwise C_u= 1 and summing is performed for integers from 0 to N-1. This two-dimensional transformation is first INT_iv= Σ_uC_uB_{u, v}Intermediate block INT by one-dimensional transformation called cos ((2i + 1) uπ / 2N)_ivAnd then to this intermediate block the next one-dimensional transformation A_ij= 2 / NΣ_vC_vINT_{i, v}It can be calculated by applying cos ((2j + 1) vπ / 2N). Therefore, this two-dimensional transformation is calculated as the composition of two one-dimensional transformations, that is, the transformation that makes B into INT and the transformation that makes INT into A (the "composition" of two transformations is the application of one transformation. It means that another transformation is applied to the result). In the IDCT example, it doesn't matter which one-dimensional transformation is applied first. In this example, first block B_{u, v}The sum is calculated along the first subscript of, and then the sum is calculated along the second subscript v, but the final result is the same even if the order is reversed. Such a two-step two-dimensional conversion can increase the calculation speed by using the SIMD instruction. Number B in intermediate block B_{u, v}Is stored as described above, that is, the number B in the same row_{u, v}When (v = 0,1,2,3) is stored in each segment of the register, the intermediate block INT_{i, v}The calculation of can be performed by converting a large number of columns in parallel (all the values of v = 0 in the first column, all the numbers of v = 1 in the second column, and so on). For example, INT in the segment of the first register_{i, v}(i = 0.3, v = 0) are stored respectively, and INT is stored in the segment of the second register._{i, v}(i = 4..7, v = 0) are stored respectively, and INT is stored in the segment of the 3rd register._{i, v}The numbers in the intermediate block are stored in the registers so that some numbers in one column are stored in one register so that (i = 0.3, v = 1) are stored respectively (and so on). If so, it is possible to perform similar parallel processing using the SIMD instruction. In this case, many lines of intermediate block INT can be converted in parallel using SIMD instructions. However, after the calculation of the intermediate block INT from block B, the numbers will not be stored in the registers in this way. That is, some number INTs in one column_{i, v}(i = 0.3 v = 0) is not stored in one register, but several integers in one row INT_{i, v}(i = 0 v = 0.3) will be stored in each register. The reason for this is that while the calculation of the intermediate block requires individual one-dimensional conversion for each column, the calculation of the final block A requires individual one-dimensional conversion for each row. To be able to use SIMD instructions for both types of conversions, you need to replace the intermediate blocks, that is, reorganize the numbers between the registers. This is a complicated operation. In the 4-segment register, 8x8 block example, 16 registers and 32 operations with 2 inputs are required for replacement. An object of the present invention is to eliminate the need for this replacement. For row conversions, the placement of numbers in intermediate blocks where different numbers in the same row are stored in registers is maintained, and one-dimensional conversion is performed in the rows stored in these registers. A dedicated instruction is used to combine these numbers in these registers. By using dedicated instructions, it is possible to perform a two-dimensional separable transformation without replacement. In addition, conversions of 3D and above can be used without the need for other measures by combining this dedicated instruction for 1D and SIMD type operations for 2D and above. In the simplest execution example, there is at least one functional unit that can execute the entire IDCT in one line. For an 8-point IDCT that uses registers that store each of the four numbers in a column, such an instruction requires two operand registers and two result registers. Figure 2 shows an example of a data flow diagram of the execution of an 8-point one-dimensional IDCT. This data flow diagram is published in Proceedings International Conference on Acoustics, Speech and Signal Processing 1989 (IC-IASSP '89), pp. 988-991, by C. Loeffler, A. Ligtenberg, G. It is based on an article entitled "Practical Fast 1-D DCT Algorithms with 11 multiplications" published by Moschytz et al. Nodes 30a-h on the left represent numbers by the value of the subscript v at position v = 0.7 in the line that needs to be converted. The right node 32a-h represents the converted numerical value by the value of the subscript j at the position j = 0.7 in the converted line. The lines from nodes 32a-h represent the data flow from the numerical value to each operation and the data flow from the result of these operations to another operation or the converted numerical value. The operation is expressed as follows. The dots entered by the two solid lines represent the total. The dots entered by one solid line and one broken line represent subtraction, and the number sent along the solid line is subtracted from the number sent along the broken line. A box with two inputs and two outputs represents rotation and factorization, that is, the calculation from (X0, Y0) to (X1, Y1) according to the following equation. X₁= I (X₀cosψ-Y₀sinψ) Y₁= I (X₀sinψ + Y₀In the cosψ) box, the value of the coefficient I and the identification of the angle ^ are written, and these are predetermined values. Blocks can be performed using four multiplications, additions, and subtractions (alternatively, three multiplications and three additions can be used). In the case of one execution example, at least one functional unit that can execute the row IDCT instruction that IDCT-converts the contents of the segment of the operand by the row IDCT instruction is provided. The 8-point IDCT example with 4 segments per register requires two operands to convert the rows. And in such an instruction, the numerical value representing the conversion is the frequency position (frequency) in the conversion. It requires two result registers to be written to each segment according to position). Execution of IDCT by such a functional unit is much faster than execution by individual instructions. The reason is that at least the combination of numerical values stored in segments at different positions in the operand can be realized by wiring within the functional unit. This wiring is unique to IDCT. Furthermore, in the data flow diagram of Fig. 3, since a considerable number of parallel processes can be performed in such a functional unit, it is possible to further increase the execution speed by executing a large number of operations in parallel. It is shown that. Thus, the 2D IDCT transformation uses the arithmetic SIMD instruction for columns, applies the 1D IDCT transformation in parallel to many columns, and uses a separate dedicated IDCT instruction for rows. It can be performed functionally by applying the same IDCT transformation to the rows. Depending on the processor architecture, the functional unit may need to use a standard instruction format that typically contains one arithmetic code, two source register references, and one result register reference. In this case, each functional unit can have two ports connected to the register file read port and one port connected to the register file write port. However, in the case of an IDCT instruction that converts a numerical value stored in two or more registers, two or more result registers are required to write the converted numerical value. For architectures that can only use one result register, this requirement can be achieved in a variety of ways, including staggering the time to write results to logically adjacent result registers. Alternatively, a combination of two instructions issued in parallel for each functional unit can be used. Normally, two such instructions would be used in parallel for two functional units. Instead, a combination of two instructions is used to program one functional unit that performs IDCT. The combination of these two instructions By using it, you can specify two different result registers. For processors that have one write port to the register file for each instruction issued in parallel, this method ensures that one write port to the register file is available for both results. .. Alternatively, two types of instructions can be defined for a functional unit: an instruction that produces half of the numbers in the register and an instruction that produces the other half. More generally, a dedicated instruction may be provided for each part of the IDCT calculation so that no instruction requires more result registers than the maximum number of result registers (eg: 1). In order to select such an instruction, the IDCT data flow diagram may be divided into partial diagrams and one dedicated instruction may be assigned to each partial diagram. By keeping the number of outputs of all partial diagrams to a certain number or less, it is possible to eliminate the need for two or more result registers for any dedicated instruction. FIG. 3 shows an example of the division into the partial view indicated by the dashed box 39a-g. Each box defines a data flow of numerous dedicated instructions that provide a combination of operations performed in parallel to speed up the calculation of the transformation. The number of segments required for the result of each instruction is 4 or less. These instructions make sure that the location of the number in each segment corresponds to the location required for SIMD conversion, that is, the number in each segment of the first register indicated by v = 0.3 on the left side of Figure 3. And, it is defined to correspond to the numerical value in each segment of the second register indicated by u = 4..7. The first instruction INS1 R1, R2, corresponding to the first dashed box 39a, which is the first example. R3 refers to two registers R1 and R2 as operands. By this instruction, the functional unit executes the following operations in parallel. --Add the numerical value (v = 0) in the first segment of the first register R1 and the numerical value (v = 4) in the first segment of the second register R2. The result is stored in the first segment of the result register R3. --The same two numbers are subtracted and the result is stored in the second segment of the result register R3. --The numerical value in the 3rd segment (v = 2) of the 1st register R1 and the numerical value in the 3rd segment of the 2nd register R2 are X in the coefficient sqrt (2) and the rotation of the predetermined sine value and cosine value.₀, Y₀Used as. The result X₁, Y₁Is stored in the 3rd and 4th segments of the result register. Figure 4b shows an example of functional unit 40 for executing the INS1 instruction. The functional unit 40 is the sum of the two input sections 42 and 46 that receive the contents of the first register R1 and the second register R2, the instruction decoder 48 that operates this functional unit, and the first segment S0 of R1 and R2. It has an arithmetic circuit 44a-c that calculates the difference between the first segment of R1 and R2 and the rotation of the third segment S2 of R1 and R2. The results of these calculations are combined into segments S0-S3 of output section 49 for writing to the result register R3. In the second example, the second instruction INS2 R3, R4 corresponding to the second dashed line box 39b refers to one register R3 as an operand. By this instruction, the functional unit executes the following operations in parallel. --Add the numerical values stored in the 1st and 4th segments of the operand register R3, and store the result in the 1st segment of the result register R4. --- The numerical values stored in the second segment and the third segment of the operand register R3 are added, and the result is stored in the second segment of the result register R4. --Subtract the numerical value in the 3rd segment of the operand register R3 from the numerical value in the 2nd segment of the operand register R3, and store the result in the 3rd segment of the result register R4. --Subtract the numerical value in the 4th segment of the operand register R3 from the numerical value in the 1st segment of the operand register R3, and store the result in the 4th segment of the result register R4. FIG. 4a shows an example of the functional unit 20 that executes the INS2 instruction. The functional unit 20 has an input section for receiving the contents of the operand register R3, arithmetic units 24a-b and 25a-b for calculating addition and subtraction, an instruction decoder 28 for operating the functional unit 20, and an output section 26. The results of addition and subtraction are combined into segments S0-S3 of output section 26 for writing to the result register R4. The third example, the third instruction INS3 R4, corresponding to the third dashed box 39c,<u style="single">R9, R5</u>Is an operand in two registers R4,<u style="single">R9</u>Refer to. By this instruction, the functional unit executes the following operations in parallel. --The first segment of the first operand register R4 and the operand register<u style="single">R9</u>Adds the numbers stored in the 4th segment of, and the result is the result register.<u style="single">R5</u>Store in the first segment of. --The second segment of the first operand register R4 and the second operand register<u style="single">R9</u>Adds the numbers stored in the 3rd segment of, and the result is the result register.<u style="single">R5</u>Store in the second segment of. --Third segment of first operand register R4 and second operand register<u style="single">R9</u>Adds the numbers stored in the second segment of, and the result is the result register.<u style="single">R5</u>Store in the third segment of. --The 4th segment of the 1st operand register R4 and the 2nd operand register<u style="single">R9</u>Adds the numbers stored in the first segment of, and the result is the result register.<u style="single">R5</u>Store in the 4th segment of. The fourth example, the fourth instruction INS4 R4, corresponding to the dashed box 39h,<u style="single">R9</u>, R6 are two registers R4, as operands<u style="single">R9</u>Refer to. By this instruction, the functional unit executes the following operations in parallel. --Operand register<u style="single">R9</u>The numerical value stored in the first segment of the first operand register R4 is subtracted from the numerical value stored in the fourth segment of, and the result is stored in the fourth segment of the result register R6. --Second operand register<u style="single">R9</u>The numerical value stored in the second segment of the first operand register R4 is subtracted from the numerical value stored in the third segment of, and the result is stored in the third segment of the result register R6. --Second operand register<u style="single">R9</u>The numerical value stored in the third segment of the first operand register R4 is subtracted from the numerical value stored in the second segment of, and the result is stored in the second segment of the result register R6. --Second operand register<u style="single">R9</u>The numerical value stored in the 4th segment of the 1st operand register R4 is subtracted from the numerical value stored in the 1st segment of, and the result is stored in the 4th segment of the result register R6. The fifth instruction, INS5 R1, R2, R7, which corresponds to the fourth dashed line box 39d, which is the fifth example, refers to two registers R1 and R2 as operands. By this instruction, the functional unit executes the following operations in parallel. --The numerical values from the 4th segment of the 1st source register R1 and the 2nd segment of the 2nd source register R2 are stored in the 2nd segment and the 3rd segment of the result register R7, respectively. --No. 2 of the 2nd register R2<u style="single">4</u>Segment (v =<u style="single">3</u>) And the number in the second segment of the first register R1, X in the rotation of the coefficient 2 and the predetermined sine and cosine values (corresponding to 45 °).₀, Y₀Used as. The resulting X₁, Y₁The result register number<u style="single">1</u>Store in the segment and the 4th segment (this rotation can be done with a small number of multiplications because the 45 ° sine and cosine are equal to each other). In the sixth example, the sixth instruction INS6 R7, R8 corresponding to the sixth dashed line box 39e refers to one register R7 as an operand. By this instruction, the functional unit executes the following operations in parallel. --The numerical values stored in the 1st and 3rd segments of the operand register R7 are summed, and the result is stored in the 1st segment of the result register R8. --The numerical values stored in the 2nd and 4th segments of the operand register R7 are summed, and the result is stored in the 4th segment of the result register R8. --Subtract the numerical value in the 3rd segment of the operand register R7 from the numerical value in the 1st segment of the operand register R7, and store the result in the 3rd segment of the result register R8. --- The numerical value in the second segment of the operand register R7 is subtracted from the numerical value in the fourth segment of the operand register R7, and the result is stored in the second segment of the result register R8. The seventh instruction, the seventh instruction INS7 R8, R9, which corresponds to the seventh dashed line box 39f, refers to one register R8 as an operand. By this instruction, the functional unit executes the following operations in parallel. --The numbers in the 1st and 4th segments of the source register R8 are X in the coefficient sqrt (2) and the rotation of the predetermined sine and cosine values.₀, Y₀Used as. The resulting X₁, Y₁Is stored in the 1st segment and the 4th segment of the result register R9. --The numbers in the 2nd and 3rd segments of the source register R8 are X in the coefficient sqrt (2) and the rotation of the predetermined sine and cosine values.₀, Y₀Used as. The resulting X₁, Y₁Is stored in the second segment and the third segment of the result register R9. In these instructions, all numbers in the register may be represented as fixed-point numbers with the same number of bits so that some least significant bits are discarded during multiplication. Almost all fixed-point numbers can be defined in the range +1 to -1. However, rotation / scaling results are an exception to this, with fixed-point numbers in the range -2 to 2 being desirable. It has been found that when this numerical representation is used and the data flow diagram is divided into instructions as described above, rounding results in little loss of accuracy. Addition and / or multiplication in these instructions should provide clipping of the result of the instruction if the magnitude of the result exceeds the range of values that can be held in the register. However, it has been found that clipping is usually not necessary when the data flow diagram is divided into instructions as shown above. If all of these instructions are provided by the data processor, the 8-point IDCT of the rows contained in the segments of the two registers R1 and R2 can be programmed using the following program: INS1 R1, R2, R3 INS2 R3, R4INS5 R1, R2, R7INS6 R7, R8INS7 R8, R9INS3 R4, R9, R5INS4 R4, R9, R6 As a result, the numbers that make up the rows of the IDCT conversion are stored in the segments of registers R5 and R6. To convert the entire block, these instructions need to be repeated for the other lines, using the other registers needed. Needless to say, in the case of a VLIW processor having two or more functional units, all the instructions INS1-INS7 can be instructions for one same functional unit, but these instructions INS 1-INS7 can be used as multiple functional units. It can also be executed by. For example, it is possible to prepare a functional unit for an instruction that performs multiplication and a functional unit for an instruction that performs only addition and subtraction. It is also possible to reorganize the grouping of operations into instructions. For example, combining the operations of INS1 and INS2 into one instruction INSA so that the sequential execution of INS1 R1, R2, X; INS2 X, R4 and the execution of INSA R1, R2, R4 are functionally equivalent. Can be done. Similarly, INS5 R1, R2, X; INS6 X, Y; Sequential execution of INS7 Y, R9 and INSB INS5, INS6, and INS7 can be combined into one instruction so that the execution of R9 is equivalent. Also, by modifying the instruction INS7 so that the result of the operation is stored in the segment of the result register in the reverse order, INS3 and INS4 can be replaced with SIMD addition and SIMD subtraction, respectively. However, in this case, an additional "reverse order" instruction is required to exchange the contents of segments 0-3 with each other and the contents of segments 1-2 with each other. This instruction should be applied to the results of the SIMD version of INS4 so that the converted numbers are obtained in the correct order. The number of instructions that need to be executed to transform a block is to take instructions INS1-INS7 and perform operations in parallel, combining different segments in one or more operands referenced in the instruction 1 It can be reduced by providing one or more functional units. This reduces the time required for conversion (the number of instruction cycles). Execution of IDCT by such a functional unit is much faster than execution by individual instructions. The reason is that at least the combination of numerical values stored in segments at different positions in the operand can be realized by wiring within the functional unit. This wiring is unique to IDCT. Of course, if one of the additional instructions INS1-INS7, or any combination of these instructions, is provided by the functional unit, the reduction in execution time has already been achieved. When one or more of these instructions are not provided, their function can be performed using conventional instructions. In addition, the memory space required to store the program is also reduced, especially in the program where the conversion takes place. Of course, this advantage is also obtained when the operations in the instruction are not executed in parallel. The program space will be reduced for any combination of instructions. However, the combination of INS1-INS7 is not optional and they provide the segments needed to calculate the IDCT. It has a special characteristic that provides an operation for further increasing the processing speed in combination and an operation for further increasing the calculation speed of IDCT by combining operations that can be executed in parallel. The example shown above uses a register with four segments to perform an 8-point 2D IDCT, for example a 64-bit register with four 16-bit segments. Naturally, the present invention is not limited to these numerical values. Segments of other sizes (eg 8-bit, 12-bit, 32-bit segments) and / or registers with other bits (eg) 128 bits) can also be used. When using 128-bit registers in a 16-bit segment, eight numbers can be stored, for example, the entire row of an 8-point IDCT and 8-bit block can be executed as one instruction with only one register and one result register. More generally, the speed of any kind of program by providing a functional unit that can execute a dedicated instruction that performs an operation that combines operands stored in segments at different positions in a register (preferably parallel execution). Can also be increased. The separable transformation described above is one example. Given a program, the appropriate dedicated instructions can be found by analyzing the data flow of that program and retrieving the most frequent combinations of operations that combine different segments within the same operand or two operands. .. If the appropriate instruction is found, the instruction decoder 120 and switch circuit 125 are designed so that the functional unit can handle the instruction. These dedicated instructions should be combined with the SIMD instruction set. In this case, one or more functional units, together or individually, provide a complete set of arithmetic instructions by SIMD data flow (combining pairs of segments at corresponding positions in the operands). .. In addition, at least one functional unit can execute a few selected instructions that combine segments at different positions within one or more operands of the instruction (in this case, "different positions" are in SIMD instructions. It means that it is different from the position in the operator land). This method can be used especially for all kinds of separable conversions, not just IDCT. For example, a two-dimensional Fourier transform, a Hadamard transform, or a two-dimensional separable kernel H (x, like a Gaussian kernel) that can be written as H1 (x) H2 (y). It can be used for folding by y), or for conversion and folding of 3D or more. In general, separable transformations use one-dimensional transformations that take a series of numbers as input values and define a series of new numbers as output. The separable transformation has a composition of two such one-dimensional transformations. The first one-dimensional transformation is calculated for each set of numbers and a new set of numbers is generated. The second transformation is calculated for the horizontal set of numbers obtained by taking the numbers at the corresponding positions in succession from this new set of numbers. In each of the above cases, the numerical value that needs to be converted may be stored in the segment of the operand. In that case, the position of the segment where the number is stored is determined in the same way for each row by the column in which the number is located (the numbers in each operand belong to the same row). The conversion can be performed any number of times in parallel using dedicated instructions and in parallel across lines with SIMD instructions.