Control method for discrimination feedback type equalizer, discrimination feedback type equalizer, signal processing circuit, and hard disk device

The present invention relates to the prevention of divergence of a determination feedback type equalizer used in a read channel IC of a hard disk device or a high-speed data communication device.

[0002] Recorded data read from a hard disk such as a magnetic disk via a read head is read as an analog read signal. This read signal is converted into a digital signal by the waveform equalizer in the read channel IC, the digital signal is subjected to various digital processing, and is output to a data reproduction processing unit composed of a DSP, a microcomputer, and the like. .. In the data reproduction processing unit, the original data is reproduced based on the input recorded data.

[0003] In recent years, in order to speed up the reproduction operation of such recorded data, the recording density on a recording medium and the digital signal processing speed have been improved. Therefore, the waveform equalizer is also required to have high processing stability and high speed.

[0004] Conventionally, an analog signal read from a hard disk via a read head is input to a read channel IC constituting a hard disk device. In the read channel IC, the input analog signal is converted into a digital signal by a waveform equalizer, and the digital signal is subjected to a predetermined digital decoding process. Then, the digitally decoded signal is converted from the serial signal into a parallel signal having a predetermined number of bits and output to a host computer or the like.

[0005] With the recent increase in the speed of reading recorded data, a decision feedback equalizer (DFE) is attracting attention in place of the PRML (partial response and maximum likelihood decoding) type waveform equalizer. Has been done. The PRML type waveform equalizer requires a high-precision digital filter and an equalizer filter, which hinder high speed and miniaturization of the circuit. On the other hand, the judgment feedback type equalizer is suitable for high-speed operation and miniaturization because the circuit configuration is simple.

[0006] FIG. 53 shows a first conventional example of the determination feedback type equalizer. The DFE 11 includes a pre-filter (feedforward filter) 12, an adder 13, a determiner 14, a shift register 15, and a feedback filter 16. The pre-filter 12 outputs the filtered signal to the adder 13. The adder 13 adds the output signal of the prefix filter 12 and the output signal of the feedback filter 16 and outputs the addition result to the determination device 14.

[0007] The determination device 14 compares the output voltage of the adder 13 with a preset reference voltage, and outputs a determination signal S1 of "1" or "0" to the shift register 15 based on the comparison result. .. As a result, the determination device 14 converts the output signal of the adder 13 into a digital signal.

[0008] The shift register 15 includes a number of registers 15a (8 in FIG. 53) corresponding to the number of taps of the feedback filter 16. The shift register 15 samples the determination signal S1 output from the determination device 14 in synchronization with the clock signal CLK, and sequentially stores the sampled data in each register 15a. As a result, the shift register 15 stores the sampled past data.

[0009] The feedback filter 16 operates to remove intersymbol interference between symbols contained in the signal. The feedback filter 16 calculates the feedback response, that is, the analog amount (feedback amount) of the signal output to the adder 13 based on the data stored in the shift register 15.

[0010] In detail, the feedback filter 16 comprises a FIR (Finite Impulse Response) filter, and includes a multiplier 17 for the number of taps, an adder 18, and a digital-to-analog converter (DAC) 19. The feedback filter 16 calculates 8-bit data input from the shift register 15 by each multiplier 17 and preset filter coefficients ω7 to ω0, respectively, and adds the calculation results by the adder 18. Then, the feedback filter 16 converts the addition result of the adder 18 into an analog signal by the DAC 19, and outputs the analog signal to the adder 13.

[0011] Therefore, the adder 13, the determination device 14, the shift register 15, and the feedback filter 16 form a feedback loop to form a determination circuit. Then, the data stored in one register of the shift register 15 is output as a reproduction signal which is a digital signal. The DFE 11 configured in this way outputs a reproduction signal from which intersymbol interference has been removed.

[0012] By the way, as described above, the DFE 11 obtains the feedback response by calculating the feedback amount by each of the arithmetic units 17 and the adder 18 of the feedback filter 16. Therefore, as for the read speed, the calculation speed of each arithmetic unit 17 and the adder 18 limits the read speed. That is, the read speed cannot be made higher than the calculation speed of the arithmetic unit 17 and the adder 18.

FIG. 54 shows a second conventional example of a determination feedback equalizer (DFE) capable of having a higher read speed than the above DFE11. The same components as those of DFE11 of the first conventional example shown in FIG. 53 will be described with the same reference numerals.

[0014] The DFE 21 includes a pre-filter 12, an adder 13, a determination device 14, a shift register 15, and a feedback filter 22. The feedback filter 22 includes a decoder 23, a memory (RAM) 24, and a DAC 25. By using RAM24, this DFE21 is sometimes called RAM-DFE.

[0015] The RAM 24 has a plurality of areas 24a, and each area 24a stores feedback response data corresponding to an 8-bit data pattern output from the shift register 15. These data are the calculation results obtained by pre-calculating the data stored in the shift register 15 and the predetermined filter coefficients ω7 to ω0.

[0016] The decoder 23 outputs an address signal for selecting one of the areas 24a corresponding to the pattern of the data to the RAM 24 based on the data output from the shift register 15. The RAM 24 outputs the data stored in the area 24a selected by the input address signal to the DAC 25. The DAC 25 converts the input data into an analog signal and outputs the analog signal to the adder 13 as a feedback response.

[0017] The feedback filter 22 configured in this way requires only the time for decoding in the decoder 23 and the time for reading the feedback response from the RAM 24. This total time is shorter than the calculation time in the feedback filter 16 of DFE 11 in FIG. 53. As a result, DFE21 makes it possible to increase the reading speed.

However, in a hard disk device, the level of the read signal (Lorentz pulse) at the magnetic change point drops in the state of the recording medium or the read head, or it is necessary for determination due to the influence of noise. You may not be able to get a good level. This causes a determination error in the determination device 14, and an erroneous value is stored in the shift register 15. The feedback loop diverges due to erroneous propagation in which this erroneous value is fed back to the adder in the feedback loop.

[0019] At this time, the DFE 21 is in a so-called fixed state in which the reproduction signal of one state (either "0" or "1") is continuously output. Then, the feedback loop becomes stable in a fixed state, and it is difficult to return to the normal state in which "0" and "1" are output according to the input signal.

[0020] In such a case, it takes time for the feedback loop to return to the normal state. Therefore, since the DFE21 outputs a reproduction signal including an error, the hard disk device must repeatedly perform a read operation for the same area of the magnetic disk. This lengthened the data read time and hindered the speeding up of the read operation.

[0021] By the way, the hard disk device manages the recording surface of the magnetic disk by a track divided concentrically in the radial direction and a sector divided radially. The hard disk device stores the same amount of data in each sector. Therefore, the recording density of each sector becomes higher as the sector is closer to the center of the magnetic disk. Then, the magnetic disk is rotationally driven at a constant speed.

Therefore, the symbol rate (the number of bits read per unit time) of the read signal read from the magnetic disk is higher as the read signal is read from the sector closer to the center. That is, the frequency characteristic of the read signal changes according to the position (distance from the center) of the sector for reading the information.

[0023] In order to accurately perform the equalization processing for the read signal, it is necessary to change the filter response stored in the RAM 24 of the feedback filter 22 in a short time according to the change in the frequency characteristic of the read signal. However, it takes time to rewrite all the filter responses of RAM24 from the outside. The rewriting time hindered the speeding up of the reading operation.

[0024] The present invention<u style="single">of</u>An object of the present invention is to provide a judgment feedback type equalizer capable of preventing the divergence of the feedback loop and increasing the reading speed.

[Means for Solving the Problems] In order to achieve the above object, the invention according to claim 1 is<u style="single">The pre-filter that filters and outputs the input signal, the output signal of the pre-filter and the feedback signal based on the judgment result stored in the shift register are added, and the signal after the addition is judged according to the judgment criteria, and the signal is judged. In a judgment feedback type equalizer including a judgment circuit that sequentially stores the judgment results in the shift register, the judgment circuit includes an adder that adds the output signal of the pre-filter and the feedback signal, and a reference level. The magnitude of the output signal of the adder is determined, and the determination result is output to the shift register. The feedback amount is calculated based on the determination result stored in the shift register, and the feedback amount is calculated according to the feedback amount. The feedback filter includes a feedback filter that outputs the feedback signal, and the feedback filter includes a first signal level generation circuit that generates a plurality of signal levels, the monitoring result is input, and the plurality of signal levels are input based on the monitoring result. A first selection circuit that selects one of them and outputs the selected signal level to the determination device as a reference level. A second signal level generation circuit that generates a plurality of signal levels and the monitoring result are input, and one of the plurality of signal levels and the feedback amount based on the determination result is selected based on the monitoring result. A second selection circuit that outputs the selected signal and a DA converter that converts the output signal of the selection circuit into an analog signal and outputs the analog signal as the feedback signal are provided.</u>。

[0036] Claim<u style="single">2</u>The invention described in is claimed.<u style="single">1</u>In the determination feedback type equalizer described in the above, the register length of the shift register is made to correspond to the sign rule of the input signal.

[0037] Claim<u style="single">3</u>The invention described in is claimed.<u style="single">1 or claim 2</u>In the determination feedback type equalizer described in the above, the shift register is composed of a first register unit composed of a number of registers corresponding to the number of taps of the feedback filter and a second register unit including a plurality of registers. Was done.

[0038] Claim<u style="single">4</u>The invention described in is claimed.<u style="single">1</u>In the determination feedback type equalizer described in the above, when a determination error based on the determination criterion is locally present in the shift register, the monitoring circuit outputs a feedback signal based on the error. ..

【0066】<u style="single">(Action)</u><u style="single"></u>Claim<u style="single">1</u>According to the invention described in the above, based on the monitoring result of the monitoring circuit that monitors the contents of the shift register.<u style="single">One of the plurality of signal levels generated by the first signal level generation circuit is selected and output to the judgment device as a reference level, and it is determined that the plurality of signal levels are generated by the second signal level generation circuit. Select one of the feedback amounts based on the result, convert the selected signal to an analog signal, and output it as a feedback signal.</u>Therefore, the sticking is eliminated and the divergence of the feedback filter is stopped.

[0067] Claim<u style="single">2</u>,<u style="single">3</u>According to the invention described in the above, since the register length of the shift register is made to correspond to the sign rule of the input signal, an increase in the configuration of the feedback filter can be suppressed.

[0068] Claim<u style="single">4</u>According to the invention described in the above, the determination error locally existing in the shift register is corrected based on the code rule, and divergence is prevented.

[Embodiments of the Invention] (First Embodiment) Hereinafter, a first embodiment embodying the present invention will be described with reference to FIGS. 1 to 10.

[0079] For convenience of explanation, the same reference numerals will be given to the same configurations as those in the prior art, and some description thereof will be omitted. FIG. 1 shows a schematic configuration of a hard disk device.

[0080] The hard disk device 31 is connected to the host computer 32. The hard disk device 31 responds to the write request of the host computer 32 and records the recording data input from the host computer 32 on the magnetic disk 33 as a recording medium. Further, the hard disk device 31 responds to the read request of the host computer 32, reads the stored data recorded on the magnetic disk 33, and outputs the stored data to the host computer 32.

The hard disk device 31 includes a magnetic disk 33, first and second motors M1 and M2, a head device 34, a signal processing circuit 35, a servo circuit 36, a microprocessor (MPU) 37, a memory (RAM) 38, and a hard disk controller. Includes (HDC) 39 and interface circuit 40. Each circuit 35 to 40 is connected to bus 41.

[0082] The magnetic disk 33 is rotationally driven by the first motor M1 at a constant rotation speed. The head device 34 is position-controlled in the radial direction of the magnetic disk 33 by the second motor M2. The head device 34 reads the information recorded on the magnetic disk 33 and outputs it as a read signal RD to the signal processing circuit 35.

The signal processing circuit (called a read / write channel IC) 35 samples the read signal RD in synchronization with the read signal RD and converts it into a digital signal. The signal processing circuit 35 performs decoding processing on the converted digital signal and outputs the processed signal.

The output signal of the signal processing circuit 35 is input to the servo circuit 36 via the bus 41. The servo circuit 36 controls the first motor M1 to rotate and drive the magnetic disk 33 at a constant speed. The servo circuit 36 controls the second motor M2 based on the information for the servo included in the output signal, and makes the head device 34 on-track to the target track.

[0085] The MPU 37 analyzes commands for write / read processing and the like input from the host computer 32 based on the program data stored in advance in the RAM 38, and controls the HDC 39 and the like via the bus 41. Output a signal. The HDC39 controls the signal processing circuit 35 and the servo circuit 36 based on the signal input from the MPU37. The HDC39 inputs the output signal of the signal processing circuit 35 via the bus 41.

[0086] The HDC39 assembles the input data into sector units consisting of a predetermined number of bytes, performs processing such as ECC (Error Correcting Code) error correction processing for each assembled sector, and performs the processed data. Output to the interface circuit 40 via bus 41. The interface circuit 40 converts the output data of the HDC 39 based on a predetermined communication method and outputs it as read data to the host computer 32.

[0087] The write data is input to the HDC 39 from the host computer 32 via the interface circuit 40. The HDC39 adds data for error correction to the written data and outputs the data to the signal processing circuit 35 via the bus 41. The signal processing circuit 35 writes the output data of the HDC 39 to the magnetic disk 33 via the head device 34.

Next, the configuration of the signal processing circuit 35 will be described with reference to FIG. 2 corresponding to the write operation and the read operation.

[Write operation] The write data (write data) output from the MPU 37 in FIG. 1 is input to the scrambler 43 via the interface circuit 42. The scrambler 43 performs a process of changing the order in which the bits of the write data are arranged by a predetermined method, and outputs the processed data to the encoder 44.

[0089] The encoder 44 encodes the output data of the scrambler 43 based on a predetermined RLL code (run-length limited code: specifically, RLL (1,7) code). Further, the encoder 44 adds control data such as preamble data for controlling the reading operation to the encoded data. The encoder 44 outputs the processed signal to the light pre-competition 45.

[0090] The write pre-competition 45 performs timing correction for correcting the timing of writing data to the magnetic disk 33. This timing correction is performed to prevent the positions of the information (the magnetic poles corresponding to "0" and "1") written on the magnetic disk 33 from being displaced by the influence of the adjacent magnetic poles. The write pre-competition 45 outputs the corrected data to the write flip-flop (write F / F) 46 in the NRZI format.

[0091] The light F / F 46 outputs a light signal WD to the light head 34a constituting the head device 34 based on the output signal of the light pre-competition 45. The light head 34a consists of a coil. The write F / F46 supplies a current corresponding to the recorded data to be written to the magnetic disk 33. By forming a magnetic pole on the magnetic disk 33 by this current, data including data, a preamble, and a sync byte are recorded on the magnetic disk 33.

[Reading Operation] The lead head 34b constituting the head device 34 includes an MR (Magne to Resistive) head. The reed head 34b outputs a reed signal RD having a value corresponding to a change in the magnetic poles of the magnetic disk 33 to the variable gain amplifier (VGA) 47. VGA47 includes Auto Gain Controller (AGC) 47a. The VGA47 amplifies the read signal RD and outputs the amplified signal to the determination feedback equalizer (DFE) 48. The AGC47a controls the gain of the VGA47 so that the amplitude of the output signal of the VGA47 becomes a predetermined amplitude. Therefore, VGA47 and AGC47a form a control loop that controls the amplitude of the signal.

[0093] A PLL circuit 49 for timing clock reproduction is connected to the DFE 48. The PLL circuit 49 generates a clock signal SCK synchronously drawn to the read signal RD based on the output signal of the DFE 48. Based on the clock signal SCK, the DFE48 performs waveform equalization processing on the output signal of the VGA 47, converts it into a digital signal, and outputs the signal to the decoder 50.

[0094] The decoder 50 decodes the output signal of the DFE 48 based on the RLL code, and outputs the decoded data to the descrambler 51. The descrambler 51 rearranges the bits of the output data of the decoder 50 by a predetermined method to generate read data. The read data is output to the MPU 37 in FIG. 1 via the interface circuit 52.

[0095] The DFE 48 outputs the processed signal to the control data detection circuit 53. The control data detection circuit 53 detects control data (preamble, sync byte) for controlling the read operation of recorded data and information for servo (servo mark), and sequences detection signals according to the detected information. Output to control circuit 54 and MPU37.

[0096] The sequence control circuit 54 receives a control signal for controlling writing / reading from the detection signal, the MPU 37. The sequence control circuit 54 controls each of the above circuits 42 to 53 according to a predetermined write / read sequence based on the detection signal and the control signal.

[0097] The MPU 37 instructs the signal processing circuit 35 to start the read operation. After that, when the MPU37 inputs a sync byte detection signal, it responds to the sync byte detection signal, treats the read data following the sync byte as recorded data (data), and processes the recorded data.

Next, the configuration of DFE48 will be described in detail with reference to FIG. A configuration similar to that of the conventional example of FIG. 54 will be described with the same reference numerals. The DFE48 includes a pre-filter 12, an adder 13, a determiner 14, a shift register 61, and a feedback filter (FB filter) 65. The adder 13, the judgment device 14, the shift register 61, and the FB filter 65 form a judgment circuit.

[0099] The output signal of VGA47 of FIG. 2 is input to the prefix filter 12. The prefix filter 12 generates a waveform signal that maximizes the S / N ratio of the input signal. As a result, the pre-filter 12 outputs the filtered signal S1 to the adder 13. The adder 13 adds the output signal S1 of the pre-filter 12 and the feedback signal S2 output from the FB filter 65, and outputs the calculated signal S3 to the determination device 14.

[0100] A reference voltage Ref is input to the determination device 14. The determination device 14 compares the voltage of the signal S3 with the reference voltage Ref, and outputs the determination signal S4 of 1 or 0 to the shift register 61 based on the comparison result. As a result, the determination device 14 converts the output signal S3 of the adder 13 into a digital signal.

[0101] The shift register 61 includes a first register unit 62 and a second register unit 63. The first and second register units 62 and 63 include a plurality of registers 64, respectively. Sampling data is sequentially stored in each register 64. The number of data stored in the shift register 61, that is, the total number of registers 64 included in the shift register 61, corresponds to the transfer code rules used in the encoder 44 and the decoder 50 in FIG.

[0102] In the present embodiment, the first register unit 62 has a number of registers 64 (8 in FIG. 3) corresponding to the number of taps of the FB filter 65, similarly to the conventional shift register 15 (see FIG. 54). Including. The second register unit 63 includes four registers 64 in the present embodiment.

[0103] Therefore, the shift register 61 includes twelve registers 64. As a result, the shift register 61 stores the sampled past 12-bit data. The shift register 61 outputs the stored data to the FB filter 65.

The FB filter 65 includes an address conversion unit 66, a memory (RAM) 24, a digital-to-analog converter (DAC) 25, a divergence monitoring circuit 67, a selection circuit 68, and a signal level generation circuit 69.

[0105] The address conversion unit 66 decodes the 8-bit data input from the first register unit 62 of the shift register 61, and outputs the result as an address signal to the RAM 24.

[0106] Since the RAM 24 is the same as the configuration of the conventional example shown in FIG. 54, the configuration will be described in detail with reference to FIG. 54. That is, the RAM 24 has a plurality of areas 24a, and each area 24a stores a feedback response corresponding to a pattern of 8-bit data output from the shift register 61. In these feedback responses, the data stored in the shift register 61 and the calculation result obtained by pre-calculating the predetermined filter coefficients ω7 to ω0 are stored.

[0107] The RAM 24 in FIG. 3 selects one area according to the address signal input from the address translation unit 66. Then, the RAM 24 outputs the data read from the selected area to the DAC 25.

[0108] The DAC 25 converts the input data into an analog signal, and outputs the analog signal to the adder 13 as a feedback response (feedback signal S2). Therefore, the adder 13, the determination device 14, the shift register 61, the address translation unit 66, the RAM 24, and the DAC 25 form a feedback loop (FB loop).

The address translation unit 66 outputs the data input from the first and second register units 62 and 63 to the divergence monitoring circuit 67. The divergence monitoring circuit 67 determines whether or not the FB loop is diverging based on the input data.

[0110] More specifically, the shift register 61 includes twelve registers 64 corresponding to the transfer code rules generated by the encoder 44 of FIG. The encoder 44 generates a bit string in which the input data is encoded based on the RLL (1,7) code. This coded data can take values from (101) to (100000001). That is, the encoded data contains 1 to 7 consecutive "0" s. Therefore, when data in a bit string in which eight or more "0" s are consecutive is stored in the shift register 61, the data contains an error. Therefore, when a bit string that is not generated by the coding of the encoder 44 is stored in the shift register 61, the bit string contains error data.

Therefore, the divergence monitoring circuit 67 monitors whether or not the data input from the address translation unit 66 contains a bit string that does not correspond to the transmission code rule, and the FB loop is generated based on the monitoring result. Determine if it is diverging. The divergence monitoring circuit 67 outputs a selection signal SEL of a value based on the determination result, that is, the state of the FB loop and the state of the fixed determination signal S4 output from the determination device 14 when the FB loop is diverging.

[0112] For example, the divergence monitoring circuit 67 outputs a selection signal SEL having a value of "0" when it is determined that the FB loop is not diverging. The divergence monitoring circuit 67 outputs a selection signal SEL having a value 1 when the FB loop diverges and the determination signal S4 is fixed to the value 1. The divergence monitoring circuit 67 outputs a selection signal SEL having a value of 2 when the FB loop diverges and the determination signal S4 is fixed to the value 0.

[0113] A signal level generation circuit 69 is connected to the selection circuit 68. The signal level generation circuit 69 has a function of generating a plurality of signal levels corresponding to the reference level of the determination device 14. The determination device 14 uses a reference voltage as a reference level. Therefore, the signal level generation circuit 69 generates a plurality of reference voltages Ref1, Ref2, and Ref3 as a plurality of signal levels. When the determination device 14 uses the current as a reference level, the signal level generation circuit is configured to generate a current having a plurality of values as the signal level.

[0114] The signal level generation circuit 69 sets the value of the first reference voltage Ref1 to the intermediate voltage (= (maximum voltage + minimum voltage) / 2) of the input signal of the determination device 14. Then, the signal level generation circuit 69 generates so that the values of the second and third reference voltages Ref2 and Ref3 are (third reference voltage Ref3 &lt;first reference voltage Ref1 &lt;second reference voltage Ref2). Then, the signal level generation circuit 69 outputs each of the generated reference voltages Ref1 to Ref3 to the selection circuit 68.

[0115] The selection circuit 68 selects one of the reference voltages Ref1 to Ref3 based on the value of the selection signal SEL. Specifically, the selection circuit 68 sets the first reference voltage Ref1 in response to the selection signal SEL of the value "0" and the second reference voltage Ref2 in response to the selection signal SEL of the value "1". The third reference voltage Ref3 is selected in response to the selection signal SEL of "2". Then, the selection circuit 68 outputs the selected voltage as a reference voltage Ref to the determination device 14.

[0116] The determination device 14 determines whether the voltage of the input signal S3 is higher or lower than the reference voltage Ref based on the input reference voltage Ref, and is "1" or "0" based on the determination result. Judgment signal S4 is output. That is, the reference voltage Ref is the determination standard of the determination device 14. The value of the reference voltage Ref is changed according to the selection signal SEL, that is, the state of the FB loop. That is, the FB filter 65 monitors the state of the FB loop, and changes the determination standard of the determination device 14 based on the monitoring result.

Next, the operation of DFE48 configured as described above will be described with reference to FIGS. 4 to 10. First, the divergence state of the FB loop will be described with reference to FIG.

[0118] Fig. 4 shows the write current and read head for writing data to the magnetic disk 33 with respect to the sampling points a (k-3) to a (k + 2) at time (k-3) to (k + 2). The waveform of the read signal RD according to 34b and the waveform of the output signal S3 of the adder 13 based on the read signal RD are shown.

[0119] The read signal RD is a Lorentz pulse having a maximum value at a change point of a write signal (between sampling points a (k-1) and a (k)). The pre-filter 12 in FIG. 3 generates a signal S1 having a waveform that maximizes the S / N ratio based on the read signal RD. The adder 13 outputs a signal S3 obtained by adding a feedback signal S2 output from the FB filter 65 to the signal S1. The determination device 14 compares the voltage of the signal S3 with the reference voltage Ref at each sampling point a (k-3) to a (k + 2), and outputs the comparison result as the determination signal S4.

[0120] When an error is propagated to the FB loop, the output signal S3 of the adder 13 decreases as shown by the alternate long and short dash line in FIG. The signal S3 is stable at sampling points a (k + 1) and a (k + 2) at a voltage lower than the reference voltage Ref. Therefore, the determination device 14 outputs the determination signal S4 of 0 at the sampling points a (k + 1) and a (k + 2). When this determination signal S4 is propagated to the FB loop and the FB loop diverges, the determination signal S4 output from the determination device 14 is fixed to one value.

Next, the state transition of DFE48 will be described with reference to FIG. DFE48 takes states 1 to 6. The DFE48 changes the state based on the value of the input signal S3 of the determination device 14. In the above description of each of the states 1 to 6, "+ q", "+ r", "-r", and "-q" indicate the theoretical values of the input signals in each of the states 1 to 6, and are "0". , "1" indicates the result of exclusive OR operation (EOR operation) of the operation result of "1 + D" operation by the FB filter 65 with respect to the determination signal S4 output from the determination device 14 which is the determination result. The result of this calculation is in NRZI format and is the output of DFE48. The "1 + D" operation is an operation of adding the determination result at that time and the next determination result.

That is, when the value of the input signal S3 is the lowest (Ref-q, or its vicinity), DFE48 is in state 4. At this time, the determination device 14 outputs "0" as the determination signal S4 based on the input signal S3.

Next, when the value of the input signal S3 becomes high (Ref-r), DFE48 transitions from state 4 to state 5. At this time, the determination device 14 outputs the determination signal S4 having the value 0 in the state 4. Therefore, in state 4, DFE48 outputs "0" as a result of EOR calculation of the value "0" of the determination signal S4 in state 4 and the value "0" of the determination signal S4 in state 5.

Then, when the value of the input signal S3 becomes higher than the reference voltage Ref (Ref + r), the DFE 48 transitions from the state 5 to the state 6 as shown in FIG. At this time, the determination device 14 outputs a determination signal S4 having a value of 1. Therefore, DFE48 outputs "1" as a result of EOR calculation of the value "0" of the determination signal S4 in the state 5 and the value "1" of the determination signal S4 in the state 6.

[0125] When the value of the input signal S3 becomes higher (Ref + q), DFE48 transitions from state 6 to state 1. At this time, the determination device 14 outputs the determination signal S4 of "1". Therefore, DFE48 outputs "0" as a result of EOR calculation of the value "1" of the determination signal S4 in the state 6 and the value "1" of the determination signal S4 in the state 1.

[0126] Explaining the case where the value of the input signal S3 becomes low in the same manner, when the value of the input signal S3 becomes low (Ref + r), the DFE 48 transitions from the state 1 to the state 2. At this time, the determination device 14 outputs the determination signal S4 of "1". Therefore, the DFE48 outputs "0" as a result of calculating the value "1" of the determination signal S4 in the state 1 and the value "1" of the determination signal S4 in the state 2.

Next, when the value of the input signal S3 becomes lower than the reference voltage Ref (Ref-r), DFE48 transitions from state 2 to state 3 (see FIG. 6). At this time, the determination device 14 outputs the determination signal S4 of "0". Therefore, DFE48 outputs "1" as a result of EOR calculation of the value "1" of the determination signal S4 in the state 2 and the value "0" of the determination signal S4 in the state 3.

[0128] When the value of the input signal S3 becomes lower (Ref-q), the DFE 48 transitions from the state 3 to the state 4. At this time, the determination device 14 outputs the determination signal S4 of "0". Therefore, DFE48 outputs "0" as a result of EOR calculation of the value "1" of the determination signal S4 in the state 3 and the value "0" of the determination signal S4 in the state 4.

When the level of the input signal S3 does not change when in the state 6, that is, when the value of the next input signal S3 is (Ref + r), the DFE 48 transitions from the state 6 to the state 2. Further, when the level of the input signal S3 does not change when in the state 3, that is, when the value of the next input signal S3 is (Ref-r), DFE48 transitions from the state 3 to the state 5.

[0130] When error propagation occurs, the change in the value of the input signal S3 of the determination device 14 becomes small. As a result, DFE48 cannot transition from state 2 to state 3 and stays in state 1. At this time, the determination device 14 continuously outputs the determination signal S4 having the value "1". In addition, DFE48 cannot transition from state 5 to state 6 and stays in state 4. At this time, the determination device 14 continuously outputs the determination signal S4 having the value 0.

The divergence monitoring circuit 67 of FIG. 3 detects the divergence of the FB loop by the determination signal S4 having the continuous value 1, and outputs the selection signal SEL of the value 1. In response to this selection signal SEL, the selection circuit 68 selects the second reference voltage Ref2 and outputs it to the determination device 14 as the reference voltage Ref2. That is, the determination standard of the determination device 14 is raised.

[0132] As a result, as shown in FIG. 7, the threshold value at which the state transitions is shifted to the state 2 side. Then, as shown in FIG. 8, even if the output signal S1 of the pre-filter 12 is a positive value, the determination device 14 determines that it is negative if it is equal to or less than the second reference voltage Ref2, and determines 0. Output signal S4. That is, the determination device 14 can easily output the determination signal S4 of 0. As a result, the divergence monitoring circuit 67 increases the sensitivity of the determination device 14 to negative signals. DFE48 makes it easier to catch the negative reed signal RD.

[0133] Therefore, DFE48 has a high degree of transition from state 2 to state 3. As a result, DFE48 prevents the determination signal S4 from sticking and prevents the FB loop from diverging.

[0134] As another example, when an error propagation occurs, the DFE48 cannot transition from the state 5 to the state 6, and goes around the states 5, 3 and 4. At this time, the determination device 14 continuously outputs the determination signal S4 having the value 0.

The divergence monitoring circuit 67 of FIG. 3 detects the divergence of the FB loop by the determination signal S4 having the continuous value 0, and outputs the selection signal SEL of the value 2. In response to this selection signal SEL, the selection circuit 68 selects the third reference voltage Ref3 and outputs it to the determination device 14 as the reference voltage Ref3. That is, the determination standard of the determination device 14 is lowered.

As a result, as shown in FIG. 9, the threshold value at which the state transitions is shifted to the state 5 side. Then, as shown in FIG. 10, the determination device 14 determines that the output signal S1 of the pre-filter 12 is positive if it is equal to or higher than the third reference voltage Ref3, and determines "1". Output signal S4. That is, the determination device 14 can easily output the determination signal of "1". As a result, the divergence monitoring circuit 67 increases the sensitivity of the determination device 14 to the positive signal. DFE48 makes it easier to catch the positive read signal RD.

[0137] Therefore, DFE48 has a high degree of transition from state 5 to state 6. As a result, DFE48 prevents the determination signal S4 from sticking and prevents the FB loop from diverging.

[0138] As described above, according to the present embodiment, the following effects are obtained. (1) The divergence monitoring circuit 67 monitors the judgment result stored in the shift register 61, and when the judgment result is fixed to one value, the judgment standard of the judgment circuit is changed. As a result, it becomes easy to detect an input signal having a different code from the fixed determination result, and it becomes difficult to detect an input signal having the same code as the fixed determination result. As a result, the sticking of the judgment criteria is eliminated, and the divergence of the feedback filter is stopped. As a result, the error of the read signal is reduced, so that the data read time can be shortened.

(2) A signal level generation circuit 69 that generates a plurality of reference voltages Ref1 to Ref3 is provided, and one of the plurality of reference voltages is selected by the selection circuit 68 based on the determination result of the divergence monitoring circuit 67. It was selected, and the selected reference voltage was used as the reference voltage Ref of the determination device 14. As a result, the determination standard of the determination circuit can be easily changed based on the monitoring result.

(Second Embodiment) Hereinafter, a second embodiment embodying the present invention will be described with reference to FIG. FIG. 11 shows a block circuit diagram of the determination feedback equalizer (DFE) 70 of the present embodiment. For convenience of explanation, the same components as those in the first embodiment of FIG. 3 are designated by the same reference numerals, and the description thereof will be partially omitted.

[0141] The DFE 70 includes a pre-filter 12, an adder 13, a determination device 14, a shift register 61, and a feedback filter (FB filter) 71. The FB filter 71 includes an address conversion unit 66, a memory (RAM) 24, a digital-to-analog converter (DAC) 25, a divergence monitoring circuit 67, a selection circuit 68, a signal level generation circuit 72, and an adder 73.

[0142] The address conversion unit 66 decodes the 8-bit data input from the first register unit 62 of the shift register 61, and outputs the result as an address signal to the RAM 24.

[0143] The RAM 24 has a plurality of areas, and each area stores a feedback response corresponding to a pattern of 8-bit data output from the shift register 61. The RAM 24 selects one area based on the address signal input from the address translation unit 66. Then, the RAM 24 outputs the data read from the selected area to the DAC 25. The DAC 25 converts the input data into an analog signal, and outputs the analog signal to the adder 13 as a feedback response (feedback signal S2).

The address translation unit 66 outputs the data input from the first and second register units 62 and 63 to the divergence monitoring circuit 67. The divergence monitoring circuit 67 monitors whether the 12-bit data input from the address conversion unit 66 contains a bit string that does not correspond to the transmission code rule, and the FB loop diverges based on the monitoring result. Determine if it is. The divergence monitoring circuit 67 sets the selection signal SEL of the value based on the judgment result, that is, the state of the FB loop and the state of the fixed judgment signal S4 output from the judgment device 14 when the FB loop is diverging, to the selection circuit 68. Output.

[0145] For example, the divergence monitoring circuit 67 outputs a selection signal SEL having a value of "0" when it is determined that the FB loop is not diverging. The divergence monitoring circuit 67 outputs a selection signal SEL having a value 1 when the FB loop diverges and the determination signal S4 is fixed to the value 1. The divergence monitoring circuit 67 outputs a selection signal SEL having a value of 2 when the FB loop diverges and the determination signal S4 is fixed to the value 0. The value of the selection signal SEL may be changed as appropriate.

[0146] A signal level generation circuit 72 is connected to the selection circuit 68. The signal level generation circuit 72 generates a plurality of offset signals Off1, Off2, and Off3 as a plurality of signal levels. When the determination device 14 uses the current as a reference level, the signal level generation circuit 72 may be configured to generate a current having a plurality of values as the signal level.

[0147] The signal level generation circuit 72 sets the value of the first offset signal Off1 to 0. Then, the signal level generation circuit 72 generates the values of the second and third offset signals Off2 and Off3 so as to be (third offset signal Off3&gt; first offset signal Off1&gt; second offset signal Off2). Since the value of the first offset signal Off1 is "0", the second offset signal Off2 has a negative value. The absolute values of the second and third offset signals Off2 and Off3 are the same. Then, the signal level generation circuit 72 outputs each of the generated offset signals Off1 to Off3 to the selection circuit 68.

[0148] The selection circuit 68 selects one of the offset signals Off1 to Off3 based on the value of the selection signal SEL. Specifically, the selection circuit 68 sets the first offset signal Off1 in response to the selection signal SEL of the value "0" and the second offset signal Off2 in response to the selection signal SEL of the value "1". The third offset signal Off3 is selected in response to the selection signal SEL of "2". Then, the selection circuit 68 outputs the selected voltage to the adder 73 as an offset signal Off.

[0149] The output signal of the RAM 24 is input to the adder 73. The adder 73 adds the output signal of the RAM 24 and the offset signal Off, and outputs the addition result to the DAC 25. As a result, a feedback response (feedback signal S2) to which any one of the first to third offset signals Off1 to Off3 is added based on the selection signal SEL is fed back to the adder 13.

[0150] When the FB loop is not diverging, the divergence monitoring circuit 67 outputs a selection signal SEL having a value of 0. As a result, the first offset signal Off1 is selected and added to the output signal of the RAM 24. The value of the first offset signal Off1 is "0". Therefore, when the FB loop is not diverging, the output signal of the RAM 24 is fed back to the adder 13 as a feedback response.

[0151] When the FB loop is stuck to "1", the divergence monitoring circuit 67 outputs a selection signal SEL having a value of "1". As a result, the second offset signal Off2 is selected and added to the output signal of the RAM 24. This second offset signal Off2 has a negative value. Therefore, a feedback response having a value smaller than that of the output signal of the RAM 24 by the amount of the second offset signal Off2 is fed back to the adder 13.

That is, the FB filter 71 offsets the analog signal with respect to the output data of the RAM 24 in the negative direction. This is equivalent to increasing the reference voltage of the determination device 14 in the first embodiment. As a result, the determination device 14 can easily output the determination signal S4 of 0. That is, the divergence monitoring circuit 67 increases the sensitivity of the determination device 14 to negative signals. As a result, as in the first embodiment, the DFE70 prevents the determination signal S4 from sticking and prevents the FB loop from diverging.

[0153] When the FB loop is stuck at "0", the divergence monitoring circuit 67 outputs a selection signal SEL having a value of "2". As a result, the third offset signal Off3 is selected and added to the output signal of the RAM 24. This third offset signal Off3 is a positive value. Therefore, a feedback response having a value larger than that of the output signal of the RAM 24 by the amount of the third offset signal Off3 is fed back to the adder 13.

That is, the FB filter 71 offsets the analog signal with respect to the output data of the RAM 24 in the positive direction. This is equivalent to lowering the reference voltage of the determination device 14 in the first embodiment. As a result, the determination device 14 can easily output the determination signal S4 of 1. That is, the divergence monitoring circuit 67 increases the sensitivity of the determination device 14 to a positive signal. As a result, as in the first embodiment, the DFE70 prevents the determination signal S4 from sticking and prevents the FB loop from diverging.

[0155] As described above, according to the present embodiment, the following effects are obtained. (1) It has the same effect as (1) of the first embodiment.

(2) The feedback amount is offset by the DAC 25 based on the determination result of the divergence monitoring circuit 67. Thereby, the determination standard of the determination circuit can be easily changed with a simple configuration.

[0157] In the above embodiment, the following changes may be made. -In the second embodiment, the DAC 25 may fix the value of the output feedback signal, that is, the feedback amount to a constant value based on the monitoring result of the divergence monitoring circuit 67. In this case, if the feedback signal is output based on the output signal of the RAM 24 including the error, the error of the determination result of the determination device 14 may be increased. Therefore, by feeding back a constant feedback amount to the adder 13 as a feedback signal, it is possible to reduce errors included in the determination result, and as a result, the divergence of the FB loop can be eliminated quickly.

In the second embodiment, the divergence monitoring circuit 67 transmits the error data when the error data by the determination device 14 is locally present in the determination result stored in the shift register 61. It is corrected based on and output to RAM24. The RAM 24 reads the feedback response stored in the area based on the data input from the divergence circuit 73, and outputs the response to the DAC 25. The DAC 25 converts the output signal of the RAM 24 into an analog signal, and outputs the converted signal to the adder 13 as a feedback signal S2. With this configuration, locally existing errors are not propagated, so FB loop divergence can be prevented.

(Third Embodiment) Hereinafter, a third embodiment embodying the present invention will be described with reference to FIGS. 12 to 20. For convenience of explanation, the same reference numerals are given to the same configurations as those of the first embodiment of FIG. 3 and the second embodiment of FIG. 11, and the description thereof will be partially omitted.

FIG. 12 shows a block circuit diagram of the determination feedback equalizer (DFE) 201 of the present embodiment. The DFE201 includes a pre-filter 12, an adder 13, a determiner 14, a shift register 61, and a feedback filter (FB filter) 202.

[0161] The shift register 61 includes a first register unit 62 and a second register unit 63. The first and second register units 62 and 63 include a plurality of registers 64, respectively. Sampling data is sequentially stored in each register 64.

[0162] In the present embodiment, the first register unit 62 includes six registers 64 corresponding to the number of taps of the FB filter 202. The second register unit 63 includes three registers 64. Therefore, the shift register 61 includes nine registers 64. As a result, the shift register 61 stores the sampled past 9-bit data d0 to d8. The shift register 61 outputs the stored data d0 to d8 to the FB filter 202.

The FB filter 202 includes a memory (RAM) 24, a digital-to-analog converter (DAC) 25, a divergence monitoring circuit 67, a first selection circuit 68, and a first signal level generation circuit (hereinafter referred to as a first generation circuit). It includes 69, a second selection circuit 203, a second signal level generation circuit (hereinafter referred to as a second generation circuit) 204, a decoder 205, an error detection circuit 206, a state machine (STM) 207, and latches 208a to 208c.

[0164] The 6-bit data d0 to d5 stored in the first register unit 62 are input to the RAM 24. The RAM 24 has a plurality of areas, and each area stores a feedback response corresponding to a pattern of 6-bit data d0 to d5 output from the shift register 61. The RAM 24 selects one area based on the address signal input from the address translation unit 66. Then, the RAM 24 outputs the data read from the selected area to the DAC 25 via the latch 208a. The DAC 25 converts the input data into an analog signal, and outputs the analog signal to the adder 13 as a feedback response (feedback signal S2).

The 9-bit data d0 to d8 stored in the shift register 61 are output to the divergence monitoring circuit 67. The divergence monitoring circuit 67 determines whether or not the FB loop is diverging based on the input data d0 to d8, as in the first and second embodiments. That is, the divergence monitoring circuit 67 monitors whether or not the input data d0 to d8 contains a bit string that does not correspond to the transmission code rule, and whether or not the FB loop diverges based on the monitoring result. To judge. The divergence monitoring circuit 67 transmits a signal S71 having a value based on the determination result, that is, the state of the FB loop and the state of the fixed determination signal S4 output from the determination device 14 when the FB loop is diverging, via the latch 208c. Output to STM207.

[0166] For example, the divergence monitoring circuit 67 outputs a signal S71 having a value of "0" when it is determined that the FB loop is not diverging. The divergence monitoring circuit 67 outputs a signal S71 having a value 1 when the FB loop diverges and the determination signal S4 is fixed to the value 1. The divergence monitoring circuit 67 outputs a signal S71 having a value 2 when the FB loop diverges and the determination signal S4 is fixed to the value 0.

The 9-bit data d0 to d8 stored in the shift register 61 are output to the decoder 205. The decoder 205 is a 1 + D decoder that performs a 1 + D operation and includes eight exclusive OR circuits (EOR circuits) 205a as shown in FIG.

[0168] Time-continuous 2-bit data is input to each EOR circuit 205a. For example, 2-bit data d0, d1 is input to the first-stage EOR circuit 205a, and 2-bit data d7, d8 is input to the final-stage EOR circuit 205a. Each EOR circuit 205a performs an exclusive OR operation on 2-bit data, and outputs the operation result as signals Ad0 to Ad7 to the error detection circuit 206.

[0169] As shown in FIGS. 15 to 18, the error detection circuit 206 decodes the input signals Ad0 to Ad7 based on the RLL code (run-length limited code: specifically, the RLL (1,7) code). At that time, the error detection circuit 206 detects the error data included in the input signal, and outputs the signal S72 to the STM 207 via the latch 208b based on the detection result.

[0170] As described in the state transition of the DFE 48 (see FIG. 5) in the first embodiment, the DFE 201 has a determination signal S4 of 1 when the input signal S3 of the determination device 14 exceeds the reference level Ref. Is output. This means that the determination signal S4 in which "1" is continuous is not output when the operation of the DFE is normal. Therefore, as shown in FIG. 15, when the signals Ad0 to Ad7 include "1" in which two or more bits are continuous, the continuous "1" is an error that exists locally.

Further, it means that the data d0 to d8 of the shift register 61 in which the determination signal S4 is sequentially stored takes only the values of (101) to (100000001). Therefore, as shown in FIG. 15, when the signals Ad0 to Ad7 are all "0" or "1", the signals Ad0 to Ad7 are erroneous, and the erroneous propagation (sticking). Become.

[0172] Therefore, the error detection circuit 206 detects whether the input signals Ad0 to Ad7 contain an error or has error propagation, and outputs the signal S72 to the STM207 based on the detection result. For example, the error detection circuit 206 outputs a signal S72 having a value of "2" (10 in binary) when a local error is detected. Further, when the error detection circuit 206 detects an error propagation, it outputs a signal S72 having a value of "3" (11 in binary) to the STM207.

[0173] The signal d0 output from the shift register 61 is input to the STM207. This signal d0 is the output signal of DFE201. The STM207 changes its operating state (state) based on the signals d0, S71, S72.

As shown in FIG. 13, the STM207 can take states Z1 to Z4. STM207 takes the state of state Z1 when the FB loop is not stuck and DFE201 is operating normally.

At this time, the STM207 outputs the first and second selection signals SEL1 and SEL2 based on the signals S71 and S72. More specifically, the STM207 outputs selection signals SEL1 and SEL2 having a value of "0" to the first and second selection circuits 68 and 203 when the DFE201 is normal.

[0176] The first generation circuit 69 is connected to the first selection circuit 68 as in the first embodiment. The first generation circuit 69 has a function of generating a plurality of signal levels corresponding to the reference level of the determination device 14. The determination device 14 uses a reference voltage as a reference level. Therefore, the first generation circuit 69 generates a plurality of reference voltages Ref1, Ref2, and Ref3 as a plurality of signal levels. When the determination device 14 uses the current as a reference level, the signal level generation circuit is configured to generate a current having a plurality of values as the signal level.

[0177] In the first generation circuit 69, the value of the first reference voltage Ref1 is set to the intermediate voltage (= (maximum voltage + minimum voltage) / 2) of the input signal of the determination device 14. Then, the first generation circuit 69 generates so that the values of the second and third reference voltages Ref2 and Ref3 are (third reference voltage Ref3 &lt;first reference voltage Ref1 &lt;second reference voltage Ref2). Then, the first generation circuit 69 outputs each of the generated reference voltages Ref1 to Ref3 to the first selection circuit 68.

[0178] The first selection circuit 68 selects one of the reference voltages Ref1 to Ref3 based on the value of the first selection signal SEL1. Specifically, the first selection circuit 68 responds to the first selection signal SEL1 having a value of 0 with the first reference voltage Ref1 and responds to the first selection signal SEL1 having a value 1 with the second reference. The voltage Ref2 is selected as the third reference voltage Ref3 in response to the first selection signal SEL1 with the value "2". Then, the first selection circuit 68 outputs the selected voltage as a reference voltage Ref to the determination device 14.

[0179] Therefore, when the STM207 is in the state Z1, the first reference voltage Ref1 of the intermediate level is input to the determination device 14 as the reference voltage Ref. The output signal of the RAM 24 is input to the second selection circuit 203. The second generation circuit 204 is connected to the second selection circuit 203. The second generation circuit 204 generates a plurality of feedback (FB) signals Feed1 and Feed2 as a plurality of signal levels. When the determination device 14 uses the current as a reference level, the second generation circuit 204 may be configured to generate a current having a plurality of values as the signal level.

[0180] The second generation circuit 204 sets the first FB signal Feed1 to a value indicating a level higher than the first reference voltage Ref1 and the second FB signal Feed2 to a value indicating a level lower than the second reference voltage Ref1. .. That is, the second generation circuit 204 is (Feed1&gt; Ref1&gt; Feed2).

[0181] More specifically, in the second generation circuit 204, the value of the first FB signal Feed1 is (Ref1 + r), and the value of the second FB signal Feed2 is (Ref1-r). These values are theoretical values that the signal S3 can take, as shown in FIG. The second generation circuit 204 outputs the generated first and second FB signals Feed1 and Feed2 to the second selection circuit 203.

[0182] The second selection circuit 203 selects one of the output signal of the RAM 24 and the first and second FB signals Feed1 and Feed2 based on the value of the second selection signal SEL2. Specifically, the second selection circuit 203 responds to the second selection signal SEL2 having a value of 0 with the output signal of the RAM 24, and responds to the second selection signal SEL2 having a value 1 with the first FB signal Feed1. , And selects the second FB signal Feed2 in response to the second selection signal SEL2 with the value "2". Then, the second selection circuit 203 outputs the selected signal to the DAC 25.

[0183] The DAC 25 converts the input signal into an analog signal, and outputs the analog signal to the adder 13 as a feedback response (feedback signal S2). As a result, a feedback response to which any one of the output signal of the RAM 24 and the first and second FB signals Feed1 and Feed2 is added is returned to the adder 13 based on the second selection signal SEL2.

[0184] If the FB loop is not diverging, the STM207 outputs a second selection signal SEL2 having a value of "0". As a result, the output signal of the RAM 24 is fed back to the adder 13 as a feedback response.

[0185] The STM207 transitions from the state Z1 to the state Z2 when the sticking occurs based on the signals S71 and S72. In that state Z2, STM207 operates to change the amount of feedback in the FB loop.

[0186] More specifically, the signal S71 output from the divergence monitoring circuit 67 indicates a stuck state. Based on the signal S71, the STM207 outputs the signal S71 as the second selection signal SEL2 to the second selection circuit 203.

[0187] The second selection circuit 203 selects one of the first and second FB signals Feed1 and Feed2 based on the second selection signal SEL2, and outputs the selection signal to the DAC 25. Based on the signal S71, the STM207 outputs the second selection signal SEL2 having the value 1 when the determination signal S4 is fixed to the value 1. The second selection circuit 203 selects the first FB signal Feed1 based on the second selection signal SEL2 having a value of 1 and outputs it to the DAC 25.

As a result, the level of the first FB signal Feed1 is output to the adder 13 as a feedback response (feedback signal S2). The level of the feedback signal S2 at this time is smaller than the level of the feedback signal S2 based on the signal output from the RAM 24 when the determination signal S4 is fixed to "1". As a result, the STM207 reduces the amount of feedback when the determination signal S4 is fixed to "1". That is, as shown in FIG. 19, STM207 forcibly transitions DFE201 in state 1 (see FIG. 5) to state 2.

[0189] This is equivalent to increasing the reference voltage of the determination device 14 in the first embodiment. Further, it is equivalent to offsetting the feedback amount in the negative direction in the second embodiment. That is, the divergence monitoring circuit 67 increases the sensitivity of the determination device 14 to negative signals. As a result, the DFE 201 easily transitions to the state 3, and the determination device 14 outputs the determination signal S4 of 0.

[0190] Based on the signal S71, the STM207 outputs a second selection signal SEL2 having a value 2 when the determination signal S4 is fixed to the value 0. The second selection circuit 203 selects the second FB signal Feed2 based on the second selection signal SEL2 having a value of 2 and outputs it to the DAC 25.

As a result, the level of the second FB signal Feed2 is output to the adder 13 as a feedback response (feedback signal S2). The level of the feedback signal S2 at this time is higher than the level of the feedback signal S2 based on the signal output from the RAM 24 when the determination signal S4 is fixed to 0. As a result, the STM207 increases the feedback amount when the determination signal S4 is fixed to "0". That is, as shown in FIG. 20, STM207 forcibly transitions DFE201 in state 4 (see FIG. 5) to state 5.

[0192] This is equivalent to lowering the reference voltage of the determination device 14 in the first embodiment. Further, in the second embodiment, it is equivalent to offsetting the feedback amount in the positive direction. That is, the STM207 increases the sensitivity of the determination device 14 to a positive signal. As a result, the DFE 201 easily transitions to the state 6, and the determination device 14 outputs the determination signal S4 of 1.

[0193] When the STM207 finishes changing the feedback amount, the STM207 transitions from the state Z2 to the state Z3. In that state Z3, the STM207 operates to change the criteria of the determiner 14.

[0194] More specifically, the signal S71 output from the divergence monitoring circuit 67 indicates a state of sticking. Based on the signal S71, the STM207 outputs the signal S71 as the first selection signal SEL1 to the first selection circuit 68.

[0195] The first selection circuit 68 selects one of the second and third reference voltages Ref2 and Ref3 based on the first selection signal SEL1, and outputs the selection signal to the DAC 25. Based on the signal S71, the STM207 outputs the first selection signal SEL1 having the value 1 when the determination signal S4 is fixed to the value 1. The first selection circuit 68 outputs the second reference voltage Ref2 as the reference voltage Ref to the determination device 14 based on the first selection signal SEL1 having the value 1.

The level of this reference voltage Ref (= Ref2) is higher than that of the first reference voltage Ref1. As a result, the STM207 raises the judgment standard of the judgment device 14. That is, the divergence monitoring circuit 67 increases the sensitivity of the determination device 14 to negative signals. As a result, the DFE 201 easily transitions to the state 3, and the determination device 14 outputs the determination signal S4 of 0.

[0197] Based on the signal S71, the STM207 outputs the first selection signal SEL1 having the value 2 when the determination signal S4 is fixed to the value 0. The first selection circuit 68 outputs the third reference voltage Ref3 as the reference voltage Ref to the determination device 14 based on the first selection signal SEL1 having the value 2.

The level of this reference voltage Ref (= Ref3) is lower than that of the first reference voltage Ref1. As a result, STM207 lowers the judgment criteria of Judgment No. 14. That is, the STM207 increases the sensitivity of the determination device 14 to a positive signal. As a result, the DFE 201 easily transitions to the state 6, and the determination device 14 outputs the determination signal S4 of 1.

[0199] When the STM207 finishes changing the reference amount, it stays in the state Z3 of FIG. Then, when the STM207 detects a pulse based on the signal d0 input from the shift register 61 in FIG. 12, the STM207 transitions from the state Z3 to the state Z4.

[0200] The pulse detection indicates that the determination signal S4 has a data transition such as "0 1" or "1 0", that is, the sticking has been resolved. Therefore, STM207 reverts the reference amount in state Z4. That is, the STM207 outputs the first selection signal SEL1 having the value 0 to the first selection circuit 68.

[0201] Further, the STM207 outputs the second selection signal SEL2 having the value 0 to the second selection circuit 203. As a result, the FB filter 202 outputs a feedback response (feedback signal S2) based on the output signal of the RAM 24 to the adder 13 based on the second selection signal SEL2. Then, when a predetermined time (for example, 10 ms) elapses in the state Z4, the SMT207 transitions from the state Z4 to the state Z1.

[0202] As described above, according to the present embodiment, the following effects are obtained. (1) When the judgment signal S4 output from the judgment device 14 is stuck, the reference level is changed and the feedback amount is changed, so that the normal state can be returned earlier than in the first and second embodiments. it can.

(2) Since the error detection circuit 206 is provided, it is possible to detect an error locally existing in the shift register 61, and the reference amount and the feedback amount are changed for the error to return to the normal state. be able to.

[0204] In the above embodiment, the following changes may be made. In the above embodiment, the order of changing the feedback amount and the reference amount may be changed. That is, the STM207 of FIG. 12 operates to change the reference amount in the state Z2 of FIG. 13, and operates to change the feedback amount in the state Z3. Even with this configuration, the same actions and effects as those of the above-described embodiment can be obtained.

(Fourth Embodiment) Hereinafter, a fourth embodiment embodying the present invention will be described with reference to FIGS. 21 and 22. For convenience of explanation, the same components as those of the conventional example of FIG. 54 are designated by the same reference numerals, and the description thereof will be partially omitted.

[0206] FIG. 21 shows a partial block circuit diagram of the signal processing circuit 81 of the present embodiment. The signal processing circuit 81 includes a DFE 82, an A / D converter (hereinafter referred to as ADC) 83, a timing recovery PLL circuit (hereinafter referred to as TR-PLL) 84, and a digital arithmetic circuit (hereinafter simply referred to as an arithmetic circuit) 85. The ADC83 and TR-PLL84 form the PLL circuit 49 for timing clock reproduction shown in FIG.

[0207] The DFE 82 includes a changeover switch (first switch) 86 and an open / close switch (second switch) 87. The output signal S1 of the pre-filter 12 and the output signal S3 of the adder 13 are input to the first switch 86. The first switch 86 switches in response to the control signal SG1 input from the sequence control circuit 54 in FIG. 2, and outputs the output signal S1 of the pre-filter 12 or the output signal S3 of the adder 13 to the ADC 83. .. For example, the first switch 86 outputs the output signal S1 of the pre-filter 12 to the ADC83 based on the H level control signal SG1, and outputs the output signal S3 of the adder 13 to the ADC83 based on the L level control signal SG1. Output.

[0208] The second switch 87 is inserted and connected between the feedback filter (hereinafter referred to as FB filter) 22 and the adder 13. The second switch 87 opens and closes in response to the control signal SG2 output from the sequence control circuit 54 of FIG. For example, the second switch 87 opens (off) based on the H-level control signal SG2 and closes (on) based on the L-level control signal SG2. The feedback loop (hereinafter referred to as FB loop) of DFE82 is opened or closed by the opening / closing operation of the second switch 87.

[0209] The sequence control circuit 54 outputs a control signal to control the first and second switches 86 and 87 based on the information included in the read signal RD read from the magnetic disk 33.

[0210] More specifically, when the read operation is started, the sequence control circuit 54 sets the H level first and second control signals SG1 and SG2 of the pre-filter 12 to the first and second switches 86,87. Output to. The first switch 86 performs a switching operation based on the H level control signal SG1, and the output signal S1 of the pre-filter 12 is input to the ADC 83 via the first switch by the operation. The second switch 87 is turned off based on the H level control signal SG2. This opens the FB loop.

[0211] The ADC 83 A / D-converts the output signal S1 of the pre-filter 12, and outputs the converted signal S11 to the digital arithmetic circuit 85. The arithmetic circuit 85 has a function of calculating the initial value of the FB filter 22 based on the output signal S11 of the ADC 83, a function of detecting preamble data based on the output signal of the ADC 83, and the initial value in the shift register 15 of the DFE 82. Has a writing function.

[0212] When the digital arithmetic circuit 85 detects the preamble data, it writes the calculated initial value to the shift register 15. The FB filter 22 of the DFE 82 calculates the feedback amount (feedback response) based on the signal input from the shift register 15, and outputs the calculation result to the adder 13. Therefore, the FB filter 22 calculates the feedback amount based on the initial value written in the shift register 15. As a result, the digital arithmetic circuit 85 realizes a function of presetting the contents of the shift register 15 based on the calculated initial value.

[0213] Further, when the digital arithmetic circuit 85 detects the preamble data, the digital arithmetic circuit 85 outputs the detection signal to the sequence control circuit 54 of FIG. The sequence control circuit 54 responds to the detection signal of the digital arithmetic circuit 85 and outputs L-level control signals SG1 and SG2 to the first and second switches 86 and 87.

[0214] The first switch 86 switches based on the L-level first control signal SG1, and the output signal S3 of the adder 13 is input to the ADC 83 via the first switch 86 by the operation. The ADC83 A / D-converts the output signal of the adder 13 and outputs the converted signal to the TR-PLL84. The TR-PLL84 pulls the phase of the reference clock signal SCK into the preamble signal based on the output signal of the ADC83.

[0215] The second switch 87 is turned on based on the L level second control signal SG2. As a result, the output signal of the FB filter 22 is fed back to the adder 13 via the turned on second switch 87. At this time, the FB filter 22 calculates the feedback amount based on the contents (initial value) of the preset shift register 15, and outputs the calculation result as the feedback signal S2. Therefore, the FB loop starts feedback based on this feedback signal S2. That is, therefore, the digital arithmetic circuit 85 determines the initial value of the FB filter 22.

As shown in FIG. 22, at the start of the read operation, the preamble data and the sync byte are first read prior to the data. This preamble data is a periodic pattern. The TR-PLL84 performs phase pull-in to match the phase of the reference clock signal SCK with the phase of the read signal RD (preamble signal) (actually, the output signal S11 of the ADC83) from which the preamble data has been read. As a result, the sink byte (SB) and data read following the preamble data are sampled at an accurate timing. However, at the start of the read operation, the TR-PLL84 has not been able to sufficiently pull in the phase, so that the phase of the reference clock signal SCK may not match the phase of the preamble signal.

The shift register 15 of the DFE 82 samples the determination signal S4, which is the determination result of the determination device 14, based on the reference clock signal SCK, and sequentially stores the sampled data. Therefore, if the phase of the reference clock signal SCK does not match the phase of the preamble signal, the shift register 15 stores erroneous data. This erroneous data is fed back to the adder 13 via the FB filter 22. As a result, the FB loop propagates erroneous data, and the FB loop diverges. The divergence of this FB loop hinders the reproduction of data and prolongs the time required for the read operation.

On the other hand, the signal processing circuit 81 of the present embodiment opens the FB loop at the start of the read operation, and determines the initial value of the FB filter 22 based on the initial value calculated by the digital arithmetic circuit 85. Then, the signal processing circuit 81 operates the FB loop from the determined initial value.

[0219] As a result, at the start of the read operation, it is possible to prevent the FB loop from diverging by feeding back the data sampled by the reference clock signal SCK whose synchronous pull-in is not sufficient with respect to the read signal RD. Further, by calculating the initial value of the FB filter 22 and setting it in the shift register, the time until the FB loop operates stably becomes shorter than the case where the initial value is not used.

[0220] As described above, according to the present embodiment, the following effects are obtained. (1) The signal processing circuit 81 controls the second switch 87 at the start of the read operation to open the FB loop. The signal processing circuit 81 controls the first switch 86 to synchronously pull in the TR-PLL84 based on the output signal S1 of the pre-filter 12. After that, the signal processing circuit 81 controls the second switch 87 and returns the determined initial value to the adder 13 to operate the FB loop. As a result, at the start of the read operation, the data sampled by the reference clock signal SCK whose synchronous pull-in is not sufficient for the read signal RD does not return to the adder 13, so that the FB loop can be prevented from diverging. it can.

(2) The signal processing circuit 81 determines the initial value of the FB filter 22 based on the initial value calculated by the digital arithmetic circuit 85. Then, the signal processing circuit 81 controls the second switch 87 and returns the determined initial value to the adder 13 to operate the FB loop. As a result, by calculating the initial value of the FB filter 22 and setting it in the shift register, erroneous data does not propagate in the RB loop. As a result, the time until the FB loop operates stably can be shortened as compared with the case where the initial value is not used.

(Fifth Embodiment) Hereinafter, a fifth embodiment embodying the present invention will be described with reference to FIG. 23. For convenience of explanation, the same components as those in the fourth embodiment of FIG. 21 are designated by the same reference numerals, and the description thereof will be partially omitted.

FIG. 23 shows a partial block circuit diagram of the signal processing circuit 81a of the present embodiment. The signal processing circuit 81a includes a DFE82, an ADC83, and a digital arithmetic circuit (hereinafter, simply referred to as an arithmetic circuit) 88. The arithmetic circuit 88 includes a digital filter 89, a timing recovery PLL circuit (hereinafter referred to as TR-PLL) 90, and a register 91.

[0224] The digital filter 89 is a filter that performs optimal waveform equalization for preamble. The digital filter 89 outputs the filtered signal to the TR-PLL90. The TR-PLL90 synchronously pulls in the reference clock signal SCK for the preamble based on the output signal of the digital filter 89. Synchronous pulling includes frequency pulling in which the frequency of the reference clock signal SCK is matched with the frequency of the preamble, and phase pulling in which the phase of the reference clock signal SCK is matched with the phase of the preamble.

[0225] The TR-PLL90 includes a register 91 that stores a periodic pattern corresponding to a preamble in advance. When the TR-PLL90 detects the input of the preamble, it first performs frequency pull-in. The TR-PLL90 detects the input of the preamble by comparing the pattern of the output signal S12 of the digital filter 89 with the periodic pattern.

[0226] For example, the 6T pattern preamble is configured so that "111" and "000" appear alternately and periodically. Then, the cycle pattern "111000" to be preambled is stored in the register 91. The TR-PLL90 performs preamble detection when the output signal S12 of the digital filter 89 is "111" or "000".

[0227] When the TR-PLL90 finishes the frequency pull-in, the TR-PLL90 then performs the phase pull-in based on the output signal S12 of the digital filter 89. As a result, the TR-PLL90 matches that of the reference clock signal SCK with the frequency and phase of the preamble. The TR-PLL90 outputs the synchronously pulled-in reference clock signal SCK to the shift register 15 of the ADC83 and DFE82.

[0228] The initial value of the feedback filter 22 is stored in the register 91. This initial value is pre-calculated based on the preamble and stored in the register 91. When the frequency is pulled in by the TR-PLL90, the arithmetic circuit 88 outputs the initial value stored in the register 91 to the shift register 15 of the DFE 82. The arithmetic circuit 88 may be configured to calculate the initial value at each time and output the arithmetic result to the shift register 15.

[0229] As described above, according to the present embodiment, the following effects are obtained. (1) It has the same effect as (1) of the fourth embodiment. (2) The arithmetic circuit 88 presets the shift register 15 based on the initial value of the feedback filter 22 stored in the register 91 in advance. As a result, the shift register 15 can be preset to prevent divergence without the need to calculate the initial value.

(3) By providing the digital filter 89 that performs the optimum waveform equalization for the preamble, the TR-PLL90 can easily perform the synchronous pull-in of the reference clock signal SCK to the preamble.

(Sixth Embodiment) Hereinafter, a sixth embodiment embodying the present invention will be described with reference to FIG. 24. For convenience of explanation, the same components as those in the fourth embodiment of FIG. 21 are designated by the same reference numerals, and the description thereof will be partially omitted.

[0232] FIG. 24 shows a partial block circuit diagram of the signal processing circuit 81b of the present embodiment. The signal processing circuit 81b includes a DFE82, an ADC83, a digital signal processor (DSP) 92, and a voltage controlled oscillator (VCO) 93.

[0233] The DSP 92 has a function of performing optimum waveform equalization for preamble, and a function of detecting the frequency difference and phase difference between the signal after waveform equalization and the reference clock signal SCK output from the VCO 93. The DSP92 outputs a signal based on the detected frequency difference and phase difference to the VCO93. The VCO93 outputs a frequency and phase reference clock signal SCK based on the output signal of the DSP 92.

[0234] Further, the DSP 92 has a function of calculating the initial value of the FB filter 22. The DSP92 outputs the calculated initial value to the shift register 15 of the DFE82. The FB filter 22 calculates the feedback amount of the FB loop based on the initial value stored in the shift register 15.

[0235] As described above, according to the present embodiment, the following effects are obtained. (1) The signal processing circuit 81b can simplify the configuration by performing signal processing for detecting the preset of the shift register 15, the frequency difference and the phase difference required for synchronous pulling of the reference clock signal SCK by the DSP92. it can. This makes it possible to reduce the chip size of the signal processing circuit 81b.

[0236] In the above embodiment, the following changes may be made. The output signal S11 of the ADC 83 of the fourth to sixth embodiments may be used for purposes other than generating the reference clock signal SCK. For example, as shown in FIG. 25, the signal processing circuit 81c used to output the signal for the servo to the servo circuit 36 may be configured. The signal processing circuit 81c includes a digital filter 94 for filtering servo information. The filter 94 performs waveform equalization processing optimally for the servo information on the output signal S11 of the ADC 83, and outputs the processed signal to the servo circuit 36. The servo circuit 36 controls the second motor M2 of FIG. 1 based on the output signal of the filter 94 to turn the head device 34 on-track. As a result, the signal processing circuit 81c and the servo circuit 36 can be mounted on one chip. As a result, in addition to the effects of the fourth embodiment, the configuration of the hard disk device 31 can be simplified.

[0237] Further, as shown in FIG. 26, the signal processing circuit 81d including the phase control circuit 95 may be used. With this configuration, phase control can be processed digitally.

(Seventh Embodiment) Hereinafter, a seventh embodiment embodying the present invention will be described with reference to FIGS. 27 to 32. For convenience of explanation, the same components as those in the fourth embodiment of FIG. 21 are designated by the same reference numerals, and the description thereof will be partially omitted.

[0239] FIG. 27 shows a partial block circuit diagram of the signal processing circuit 101 of the present embodiment. The signal processing circuit 101 includes a determination feedback equalizer (hereinafter referred to as DFE) 82, an ADC 83, a digital filter 102, a zero phase restart circuit 103, and a timing recovery PLL circuit (hereinafter referred to as TR-PLL) 104.

[0240] The digital filter 102 equalizes the preamble data into an optimum waveform. The digital filter 102 outputs the waveform-equalized signal S21 to the zero-phase restart circuit (hereinafter, simply referred to as a restart circuit) 103.

[0241] The restart circuit 103 generates a reference clock signal SCK based on the output signal S21 of the digital filter 102, and outputs the reference clock signal SCK to the TR-PLL104. The TR-PLL104 generates a system clock signal SCK to be supplied to the shift register 15 of the ADC83 and DFE83. Based on the reference clock signal SCK, the TR-PLL104 performs phase pulling to match the phase of the system clock signal SCK with the phase of the read signal RD read from the magnetic disk 33 of FIG.

[0242] The restart circuit 103 determines the phase of the reference clock signal SCK supplied to the TRPLL based on the control data (specifically, the preamble data) included in the read signal RD read from the magnetic disk 33 of FIG. It has a function to perform initial phase pull-in to the phase of the lead signal RD. The initial phase pull-in operates so as to roughly match the phase of the reference clock signal SCK with the phase of the read signal RD. This initial phase pull-in shortens the phase pull-in time in the TR-PLL104.

[0243] That is, the TR-PLL104 requires a time for phase pulling according to the phase difference between the generated system clock signal SCK and the read signal RD. Therefore, if the system clock signal SCK and the read signal RD are out of phase, the time required for phase pulling becomes long. This prolongs the time until the data is read, which hinders the speeding up of the reading process.

Further, when the phase of the system clock signal SCK and the phase of the lead signal RD are largely out of phase, the TR-PLL104 sufficiently draws the phase of the system clock signal SCK into the phase of the lead signal RD (phase shift). It may not be possible to make it almost zero). In order to make the sampling of data inaccurate, these require repeated execution of the read process, which also hinders the speeding up of the read process.

[0245] On the other hand, the restart circuit makes the phase difference of the read signal RD with respect to the reference clock signal SCK smaller than that of the output signal of the ADC 83 by performing the initial phase pull-in. The TR-PLL104 pulls in the phase of the system clock signal SCK based on the phase difference between the reference clock signal SCK and the system clock signal SCK. As a result, the time required for phase pulling is shorter than when the phase of the system clock signal SCK is pulled into the read signal RD based on the output signal of the ADC83.

[0246] Further, the restart circuit 103 has a function of presetting the shift register 15 of the DFE 82. The restart circuit 103 holds a plurality of data obtained by sampling the output signal S11 of the ADC 83 when the initial phase is pulled in. Based on this retained data, the restart circuit 103 extracts the characteristics of the read signal RD (hereinafter, simply referred to as a printable signal) from which the preamble data has been read. Based on the extracted features, initial phase pull-in is performed to match the phase of the reference clock signal SCK with the printable signal.

[0247] When the initial phase pull-in is completed, the restart circuit 103 presets the shift register 15 based on the stored data. With this configuration, it is possible to preset the error data of the DFE 82 in the initial phase pull-in and suppress the divergence of the feedback loop, as in the fourth to sixth embodiments.

Next, the configuration of the restart circuit 103 will be described in detail. FIG. 28 shows a schematic block circuit diagram of the restart circuit 103. The restart circuit 103 is a circuit for performing initial phase pull-in based on the preamble signal of the 4T pattern. In FIG. 28, the digital filter 102 of FIG. 27 is omitted.

[0249] The restart circuit 103 includes a first shift register 105, a tilt calculation circuit 106, a second shift register 107, a phase difference detection circuit 108, a pattern determination circuit 109, a third shift register 110, a register 111, and a phase control decoder 112. , Sequencer 113, phase retention register 114, clock switching circuit 115, voltage controlled oscillator (VCO) 116 as clock signal generation circuit.

[0250] The output signal S11 of the ADC 83 is input to the first shift register 105 of the restart circuit 103. The first shift register 105 includes two registers 105a and 105b that operate based on the clock signal CLK1. The clock signal CLK1 is generated by a clock circuit (not shown) based on the reference clock signal SCK.

[0251] Each of the registers 105a and 105b has a function of holding data of a plurality of bits (the number of bits of the output signal of the ADC 83). Therefore, the first shift register 105 holds two data samples of the output signal S11 of the ADC 83 based on the clock signal CLK1. The first shift register 105 outputs the held data to the gradient calculation circuit 106.

[0252] The slope calculation circuit 106 calculates the slope of the line segment connecting the coordinates of the two data based on the two data input from the first shift register 105. The inclination calculation circuit 106 outputs the calculation result to the second shift register 107.

[0253] The second shift register 107 includes three registers 107a to 107c that operate based on the clock signal CLK1. Therefore, the second shift register 107 holds the data output from the inclination calculation circuit 106 at that time and the two data output before the data. Each data is the value of the slope between two consecutive sampling points. Therefore, the second shift register 107 holds the values of the three slopes between the four consecutive sampling points, and outputs the three held data to the phase difference detection circuit 108.

[0254] The first-stage register 105a constituting the first shift register 105 outputs the held data to the pattern determination circuit 109. A predetermined slice level is input to the pattern determination circuit 109. The pattern determination circuit 109 sequentially determines the level of data based on the slice level. Then, the pattern determination circuit 109 outputs the determination signal S22 based on the determination result to the third shift register 110.

[0255] In detail, the first and second determination levels are input to the pattern determination circuit 109 as slice levels. The first judgment level is set to a level higher than the second judgment level. For example, the first judgment level is set to + α (v) and the second judgment level is set to -α (v) and input.

[0256] The pattern determination circuit 109 compares the level of the output data of the first shift register 105 with the first and second determination levels. Then, the pattern determination circuit 109 outputs the determination signal S22 of "1" when the output data is larger than the first determination level. Further, the pattern determination circuit 109 outputs a determination signal S22 of "0" when the output data is at a level between the first determination level and the second determination level. Further, the pattern determination circuit 109 outputs the determination signal S22 of "-1" when the output data is smaller than the second determination level.

[0257] The third shift register 110 includes four registers 101a to 101d that operate based on the clock signal CLK1. Therefore, the third shift register 110 holds the data which is the determination result output from the pattern determination circuit 109 at that time and the three data output from the pattern determination circuit 109 before the data. That is, the third shift register 110 holds data at four consecutive sampling points. Each data shows a pattern with four sampling points that sampled the output signal S11 of ADC83. The third shift register 110 outputs the held four data to the phase difference detection circuit 108.

The phase difference detection circuit 108 detects the phase difference of the reference clock signal SCK with respect to the input signal (read signal RD) of the ADC 83 based on the output data of the second and third shift registers 117 and 110. More specifically, the phase difference detection circuit 108 selects one of the output data of the second shift register 107 based on the output data of the third shift register 110.

[0259] The third shift register 110 holds data at four sampling points that sample the preamble signal. The phase difference between the phase of the output signal S11 of the ADC83 and the reference clock signal SCK (sampling clock CLK1) appears as the slope of the sampling point. That is, the slope is 0 (zero) when the phases are in phase. The larger the phase difference, the larger the slope of the sampling point.

[0260] Further, in the preamble signal of the 4T pattern, the determination result of the pattern determination circuit 109 corresponds to "1100" which is the pattern of the preamble signal. Therefore, the phase difference between the preamble signal and the reference clock signal SCK can be detected by examining the slopes of the two sampling points that are "11" or "00".

Therefore, the phase difference detection circuit 108 has a slope (position) at the sampling point of the pattern of 11 or 00 based on the pattern of four consecutive sampling points held in the third shift register 110. Phase difference) is input from the second shift register 107.

[0262] The phase difference detection circuit 108 outputs data based on the detected phase difference to the first register 111. The first register 111 latches the output data of the phase difference detection circuit 108, and outputs the latched data to the phase control decoder 112.

The phase control decoder 112 is controlled by the sequencer 113. The phase control decoder 112 generates control data obtained by decoding both data based on the data input from the first register 111 and the data input from the second register (phase holding register) 114. The control data generated and output by the phase control decoder 112 based on the previous sampling data is latched in the second register 114. Therefore, the phase control decoder 112 generates the control data at that time based on the data latched in the first register 111 at that time and the control data generated immediately before that time. Then, the phase control decoder 112 outputs the generated control data to the second register 114. The second register 114 latches the output data of the phase control decoder 112, and outputs the latched control data to the clock switching circuit 115.

[0264] A plurality of (six in this embodiment) clock signals CK1 to CK6 generated by the VCO 116 are input to the clock switching circuit 115. As shown in FIG. 29, these clock signals CK1 to CK6 have the same frequency but different phases. More specifically, the VCO116 divides one cycle of the reference first clock signal CK1 into equal parts (six divisions), and generates clock signals CK2 to CK6 whose phases are out of phase by the equally divided periods. The phases of the second to fourth clock signals CK2 to CK4 are ahead of those of the first clock signal CK1 with respect to the reference first clock signal CK1, and the fifth and sixth clock signals CK5 and CK6 are the fifth. The phase is behind the 1 clock signal. Then, each clock signal CK1 to CK6 is generated so as to be CK4, CK3, CK2, CK1, CK6, CK5 in order from the one in which the phase is advanced.

[0265] The clock switching circuit 115 selects one of the first to sixth clock signals CK1 to CK6 based on the control data input from the phase control decoder 112. Then, the clock switching circuit 115 outputs the selected clock signal as the reference clock signal SCK to the TR-PLL104.

Next, the operation of the zero-phase restart circuit 103 configured as described above will be described with reference to FIG. Now, the sampling clock CLK1 is generated based on the first clock signal CK1 (reference clock signal SCK). The restart circuit 103 samples sampling points P1 to P4 based on the sampling clock CLK1. Based on these points P1 to P4, the second shift register 107 stores the slope between points P1-P2, P2-P3, and P3-P4. Further, the third shift register 110 stores the pattern "1100" based on the determination result of the pattern determination circuit 109.

[0267] The phase difference detection circuit 108 inputs the slope between points P1-P2 to be "11" based on the pattern stored in the third shift register 110. The slope between points P3-P4, which is "00", may be input.

[0268] The phase difference detection circuit 108 determines that the phase is advanced based on the input slope, and generates control data for delaying the phase of the reference clock signal SCK. Then, the phase difference detection circuit 108 outputs the control data to the clock switching circuit 115 via the second register 114.

[0269] The clock switching circuit 115 selects a sixth clock signal CK6 having a phase slower than that of the first clock signal CK1 based on the control data, and outputs the sixth clock signal CK6 as a reference clock signal SCK.

Next, the restart circuit 103 samples points P5 to P8 by the sampling clock CLK1 based on the sixth clock signal CK6. In the same manner as described above, the second shift register 107 stores the slope between points P5-P6, P6-P7, and P7-P8. The third shift register 110 stores the pattern 0110.

[0271] The phase difference detection circuit 108 inputs the inclination between points P6-P7 to be 00, and determines that the phase is advanced based on the inclination. Based on the determination result, the phase difference detection circuit 108 generates control data for delaying the phase of the reference clock signal SCK. Then, the phase difference detection circuit 108 outputs the control data to the clock switching circuit 115 via the second register 114.

[0272] The clock switching circuit 115 selects a fifth clock signal CK5 having a phase slower than that of the sixth clock signal CK6 based on the control data, and outputs the fifth clock signal CK5 as a reference clock signal SCK.

Next, the restart circuit 103 samples points P9 to P12 by the sampling clock CLK1 based on the fifth clock signal CK5. In the same manner as described above, the second shift register 107 stores the slope between points P9-P10, P10-P11, and P11-P12. The third shift register 110 stores the pattern 0011.

[0274] The phase difference detection circuit 108 inputs the inclination between the points P11 and P12 to be "11", and determines that the phases match based on the inclination. Based on the determination result, the sequencer 113 stops the phase control decoder 112.

At this time, the control data for selecting the fifth clock signal CK5 is held in the second register 114. The restart circuit 103 continuously outputs the reference clock signal SCK based on the fifth clock signal CK5.

[0276] With respect to the restart circuits 103 and TR-PLL104 configured as described above, the sequence control circuit 54 of FIG. 2 controls according to the timing shown in FIG. 31. That is, when the reading of the preamble is started, the start signal XRG of the L level is input to the sequence control circuit 54 from the MPU 37 of FIG. The sequence control circuit 54 outputs an H level phase control signal CNZ based on the L level start signal XRG.

[0277] Further, the sequence control circuit 54 outputs the first and second control signals SG1 and SG2. As a result, the output signal S1 of the pre-filter 12 is input to the restart circuit 103. The restart circuit 103 responds to the phase control signal CNZ and starts initial phase pulling based on the signal S1.

[0278] When the restart circuit 103 finishes the initial phase pull-in, the shift register 15 of the DFE 82 is preset. In response to this, the sequence control circuit 54 outputs the L-level phase control signal CNZ and outputs the H-level frequency control signal CT2. Further, the sequence control circuit 54 outputs the first and second control signals SG1 and SG2. As a result, the FB loop of the DFE82 is closed, and the output signal S3 of the adder 13 is input to the TR-PLL104. Then, the TR-PLL104 responds to the H level control signal CT2 and pulls in the frequency based on the output signal S3.

[0279] When the sequence control circuit 54 finishes reading the preamble, the sequence control circuit 54 outputs the L level frequency control CT2 in response to the reading of the preamble. Then, when the sync byte is detected in the control data detection circuit 53 of FIG. 2, the sink byte detection signal SB is output to the MPU 37. The MPU37 handles and processes the data following the sink byte as data based on the sink byte detection signal SB.

[0280] As described above, according to the present embodiment, the following effects are obtained. (1) A zero-phase restart circuit 103 is provided, and the restart circuit 103 is used to pull in the initial phase of the preamble signal and the reference clock signal SCK. As a result, the time required for the synchronous pull-in in the TR-PLL104 is shortened, the synchronization can be established quickly, and the read operation can be speeded up.

(2) The zero-phase restart circuit 103 extracts the characteristics of the preamble signal and calculates the phase difference between the preamble signal and the reference clock signal SCK based on the characteristics. As a result, the phase difference can be easily detected and the time required for the initial synchronous pull-in can be shortened.

(3) A VCO116 that generates a plurality of clock signals CK1 to CK6 having different phases is provided, and one of the clock signals CK1 to CK6 is selected according to the calculated phase difference. As a result, the clock signal CLK whose phase is close to that of the preamble signal can be easily output.

[0283] In the above embodiment, the following changes may be made. The sequence control circuit 54 of the above embodiment may be configured to perform phase pull-in stepwise in response to two types of preamble signals. That is, as shown in FIG. 32, the 6T pattern preamble is read out from the magnetic disk 33 of FIG. 2 following the 4T pattern preamble. The sequence control circuit 54 outputs an H-level phase control signal CNZ in response to the start signal XRG.

[0284] Further, the sequence control circuit 54 outputs the first and second control signals SG1 and SG2. As a result, the output signal S1 of the pre-filter 12 is input to the restart circuit 103. The restart circuit 103 responds to the phase control signal CNZ and starts the initial phase pull-in based on the preamble signal of the 4T pattern.

[0285] When the restart circuit 103 finishes the initial phase pull-in, the shift register 15 of the DFE 82 is preset. In response to this, the sequence control circuit 54 outputs an L-level phase control signal CNZ.

Next, when the 6T pattern preamble is read out, the sequence control circuit 54 outputs the H level frequency control signal CT2 in response to the reading. Further, the sequence control circuit 54 outputs the first and second control signals SG1 and SG2. As a result, the FB loop of the DFE82 is closed, and the output signal S3 of the adder 13 is input to the TR-PLL104. Then, the TR-PLL104 responds to the H-level control signal CT2 and pulls in the frequency based on the preamble signal of the 6T pattern.

(Eighth Embodiment) Hereinafter, an eighth embodiment embodying the present invention will be described with reference to FIGS. 33 to 43. For convenience of explanation, the same reference numerals will be given to the same configurations as those of the conventional example and the first embodiment of FIG. 54, and the description thereof will be partially omitted.

[0288] FIG. 33 shows a partial circuit diagram of the signal processing circuit 121 of the present embodiment. The signal processing circuit 121 includes a judgment feedback equalizer (DFE) 82, an analog-to-digital converter (hereinafter referred to as ADC) 122, a zero-phase restart circuit (hereinafter referred to as a restart circuit) 123, and a clock signal generation circuit. Includes a timing recovery PLL circuit (hereinafter referred to as TR-PLL) 124. In FIG. 33, the feedback filter 22 and the first and second switches 86 and 87 constituting the DFE 82 are omitted.

[0289] The ADC 122 converts the output signal S3 of the adder 13 into a digital signal having a predetermined number of bits (6 bits in this embodiment), and outputs the digital signal to the restart circuit 123.

[0290] The restart circuit 123 is a circuit corresponding to preamble data of a 6T pattern. The 6T pattern is a cycle pattern (111000111000 ....) in which data of the same value appears in 6 cycles (6 clocks) of the system clock signal SCK.

[0291] The restart circuit 123 includes a print detection circuit 125, an arithmetic circuit 126, a decoding circuit 127, a selection circuit 128, and a frequency divider 129. The data stored in the shift register 15 of the DFE 82 is input to the preamble detection circuit 125. When the preamble detection circuit 125 detects the read signal RD (hereinafter referred to as the preamble signal) from which the preamble data has been read based on the input data, the preamble detection circuit 125 outputs the detection signal S25 to the arithmetic circuit 126.

[0292] Further, the preamble detection circuit 125 has a function of presetting the shift register 15 based on the preamble data when the preamble signal is detected. This preset function presets the feedback amount of the feedback loop of the DFE82 and prevents the FB loop of the DFE82 from diverging, as in the fourth embodiment.

[0293] The arithmetic circuit 126 responds to the detection signal S25 input from the preamble detection circuit 125, and at that time, performs the initial phase pull-in of the system clock signal SCK with respect to the output signal S26 of the ADC 122. The detection signal S25 is the result of detecting the preamble signal. Therefore, the arithmetic circuit 126 calculates the cross-correlation function in the sampling data of the preamble signal in response to the detection signal S25. Further, the arithmetic circuit 126 calculates the phase difference between the printable signal and the reference clock signal SCK based on the calculated cross-correlation function. Then, the arithmetic circuit 126 outputs a signal corresponding to the calculated phase difference to the decoding circuit 127.

[0294] The decoding circuit 127 decodes the output signal of the arithmetic circuit 126 to generate the selection signal S27, and outputs the selection signal S27 to the selection circuit 128. A plurality of clock signals CK1 to CK6 having different phases from TR-PLL124 are input to the selection circuit 128. The selection circuit 128 selects one of a plurality of clock signals CK1 to CK6 based on the selection signal S27, and outputs the selected clock signal as the system clock signal SCK. The phase of this system clock signal SCK roughly matches the phase of the preamble signal. The TR-PLL pulls in the phase of the system clock signal SCK and the preamble signal output from the ADC 122. As a result, the time required for phase pull-in is shortened as in the seventh embodiment.

[0295] The outline of the principle of the restart circuit 123 of the present embodiment will be described. The preamble signal is a signal obtained by reading preamble data which is a periodic pattern. This preamble signal is the target of pulling in the phase. Let it be a function fc (τ) of this preamble signal.

First, the arithmetic circuit 126 generates two reference signals having different phases from the reference clock signal SCK. At this time, in the arithmetic circuit 126, the first reference signal whose phase is one symbol rate ahead of the reference clock signal SCK (one cycle of the reference clock signal SCK) and one symbol rate phase behind the reference clock signal SCK are delayed. Generate a second reference signal.

Next, the arithmetic circuit 126 calculates the cross-correlation functions ff (τ) and fd (τ) of the preamble signal and the first and second reference signals, respectively. The arithmetic circuit 126 calculates the difference dcn (τ) (= | ff (τ) -fd (τ) |) between the two calculated cross-correlation functions ff (τ) and fd (τ). As shown in FIG. 35, the value of this difference dcn (τ) (the value on the vertical axis in FIG. 35) is proportional to the phase difference (phase shift) between the reference clock signal SCK and the preamble signal. Therefore, based on this difference, a clock signal close to the phase of the preamble signal is selected from the plurality of clock signals output from the TR-PLL124. In this way, the restart circuit 123 performs the initial phase pull-in.

Next, the configurations of the arithmetic circuit 126 and the decoding circuit 127 will be described in detail with reference to FIG. 34. The output signal S26 of the ADC 122 is input to the first register 131 of the arithmetic circuit 126. The first register 131 latches the output signal S26 based on the clock signal CK, and outputs the latched signal to the first and second adders 132a and 132b. The control signals CNTL1 and CNTL0 are input from the control circuit 133 to the first and second adders 132a and 132b. The detection signal S25 output from the pull amble detection circuit 125 of FIG. 33 and the reference clock signal SCK are input to the control circuit 133. The control circuit 133 generates the control signals CNTL1 and CNTL0 based on the detection signal S25 as shown in FIG. 36, and outputs them to the first and second adders 132a and 132b.

[0299] The output signal S32a of the second register 134a is input to the first adder 132a. The first adder 132a adds the output signal of the first register 131 and the output signal S32a of the second register 134a based on the control signals CNTL1 and CNTL0.

As shown in FIG. 36, for example, when the control signals CNTL1 and CNTL0 are 00, the first adder 132a is the result of adding the input a (output signal S26) and the input b (output signal S32a). Output x. When the control signals CNTL1 and CNTL0 are "01", the first adder 132a outputs x as a result of adding the input -a (inverted signal of the output signal S26) and the input b (output signal S32a).

[0301] The first adder 132a outputs the calculation result to the second register 134a. The second register 134a latches the output signal S31a of the first adder 132a based on the clock signal CK.

[0302] The output signal S32b of the third register 134b is input to the second adder 132b. The second adder 132b adds the output signal of the first register 131 and the output signal S32b of the third register 134b based on the control signals CNTL1 and CNTL0, and outputs the calculation result to the third register 134b. The third register 134b latches the output signal S31b of the second adder 132b based on the clock signal CK.

[0303] With the above configuration, the first adder 132a and the second register 134a generate a reference signal whose phase is different by one symbol rate from the preamble signal which is an input signal, and preamble with the reference signal. Construct a first correlator that computes the signal cross-correlation function. Similarly, the second adder 132b and the third register 134b generate a reference signal whose phase is different by one symbol rate from the preamble signal which is an input signal, and the cross-correlation function of the reference signal and the preamble signal. Construct a second correlator that calculates.

The second and third registers 134a and 134b output the output signals S32a and S32b to the first and second subtractors 135a and 135b, respectively. The first subtractor 135a subtracts the output signal S32b of the third register 134b from the output signal S32a of the second register 134a, and outputs the subtraction result to the fourth register 136a. The fourth register 136a latches the output signal based on the clock signal CK, and outputs the latched signal S33a to the selection circuit 137. Further, the fourth register 136a outputs the sign bit f1a of the output signal S33a to the decoder 139 of the decoding circuit 127.

The second subtractor 135b subtracts the output signal S32a of the second register 134a from the output signal S32b of the third register 134b, and outputs the subtraction result to the fifth register 136b. The fifth register 136b latches the output signal based on the clock signal CK, and outputs the latched signal S33b to the selection circuit 137. Further, the fifth register 136b outputs the sign bit f1b of the output signal S33b to the decoder 139.

[0306] The decoder 139 generates a selection signal SL1 corresponding to a positive sign bit based on the sign bits f1a and f1b input from the fourth and fifth registers 136a and 136b, and selects the selection signal SL1. Output to circuit 137. The selection circuit 137 outputs a positive value signal S34 selected from the output signals S33a and S33b of the fourth and fifth registers 136a and 136b to the first to third comparators 138a to 138c based on the selection signal SL1. .. With this configuration, the absolute values of the output signals of the first and second correlators are input to the first to third comparators 138a to 138c.

[0307] The first to third comparison signals R1 to R3 are input to the first to third comparators 138a to 138c, respectively. The 1st to 3rd comparison signals R1 to R3 are the values of the 1st to 3rd comparison levels Low to High with respect to the phases P3 to P1, Z and N1 to N3 shown in FIG. 37, and this value is used as the reference clock signal CK. On the other hand, it corresponds to the phase difference of a plurality of clock signals CK1 to CK6 generated by the TR-PLL124.

[0308] More specifically, the TR-PLL124 divides one cycle of the reference first clock signal CK1 into equal parts (six divisions), similarly to the VCO116 (see FIG. 28) of the seventh embodiment. The second to sixth clock signals CK2 to CK6, which are out of phase by the equally divided period, are generated (see FIG. 29).

[0309] The second to fourth clock signals CK2 to CK4 are 1/6 cycle ahead of the first clock signal CK1, and the sixth and fifth clock signals CK6 and CK5 are the first clock signals CK1. The phase is delayed by 1/6 cycle. Further, the fourth clock signal CK4 is 3/6 cycle ahead of the first clock signal CK1. This is equivalent to a 3/6 cycle phase lag behind the first clock signal CK1.

[0310] The level of the first comparison signal R1 is set to a value corresponding to the phase difference between the reference first clock signal CK1 and the second and sixth clock signals CK2 and CK6. The level of the second comparison signal R2 is set to a value corresponding to the phase difference between the first clock signal CK1 and the third and fifth clock signals CK3 and CK5. The level of the third comparison signal R3 is set to a value corresponding to the phase difference between the first clock signal CK1 and the fourth clock signal CK4.

[0311] The first to third comparators 138a to 138c compare the level of the output signal S34 of the selection circuit 137 with the level of the first to third comparison signals R1 to R3, respectively, and a signal based on the comparison result. Outputs S35a to S35c to the decoder 139. Specifically, the 1st to 3rd comparators 138a to 138c preamble the H level (1) signals S35a to S35c when the preamble signal level is higher than that of the 1st to 3rd comparators R1 to R3. When the signal level is smaller than that of the first to third comparison signals R1 to R3, the L level (0) signals S35a to S35c are output, respectively.

[0312] For example, when the phase difference between the preamble signal and the reference clock signal (first clock signal) CK1 is within 1/6 cycle (phase Z in FIG. 38), both the first to third comparators 138a to 138c are used. Outputs "0" signals S35a to S35c. When the phase difference between the preamble signal and the reference clock signal CK1 is 1/6 cycle or more and 2/6 cycle or less (Phase P1 in FIG. 38), the first comparator 138a sets the signal S35a of "1". The second and third comparators 138b and 138c output "0" signals S35b and S35c.

[0313] The decoder 139 generates a phase selection signal S36 based on the output signals S35a to S35c of the first to third comparators 138a to 138c and the sign bit f1a constituting the output signal S33a of the fourth register 136a. .. The sign bit indicates whether the phase of the preamble signal is ahead or behind the phase of the reference clock signal CK1. Therefore, the decoder 139 responds to the sign bit f1a of "0" and selects the second to fourth clock signals CK2 to CK4 whose phase is ahead of the first clock signal CK1 based on the output signals S35a to S35c. To generate the phase selection signal S36 for. The decoder 139 responds to the sign bit of "1" and selects the sixth to fourth clock signals CK6 to CK4 whose phase is behind the first clock signal CK1 based on the output signals S35a to S35c. Generates the selection signal S36.

[0314] For example, when the output signals S35a to S35c are all "0", the decoder 139 generates a phase selection signal S36 to select the first clock signal CK1. When the output signals S35a to S35c are "100", the decoder 139 has the second clock signal CK2 corresponding to the sign bit of "0" and the sixth clock signal CK6 corresponding to the sign bit of "1". The phase selection signal S36 is generated to select.

[0315] The decoder 139 outputs the generated phase selection signal S36 to the sixth register 140. The zero phase selection signal SL0 is input from the control circuit 133 to the sixth register 140. The sixth register 140 latches the phase selection signal S36 output by the decoder 139 in response to the rising edge of the zero phase selection signal SL0, and outputs the latch signal as the selection signal S27 to the selection circuit 128 of FIG. 33. The selection circuit 128 selects one of the first to sixth clock signals CK1 to CK6 output from the TR-PLL124 based on the selection signal S27, and divides the selected clock signal as the reference clock signal SCK. Output to the peripheral device 129. The frequency divider 129 outputs a clock signal CKa obtained by dividing the frequency of the reference clock signal SCK by 1/2 to the ADC 122.

As shown in FIG. 39, the restart circuit 123 configured as described above obtains the cross-correlation function value for one cycle of the 6T pattern preamble signal from the points sampled based on the reference clock signal SCK. , Initial phase pulling is performed to roughly match the phase of the reference clock signal SCK with respect to the phase of the preamble signal based on the cross-correlation function value.

[0317] The TR-PLL124 inputs the output signal S26 of the ADC 122. Then, the TR-PLL124 pulls in the phase of the reference clock signal SCK on which the initial phase pull is performed with respect to the phase of the preamble signal, and matches the phase of the reference clock signal SCK with the phase of the preamble signal. As a result, the time required for phase pull-in is shorter than in the conventional case.

[0318] As shown in FIG. 40, the ADC 122 of FIG. 33 includes a main ADC 141 and a plurality (two in this embodiment) of auxiliary ADCs 142a and 142b. The main ADC 141 can convert the output signal S3 of the adder 13 into a digital signal, and has an input range (signal input range) centered on 0V. A clock signal CKa obtained by dividing the reference clock signal SCK by 1/2 is input to the main ADC 141. The main ADC 141 sequentially converts the output signal S3 into a 6-bit digital signal based on the rising edge of the frequency-divided clock signal CKa, and outputs the digital signal to the arithmetic circuit 126 and TR-PLL124 of FIG. 33.

[0319] The auxiliary ADCs 142a and 142b have an input range narrower than that of the main ADC 141, centered on a predetermined reference voltage set for each of the auxiliary ADCs 142a and 142b. An inverted clock signal XCKa forming a complementary signal with the clock signal CKa is input to each of the auxiliary ADCs 142a and 142b. Each of the auxiliary ADCs 142a and 142b converts the output signal S3 into a 3-bit digital signal based on the rising edge of the inverted clock signal, and outputs the digital signal to the arithmetic circuit 126 and TR-PLL124 of FIG. 33.

As shown in FIG. 41, the divided clock signal CKa and the inverted clock signal XCKa, which are complementary signals, alternately appear at rising edges of the reference clock signal SCK. Further, the time between the rising edge of the divided clock signal CKa and that of the inverted clock signal XCKa is the same as the time between the rising edge of the reference clock signal SCK. Therefore, the main ADC 141 and the auxiliary ADCs 142a and 142b alternately perform AD conversion in synchronization with the rising edge of the reference clock signal SCK.

[0321] The reference voltages of the auxiliary ADCs 142a and 142b are set to different voltages. As shown in FIG. 43, the first auxiliary ADC 142a is centered on the first reference voltage + Ref, and the second auxiliary ADC 142b is centered on the second reference voltage -Ref.

[0322] Each reference voltage + Ref, -Ref corresponds to the voltage at the sampling point of the preamble signal. That is, as shown in FIG. 42, when the preamble signal is sampled by the reference clock signal SCK, the voltage at the sampling point is a voltage near the voltages RefH, RefL, -RefL, and -RefH. The TR-PLL124 in FIG. 33 captures the transition point at which the preamble signal transitions from positive to negative and negative to positive, and draws the phases of the clock signals CK1 to CK6 into the phase of the preamble signal based on this transition point. It is configured as follows.

[0323] Therefore, TR-PLL124 requires sampling points before and after the transition point. Therefore, as shown in FIG. 42, the voltage at the required sampling point, that is, the voltage RefL is set as the first reference voltage, and the voltage-RefL is set as the second reference voltage. As a result, the TR-PLL124 inputs the voltage value of the same point as the sampling point based on the required reference clock signal SCK even when the main ADC 141 and the auxiliary ADCs 142a and 142b are operated alternately. As a result, the TR-PLL124 can perform phase pulling in the same manner as when sampling with the reference clock signal SCK.

[0324] Generally, when the sampling frequency is lowered (the period is lengthened), the number of transition points is reduced, so that the phase comparison gain in the TR-PLL is lowered. This makes it difficult to pull in the phase and prolongs the time required for pulling in the phase to match the phase of the reference clock signal SCK with the phase of the preamble signal.

[0325] On the other hand, in the present embodiment, the auxiliary ADCs 142a and 142b are provided, and the main ADCs 141 and the auxiliary ADCs 142a and 142b are operated alternately to suppress the decrease in the phase comparison gain in the TR-PLL124. This prevents the time required for phase pull-in from becoming long.

[0326] In the ADC 122 configured as described above, since the main ADC 141 operates on the clock signal CKa having a frequency slower (1/2) than the reference clock signal SCK, it operates on the reference clock signal SCK as compared with the case where it operates on the reference clock signal SCK. Power consumption is halved. Since the number of bits of the output signal of the auxiliary ADCs 142a and 142b is smaller than that of the main ADC141, the circuit scale is smaller than that of the main ADC141, and the auxiliary ADCs 142a and 142b operate with the inverted clock signal XCKa having the same frequency as the main ADC. As a result, the total power consumption of each of the auxiliary ADCs 142a and 142b is less than that of the main ADC 141. Therefore, the power consumption of the ADC 122 is smaller than that of operating the main ADC 141 with the reference clock signal SCK.

[0327] Since the auxiliary ADCs 142a and 142b have a smaller number of bits of the output signal than the main ADC141, the circuit scale is sufficiently small. As a result, it is possible to suppress an increase in the chip area of the semiconductor device forming the ADC 122.

[0328] As described above, according to the present embodiment, the following effects are obtained. (1) The zero-phase restart circuit 123 obtains a cross-correlation function value from a reference signal having a slow phase and a reference signal having a fast phase with respect to the output signal S26 of the AD converter 122, and the phase difference is based on the value. I tried to find out. As a result, the time required to obtain the phase difference is shortened, the synchronization can be established quickly, and the read operation can be speeded up.

(2) The ADC 122 is composed of the main ADC 141 and a plurality of auxiliary ADCs 142a and 142b, and the main ADC 141 and the auxiliary ADC ADCs 142a and 142b are alternately operated by the clock signals CKa and XCKa obtained by dividing the reference clock signal SCK. I made it. As a result, the power consumption of the ADC 122 can be reduced.

(3) By reducing the input range of the auxiliary ADCs 142a and 142b, the area of the auxiliary ADCs 142a and 142b can be made smaller than that of the main ADC 141. As a result, it is possible to suppress an increase in the chip area of the semiconductor device forming the ADC 122.

[0331] In the above embodiment, the following changes may be made. Instead of the selection circuit 128 of the restart circuit 123 of the present embodiment, the clock switching circuit 115 and the VCO 116 of the seventh embodiment may be provided. In that case, TR-PLL104 of the seventh embodiment is used instead of TR-PLL124.

(Ninth Embodiment) Hereinafter, a ninth embodiment embodying the present invention will be described with reference to FIGS. 44 and 45. For convenience of explanation, the same components as those in the prior art shown in FIG. 54 are designated by the same reference numerals, and the description thereof will be partially omitted.

FIG. 44 shows a block circuit diagram of the determination feedback equalizer (DFE) 151 of this embodiment. The DFE 151 includes a pre-filter 12, an adder 13, a determination device 14, a shift register 15, a feedback filter (FB filter) 152, an abnormality detection circuit 153, a selection circuit 154, a transition detection circuit 155, and an approximation circuit 156.

[0334] The output signal of VGA47 of FIG. 2 is input as signal S41 to the pre-filter 12 of DFE151. The DFE151 operates so as to output a reproduction signal from which the intersymbol interference of the input signal S41 is removed.

[0335] The abnormality detection circuit 153 has a function of detecting whether the input signal S41 of the DFE 151 is normal or abnormal. In addition, the abnormality detection circuit 153 is a thermal asperity (TA (Thermal Asperity): read signal RD.<u style="single">Abnormal</u>It has a function to detect (phenomenon that induces). The abnormality detection circuit 153 outputs an L-level detection signal S42 when the input signal S41 is normal. When the abnormality detection circuit 153 detects an abnormality in the input signal, it outputs a predetermined level (H level) detection signal S42 to the selection circuit 154.

To elaborate on the anomaly detection method, the level of the input signal S41 changes corresponding to the transmission code rules (RLL (1,7) code) used for coding in the encoder 44 of FIG. To do. That is, the input signal S41 of a certain level or more (or a certain level or less) continues for a predetermined period applicable to the transmission code rule. Therefore, when the input signal S41 of a certain level or more (a certain level or less) is input beyond a predetermined period, the input signal S41 within the predetermined period contains an error.

Therefore, the abnormality detection circuit 153 measures the period during which the input signal S41 of a certain level or more (a certain level or less) is input. When the level of the input signal S41 changes from a certain level or more to a certain level or less (or from a certain level or less to a certain level or more) within the predetermined period, the abnormality detection circuit 153 detects that the input signal is normal. Then, the abnormality detection circuit 153 outputs the L level detection signal S42 based on the detection result.

On the other hand, when the input signal S41 of a certain level or more (a certain level or less) is input beyond the predetermined period, the abnormality detection circuit 153 detects that the input signal S41 is abnormal. Then, the abnormality detection circuit 153 outputs an H level detection signal S42 based on the detection result.

[0339] Based on the detection result, the abnormality detection circuit 153 outputs an H level detection signal S42 when the input signal S41 is normal, and an L level detection signal S42 when the input signal S41 is abnormal. It may be configured to output.

[0340] The detection signal S42 output from the abnormality detection circuit 153 is input to the selection circuit 154. Further, the external detection signal S43 and the selection signal S44 are input to the selection circuit 154. The external detection signal S43 is generated by an abnormality detection circuit (not shown) outside the DFE151. Similar to the abnormality detection circuit 153, the abnormality detection circuit detects whether the input signal S41 of the DFE 151, that is, the output signal of the VGA 47 in FIG. 2 is normal or abnormal, and based on the detection result, the abnormality detection circuit detects the DFE 151. The external detection signal S43 is output to.

[0341] The selection signal S44 is input from HDC39 in FIG. The HDC39 outputs the selection signal S44 to the selection circuit 154 based on the settings of the hard disk device. The selection circuit 154 selects either the detection signal S42 or the external detection signal S43 based on the input selection signal S44. Then, the selection circuit 154 outputs the selected signal as the hold signal S45 to the FB filter 152.

[0342] The configuration may be such that the external detection signal S43 is not input. In that case, the selection circuit 154 may be omitted, and the abnormality detection circuit 153 may be configured to output the detection result as the hold signal S45 to the FB filter 152.

[0343] A plurality of bits of signals stored in the shift register 15 are input to the FB filter 152. The FB filter 152 calculates the feedback amount based on the data input from the shift register 15 while the hold signal S45 is at the L level. Then, the FB filter 152 outputs the signal S46 of the feedback amount (level of voltage value, current amount, etc.) according to the calculation result to the adder 13.

[0344] The FB filter 152 outputs a constant feedback amount, that is, a predetermined level signal S46 to the adder 13 in response to the H level hold signal S45. The level of the signal S46 at this time is set in advance to, for example, the average value of the feedback amount calculated based on the data stored in the shift register 15 when the input signal S41 is normal. This average value is smaller than the maximum value (or larger than the minimum value) of the output signal of the FB filter 152. Therefore, when the input signal S41 is abnormal, the feedback loop (FB loop) feeds back a constant feedback amount (feedback (FB) response) instead of the feedback amount calculated based on the abnormal signal.

The hold signal S45 and the determination signal S4 output from the determination device 14 are input to the transition detection circuit 155. The transition detection circuit 155 detects a specific transition point after the H level hold signal S45 is input, and outputs the second detection signal S47 to the approximation circuit 156.

[0346] Specifically, when the determination signal S4 detects a specific transition point at which data transitions, such as 0 1 or 1 0, the transition detection circuit 155 becomes the H level for a predetermined period. The second detection signal 47 of the pulse is output to the approximation circuit 156. The pulse width of the second detection signal 47 corresponds to the time (number of clocks) required for the normal determination signal S4 output from the determination device 14 to be stored in the register of the final stage constituting the shift register 15. ing.

The approximation circuit 156 includes a register 157 having a plurality of storage areas. The determination signal S4 output from the determination device 14 is input to the approximation circuit 156. The approximation circuit 156 sequentially stores the determination signal S4 in the register 157 in response to the H level second detection signal S47. The approximation circuit 156 calculates an approximate feedback amount based on the data stored in the register 157. Then, the approximation circuit 156 outputs the calculated approximate feedback amount signal S48 to the FB filter 152.

[0348] The detection signal S47 is input to the FB filter 152. The FB filter 152 outputs the output signal S48 of the approximation circuit 156 to the adder 13 based on the H level second detection signal S47. Therefore, while the second detection signal S47 is at the H level, the feedback signal S46 corresponding to the approximate feedback amount calculated by the approximate circuit 156 is fed back to the adder 13.

[0349] The FB filter 152 outputs the feedback signal S46 of the feedback amount calculated based on the data input from the shift register 15 to the adder 13 based on the second detection signal S47 of the L level.

Next, the operation of the DFE 151 configured as described above will be described with reference to FIG. 45. When the input signal S41 becomes abnormal, the abnormality detection circuit 153 detects the abnormality signal and outputs the H level first detection signal S42, and the selection circuit 154 holds the first detection signal S42 based on the selection signal S44. Output to FB filter 152 as S45. The FB filter 152 feeds back a constant feedback amount based on the hold signal S45.

At this time, the amount of feedback input to the adder 13 is smaller than the amount of feedback based on the abnormal signal. Therefore, the output signal of the adder 13 has a value closer to the output signal S46 when the feedback amount based on the normal input signal S41 is fed back, as compared with the case where the feedback amount based on the abnormal signal is fed back.

[0352] As a result, the FB loop is less likely to diverge than in the case of feeding back the FB response based on the abnormal signal. That is, the DFE 151 of the present embodiment suppresses the divergence of the FB loop due to the abnormality of the input signal S41.

Further, feeding back a constant feedback amount is the time until the FB loop operates normally by the FB response calculated based on the normal input signal when the input signal S41 becomes normal. To shorten. That is, when the feedback amount is calculated based on the abnormal signal, the FB response becomes the maximum value (or minimum value) of the output signal of the FB filter 152. The FB response of this maximum value (or minimum value) affects the output signal S46, which is the calculation result of the FB filter 152 for a long time after the input signal S41 becomes normal. Due to this effect, DFE151 may not return to normal for a long time.

However, the time during which the predetermined amount of FB response affects the output signal of the FB filter 152 is shorter than that of the FB response having the maximum value (or minimum value). That is, the FB loop becomes a normal operation in a short time. As a result, DFE151 returns to normal in a short time.

Next, when the input signal S41 becomes normal, the abnormality detection circuit 153 outputs an L-level first detection signal S42. The transition detection circuit 155 detects a specific transition point of the judgment signal S4 output from the judgment device 14 based on the normal input signal S41, and approximates the second detection signal S47 having a predetermined pulse width to the approximation circuit 156 and the FB filter 152. Output to. The approximation circuit 156 sequentially stores the determination signal S4 output from the determination device 14 in the register 157. Then, the approximate circuit 156 calculates the approximate feedback amount based on the plurality of bits of data stored in the register 157, and outputs the signal S48 of the approximate feedback amount to the FB filter 152.

Therefore, the approximate feedback amount is fed back to the FB loop. The value of the feedback signal at this time is an approximate value based on the normal determination signal S4. Therefore, the FB response at this time is closer to the normal feedback amount than the FB response (constant feedback amount) when the abnormal signal is input. As a result, the FB loop returns to normal in a shorter time than when returning a certain amount.

[0357] As described above, according to the present embodiment, the following effects are obtained. (1) An abnormality abnormality detection circuit 153 that detects an abnormality in the input signal of the pre-filter 12 is provided, and the feedback of the feedback filter is stopped based on the detection result. As a result, the determination result based on the abnormal signal is not returned, and divergence can be prevented.

(2) The approximate value of the feedback amount was calculated by the approximate circuit 156, and the feedback signal of the approximate feedback amount was output by the FB filter 152. As a result, the FB loop can be returned to normal in a shorter time than when returning a certain amount.

(10th Embodiment) Hereinafter, a tenth embodiment embodying the present invention will be described with reference to FIGS. 46 and 47. For convenience of explanation, the same reference numerals will be given to the same configurations as those of the first and ninth embodiments, and some drawings and explanations will be omitted.

[0360] FIG. 46 shows a partial block circuit diagram of the signal processing circuit of the present embodiment. The signal processing circuit includes an error calculation circuit 158. The error calculation circuit 158 calculates the error between the input signal S3 and the output signal S4 of the determination device 14, and outputs the calculation result as an output signal to the AGC circuits 47a and TR-PLL49. The AGC circuit 47a outputs a control signal based on the output signal of the error calculation circuit 158 to the VGA 47. The VGA47 amplifies the read signal RD with a gain based on the control signal, and outputs the amplified signal as the signal S41. The TR-PLL49 pulls in the phase of the reference clock signal SCK based on the output signal of the error calculation circuit 158.

[0361] Further, the signal processing circuit includes an abnormality detection circuit 153a. The output signal S41 of VGA47 is input to the abnormality detection circuit 153a. The abnormality detection circuit 153a has a function of detecting whether the input signal S41 is normal or abnormal. Further, the abnormality detection circuit 153a has a function of detecting thermal asperity.

As shown in FIG. 47, the abnormality detection circuit 153a sets a detection flag based on the detection of the thermal asperity and the input signal S43 when there is an abnormality in the input signal S41 based on the detection result. Then, the abnormality detection circuit 153a outputs the H level hold signals S45, AH, and PH to the feedback filter (FB filter) 152, the AGC circuit 47a, and the TR-PLL49.

[0363] The FB filter 152 stops the output of the feedback signal S46 based on the hold signal S45. This can prevent the feedback loop from diverging by controlling the feedback loop to stop the feedback when the input signal is abnormal.

[0364] The AGC circuit 47a stops the output of the control signal based on the H level hold signal AH. At this time, the AGC circuit 47a amplifies the read-read signal RD by setting the gain to a preset constant value. As a result, the abnormality detection circuit 153a prevents the input signal S41 from being abnormal due to the thermal asperity. That is, the abnormality detection circuit 153a can prevent the control loop composed of the VGA 47 and the AGC 47a from diverging.

[0365] The TR-PLL49 stops control based on the H level hold signal PH. That is, the TR-PLL49 holds the frequency and phase of the reference clock signal SCK. As a result, the abnormality detection circuit 153a can prevent the PLL circuit 49 from diverging.

[0366] Based on the first pulse detection at the time of recovery, the transition detection circuit 155 of FIG. 44 outputs the L level output signal S47 after a lapse of a predetermined period. As a result, a feedback response is calculated based on the normal signal S41, and the response is fed back. The abnormality detection circuit 153a outputs L-level hold signals AH and PH after a predetermined period of time has elapsed from the fall of the signal S47. The AGC circuit 47a outputs a control signal based on the L-level hold signal AH. The TR-PLL49 controls the reference clock signal SCK based on the L-level hold signal PH.

[0367] In the above embodiment, the following changes may be made. -In the ninth embodiment, the DFE 151 is configured to include the abnormality detection circuit 153, but it may be configured not to include the abnormality detection circuit 153 as in the tenth embodiment. In that case, the abnormality detection circuit 153 may be included in the signal processing circuit, or the hard disk device 31 in FIG. 1 may be provided with the abnormality detection circuit independently, and the abnormality detection circuit 153 may be included in the MPU37, HDC39, or the like.

(11th Embodiment) Hereinafter, the eleventh embodiment embodying the present invention will be described with reference to FIGS. 48 and 49.

[0369] For convenience of explanation, the same components as those in the first embodiment of FIG. 3 are designated by the same reference numerals, and the description thereof will be partially omitted. FIG. 48 shows a partial block circuit diagram of the signal processing circuit of the present embodiment. Since other parts of the signal processing circuit not shown in FIG. 48 are the same as those in the first embodiment, refer to FIG.

[0370] The signal processing circuit 161 includes a controller 162. The controller 162 includes a register 163 and a timing control circuit 164. Detection data of known values (for example, DDh) is stored in register 163 from MPU37 in FIG. The controller 162 outputs the detection data stored in the register 163 to the encoder 165 and the feedback filter (FB filter) 167 of the judgment feedback equalizer (DFE) 166.

[0371] A predetermined timing value is stored in the timing control circuit 164 from the MPU 37 or the like. A clock signal SCK for timing read / write to the magnetic disk 33 of FIG. 1 is input to the timing control circuit 164.

[0372] The timing control circuit 164 outputs an interrupt signal S51 to the encoder 165 and the FB filter 167 at regular intervals based on the timing value based on the clock signal SCK.

The controller 162 has a function of controlling the encoder 165 at the time of data writing to write data to the magnetic disk 33 of FIG. The controller 162 has a function of controlling the judgment feedback equalizer (DFE) 166 at the time of data reading for reading the information of the magnetic disk 33. These functions will be described corresponding to data write and data read.

[At the time of data writing] The controller 162 has a function of detecting the output timing of the sink byte indicating the start of data from the encoder 165. The controller 162 operates the timing control circuit 164 in response to the output timing detection of the sink byte. As a result, the timing control circuit 164 outputs an interrupt signal S51 to the encoder 165 at regular intervals based on the timing value after the sink bite is output from the encoder 165.

[0375] The encoder 165 responds to the interrupt signal S51 input at regular intervals, temporarily stops the output of data, and outputs the detection data input from the register 163. As a result, as shown in FIG. 49A, the controller 162 performs interrupt processing for interrupting the detection data stored in the register 163 for each predetermined number of bits of data.

[During data read] A sink byte detection signal SB is input to the controller 162 from the control data detection circuit 53 of FIG. The controller 162 operates the timing control circuit 164 in response to the sink bite detection signal SB. The MPU 37 in FIG. 1 detects the beginning of data by the sink byte detection signal SB and establishes synchronization for processing in synchronization with the data.

As a result, as shown in FIG. 49 (b), the timing control circuit 164 sets the interrupt signal S51 to the FB filter 167 at regular intervals based on the timing value after the sink byte is detected, that is, after the synchronization is established. Output to. Further, the controller 162 outputs the detection data stored in the register 163 to the FB filter 167 at the same time as the interrupt signal S51.

[0378] The FB filter 167 responds to the interrupt signal S51 input at regular intervals, and calculates the feedback amount based on the detection data input from the register 163. Then, the FB filter 167 outputs the calculated feedback amount signal to the adder 13. As a result, the controller 162 performs a preset operation of presetting the FB loop by the FB response based on the detection data stored in the register 163 at regular intervals.

[0379] The detection data read from the magnetic disk 33 is input to the DFE 166 at the same timing as the interrupt signal S51. The FB filter 167 of the DFE166 calculates the feedback response (FB response) of the feedback loop (FB loop) based on the detection data. Therefore, if an error occurs in the detected data or the data read before that, the error is propagated and the feedback loop (FB loop) of the DFE166 diverges.

[0380] However, known detection data is input to the FB filter 167 from the controller 162 at the same timing as the interrupt signal S51. Since this detection data is input from the controller 162, it is not affected by the state of the magnetic disk 33 or the head device 34. That is, there is no error in the detection data input from the controller 162.

[0381] Therefore, the FB filter 167 of the DFE166 calculates the FB response based on this error-free detection data. This prevents erroneous propagation to the next determination data. As a result, the controller 162 prevents the FB loop of the DFE 166 from diverging.

[0382] As described above, according to the present embodiment, the following effects are obtained. (1) The controller 162 writes the known detection data to the FB filter 167 of the DFE166 at predetermined intervals at the time of data reading to preset the FB loop. As a result, it is possible to prevent the FB loop from diverging after the synchronization is established.

(Twelfth Embodiment) Hereinafter, a twelfth embodiment embodying the present invention will be described with reference to FIGS. 50 and 51.

[0384] For convenience of explanation, the same components as those in the eleventh embodiment are designated by the same reference numerals, and the description thereof will be partially omitted. FIG. 50 shows a partial block circuit diagram of the signal processing circuit of the present embodiment. Since other parts of the signal processing circuit not shown in FIG. 50 are the same as those in the first embodiment as in the eleventh embodiment, refer to FIG.

[0385] The signal processing circuit 171 includes a controller 172. The controller 172 includes a timing control circuit 174 and a register 173. A predetermined timing value is stored in the timing control circuit 174 from the MPU 37 or the like. A clock signal SCK for timing read / write to the magnetic disk 33 of FIG. 1 is input to the timing control circuit 174.

Based on the clock signal SCK, the timing control circuit 174 outputs an interrupt signal S51 to the encoder 175 and the feedback filter (FB filter) 167 of the determination feedback equalizer 166 at regular intervals based on the timing value. ..

[0387] The encoder 175 outputs the data output at that time to the controller 172 in response to the interrupt signal S51. Register 173 has a capacity that can store a plurality of data. The controller 172 sequentially stores the data input from the encoder 175 in the register 173. Further, the controller 172 outputs the detection data stored in the register 173 to the FB filter 167.

The controller 172 has a function of controlling the encoder 175 at the time of data writing to write data to the magnetic disk 33 of FIG. The controller 172 has a function of controlling the judgment feedback equalizer (DFE) 166 at the time of data reading for reading the information of the magnetic disk 33. These functions will be described corresponding to data write and data read.

[At the time of data writing] The controller 172 has a function of detecting the output timing of the sink byte indicating the start of data from the encoder 175. The controller 172 operates the timing control circuit 174 in response to the output timing detection of the sink byte. As a result, the timing control circuit 174 outputs an interrupt signal S51 to the encoder 175 at regular intervals based on the timing value after the sink bite is output from the encoder 175.

[0390] The encoder 175 responds to the interrupt signal S51 input at regular intervals, and outputs the data for writing to be output at each time to the controller 172. As a result, as shown in FIG. 51 (a), the controller 172 performs interrupt processing for sequentially storing the data output at a predetermined timing in the register 173.

[At the time of data read] The sink byte detection signal SB is input to the controller 172 from the control data detection circuit 53 of FIG. The controller 172 operates the timing control circuit 174 in response to the sink bite detection signal SB. As a result, as shown in FIG. 51 (b), the timing control circuit 174 outputs an interrupt signal S51 to the FB filter 167 at regular intervals based on the timing value after the sink byte is detected. Further, the controller 172 sequentially outputs the data stored in the register 173 to the FB filter 167 as detection data.

[0392] The FB filter 167 responds to the interrupt signal S51 input at regular intervals, and calculates the feedback amount based on the detection data sequentially input from the register 173. Then, the FB filter 167 outputs the calculated feedback amount signal to the adder 13. As a result, the controller 172 performs a preset operation of presetting the FB loop by the FB response based on the detection data stored in the register 173 at regular intervals.

[0393] The detection data read from the magnetic disk 33 is input to the DFE166 at the same timing as the interrupt signal S51. The FB filter 167 of the DFE166 calculates the feedback response (FB response) of the feedback loop (FB loop) based on the detection data. Therefore, if an error occurs in the detected data or the data read before that, the error is propagated and the feedback loop (FB loop) of the DFE166 diverges.

[0394] However, known detection data is input from the controller 172 to the FB filter 167 at the same timing as the interrupt signal S51. Since this detection data is input from the controller 172, it is not affected by the state of the magnetic disk 33 or the head device 34 in FIG. That is, there is no error in the detection data input from the controller 172.

Therefore, the FB filter 167 of the DFE166 calculates the FB response based on this error-free detection data. This prevents erroneous propagation to the next determination data. As a result, the controller 172 prevents the FB loop of the DFE166 from diverging.

[0396] The present embodiment is particularly effective when performing a write / read test on the magnetic disk 33. That is, when writing general data to the magnetic disk 33, the data has an arbitrary value. Therefore, a huge amount of registers are required to store the data to be written in all the sectors of the magnetic disk 33 at a predetermined timing. This increases the scale (chip size) of the signal processing circuit 171.

However, the write / read test checks whether the data written on the magnetic disk 33 is read normally. Therefore, the write operation and the read operation are performed on one or a plurality of (about 2 to 10) sectors. Therefore, the amount of data stored in the register 173 is small. As a result, the scale of the signal processing circuit is not increased without requiring the register 173 having a large capacity.

[0398] As described above, according to the present embodiment, the following effects are obtained. (1) It has the same effect as that of the eleventh embodiment. (2) Further, in the present embodiment, the data to be written to the magnetic disk 33 is stored in the register 173. The FB loop of DEF166 is preset at the time of data read based on the data stored in the register 173. Therefore, since the process of storing the detection data in the register 173 in advance is not required, the process of HDC39 in FIG. 1 is simplified and the terminal for writing the detection data is not required. Therefore, the signal processing circuit 171 It is possible to reduce the chip size and simplify the circuit configuration.

(13th Embodiment) Hereinafter, a thirteenth embodiment embodying the present invention will be described with reference to FIG. 52. For convenience of explanation, the same components as those of the conventional example of FIG. 54 are designated by the same reference numerals, and the description thereof will be partially omitted.

FIG. 52 shows a block diagram of the determination feedback equalizer (DFE) of this embodiment. The DFE181 includes a pre-filter 12, an adder 13, a judgment device 14, a shift register 15, a feedback filter (hereinafter referred to as an FB filter) 182, and a feedback response rewriting circuit 183. The FB filter 182 includes an address translation decoder 184, a memory (RAM) 185, and a DAC 186.

[0401] The output signal of VGA47 of FIG. 2 is input to the front filter 12. The pre-filter 12 filters the input signal and generates a waveform signal that maximizes the S / N ratio. As a result, the pre-filter 12 outputs the filtered signal to the adder 13. The adder 13 adds up the output signal of the prefix filter 12 and the output signal of the FB filter 182, and outputs the calculated signal to the determination device 14.

[0402] The determination device 14 compares the output voltage of the adder 13 with a preset reference voltage, and outputs a determination signal S1 of "1" or "0" to the shift register 15 based on the comparison result. .. As a result, the determination device 14 converts the output signal of the adder 13 into a digital signal.

[0403] The shift register 15 includes a number of registers 15a (8 in FIG. 52) corresponding to the number of taps of the FB filter 182. The shift register 15 samples the determination signal output from the determination device 14 in synchronization with the clock signal, and sequentially stores the sampling data in each register 15a. As a result, the shift register 15 stores the sampled past data. The shift register 15 outputs the stored past data to the FB filter 182.

The FB filter 182 includes an address translation decoder 184, a memory (RAM) 185, and a digital-to-analog converter (DAC) 186. The conversion decoder 184 decodes the data input from the shift register 15 and outputs the result to the RAM 185 as the read address RAD.

[0405] Since the RAM 185 is the same as the configuration of the conventional example shown in FIG. 54, the configuration will be described in detail with reference to FIG. 54. That is, the RAM 185 has a plurality of areas, and each area stores a feedback response corresponding to a pattern of 8-bit data output from the shift register 15. These feedback responses are the calculation results obtained by pre-calculating the data stored in the shift register 15 and the predetermined filter coefficients ω7 to ω0.

[0406] The RAM 185 selects one area by the read address RAD. RAM185 outputs the data read from the selected area to DAC186. The DAC 186 converts the data input from the RAM 185 into an analog signal, and outputs the analog signal to the adder 13 as a feedback response. Therefore, the adder 13, the determination device 14, the shift register 15, the conversion decoder 184, the RAM 185, and the DAC 186 form a feedback loop (FB loop).

The rewriting circuit 183 includes a coefficient register 187, a programmable filter arithmetic unit (hereinafter referred to as an arithmetic unit) 188, an external interface circuit (hereinafter referred to as an I / F circuit) 189, and an input pattern generation state machine (hereinafter referred to as a state machine). ) Includes 190.

[0408] The coefficient register 187 is a readable and rewritable memory, and is composed of, for example, DRAM. The coefficient register 187 may be configured by SRAM, EEPOM, or the like. The coefficient register 187 has a plurality of regions 187a. Filter coefficients ω0, ω1, ω2, ... Are stored in each region 187a. Each filter coefficient ω0, ω1, ω2, ... Is rewritten by MPU37 in FIG. Based on the servo information read from the magnetic disk 33 in FIG. 2, the MPU37 sets the filter coefficients ω0, ω1, ω2, ... Stored in coefficient register 187.

[0409] Each filter coefficient ω0, ω1, ω2, ... Is read by the arithmetic unit 188. Information on the zone to be read from the MPU 37 in FIG. 2 is input to the arithmetic unit 188 via the I / F circuit 189. The zone information includes the position information of the zone and the characteristics (transmission line characteristics) of the read signal RD that reads data from the sectors included in the zone.

Further, the state signal S61 is input from the state machine 190 to the arithmetic unit 188. The state machine 190 outputs a state signal S61 having a value corresponding to the pattern of data stored in the shift register 15 to the arithmetic unit 188.

[0411] The shift register 15 has eight registers 15a, and outputs the data stored in each register 15a to the FB filter 182. Therefore, the state machine 190 sequentially outputs the state signals S61 from "00000000" (all 0) to "11111111" (all 1) to the arithmetic unit 188.

[0412] The arithmetic unit 188 is configured to execute a rewriting process based on a preset sequence. The start trigger signal S62 is input to the arithmetic unit 188 from the MPU 37 in FIG. 2 via the I / F circuit 189.

[0413] The MPU 37 stores the filter coefficients ω0, ω1, ω2, ... Corresponding to the zone in which the head device 34 of FIG. 2 is located in the coefficient register 187 via the I / F circuit 189. After that, the MPU 37 outputs the start trigger signal S62 and the zone information to the arithmetic unit 188 via the I / F circuit 189.

[0414] The arithmetic unit 188 responds to the start trigger signal S62 and executes a rewriting process for rewriting the filter response of the RAM 185 according to a predetermined sequence.

[0415] Next, the rewriting process will be described in detail according to the sequence. First, the arithmetic unit 188 outputs the start signal S63 to the state machine 190. Further, the arithmetic unit 188 reads out each filter coefficient ω0, ω1, ω2, ... From the coefficient register 187.

[0416] The state machine 190 responds to the start signal S63 to generate all combinations of data stored in the shift register 15. The state machine 190 outputs the generated combination of state signals S61 to the arithmetic unit 188 and the address translation decoder 184.

Next, the arithmetic unit 188 calculates the filter response corresponding to the pattern of each state signal S61 based on each filter coefficient ω0, ω1, ω2, ..., Zone information, and the state signal S61. The arithmetic unit 188 outputs the calculated filter response to the RAM 185.

[0418] The address translation decoder 184 decodes the state signal S61 input from the state machine 190, and outputs the result as a write address WAD to the RAM 185. The RAM 185 stores the filter response output from the arithmetic unit 188 in the area selected based on the write address WAD.

[0419] As described above, the rewriting circuit 183 rewrites the filter response of the RAM 185. The time required for this rewriting process is shorter than the time required for directly rewriting the contents (filter response) of RAM185 from the external MPU37 (see Fig. 2).

That is, when the contents of the RAM 185 are directly rewritten, the MPU 37 outputs the write address WAD corresponding to one area of the RAM 185 and the filter response to be rewritten. Then, in order to rewrite all the contents of the RAM 185, the MPU 37 repeats the output of the write address WAD and the filter response for the number of data stored in the RAM 185. The amount of data output by the MPU 37 at this time is much larger than the amount of data output by the MPU 37 (filter coefficient and start trigger signal S62) in the rewriting process of the present embodiment.

[0421] However, this is a process for one zone. When the read operation spans a plurality of zones, the MPU37 needs to rewrite all the contents of the RAM 185 for each zone. Therefore, when the contents of the RAM 185 are directly rewritten by the MPU 37, the amount of output data of the MPU 37 becomes very large, and the time required for data transfer becomes long. Further, the output data imposes a heavy load on the external interface including the bus 41 in FIG. 1, which slows down the data transfer rate. Since these increase the time required for rewriting, they hinder the speeding up of the reading process.

On the other hand, in the present embodiment, since the MPU 37 only writes the filter coefficient and outputs the start trigger signal S62, the time required for data transfer is shorter than that in the case of direct rewriting. Further, when the amount of data is small, the load on the external interface is also small, so that the data transfer rate does not slow down. As a result, the time required for rewriting is shorter than in the case of direct rewriting, and the reading process can be speeded up.

[0423] As described above, according to the present embodiment, the following effects are obtained. (1) The rewriting circuit 183 rewrites the filter response of the RAM 185. The time required for this rewriting process is shorter than the time required for directly rewriting the contents (filter response) of the RAM 185 from the external MPU 37. As a result, the data transfer time in each zone can be shortened and the read time can be shortened.

[Effects of the Invention] As described in detail above, according to the invention of claim 1, according to the invention.<u style="single">Based on the monitoring result of the monitoring circuit that monitors the contents of the shift register, one of the plurality of signal levels generated by the first signal level generation circuit is selected and output to the judgment device as the reference level. 2 Select one of the multiple signal levels generated by the signal level generation circuit and the feedback amount based on the judgment result, convert the selected signal to an analog signal, and output it as a feedback signal.</u>Therefore, the sticking can be eliminated and the divergence of the feedback filter can be stopped.

[0427] Claim<u style="single">2</u>,<u style="single">3</u>According to the invention described in the above, since the register length of the shift register is made to correspond to the sign rule of the input signal without depending on the number of taps of the feedback filter, an increase in the configuration of the feedback filter is suppressed and divergence is prevented. be able to.

[0428] Claim<u style="single">4</u>According to the invention described in the above, the determination error locally existing in the shift register is corrected based on the code rule, and divergence can be prevented.

[Brief description of drawings] [Fig. 1] Schematic configuration diagram of a hard disk device.

FIG. 2 is a block circuit diagram of a signal processing circuit.

FIG. 3 is a block circuit diagram of the DFE of the first embodiment.

FIG. 4 is a timing diagram for explaining the operation of DFE.

FIG. 5 is a state transition diagram for explaining the operation of DFE.

FIG. 6 is a timing diagram for explaining the operation of DFE.

FIG. 7 is a state transition diagram for explaining the operation of DFE.

FIG. 8 is a timing diagram for explaining the operation of DFE.

FIG. 9 is a state transition diagram for explaining the operation of DFE.

FIG. 10 is a timing diagram for explaining the operation of DFE.

FIG. 11 is a block circuit diagram of the DFE of the second embodiment.

FIG. 12 is a block circuit diagram of a DFE according to a third embodiment.

FIG. 13 is a state transition diagram of a state machine.

FIG. 14 is a circuit diagram of a decoder.

FIG. 15 is an explanatory diagram of the operation of an error detection circuit.

FIG. 16 is an explanatory diagram of the operation of an error detection circuit.

FIG. 17 is an explanatory diagram of the operation of an error detection circuit.

FIG. 18 is an explanatory diagram of the operation of an error detection circuit.

FIG. 19 is a timing diagram for explaining the operation of DFE.

FIG. 20 is a timing diagram for explaining the operation of DFE.

FIG. 21 is a partial block circuit diagram of a signal processing circuit according to a fourth embodiment.

FIG. 22 is an explanatory diagram showing read signal data.

FIG. 23 is a partial block circuit diagram of a signal processing circuit according to a fifth embodiment.

FIG. 24 is a partial block circuit diagram of a signal processing circuit according to a sixth embodiment.

FIG. 25 is a partial block circuit diagram of another signal processing circuit.

FIG. 26 is a partial block circuit diagram of another signal processing circuit.

FIG. 27 is a partial block circuit diagram of a signal processing circuit according to a seventh embodiment.

FIG. 28 is a block circuit diagram of a zero phase restart circuit.

FIG. 29 is a waveform diagram showing clock signals having different phases.

FIG. 30 is a waveform diagram showing the operation of a zero-phase restart circuit.

FIG. 31 is a timing diagram illustrating an operation with respect to a read signal.

FIG. 32 is a timing diagram illustrating an operation with respect to a read signal.

FIG. 33 is a partial block circuit diagram of a signal processing circuit according to an eighth embodiment.

FIG. 34 is a block circuit diagram of a zero phase restart circuit.

FIG. 35 is a characteristic diagram showing a correlation function value for a phase shift of a clock signal.

FIG. 36 is an explanatory diagram showing the operation of an adder with respect to a control signal.

FIG. 37 is an explanatory diagram showing comparison levels for phases.

FIG. 38 is an explanatory diagram showing the operation of a comparator with respect to a phase and a comparison level.

FIG. 39 is a waveform diagram showing the operation of a zero-phase restart circuit.

FIG. 40 is a block circuit diagram of a DFE and ADC.

FIG. 41 is a waveform diagram of a clock signal.

FIG. 42 is a waveform diagram showing the operation of the ADC.

FIG. 43 is an explanatory diagram showing an operating range of a main ADC and a sub ADC.

FIG. 44 is a block circuit diagram of the DFE of the ninth embodiment.

45 is a waveform diagram showing the operation of the DFE of FIG. 44. FIG.

FIG. 46 is a block circuit diagram of a DFE according to a tenth embodiment.

47 is a waveform diagram showing the operation of the DFE of FIG. 46. FIG.

FIG. 48 is a partial block circuit diagram of the signal processing circuit of the eleventh embodiment.

FIGS. 49 (a) and 49 (b) are waveform diagrams showing the operation of a timing control circuit.

FIG. 50 is a partial block circuit diagram of a signal processing circuit according to a twelfth embodiment.

51 (a) and 51 (b) are waveform diagrams showing the operation of a timing control circuit.

FIG. 52 is a block circuit diagram of a DFE according to a thirteenth embodiment.

FIG. 53 is a block circuit diagram of a conventional DFE.

FIG. 54 is a block circuit diagram of a conventional DFE.

[Description of sign] 12 Prefix filter 13 Adder 14 Judgment device 48,70 Judgment feedback type equalizer 61 Shift register 65,71 Feedback filter 67,73 Divergence monitoring circuit 68 Selection circuit 69 Signal level generation circuit 84 As a PLL circuit TR-PLL85 Digital arithmetic circuit 103,123 Zero phase restart circuit 162,172 Controller 183 Rewriting circuit Ref Reference voltage Ref1 to Ref3 1st to 3rd reference voltage as signal level Off1 to Off3 1st to 3rd offset voltage SEL as signal level Selection signal as a monitoring result