A/d converter

The present invention generally relates to an AD converter that converts an analog signal into a digital signal, and more particularly to a sequential comparison type AD converter that converts an analog signal into a digital signal by a sequential comparison operation.

[Conventional Technology] The successive approximation type AD converter is realized by a relatively simple circuit configuration, has high consistency with a CMOS process, can be manufactured at a relatively low cost, and achieves a relatively high conversion time. Can be done. Among the sequential comparison type AD converters, the double stage type can realize a high resolution AD converter with a small mounting area.

[0002] The double-stage sequential comparison type AD converter has a main DAC (DA converter) for determining the maximum bit (MSB) side and a sub DAC (DA) for determining the minimum bit (LSB) side. It has a two-stage configuration with a converter). First, the high-order bit is determined by comparing the analog potential set by the main DAC (DA converter) with the input analog potential. The analog potential of the main DAC corresponding to the determined upper bit and the analog potential set by the sub DAC are added, and the lower bit is determined by comparing this sum with the input analog potential.

[0003] The DAC constituting the main DAC or the sub DAC can be realized by a resistance string or a capacitive array. Depending on which type is used for the main DAC and the secondary DAC, (1) capacitive array + capacitive array type (hereinafter CC type), (2) resistor string + capacitive array type (hereinafter RC type), (3) capacitive array There are four types: + resistance string type (hereinafter CR type) and (4) resistance string + resistance string type (hereinafter RR type).

[0004] FIG. 1 is a circuit diagram of a sequential comparison type AD converter using a conventional CR type double stage DAC.

[0005] The sequential comparison type AD converter of FIG. 1 has input terminals 10, nodes 20 to 23, nodes 40 to 44, switch circuit 100, switch circuit 200, switch circuit 201, and switch circuit 202 to which input potential Vin is applied. It includes a comparator 300, a sequential comparison control circuit 301, resistors R1 to R16, and capacitors C1 to C5. The operation of each switch circuit 100, 200, 201, 202, etc. is controlled by the sequential comparison control circuit 301.

[0006] R1 to R16 and the switch circuit 100 form a 4-bit sub DAC, and C1 to C5 and the switch circuit 200 (and 201, 202) form a 4-bit main DAC. C1 to C5 constituting the main DAC are weighted as 2Cx for C3, 4Cx for C4, and 8Cx for C5, where Cx is the capacitance value of C1 and C2, respectively. At the time of sampling, all of C1 to C5 are connected to the analog input terminal 10 (Vin) via the switch circuit 200, the node 21, and the switch circuit 201, and the input potential Vin is charged. At this time, the switch 202 is controlled so that the node 20 becomes GND. Sampling capacitances C3 to C5 are generally realized by connecting a certain unit capacitance Cx in parallel, for example, 2, 4, or 8 in order to ensure relative accuracy.

[0007] After the sampling is completed, the comparison operation is started, and the digital data corresponding to the input potential Vin is determined in order from the MSB. Specifically, the switch 202 is opened to put the node 20 in a floating state, and for example, the nodes 40 to 43 are connected to GND via the switches 200 and 201, and the node 44 is connected to the reference potential Vref (terminal 1). .. By this connection, the electric charge stored by the input potential Vin at the time of sampling is redistributed between the sampling capacities C1 to C5, and the potential of the node 20 becomes Vref / 2-Vin. The node 20 is connected to the input of the comparator 300, and whether the analog input potential Vin is larger or smaller than 1/2 of the reference potential Vref can be determined by the potential of the node 22 which is the output of the comparator 300.

[0008] In the above connection, the node 44 is connected to the reference potential Vref, and the other nodes 40 to 43 are connected to GND. That is, 8Cx of C5 was connected to the reference potential Vref, and the total of 8Cx of the remaining C1 to C4 was connected to GND. In general, if the number of unit capacitance Cx connected to the reference potential Vref is m and the number of remaining unit capacitance Cx connected to GND is 16-m, the potential V of node 20 is V = (m / 16) Vref. --Vin. For example, if node 41 is connected to Vref and the remaining nodes 40, 42, 43, and 44 are connected to GND, the potential of node 20 is Vref / 16-Vin because m is 1.

[0009] Therefore, by sequentially changing m, the potential of the node 20 can be changed in Vref / 16 increments, and the MSB side (upper 4 bits) of the digital data can be determined. ..

Next, let m'determined as described above be m', and connect m'unit capacitance Cx among C2 to C5 to the reference potential Vref, and the remaining 15 of C2 to C5. Connect -m'unit capacitance Cx to GND, and connect node 40 of one unit capacitance Cx of C1 to the sub DAC (R1 to R16 and switch circuit 100). By changing the potential of the node 40 in Vref / 16 steps by the sub DAC, the potential of the comparator input 20 can be changed in Vref / 256 steps. As a result, the LSB side (lower 4 bits) of the digital data can be determined, and a total of 8 bits of digital data can be obtained.

In the circuit of FIG. 1, by preparing 16 unit capacitances Cx and 16 unit resistors, AD conversion with 8-bit precision is realized. If you try to make a single-stage 8-bit precision DAC with only capacitance or resistance, you will need 256 unit capacitances or 256 unit resistors. By using a double-stage DAC as shown in the circuit in Fig. 1, the number of parts can be significantly reduced. Further, in the circuit of FIG. 1, the accuracy of the resistance of the 4-bit sub-DAC may be about 4-bit accuracy, and the resistance sub-DAC can be realized in a small area.

PROBLEM TO BE SOLVED: To increase the speed of an AD converter in recent years, and there is a strong demand for a speed-up of a sequential comparison type AD converter capable of configuring a circuit in a small area. ..

[0012] A first object of the present invention is to provide a circuit in which the processing time of AD conversion of a successive approximation type AD converter is shortened.

Further, in the conventional circuit shown in FIG. 1, when the potential of the node 23, which is the output of the sub DACs (R1 to R16 and the switch circuit 100), is set to Vref / 2, for example, switching becomes slow. There's a problem. This is because the switch circuit is generally realized by a CMOS transfer gate, so when the power supply voltage (Vref) is low, the ON resistance of both the MOSFET and the NMOS becomes high with respect to the source / drain voltage of Vref / 2, and the switch circuit This is because the delay time at 100 becomes large.

[0014] Therefore, a second object of the present invention is to provide a circuit in which the delay time in the resistance DAC does not increase even when the power supply voltage is low.

SOLUTION: The successive approximation type AD converter according to the present invention includes a capacitance array consisting of a plurality of capacitances for sampling an input potential and storing an electric charge.<u style="single">Only, the first reference potential and the second reference potential are selectively applied to the capacitive array.</u>An L-bit capacitance type DA converter, a first M-bit resistance type DA converter that generates a desired potential by potential division, and a second N-bit resistance type DA converter that generates a desired potential by potential division. The first signal path that adds the output of the first M-bit resistance type DA converter to the output of the L-bit capacitive DA converter by capacitive coupling, and the second N-bit resistance type DA converter. In a sequential comparison type AD converter having a resolution of (L + M + N) bits including a second signal path that adds the output to the output of the L-bit capacitance type DA converter by capacitance coupling, and a comparer. The L-bit capacitive DA converter corresponds to the most significant bit to the L-bit of all the bits to be AD converted, and the first M-bit resistance type DA converter corresponds to the M-bit following the L-bit. However, the second N-bit resistance type DA converter corresponds to the N bits following the M bit, and the first M-bit resistance type DA converter and the second N-bit resistance type DA converter are , The resistance sequence is shared for potential division, and the first M-bit resistance type DA converter and the second N-bit resistance type DA converter are a total number of 2 (M + N) powers. Including resistance element<u style="single">In the first M-bit resistance type DA converter and the second N-bit resistance type DA converter, the first reference potential and the second reference potential are potential-divided by a resistance train, and the first reference potential is divided by a resistance train. Within the range from the reference potential of 1 to the second reference potential, only in either the upper half or the lower half of the range, the output of the first M-bit resistance type DA converter and the second There is an output of the N-bit resistor type DA converter</u>It is characterized by that.

[0015] In the above configuration, for example, in the case of 8-bit AD conversion, a first resistance type DA is compared with a 16: 1 selector in which the switch circuit of the sub DAC of the conventional circuit determines the lower 4 bits. The switch circuit of the converter and the second resistance type DA converter may be a 4: 1 selector that determines 2 bits each, and the scale of the switch circuit can be significantly reduced. In the switch circuit, the junction capacitance of the MOS transfer gates that make up the switch acts as a parasitic capacitance, causing a delay in signal change, which increases the time required for the AD conversion comparison process. In the configuration of the present invention, the switch circuits of the first resistance type DA converter and the second resistance type DA converter can be reduced in size, so that the parasitic capacitance can be significantly reduced and the time required for the comparison process can be reduced. Can be shortened.

[0016] Further, in order to reduce the sampling time, even when the number of bits of the capacitive DAC is reduced and the number of bits of the resistance DAC is increased, the increase in the delay time in the resistance DAC can be suppressed. Therefore, among the conversion times of the AD converter, the sampling time can be reduced with almost no increase in the comparison time, and the conversion time can be increased.

In this configuration, for example, in the case of a resistor sequence that divides Vref into 16, the output of the first resistor type DA converter can be set to the highest possible voltage range, such as 12Vref / 16 to 15Vref / 16. , The switch circuit of the resistance type DA converter can be used in the region where the ON resistance is small. In the transfer of the polymerase and the NMOS, the ON resistance becomes large at a voltage near 1/2 of the power supply voltage (Vref), which makes high-speed operation difficult. However, by using a voltage close to the power supply voltage (Vref), the delay time is reduced. This makes it possible to achieve high speed conversion processing.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, examples of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram showing a first embodiment of the successive approximation type AD converter according to the present invention. In FIG. 2, the same elements as in FIG. 1 are referred to by the same number.

In the sequential comparison type AD converter of FIG. 2, the input terminal 10, nodes 20 to 23, nodes 40 to 45, switch circuit 101, switch circuit 102, switch circuit 200, switch circuit 201, to which the input potential Vin is applied, It includes a switch circuit 202, a comparator 300, a sequential comparison control circuit 302, resistors R1 to R16, and capacitors C1 to C6. The operation of each switch circuit 101, 102, 200, 201, 202, etc. is controlled by the sequential comparison control circuit 302.

[0021] The resistors R1 to R16, the switch circuits 101 and 102, and the capacitor C6 form a sub DAC, and the switches C1 to C5 and the switch circuit 200 (and 201, 202) form a 4-bit main DAC. C1 to C5 constituting the main DAC are weighted as 2Cx for C3, 4Cx for C4, and 8Cx for C5, where Cx is the capacitance value of C1 and C2, respectively. At the time of sampling, all of C1 to C5 are connected to the analog input terminal 10 (Vin) via the switch circuit 200, the node 21, and the switch circuit 201, and the input potential Vin is charged. At this time, the switch 202 is controlled so that the node 20 becomes GND. Sampling capacitances C3 to C5 are generally realized by connecting a certain unit capacitance Cx in parallel, for example, 2, 4, or 8 in order to ensure relative accuracy.

After the sampling is completed, the comparison operation is started, and the digital data corresponding to the input potential Vin is determined in order from the MSB. Specifically, the switch 202 is opened to put the node 20 in a floating state, and for example, the nodes 40 to 43 are connected to GND via the switches 200 and 201, and the node 44 is connected to the reference potential Vref (terminal 1). .. The node 45 is connected to GND by the switch circuit 102. By this connection, the electric charge stored by the input potential Vin at the time of sampling is redistributed between the sampling capacities C1 to C5, and the potential of the node 20 becomes a potential proportional to Vref / 2-Vin. The node 20 is connected to the input of the comparator 300, and whether the analog input potential Vin is larger or smaller than 1/2 of the reference potential Vref can be determined by the potential of the node 22 which is the output of the comparator 300.

In the above connection, for the sampling capacitances C1 to C5, the node 44 was connected to the reference potential Vref, and the other nodes 40 to 43 were connected to GND. That is, 8Cx of C5 was connected to the reference potential Vref, and the total of 8Cx of the remaining C1 to C4 was connected to GND. In general, if the number of unit capacitance Cx connected to the reference potential Vref is m and the number of remaining unit capacitance Cx connected to GND is 16-m, the potential V of node 20 is V = (16/17) [ (m / 16) Vref --Vin] (1). For example, if you connect node 41 to Vref and the remaining nodes 40, 42, 43, and 44 to GND, the potential of node 20 is (16/17) [Vref / 16-Vin] because m is 1. It becomes. The coefficient (16/17) in the above equation takes into account the effect of the capacitor C6, which is not used as the sampling capacitance.

[0024] By sequentially changing m, it is possible to change the potential of the node 20 in Vref / 16 increments. Therefore, the MSB side (upper 4 bits) of the digital data can be determined.

FIG. 3 is a diagram conceptually showing the configuration and operation of the circuit of FIG.

The sequential comparison AD converter of FIG. 3 includes a sequential comparison control circuit 302, a local DA converter 303, and a comparator 300A. The local DA converter 303 is a combination of the main DAC and the sub DAC shown in FIG. 2, and generates a voltage in Vref / 256 increments by an 8-bit DA conversion operation. The sequential comparison control circuit 302 controls the operation of the local DA converter 303 by controlling the opening and closing of the switch circuit and the like. The comparator 300A compares the voltage generated by the local DA converter 303 with the input voltage Vin to determine the magnitude relationship. In the configuration of Fig. 2, after Vin is sampled, the result of subtracting Vin from (m / 16) Vref is supplied to the comparator 300 as an input, but Fig. 3 shows the conceptual configuration of the comparator. It is shown as comparing by subtracting Vin from (m / 16) Vref by 300A.

In the sequential comparison type AD conversion circuit of FIG. 3, the sequential comparison control circuit 302 sets digital data, and the local DA converter 303 DA-converts the digital data to generate a local analog voltage. The magnitude relationship between the input analog voltage Vin and the local analog voltage of the local DA converter 303 is compared and judged by the comparator 300A, and the sequential comparison control circuit 302 controls the local DA converter 303 based on the comparison judgment output 22. .. As a result, the digital data when the local analog voltage output of the local DA converter 303 becomes substantially equal to the input analog voltage Vin is obtained, and this digital data is used as the AD conversion output. In the comparison operation, each bit of the digital data is determined in order from the MSB toward the LSB side.

[0028] Hereinafter, a process of determining the lower bits on the LSB side by the sub DAC will be described.

[0029] At node 40 of C1 having a capacitance value Cx having a magnitude of 1/16 with respect to the total sampling capacitance of 16 Cx of C1 to C5, a 2-bit resistor DAC (R1 to R16 and a switch circuit 101) is used. Change the potential in Vref / 4 increments. As a result, the potential of the node 20 which is the input of the comparator can be changed in Vref / 64 steps.

[0030] For example, the capacitance value of the capacitance connected to Vref by the switch circuit 200 is mCx (m is 0 to 15), and the capacitance value of the capacitance connected to GND by the switch circuit 200 is (15-m) Cx. To do. Further, the potential of the node 40 of C1 set by the 2-bit resistance DAC is set to nVref / 4 (n is 0 to 3). At this time, the potential V of the node 20 determined by the charge redistribution is V = (16/17) [(m / 16 + n / 64) Vref-Vin] (2). In the above equation, it is assumed that the potential of the node 45 is set to GND.

Therefore, after determining the value of m corresponding to the digital data of the upper 4 bits, the value of V is changed in voltage increments obtained by dividing the reference potential Vref into 64, and the value of n is determined by the comparator 300. Can be done. In other words, following the upper 4 bits of digital data, the 2 bits of data corresponding to n can be determined.

From the above, 6-bit digital data can be obtained from the MSB side.

Further, at the node 45 of C6 having a capacitance value Cx having a magnitude of 1/16 with respect to the total sampling capacitance 16Cx of C1 to C5, a 2-bit resistor DAC (R1 to R16 and a switch circuit 102) is used. Then, the potential is changed in increments of Vref / 16. As a result, the potential of the node 20 which is the input of the comparator can be changed in increments of Vref / 256.

[0034] For example, the capacitance value of the capacitance connected to Vref by the switch circuit 200 is mCx (m is 0 to 15), and the capacitance value of the capacitance connected to GND by the switch circuit 200 is (15-m) Cx. To do. Further, the potential of the node 40 of C1 is set to nVref / 4 (n is 0 to 3), and the potential of the node 45 of C6 set by the above-mentioned 2-bit resistance DAC is set to pVref / 16 (p is 0 to 3). At this time, the potential V of the node 20 determined by the charge redistribution is V = (16/17) [(m / 16 + n / 64 + p / 256) Vref-Vin] (3).

Therefore, after determining the values of m and n corresponding to the digital data of the upper 6 bits, the value of V is changed in voltage increments obtained by dividing the reference potential Vref by 256, and the value of p is determined by the comparator 300. can do. In other words, following the upper 6-bit digital data, the 2-bit data corresponding to p can be determined.

[0036] From the above, all 8-bit digital data can be obtained.

[0037] FIG. 4 is a diagram showing a configuration of the local DA converter 303 of FIG. 3 in order to conceptually explain the operation of the circuit of FIG.

[0038] The local DA converter 303 of FIG. 3 includes a capacitance array type DA converter 304, a resistance type DA converter 305, and a resistance type DA converter 306.

[0039] m is the upper 4 bits of the digital data, n is the middle 2 bits of the digital data, and p is the lower 2 bits of the digital data. The capacitive array type DA converter 304 indicates a capacitive array DAC that converts the high-order bits of the local DA converter 303, and corresponds to C1 to C5 in FIG. 2 and the switch circuit 200 (and 201, 202). The resistance type DA converter 305 shows a resistance DAC that converts the middle 2 bits among the local DA converters 303, and corresponds to R1 to R16 in FIG. 2 and the switch circuit 101. Further, the resistance type DA converter 306 indicates a resistance DAC that converts the lower two bits of the local DA converter 303, and corresponds to R1 to R16 and the switch circuit 102 in FIG. In FIG. 2, C1 is shown as part of the capacitive array DAC, but in FIG. 4, it is shown separately from the capacitive array DAC.

[0040] The output of the resistance type DA converter 305 is capacitively coupled via C1 to the output of the capacitance array type DA converter 304, and the output of the resistance type DA converter 306 is capacitively coupled via C6. To. By capacitively coupling the output of the resistance type DA converter 305, the voltage corresponding to the middle bit represented by n can be scaled down and added. Further, by capacitively coupling the output of the resistance type DA converter 306, the voltage corresponding to the lower bit represented by p can be scaled down and added.

[0041] In the examples of FIGS. 2 and 4, a configuration is shown in which the output potentials of two resistance DACs are capacitively added to the output potentials of the capacitance DACs, but the number of resistance DACs is not limited to two, and two or more resistors. The DAC may be provided together with the capacitive coupling means. Further, the output potential of the resistor DAC applied to the node 45 of C6 need only be able to be changed in voltage increments of Vref / 16 as a relative change from the time of sampling, and the absolute value does not have to be the potential corresponding to R1 to R4.

[0042] Further, the capacitance DAC corresponds to 4 bits and the resistance DAC corresponds to 4 bits, but the present invention is not limited to this, and for example, the capacitance DAC may correspond to 3 bits and the resistance DAC may correspond to 5 bits.

Further, as compared with the switch circuit 100 of the conventional circuit of FIG. 1 having a 16: 1 selector, in the circuit of the present invention of FIG. 2, both the switch circuits 101 and 102 have a 4: 1 selector, so that the switch circuit is a switch circuit. Can be significantly reduced in scale.

[0044] Specifically, the switch circuit is realized by a MOS transfer gate, and when the resistance DAC is 4 bits as shown in FIG. 1, the junction capacitance of the MOS transfer gate for 16 taps becomes the parasitic capacitance of the node 23. .. Due to the influence of this parasitic capacitance, the signal change of the node 23 is delayed, the settling time of the node 20 becomes long, and the time required for the comparison process increases.

Since the circuit scales of the switch circuits 101 and 102 in FIG. 2 are small, the parasitic capacitances of the nodes 23 and 45 in FIG. 2 are significantly smaller than the parasitic capacitances of the nodes 23 in FIG. 1, and the time required for the comparison process. Can be shortened.

[0046] In the sequential comparison type AD converter, the processing time of the AD conversion process for converting an analog signal into a digital signal is a comparison in which the sampling time for storing the analog signal in the sampling capacity and the digital value are determined after the sampling is completed. It consists of time. In order to shorten the conversion processing time, the sampling time and the comparison time must be shortened. In order to shorten the sampling time, assuming that the signal source impedance of the external circuit that supplies the analog input signal is constant, it is necessary to reduce the capacitance value of the sampling capacitance. However, in order to maintain the relative accuracy, the value of the unit capacity cannot be reduced so much, and the sampling capacity must be reduced by reducing the number of capacities.

[0047] In order to reduce the capacitance value of the sampling capacitance, the capacitance main DAC may have a 3-bit configuration and the resistor sub DAC may have a 5-bit configuration, for example. In this case, since the sampling capacity is eight unit capacities, the capacity value can be halved with respect to the original total sampling capacity. However, since the number of bits of the resistance DAC is 5 bits, the junction capacitance of the MOS transfer gate for 32 taps becomes the parasitic capacitance of the node 23, which increases the settling time of the node 20 and the comparison time.

[0048] In the configuration according to the present invention, the comparison time can be shortened by shortening the delay time of the resistance DAC output as compared with the configuration of the prior art with the same number of resistance DAC bits. Further, in order to reduce the sampling time, even when the number of bits of the capacitive DAC is reduced and the number of bits of the resistance DAC is increased, the increase in the delay time of the resistance DAC can be suppressed. Therefore, among the conversion times of the AD converter, the sampling time can be reduced with almost no increase in the comparison time, and the conversion time can be increased.

FIG. 5 is a diagram showing a modification of the sequential comparison type AD converter according to the present invention.

[0050] In FIG. 5, a switch circuit 103 is provided in the successive approximation type AD converter according to the present invention shown in FIG. 2, and the voltage dividing potential generated by the resistance trains R1 to R16 can be supplied to the outside. ing.

[0051] In the circuit of FIG. 2, the DAC operation corresponding to 4 bits is realized by taking out the DA output corresponding to 2 bits from the resistance train by the two switch circuits 101 and 102, respectively. In this configuration, it is not possible to directly take out the resistance DAC output (16-step output) equivalent to 4 bits.

[0052] During testing or actual use, it may be necessary to supply a voltage dividing potential equivalent to 4 bits to the outside of the device. Therefore, in the configuration of FIG. 5, the switch circuit 103 is provided so that the 4-bit DAC output can be taken out. Even if this switch circuit 103 is added, the parasitic capacitance of the nodes 23 and 45 does not increase, so that the AD conversion performance does not deteriorate.

FIG. 6 is a circuit diagram showing a second embodiment of the successive approximation type AD converter according to the present invention. In FIG. 6, the same elements as in FIG. 2 are referred to by the same number.

[0054] In the successive approximation type AD converter of FIG. 6, the input terminal 10, the nodes 20 to 23, the nodes 40-44 and 47, the switch circuit 101, the switch circuit 104, the switch circuit 200, and the switch circuit to which the input potential Vin is applied are applied. Includes 201, switch circuit 202, comparator 300, sequential comparison control circuit 302A, resistors R1 to R16, and capacitors C1-C5 and C7. The operation of each switch circuit 102, 104, 200, 201, 202, etc. is controlled by the sequential comparison control circuit 302A.

The resistors R1 to R16, the switch circuits 102 and 104, and the capacitor C7 form a sub DAC, and the switches C1 to C5 and the switch circuit 200 (and 201, 202) form a 4-bit main DAC. C1 to C5 constituting the main DAC are weighted as 2Cx for C3, 4Cx for C4, and 8Cx for C5, where Cx is the capacitance value of C1 and C2, respectively. At the time of sampling, all of C1 to C5 are connected to the analog input terminal 10 (Vin) via the switch circuit 200, the node 21, and the switch circuit 201, and the input potential Vin is charged. At this time, the switch 202 is controlled so that the node 20 becomes GND. Further, the potential of the node 60 is supplied to the node 47 via the switch circuit 104. The charge stored in C1-C5 and C7 during this sampling is 16CxVin + 4CxV.₆₀(V₆₀Is the potential of node 60). The capacity of C7 is 4Cx.

[0056] After the sampling is completed, the comparison operation is started, and the digital data corresponding to the input potential Vin is determined in order from the MSB. Assuming that the number of unit capacitances Cx connected to the reference potential Vref is m and the number of remaining unit capacitances Cx connected to GND is 16-m, the potential V of node 20 is V = (16/20) [(m). / 16) Vref --Vin] (4). Here node 47 is connected to node 60 and the potential V₆₀Is set to.

[0057] By sequentially changing m, it is possible to change the potential of the node 20 in Vref / 16 increments. Therefore, the MSB side (upper 4 bits) of the digital data can be determined.

Next, a process of determining the lower bits on the LSB side by the sub DAC will be described.

[0059] At node 47 of C7 having a capacitance value of 4Cx, which is 1/4 of the total sampling capacitance of C1 to C5, 16Cx, a 2-bit resistor DAC (R1 to R16 and a switch circuit 104) is used. Change the potential in Vref / 16 increments. As a result, the potential of the node 20 which is the input of the comparator can be changed in Vref / 64 steps.

[0060] For example, the capacitance value of the capacitance connected to Vref by the switch circuit 200 is mCx (m is 0 to 15), and the capacitance value of the capacitance connected to GND by the switch circuit 200 is (15-m) Cx. To do. Furthermore, the potential of node 47 of C7 set by the above 2-bit resistance DAC is set to nVref / 16 (n is 0 to 3) + V.₆₀And. At this time, the potential V of the node 20 determined by the charge redistribution is V = (16/20) [(m / 16 + n / 64) Vref-Vin] (5). At this time, the node 40 is connected to GND.

Therefore, after determining the value of m corresponding to the digital data of the upper 4 bits, the value of V is changed in voltage increments obtained by dividing the reference potential Vref into 64, and the value of n is determined by the comparator 300. Can be done. In other words, following the upper 4 bits of digital data, the 2 bits of data corresponding to n can be determined.

From the above, 6-bit digital data can be obtained from the MSB side.

[0063] Further, a 2-bit resistor DAC (R1 to R16 and a switch circuit 102) is used at the node 40 of C1 having a capacitance value Cx having a size of 1/16 with respect to the total sampling capacitance 16Cx of C1 to C5. Then, the potential is changed in increments of Vref / 16. As a result, the potential of the node 20 which is the input of the comparator can be changed in increments of Vref / 256.

[0064] For example, the capacitance value of the capacitance connected to Vref by the switch circuit 200 is mCx (m is 0 to 15), and the capacitance value of the capacitance connected to GND by the switch circuit 200 is (15-m) Cx. To do. Furthermore, the potential of node 47 of C7 is set to nVref / 16 + V.₆₀Let (n be 0 to 3), and let the potential of node 40 of C1 set by the above 2-bit resistance DAC be pVref / 16 (p is 0 to 3). At this time, the potential V of the node 20 determined by the charge redistribution is V = (16/20) [(m / 16 + n / 64 + p / 256) Vref-Vin] (6).

Therefore, after determining the values of m and n corresponding to the digital data of the upper 6 bits, the value of V is changed in voltage increments obtained by dividing the reference potential Vref by 256, and the value of p is determined by the comparator 300. can do. In other words, following the upper 6-bit digital data, the 2-bit data corresponding to p can be determined.

[0066] From the above, all 8-bit digital data can be obtained.

[0067] As described above, an 8-bit successive approximation type AD converter can be realized by the configuration of FIG. In the circuit of FIG. 2, the step of the output potential of the resistor DAC used for the conversion of the middle bit is Vref / 4. On the other hand, in the configuration of Fig. 6, the step of the output potential of the resistor DAC used for medium bit conversion is Vref / 16, and C7 has a capacitance value of 4Cx, which is 1/4 of the total sampling capacitance of 16Cx. The potential is added to the node 20 via.

[0068] In this configuration, the bias potential V₆₀To increase the output potential of the resistor DAC to nVref / 16 + V₆₀By setting (n is 0 to 3), the highest possible voltage range from 12Vref / 16 to 15Vref / 16 is used. As a result, the switch circuit 104 can be used in a region where the ON resistance is small. In the transfer of the polymerase and the NMOS, when the voltage is around 1/2 of the power supply voltage (Vref), the ON resistance becomes large and high-speed operation becomes difficult, but it is close to the power supply voltage (Vref) as shown in the switch circuit 104 in Fig. 6. By using a voltage, it is possible to reduce the delay time, and thereby speed up the conversion process can be achieved.

[0069] Although the present invention has been described above based on Examples, the present invention is not limited to the above Examples, and various modifications can be made within the scope of the claims.

According to the present invention, in the AD converter according to the present invention, the scale of the switch circuit is significantly reduced by dividing the sub DAC into a first resistance type DA converter and a second resistance type DA converter. Can be done. As a result, the parasitic capacitance in the switch circuit can be significantly reduced, and the time required for the comparison process can be shortened.

[0070] Further, by operating the resistance DAC while avoiding the voltage region in which the ON resistance of the MOS transfer gate becomes high, it is possible to achieve high speed in the comparison process.

BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1] Fig. 1 is a circuit diagram of a sequential comparison type AD converter using a conventional CR type double stage DAC.

FIG. 2 is a circuit diagram showing a first embodiment of a successive approximation type AD converter according to the present invention.

FIG. 3 is a diagram conceptually showing the configuration and operation of the circuit of FIG.

4 is a diagram showing a configuration of a local DA converter of FIG. 3 in order to conceptually explain the operation of the circuit of FIG. 2. FIG.

FIG. 5 is a diagram showing a modified example of the sequential comparison type AD converter according to the present invention.

FIG. 6 is a circuit diagram showing a second embodiment of the sequential comparison type AD converter according to the present invention.

[Code description] 10 Input terminal 101 Switch circuit 102 Switch circuit 200 Switch circuit 201 Switch circuit 202 Switch circuit 300 Comparator 302 Sequential comparison control circuit