Apparatus and method for performing initial cell search in a wireless communications system

The present invention relates to synchronization of user equipment (UE) with respect to a base station. More specifically, the present invention relates to improved initial cell search methods and systems.

Figure 1 shows a wireless communication system. This communication system has multiple base stations 2₁~2_nHas (2). Each base station 2 has its own operating area, ie cell 6.₁~6_nUser device (UE) 4 in (6)₁~4_nCommunicate with (4).

When UE4 is first activated, it does not know its location and base station 2 (or cell 6) to communicate with. The process by which UE4 determines cell 6 to communicate with is called a "cell search".

A typical code division multiple access (CDMA) communication system uses a multi-step process for cell search. In stage 1, each base station 2 transmits the same primary synchronization code (PSC) on the primary synchronization channel (PSCH). In time division duplex (TDD) communication systems using CDMA, PSCHs are slot 0 or generally 15 time slots (time slots) such as K for cell search in Case 1 (shown in Figure 2a). ), And in the case of Case 2 cell search (shown in Figure 2b), there are slot 0 or generally K, and two time slots such as 8 and K + 8. Each base station sends the same PSC to its PSCH time slot. Secondary synchronization code (SSC) used in stage 2 Each PSC is transmitted at a different time offset to reduce interference between code)). The PSC offset is a set number of chips.

UE4 determines which base station 12 to synchronize by looking for a PSCH for the received PSC, such as by using a matched filter. Figure 3 shows an example of the results of such a search. Peak 26, as shown in Figure 3₁,26₂Occurs where there is a high correlation with the PSC code in PSCH. Usually, the search result is accumulated over multiple frames for better accuracy. The accumulated results are used to determine the PSC peal location in PSCH.

Seeing Figure 2a and Figure 2b again, each base station 2 has a secondary synchronization code (SSC), such as three, in both cases 1 and 2 of TDD, along with the PSC transmitted by each base station. Send at the same time. The SSC transmitted by each base station 2 is used to identify cell parameters such as the code group and frame timing used in the cell. UE4 typically uses a correlator to detect the SSC at each PSC peak identified in step 1 and the data modulated by them. UE4 reads the broadcast control channel. In stage III of TDD for both types I and II, UE4 typically detects the midamble used in the broadcast channel and then reads the broadcast channel.

<p> The drawback of the initial cell search system described above is that the performance of the second stage (SSC detection) depends on the quality of the received signal, and the quality of the signal depends on the quality of the received signal. If it is poor quality, false detection may occur. In a conventional system, even if the execution of step 1 is successful (successful execution of step 1), the benefit cannot be obtained from it in the second stage.</p><p> Therefore, there is a need for an initial cell search system that provides more accurate SSC detection, where the performance of the second stage is not determined solely by the received input signal.</p>

<p> In the systems and methods according to the invention,<u style="single">Multiple bases where each base station transmits a common primary synchronization code (PSC) on the primary synchronization channel, as well as each of the multiple base stations transmitting a base station-specific secondary synchronization code (SSC) within the system frame. In a communication system having a station, a communication link is established between a user device (UE) and a base station. The UE receives input signals, including PSCs and SSCs, from at least one of the base stations. The first processor analyzes the input signal to detect the PSC within a frame of the selected time period and determine the relative position of the strongest PSC in the system frame. The first offset processor and the second offset processor process the input signal to remove the PSC and SSC from the determined PSC position. After the PSC is removed from the input signal, the second processor detects the SSC in the input signal at the determined position. The third processor detects the scrambling code from the processed signal in order to determine the cell parameters of the base station associated with the detected SSC.</u></p>

Preferred embodiments will be described with reference to the drawings. In the drawings, similar elements are represented by similar reference numerals.

FIG. 4 shows an initial cell search system 10 according to a preferred embodiment of the present invention. The system 10 has a step 1 processor 12, a cancellation device 18, and a stage 2 to achieve the initial synchronization between the user equipment (UE) and the base station. Includes step 2 processor 14 and step 3 processor 16.

Stage 1 of the initial cell search algorithm is accomplished using the Stage 1 processor 12. FIG. 4 shows one embodiment of a stage 1 processor, but other embodiments can be used. The stage 1 processor 12 includes a Hierarchical Golay Correlator (HGC) 21 and a PSC decision device 22. The purpose of Stage 1 Processor 12 is to find the strongest base station PSC over one or more frames of samples. The chip sampled input signal I is received by the UE and processed by the HGC21. This HGC21 is an example in which the complexity of the correlation process between the PSC at the continuous chip location and the input signal I is reduced. The output of the HGC21 is the detected PSC power level for the base station detected by the HGC21. Represents the magnitude of level). The PSC of a base station with a high received power level appears as a peak in the frame. The output of HGC21 is input to the PSC determination device 22.

The PSC determination device 22 is coupled to the HGC21 and receives the correlation value output by the HGC21 for each chip in a frame worth of chips. It is preferable that one frame's worth of chips corresponds to a system frame (equivalent), which corresponds to 38,400 chips as an example. As will be known to those of skill in the art, this system frame may be more or less than those disclosed herein.

The determination device 22 stores the correlation value of each chip passed from the HGC 21 over a predetermined number of frames N, and averages the correlation value of each chip. As an example, one system frame is four chips long and N = 2. HGC21 outputs correlation values A1, B1, C1 and D1 for each of the four chips. The determination device 22 stores these values and receives the output of the correlation values A2, B2, C2, and D2 of the next frame of each chip from HGC21. The correlation values for each chip are then averaged (ie A).₁+ A₂/ 2; B₁+ B₂/ 2; C₁+ C₂/ 2; D₁+ D₂/2)。

Once the determination device 22 finds an average correlation value for each average correlation chip in a frame, the position of the maximum of those frames. The average of the frames) is determined and its value is compared with the determined threshold. This threshold is based on the noise level at the receiver (ie, interference + thermal noise). The noise estimator 24 has an auxiliary HGC (auxiliary HGC) (not shown). This auxiliary HGC is based on a code with very low cross correlation with PSC and SSC. The noise estimator HGC has a noise estimate for every chip in the system frame. estimate) is calculated. The noise estimator is repeatedly applied in the same number of frames as the HGC21 and averages several noise estimates in a window surrounding the estimated PSCH location. This window size is preferably about 128, i.e. 64 chips on both sides of the PSCH location. As will be appreciated by those skilled in the art, this window size may be greater than or less than 128. If the maximum average is greater than the threshold, the determination device 22 has a base station transmission pattern associated with its maximum average location in Case 1 or Case 2. Is determined. This determination is based on the correlation value of the chip at maximum position + (8 * 2560) or maximum position + (7 * 2560). This is done by comparing chip). If the value is greater than the threshold, the transmission pattern is Case 2. If not, the transmission pattern is case 1.

If the value of the maximum location is less than the threshold, the stage 1 processor 12 continues processing the input signal until a correlation value greater than the threshold is found or a failed condition is met. As will be known to those of skill in the art, the determination processor 22 can utilize many methods to determine the location of the strongest PSC code. When the maximum position is found, the determination processor 22 transfers that position and the PSC to the offsetting device 18 and the stage 2 processor 14.

The offset device 18 is coupled to the stage 1 processor 12 and the stage 2 processor 14 and receives the maximum position, PSC, and input signal I and subtracts the PSC from the input signal I. This subtraction eliminates the PSC from the chip at the maximum position on the input signal I. Subtraction of the PSC from the input signal I can be done by one of several cancellation methods, such as the cancellation of interference. When using interference cancellation, the PSC uses an interference construction device (not shown) to an estimate its contribution to the input signal I. Converted to of its contribution to the input signal I). Received PSC's contribution) is subtracted by a subtractor or the like. The resulting signal has a PSC's contribution removed from the input signal I at the maximum position. In a code multiplexing system, one code appears as noise to the other code. Therefore, PSC is essentially noise to SSC. As a result, offsetting the PSC from the input signal I allows the stage 2 processor 14 to locate the SSC and slot offset with greater accuracy and speed.

The stage 2 processor 14 is coupled to the offset device 18, the stage 1 processor 12, and the stage 3 processor 16 to transfer the modified input signal from the offset device 18 to the position of the PSC from the stage 1 processor 22. Receive (location of the PSC).

Figure 5 shows an example of a step 2 device, but other devices can also be used. This stage 2 processor includes a correlator 31, a fast Hadamard transform device (FHT) 33, a phase estimator device 37, a derotate device 34, an accumulator 36, And includes a decision device 39. Since the position of the PSC is determined by the stage 1 processor 12, the stage 2 processor 14 only needs to search for the maximum location SSC input from the stage 1 processor 12. At this stage, the UE is the code group and t associated with the base station in the highest position._offsetIdentify. The stage 2 processor 14 also determines the frame index number within the interleaving period of two frames and the slot index (K or K). +8) is determined. As is known to those skilled in the art, it is judged at this stage._offsetBy the slot boundary (boc)_r(i) = c (i) * z (i), i ..., 255undary) can be synchronized. The modified input signal and the position of the PSC are input to the correlator 31. The correlator 31 is coupled to the FHT33 and the offsetting device 18 and correlates the received input signal with the length 256 chip code at the PSC position, resulting in 16 correlation values. Get (16 correlation values). This code C_RIs the first SSC, C₁, And masking sequence Z obtained from the chip by chip multiplication. This is shown below.

c_r(i) = c₁(i) * z (i), i = 0, ..., 255 Equation 1

By using the above code, 16 complex correlation values R_C(K) is obtained. R_C(K) is obtained by the following equation 2.

<maths num="1"><img file="JP3962016B2_D0001.tif" /></maths>

Here t_cpIs the PSC position obtained from the stage 1 processor 12, and N is the maximum number of PSC time slots used for averaging.

The correlation value obtained from the output of the correlator 31 is supplied to the FHT 33. The FHT33 is coupled to the correlator 31 and the derotate device 34 to obtain 16 complex correlation values corresponding to the correlation between the 16 SSCs and the received signal. That is,

<maths num="2"><img file="JP3962016B2_D0002.tif" /></maths>

As known to those skilled in the art, R_cObtaining an FHT of (K)'is equivalent to correlating an unmasked SSC (unmasked SSC) with a received signal. This is possible because the 16 SSCs have a special structure. Note that the case 1 signal uses 6 SSCs and the case 2 signal uses 12 SSCs. The four SSCs are not used.

The phase estimator 37 receives the modified chip sampled signal and the PSC position from the stage 1 processor 12. The output of step 1 HGC (step 1 HGC) 21 at the PSC position corresponds to the correlation between the PSC and the received signal at that PSC position. This complex correlation value is the input to the phase estimator 37. In this phase estimator 37, the complex correlation value is normalized and then conjugate. This phase estimation is needed for the derotation of SSC.

The derotate device 34 is coupled to the phase estimator 37 and the FHT33 and receives 16 SSCs from the FHT33 and a phase estimate from the phase estimator 37. The derotate device 34 derotates the output of the FHT33. The derotation phase is the PSC phase of the PSC. The complex correlation value is complex multiplied with its phase.

The derotated correlation value is then transferred to the accumulator 36. The accumulator 36 is coupled to a derotate device 34 and a step 2 decision device 39. The derotated correlation value is in the period of two (for case 1) or the period of four (for case 2) according to Equation 4 below. N iterations are added coherently.

<maths num="3"><img file="JP3962016B2_D0003.tif" /></maths>

Where N is the maximum number of iterations to obtain a reliable signal value, and K is the number SSCs used (K = in case 1). 6. In case 2, K = 12), and L is the periodicity of PSCH (L = 2 in case 1, L = 4 in case 2). These correlation values are initialized to zero. A decision variable is formed from its correlation values according to the SSC transmission pattern.

This decision variable obtained by the accumulator 36 is transferred to the decision device 39. Case 1 has 64 decision variables, 32 code groups, and 2 frame indexes. In case 2, there are 128 decision variables, 32 code groups, 2 frame indexes, and 2 slots (K or K + 8). The determination device 39 compares all the decision variables sequentially (one by one). This method is efficient because it does not have a large number of decision variables and can be implemented without much complexity. The long transmission pattern to which the largest coefficient of determination belongs indicates the code group numbers in cases 1 and 2 and the PSCH slot index in case 2.

Then t_offset, Scrambling code group number, SSC, and PSC positions are transferred to step 3 processor. This stage 3 processor 16 is coupled to stage 2 processor 14 and retrieves the midamble and primary scrambling code used by the UE. The code group number retrieved by the stage 2 processor 14 is associated with four cell parameters. Therefore, identification of the code group number identifies the midamble code used by the cell. The four cell parameters associated with the code group are cycled by system frame numbers (SFN), as shown in Table 1.

<tables num="1"><img file="JP3962016B2_D0004.tif" /></tables>

FIG. 6 shows an exemplary Stage 3 processor 16. Although an example of a stage 3 processor is shown here, any stage 3 processor may be used. The stage 3 processor 16 includes a correlation device 41, an accumulation device 42, and a decision device 43. The code group and frame index are transferred from the stage 2 processor 14 to the correlation device 41, and the PSC position is transferred from the stage 1 processor 12 to the correlation device 41. Periodic window size pWS and multipath window size mpWS are also input to the correlation device 41. The correlation device 41 correlates the input signal I with the four mid ambles associated with the code group. This correlation is WS3 calculated candidate midamble on P-CCPCH. location), this location is t in the code group_offset, Periodic window size pWS, and multipath window size mpWS. Here, WS3 = pWS + 2mpWS.

The basic midamble code switches according to the SFN (odd / even). If the SFN is even, the correlation device 41 correlates to the basic mid-amble code. If the SFN is odd, the correlation device 41 correlates with the cycled midamble code. For example, for code group 0, the correlation device 41 correlates to midamble codes 0,1,2 and 3 for even SFNs and midamble codes 1,0,3 and 2 for odd SFNs. Correlate with. Note that cell search does not know the SFN, but it does tell whether the SFN is even or odd based on the frame index (1 or 2) found by the stage 2 processor 14.

Correlation device 41 calculates the correlation of 4 × WS3. The periodic window allows the correlation device 41 to find the maximum correlation. The purpose of the multipath window is to adjust the PSCH position to include the maximum amount of multipath. This may be necessary if the strongest multipath component is not the first significant multipath component.

The correlation value output from the correlation device 41 is transferred to the accumulation device 42 coupled to the correlation device 41 and the determination device 43. The accumulating device 42 accumulates the correlation value over a predetermined number of frames N3. Since the initial cell search does not know the frame boundary, this initial cell search system typically uses a block of 38400 chips (2560 chips x 15 slots) instead of a frame. Please note that. The accumulation device 42 forms a decision variable by adding the absolute values of the real and imaginary parts of the complex number representing the correlation value. The coefficient of determination is the magnitude of the corresponding correlation value. measure). To obtain a more reliable determination, these factors can be repeatedly accumulated N3 times. Here, N3 is the maximum number of iterations for obtaining a reliable signal-to-noise ratio level.

The coefficient of determination generated by the accumulation device 42 is transferred to the determination device 43. The determination device 43 is coupled to the accumulation device 42 and determines the largest coefficient of determination by a simple sequential comparison. The largest coefficient of determination corresponds to the basic midamble used for that cell. The scrambled code number associated with the identified midamble is the scrambled code for that cell. The scrambled code is then utilized by the UE for broadcast channel processing.

FIG. 7 shows a flow chart of the initial cell search system. The UE receives the input signal through a common downlink channel (step 601). Stage 1 Processor 12 detects the location of the PSC associated with the strongest base station (step 602). Stage 1 Processor 12 transfers its PSC to the offsetting device 18 (step 603). The offset device 18 subtracts the PSC detected by the stage 1 processor 12 from the input signal I (step 604) and transfers the modified signal to the stage 2 processor 14 (step 605). Using the modified input signal from offsetting device 18 and the position of the PSC from stage 1 processor 12, stage 2 processor 14 retrieves the SSC and is associated with the strongest base station._offsetAnd determine the code group number (step 607). The code group number is transferred to stage 3 processor 16 (step 608). Stage 3 Processor 16 looks up the midamble and primary scrambling code from its code group number (step 609). These codes are used by the UE to synchronize with the base station (step 610).

Since the second step is the weakest in the initial cell search, a cleaner signal can be obtained by canceling the PSC from the signal input to the stage 2 processor 14. The result is a better estimation of the SSCs time. The result is a more accurate slot offset and code group number determination. Ultimately, this procedure reduces the number of false detections by the UE.

FIG. 8 shows a second embodiment. Similar to the system of FIG. 1, the system of this second embodiment is also an offset device 18₂Is used to subtract the PSC and SSC from the input signal I before processing by the stage 3 processor 16. In step 2, the PSC does not receive the removed input signal (a PSC removed input signal), but instead the modified signal input to the stage 3 processor 16 of the base station detected. Midambles and code groups can be detected more accurately.

FIG. 9 shows a third embodiment. In this third embodiment, the offset device 18₁And 18₂Is used to improve the accuracy of the initial cell search system 10. Offset device 18₁Is located in front of the stage 2 processor 14 and removes the PSC from the detected location in the input signal. Offset device 18₂Removes the SSC before stage 3 processor 16.

<figref num="1">It is a figure which shows the wireless communication system.</figref><figref num="2a">It is a figure which shows the physical synchronization channel (PSCH) in case 1.</figref><figref num="2b">It is a figure of the physical synchronization channel (PSCH) in case 2.</figref><figref num="3">It is a figure which shows the peak in PSCH.</figref><figref num="4">It is a block diagram which shows the initial cell search system by this invention.</figref><figref num="5">It is an exemplary block diagram of a stage 2 processor.</figref><figref num="6">It is an exemplary block diagram of a stage 3 processor.</figref><figref num="7">It is a flow chart which shows the initial cell search system by this invention.</figref><figref num="8">It is a block diagram which shows the 2nd Embodiment of the initial cell search system.</figref><figref num="9">It is a block diagram which shows the 3rd Embodiment of an initial cell search system.</figref>