Ozone gas processing for ferroelectric memory circuits.

The present invention relates to a method of forming a ferroelectric integrated circuit, particularly a method of forming a ferroelectric capacitor.

Ferroelectric capacitors are generally formed through a series of thin-film deposition and drawing steps. In this step, oxygen annealing needs to be performed several times. Oxygen annealing is used to accurately form the crystalline phase of thin-film, sputtered, or spin-coated "PZT (lead zirconate titanate)" and to reduce electrode and material defects. Needed for.

"PZT" is the name of a ferroelectric substance composed of lead zirconate titanate, and Pb (Ti)._x Zr_1-x ) O₃ Has the general formula of. Here, x represents the composition ratio and is a value in the range of x = 0 to 1. Deposited, sputtered, or spin-coated PZTs are amorphous and do not have ferroelectric properties (or have insufficient ferroelectricity). Annealing in an oxygen atmosphere is necessary to accurately form the crystallographic phase that can produce the desired ferroelectric properties. For example, when PZT is used in a memory circuit, the required ferroelectric phase (ferroelectric phase) is a tetragonal phase. One of the desired ferroelectric properties is the permanent dipole moment that occurs without applying an electric field. This is a positively charged Ti⁺⁴Ions are negatively charged O^-2It can only occur if it is displaced in one direction with respect to the environment. Empty lattice points of oxygen tend to occur in the sputtered PZT material due to target defects and oxygen reactivity. Thus, oxygen is needed to repair these defects and ensure good ferroelectricity. These oxygen annealings also affect the electrode / PZT interface by acting as acceptor atoms that reduce excess charge at the interface resulting from material lattice mismatch.

Currently, oxygen annealing is O at temperatures above 500 ° C.₂ It is done in the atmosphere of. Generally, oxygen annealing is performed by an electric furnace annealing method or a short-time annealing method (RTA).

However, the effects of these annealings may be reduced or even extinguished by some of the processing steps performed to form the ferroelectric capacitors. For example, many subsequent integrated circuit processing steps are in a low pressure, weakly ionized and highly activated gas state (known as plasma). Medium energy (<1 keV) electrons and protons are generated in this plasma. These particles can be ionized in a ferroelectric material to form electron-hole pairs and ionize the constituent PZT atoms. The extra charge generated as a result of these processing steps accumulates, forming an internal electric field greater than and / or opposite to the internal electric field of the structural dipole moment induced in the ferroelectric.

For example, SiH on a ferroelectric capacitor₄ Gas and oxygen or N₂ When a silicate glass film is deposited using O gas, H₂ Or N₂ Becomes a substitutional impurity in the ferroelectric crystal, which may impair the ferroelectric effect of the crystal. Enough H₂ When is substitutablely accumulated in the ferroelectric crystal, the induced structural dipole moment is zero and the ferroelectric histeresis curve approximates that of a conventional linear dielectric medium. This can be understood as a region embedded in the ferroelectric substance and the resistivity is significantly reduced.

<p> An object of the present invention is to provide a ferroelectric capacitor that does not have the above-mentioned drawbacks and an improved method for forming a ferroelectric memory circuit using the same.</p>

<p> The present invention relates to a ferroelectric capacitor and a method of forming a ferroelectric memory circuit using the capacitor by annealing. The method generally consists of a series of processing steps, including a series of annealings.</p><p> According to the method for forming a ferroelectric memory circuit of the present invention, in forming a ferroelectric memory circuit, a) a step of forming a lower electrode on a substrate and b) a ferroelectric substance on the lower electrode. The step of providing the layer, c) the step of forming the upper electrode on the ferroelectric layer, d) the step of defining the upper electrode using the first mask, and e) the first annealing. It is characterized in that the steps to be performed and the steps to be performed are performed in this order.</p><p> Further, in carrying out the present invention, preferably, between the step of b) providing the ferroelectric layer on the lower electrode and the step of c) forming the upper electrode on the ferroelectric layer, It is preferable to further include a step of performing a second annealing.</p><p> Further, in carrying out the present invention, it is preferable to further include a step of exposing the substrate to ozone at a temperature higher than 450 ° C. prior to carrying out the step of e) the first annealing.</p><p> Further, in carrying out the present invention, preferably, after the step of e) the first annealing, f) the step of defining the ferroelectric layer using the second mask, and g) the third mask. It is preferable to carry out the step of defining the lower electrode using the above and the step of h) performing the third annealing in this order.</p><p> Further, in carrying out the present invention, preferably, the upper electrode, the ferroelectric layer and the lower electrode are placed in the range of 400 ° C to 450 ° C prior to the implementation of the h) third annealing step. It is preferable to further include a step of exposing to ozone at temperature.</p><p> Ozone quickly O at temperatures above 400 ° C₂ And O^- Ozone annealing is superior to oxygen annealing as a method for imparting oxygen to a ferroelectric substance. As a result of this decomposition, the ferroelectric is O₂ Is not only given, but also highly reactive, O₂ O with higher electron affinity^- Seed (O^- species) is also given. In addition, ozone gas is extremely reactive and naturally tries to stabilize by letting go of oxygen, so ozone is a normal Ozone.₂ Not limited by the same surface adsorption / desorption kinematics as. In other words, oxygen molecules are adsorbed on the surface of the strong dielectric at 500 ° C, and oxygen molecules require sufficient energy to break covalent bonds, whereas ozone molecules are above 500 ° C. Then, it decomposes into oxygen atoms and oxygen molecules in a few milliseconds. As a result, when the ferroelectric is exposed to ozone, the ferroelectric becomes O₂ Oxygen atoms can be obtained much faster than they receive from. Therefore, ozone can diffuse a high concentration of reactive oxygen atoms into the ferroelectric substance, so that oxygen can diffuse (penetrate) into the ferroelectric substance relatively quickly. This is important because the faster oxygen is applied to the ferroelectric crystal, the less lead (Pb) atoms are lost.</p>

[Example 1] Hereinafter, examples of the present invention will be described with reference to the drawings. In the figure, the same parts are indicated by the same reference numerals. In addition, each figure shows a structure obtained in the main process step in a cross section, and a hatching or the like showing the cross section is partially omitted. Hereinafter, preferred embodiments will be described.

Preferred examples of the methodological aspects of the present invention include a series of manufacturing steps carried out in the embodiments described below.

FIG. 1 shows a base on which a ferroelectric layer should be formed, and according to an embodiment of the present invention, a lower electrode 12 is provided on a flowed glass layer 10. The cast glass layer 10 separates between the doped polysilicon gate 9, the substrate 8 (compound semiconductor such as Si (silicon) or GaAs (gallium arsenide)), and the subsequent wiring layer (interconnect layer). (Insulate). Source and drain regions (S, D) are also shown.

In this embodiment, the substrate is composed of a source and drain regions (S, D), a substrate 8 on which a separation region is formed, a doped polysilicon gate 9, and a flattened cast glass layer 10. However, it is not limited to this.

Polysilicon, which is a gate material, is deposited by the CVD (Chemical Vapor Deposition) method. Polysilicon gate 9 can be doped in three ways. The method includes doping by introducing a dopant gas during the deposition of polysilicon, ion implantation, or doping by diffusion after deposition. Doping the gate is usually done with POCl as a solid source adjacent to the wafer or as a dopant.₃ This is done by diffusing the dopant at high temperature using (phosphoryl chloride). The doped polysilicon gate is then patterned by photolithography and dry plasma etching.

The poured glass layer 10 is preferably PSG (PhosphoSilicate Glass) or BPSG (Boron PhosphoSilicate Glass). These materials contain dopants, such as phosphorus (P) in the case of PSG and boron (B) and phosphorus (P) in the case of BPSG, which are silicates. It is used to lower the softening point of salt glass. These glasses are generally SiH₄ , O₂ , PH₃ , B₂ H₆ It is deposited by the CVD method using, or TEOS (Tetra Ethyl Ortho Silane), O at a temperature of less than 500 ° C.₂ , TMP (Tri Methyl Phosphite) and TMB (Tri Methyl Borate), BSG containing 6-10% by weight P, or 4% by weight B and 4% by weight Use any of the BPSGs containing P in the flow-glass composition. The glass is allowed to flow in steam, or oxygen or nitrogen, at a temperature in the range of 800 ° C to 1100 ° C for a time in the range of 20 to 30 minutes.

The lower electrode 12 can be provided, for example, by deposition or vapor deposition by sputtering.

In another embodiment, the lower electrode may be formed directly in an active region such as a source or drain region of the substrate.

The lower electrode 12 can be formed from a noble metal such as platinum (Pt), gold (Au), or molybdenum (Mo), for example. Preferably, the lower electrode 12 consists of a 200 angstrom (20 nanometer) titanium (Ti) layer and a 1500 angstrom (150 nanometer) platinum (Pt) layer, vacuuming between the metal deposition processes of both layers. It is deposited in one continuous processing process (single pass) that does not break the state. Generally, the adhesive force of platinum to cast glass is weak, so a titanium layer is used as an adhesive layer.

Further, in order to heat-treat the lower electrode 12, an electric furnace annealing (furnace anneal) method or a short-time annealing (RTA) is performed at a temperature between 500 ° C. and 700 ° C. in an oxygen, ozone, air or forming gas atmosphere. Preliminary annealing is performed by the method. By this annealing, titanium dioxide (TiO)₂ ) Is formed in several layers, and the lower electrode 12 and the cast glass 10 are well bonded. Furthermore, as a result of this annealing, titanium dioxide (TiO) was placed on the upper side of the platinum film.₂ ) (When oxygen is used during annealing) or titanium nitride (TiN) (when air and / or forming gas is used during annealing), several islands are formed. This improves the adhesion between the lower electrode 12 and the ferroelectric material that is subsequently deposited.

As shown in FIG. 2, the ferroelectric layer 14 is provided on the lower electrode 12. For example, a perovskite (perovskite) crystalline or high dielectric constant material such as tantalum pentoxide can be deposited as the ferroelectric layer 14. For example, general formula A_x B_y O_z A material having (where x, y, and z each represents a composition ratio) and typically having a z of 3 can be used as the ferroelectric 14. Included in this group are, for example, YBa₂ Cu₃ O₇ It is a class of high-temperature superconductors of crystals with a perovskite structure such as. However, ferroelectrics are, for example, Pb (Ti)._x Zr_1-x ) O₃ However, it is preferably a doped PZT such as PZT (lead zirconate titanate) having a general formula of (where x represents a composition ratio) or PLZT (lead lanthanate titanate zirconate). The strong dielectric layer 14 is deposited, for example, by RF (high frequency) sputtering of a PZT oxide ceramic target in an atmosphere of argon and oxygen, argon and ozone, argon, oxygen, or ozone, or an atmosphere of argon and oxygen. It can be provided in the medium or by deposition by DC (DC) / RF sputtering of the Pb-Ti-Zr metal target in an atmosphere of argon and ozone. Further, the ferroelectric layer 14 is removed by removing the organic solvent by spinning the precursor material of Pb-Ti-Zr oxide suspended in the organic solvent at a high rotation speed and then annealing. , Can also be deposited and formed.

Next, the first annealing is performed on the ferroelectric layer 14. This initial annealing is performed in an ozone atmosphere by a short-time annealing (RTA) method or an electric furnace annealing method. When an electric furnace annealing method or a short-time annealing method is performed to anneal the entire wafer in which the ferroelectric substance is present, the annealing can be performed using a laser, a microwave, or a gas discharge (plasma). Since the memory ferroelectric capacitor can exhibit good ferroelectric characteristics by the short-time annealing method, annealing is performed by the short-time annealing method in a preferred embodiment.

In the short-time annealing method, the temperature of the wafer is rapidly increased by heat radiation from the tungsten halogen lamp. The wafer is placed in a crystal cage and the temperature of the wafer is adjusted using a thermocouple and / or an optical pyrometer. Gases such as oxygen, ozone or air can be used in the annealing step. When performing the short-time annealing (RTA) method, the annealing is preferably performed at a temperature in the range of about 650 ° C to 850 ° C for about 5 to 30 seconds. The use of ozone gas during the rapid heat treatment of the ferroelectric layer 14 to convert the PZT's micro-crystalline phase into a perovskite crystalline phase exhibiting ferroelectric properties. Is preferable. In addition, short-time annealing in an ozone atmosphere (RTA) is also preferable in that it significantly reduces the number of lead (Pb) atoms lost during annealing compared to oxygen annealing in a conventional electric furnace. ..

This initial annealing can be performed by a single annealing step or a combination thereof. Annealing is oxygen (O) at any pressure above the Curie point of the ferroelectric.₂ ) And / or ozone (O₃ ) It can be performed by a short-time annealing method using an atmosphere or an electric furnace annealing method. Possible combinations are ozone short-time annealing-oxygen short-time annealing, ozone short-time annealing-oxygen electric furnace annealing, oxygen electric furnace annealing-ozone short-time annealing, or in a single electric furnace or two different electric furnaces. Ozone electric furnace annealing carried out in-Oxygen electric furnace annealing and the like. The type of annealing used is determined according to the ferroelectric properties required at the end of the manufacturing process. In a preferred embodiment, either ozone short-time annealing-oxygen electric furnace annealing or oxygen electric furnace annealing-ozone short-time annealing is utilized.

Next, as shown in FIG. 3, the upper electrode 16 is formed on the ferroelectric layer 14 by, for example, a deposition method by DC magnetron sputtering. The upper electrode 16 can be made of a noble metal such as platinum, gold, or molybdenum. The top electrode 16 preferably has a thickness of about 1500 angstroms (150 nanometers).

Next, the first photoresist pattern is provided on the upper electrode 16. This first photoresist pattern can be formed, for example, by photolithography. Next, the upper electrode 16 is defined based on the pattern. The upper electrode 16 is, for example, Freon-12 (trade name) (dichlorodifluoromethane: CCl).₂ F₂ ) It can be defined by anisotropic reactive ion etching using plasma. Sputter etching or ion milling (using a metal hardmask such as TiW) in an argon atmosphere can also be used to define the upper electrode 16. Next, the first photoresist pattern is removed. The resulting structure is shown in Fig. 4. This structure has a patterned top electrode 16.

Next, a second annealing, that is, an annealing of the entire laminate (12, 14, 16) is performed. This annealing is performed by an electric furnace annealing method or a short-time annealing method. In the case of a memory circuit, it is preferable to perform electric furnace annealing in an oxygen atmosphere at a certain temperature in the range of 650 ° C to 750 ° C for 1 hour. However, after short ozone annealing for 45 seconds at a temperature above 750 ° C, oxygen annealing may be performed in an electric furnace at a temperature of 750 ° C for 1 hour. Further, by pre-exposing the entire wafer to ozone for 30 minutes at a temperature higher than 450 ° C. prior to this second annealing, the ferroelectric properties that can be achieved by this annealing can be improved.

Next, in order to form or define the ferroelectric substance 14, a second photoresist pattern is provided on the ferroelectric layer 14 and the upper electrode 16 by a conventional method. In this case, the pattern of the ferroelectric layer 14 is determined by, for example, an optical lithography technique. After etching the exposed ferroelectric layer portion, the photoresist pattern is removed to obtain the structure of FIG. This structure has a patterned ferroelectric layer 14.

Next, in order to define the region of the lower electrode 12, a third photoresist pattern is provided by a usual method. In this case, after the lower electrode 12 is optically exposed for pattern formation, the exposed portion of the lower electrode is removed by etching. After that, the third photoresist is removed. FIG. 6 shows a structure with a patterned lower electrode 12.

Next, a third annealing is performed. This annealing is performed by electric furnace annealing at a temperature of 550 ° C for 1 hour in an oxygen atmosphere, or after exposing the structure to ozone for 30 minutes at a temperature in the range of 400 ° C to 450 ° C. It can be carried out by one of two steps of electric furnace annealing at a temperature of 550 ° C for 1 hour in an oxygen atmosphere.

Next, as shown in FIG. 7, the glass layer 18 is formed on the wafer. The glass layer 18 can be deposited by various methods. For example, a CVD method using oxygen and TEOS (Tetra-Ethyl-Ortho-Silicate) at 600 ° C or higher, oxygen (O) at 380 ° C or higher.₂ ) And monosilane (SiH)₄ ), The PECVD (Plasma Enhanced CVD) method using oxygen and TEOS at 390 ° C, or the Thermal CVD method using ozone and TEOS at 390 ° C. By using ozone in the atmosphere for depositing glass, the deterioration of the lower ferroelectric can be reduced. A preferred glass film laminate is ozone (O) by thermal CVD.₃ ) / TEOS glass followed by TEOS / oxygen (O) by PECVD₂ ) Consists of glass. The thickness of the glass layer 18 is about 5000 angstroms (500 nanometers).

Next, the first contact window 20 to the upper electrode 16 is formed by etching. Preferably, the first contact window 20 is formed by plasma etching through the glass layer 18 using a photoresist contact mask. Further, a second contact window 22 to the lower electrode 12 is formed through the glass layer 18 in the same manner. It is desirable that the two contact windows 20 and 22 are formed at the same time.

Next, a fourth annealing is performed. The fourth annealing can be performed as described above for the third annealing. After the fourth annealing, the contact window 24 to the substrate 8 is etched through the glass layer 18 and the poured glass layer 10. FIG. 8 shows the resulting structure.

Next, as shown in FIG. 9, a metal wiring layer (also referred to as an interconnect metal layer) 26 is provided on the glass layer 18 and in the contact windows (20, 22, 24), for example, by deposition by sputtering. .. The wiring layer 26 is composed of a TiN (titanium nitride) barrier layer and an Al-Si metal layer such as Al (aluminum) to which 1% by weight of Si (silicon) is added. The Al-Si metal layer is sputtered onto the lower TiN barrier layer (barrier layer) formed by sputtering. This barrier layer (barrier layer) functions to prevent the Al-Si metal and the upper and lower electrodes from interdiffusing during the subsequent annealing. The thickness of the TiN barrier layer is about 500 angstroms (50 nanometers), and the thickness of Al-Si metals ranges from 5000 angstroms (500 nanometers) to 8000 angstroms (800 nanometers).

Next, a fourth photoresist pattern is provided on the metal wiring layer 26 by a conventional method. Further, after etching the exposed metal wiring layer 26 portion, the fourth photoresist pattern is removed to obtain the structure shown in FIG. This structure has a patterned metal wiring layer 26.

The fifth annealing is then performed in an ozone and / or oxygen atmosphere. The fifth annealing is performed by an electric furnace annealing method or a short-time annealing method. Electric furnace annealing should be performed at temperatures below 450 ° C for only 30 minutes.

Next, as shown in FIG. 11, a flattened intermetal dielectric layer 28 is provided. The metal interlayer dielectric layer 28 is, for example, SiH.₄ (Monosilane) and N₂ Plasma enhanced chemical vapor deposition (PECVD oxide) / spin-on glass (SOG) / PECVD oxide of 0 (dinitrogen monoxide) alternately stacked, or PECVD oxide / TEOS-normal pressure of ozone CVD (APCVD) / PECVD oxides may be stacked alternately. Further, a fifth photoresist pattern is formed on the metal interlayer dielectric layer 28 by conventional means. Next, the exposed metal interlayer dielectric layer 28 is etched to form contacts (vias) to the first metal wiring layer 26. Further, the fifth photoresist pattern is removed to obtain the structure of FIG. On the dielectric layer 28, for example, a second metal wiring layer 29 made of aluminum containing 1% by weight of silicon or aluminum containing 1% by weight of silicon and 0.5% by weight of copper is provided. If necessary, a barrier layer such as TiN (titanium nitride) or TiW (tungsten / titanium) may be vapor-deposited under the second metal wiring layer 29.

The sixth annealing is then performed in an ozone and / or oxygen atmosphere to complete the structure of the present invention. The sixth annealing is carried out in the same manner as the fifth annealing described above. The steps of depositing and forming the metal interlayer dielectric layer 28 and depositing the metal wiring layer may be repeated as necessary to form a higher-order multi-stage wiring layer.

The above description merely provides a preferred example, and thus the present invention is not limited to the above-mentioned examples.

<figref num="1">A partial cross-sectional view of the substrate on which the ferroelectric layer should be formed.</figref><figref num="2">A partial cross-sectional view showing a structure in which a ferroelectric layer is formed on the lower electrode of FIG.</figref><figref num="3">FIG. 2 is a partial cross-sectional view showing a structure in which an upper electrode is formed on the ferroelectric layer of FIG.</figref><figref num="4">A partial cross-sectional view showing a state in which a part of the upper electrode is removed from the structure of FIG.</figref><figref num="5">A partial cross-sectional view showing a state in which a part of the ferroelectric layer is removed from the structure of FIG.</figref><figref num="6">A partial cross-sectional view showing a state in which a part of the lower electrode is removed from the structure of FIG.</figref><figref num="7">FIG. 6 is a partial cross-sectional view showing a structure in which a glass layer is formed on the upper electrode, the ferroelectric substance, and the lower electrode of FIG.</figref><figref num="8">FIG. 6 is a partial cross-sectional view showing a structure in which a contact window to an upper electrode, a ferroelectric substance, and a lower electrode is formed in the glass layer of FIG. 7.</figref><figref num="9">FIG. 8 is a partial cross-sectional view showing a structure in which a first metal wiring layer is formed on the glass layer of FIG.</figref><figref num="10">FIG. 9 is a partial cross-sectional view showing a structure in which a part of the metal wiring layer of FIG. 9 is removed.</figref><figref num="11">A partial cross-sectional view showing a state in which a metal interlayer dielectric layer is formed in the structure of FIG.</figref><figref num="12">FIG. 6 is a partial cross-sectional view showing a structure in which a second metal wiring layer is formed on the metal interlayer dielectric layer of FIG.</figref>

Code description

8: Substrate 10: Pour glass layer 12: Lower electrode 14: Ferroelectric layer 16: Upper electrode 18: Glass layer 20: First contact window 22: Second contact window 24: Contact window 26: Metal wiring layer 28: Inter Metal dielectric layer 29: Metal wiring layer