Decoding method, decoding apparatus and digital transmission system of product code

The present invention relates to a product code decoding method, a decoding device, and a digital transmission system applied to improve the reliability of a digital communication system or a digital recording system.

[0002] Conventional Techniques Conventionally, an error correction code such as a Reed-Solomon code has been applied in order to improve the reliability of a digital communication / recording system, but in recent years, as the speed and capacity of the system have increased. , It is necessary to apply a stronger error correction code. Generally, a code having a high correction ability has a high decoding complexity and is difficult to make into a device, but a high-performance code can be realized relatively easily by using a method of a concatenated code or a product code. In particular, the product code has the advantage of having high redundancy and high correction capability because it encodes information data twice, and is applied to error correction methods for CD-ROMs and DVDs.

[0003] FIG. 9 is an explanatory diagram showing the configuration of the product code. The vertical code is a binary linear code C1 having a code length N1 and an information length K1, and the horizontal code is a code length N2 and an information length K2. The original linear code C2. In the figure, block 1 represents information data, and blocks 2 to 4 represent check (redundancy).

[0004] Next, a method of coding the product code will be described with reference to FIG. First, the information data K1 and K2 bits are stored in a two-dimensional array (block 1) of K1 rows and K2 columns. Here, the following equation (1) represents block 1. However, D_{i, j}(i = 1,2, ..., K1, j = 1,2, ..., K2) represents the binary number 0 or 1.

[Number 1]<img file="JP3889286B2_D0001.tif" />Next, a C1 code check (N1-K1 bits) is added to each column from the first column to the K2 column to generate a two-dimensional array of N1 rows and K2 columns as a whole (block 2). Generation). Next, a C2 code check (N2-K2 bits) is added to the 1st to N1st rows to generate a product code of N1 rows and N2 columns as a whole (generation of blocks 3 and 4).

[0006] FIG. 10 is a configuration diagram showing, for example, a conventional digital transmission system shown in Japanese Patent Application Laid-Open No. 7-202722. In the figure, 1 is a code for encoding input information data to generate a product code. Chemical device, 2 is a modulator that converts the product code generated by the encoder 1 into a signal suitable for the communication path 3, 3 is the communication path, and 4 is the demodizing and decoding of the received signal supplied from the communication path 3. The demodulator that supplies the demodulated data to the device 5 is a decoder that decodes the demodulated data supplied from the demodulator 4 and estimates the information data. The transmitter is composed of the encoder 1 and the modulator 2, and the receiver is composed of the demodulator 4 and the decoder 5.

[0007] Next, the operation will be described. The input information data K1 and K2 bits are supplied to the encoder 1 to generate the product code of N1 rows and N2 columns described above. The matrix C in Eq. (2) below represents the generated product code. The element of the product code C is represented by a binary number 0 or 1, but in the following, the binary number 0 is represented by "+1" and the binary number 1 is represented by "-1".

[Number 2]<img file="JP3889286B2_D0002.tif" />[0008] The product code generated in the encoder 1 is supplied to the modulator 2, converted into a signal suitable for the communication path 3, and sent to the communication path 3. It is assumed that additive noise is superimposed on the transmission signal in the communication path 3. The signal received via the communication path 3 is supplied to the demodulator 4 of the receiver.

[0009] In the demodulator 4, the received signal is shaped and demodulated data is generated. The matrix Y in Eq. (3) below represents the demodulated data. However, each component of the matrix Y is Y_{i, j}= C_{i, j}+ N_{i, j}(N_{i, j}Is a noise component). The demodulated data generated by the demodulator 4 is supplied to the demodulator 5 to estimate the transmitted information data.

[Number 3]<img file="JP3889286B2_D0003.tif" />[0010] In the following, the matrix is distinguished by the curly braces and the vector by the brackets. For example, the demodulated data of Eq. (3) is expressed as {Y} (hereinafter referred to as the input matrix). Also, the first column (N1 dimensional vector) of the input matrix {Y} is set to [V._{k, 1}], Especially when clarifying the range of the subordinate index k [V_{k, 1}] (K = 1,2, ..., N1).

FIG. 11 is a flowchart for explaining the operation of the decoder 5. In the figure, ST1 is an input step of an input matrix {Y}, and ST2 is an initial value in a correction matrix {W} and a determination matrix {D}. Step, ST3 is the step to set the initial value to the counter j, ST4 is the soft input vector [R_k] (K = 1,2, ..., N1), ST5 is the soft output vector [L_k] (K = 1,2, ..., N1), ST6 is the step to update the correction matrix {W}, ST7 is the step to compare the value of counter j, ST8 is the step to increment counter j. Is.

[0012] ST9 is the step of setting the initial value in the counter i, and ST10 is the soft input vector [R]._k] (K = 1,2, ..., N2) calculation step, ST11 is the soft output vector [L_k] (K = 1,2, ..., N2), ST12 is the step to update the correction matrix {W}, ST13 is the step to compare the value of counter i, ST14 is the step to increment counter i. , ST15 is a step of determining whether or not to repeat the decoding of the product code, and ST16 is a step of outputting the determination matrix {D}.

Next, the operation of the decoder 5 will be described with reference to FIG. First, in step ST1, the input matrix {Y} (Equation 3) of N1 rows and N2 columns is input. Next, in step ST2, the initial value 0 is stored in all the elements of the correction matrix {W} (Equation 4) of N1 row and N2 column.

[Number 4]<img file="JP3889286B2_D0004.tif" />Further, the initial value sgn {Y} is stored in the determination matrix {D} of N1 rows and N2 columns. That is, the (i, j) component D of the determination matrix {D}_{i, j}In addition, the (i, j) component Y of the input matrix {Y}_{i, j}Sign sgn (Y_{i, j}) Is substituted. However, sgn is a function defined by the following equation (5).

[Number 5]<img file="JP3889286B2_D0005.tif" />[0015] In step ST3, the initial value 1 is set in the counter j. Next, in step ST4 and subsequent steps, decoding of the C1 code is started. In step ST4, the jth column of the input matrix {Y} and the jth column of the correction matrix {W} are added for each component. That is, the (k, j) element Y of the input matrix according to the following equation (6)._{k, j}And the (k, j) element W of the correction matrix_{k, j}Is added, and the soft input value R_kCalculate (k = 1,2, ..., N1). However, α in Eq. (6) is an appropriate normalization constant. R_k Y_{k, j}+ α W_{k, j}(k = 1,2, ..., N1) (6) [0016] In the following, the jth column of the input matrix is set to [Y] according to the above-mentioned literature._{k, j}], The jth column of the decision matrix is [D_{k, j}], The jth column of the correction matrix is [W_{k, j}], And will be called the input vector, the decision vector, and the correction vector, respectively. In step ST5, the decision vector [D_{k, j}] Is updated and the soft output vector [L_k] (K = 1,2, ..., N1) is calculated. The detailed operation of step ST5 will be described later.

In step ST6, as shown in the following equation (7), the soft output vector calculated in step ST5 minus the soft input vector is stored in the j-th column of the correction matrix {W}. W_{k, j} L_k-R_k(k = 1,2, ..., N1) (7) [0018] Next, in step ST7, it is determined whether or not the value of the counter j is less than N2, and if it is less than N2, the counter j is set. Increment (step ST8) and repeat the processing after step ST4. On the other hand, if the value of the counter j is N2, the process proceeds to step ST9 to start decoding the C2 code. At this point, all the elements of the correction matrix {W} have been updated.

[0019] In step ST9, the initial value 1 is set in the counter i, and the process proceeds to step ST10. In step ST10, the i-th row of the input matrix {Y} and the i-th row of the correction matrix {W} are added for each component. That is, the (i, k) element Y of the input matrix according to the following equation (8)._{i, k}And the (i, k) element W of the correction matrix_{i, k}Soft input value R by adding_kCalculate (k = 1,2, ..., N2). However, α in Eq. (8) is an appropriate normalization constant. R_k Y_{i, k}+ α W_{i, k}(k = 1,2, ..., N2) (8) [0020] Similar to the decoding of the C1 code described above, the i-th row of the input matrix is [Y._{i, k}], The i-th row of the decision matrix is [D_{i, k}], The i-th row of the correction matrix is [W_{i, k}], And will be called the input vector, the decision vector, and the correction vector, respectively. In step ST11, the decision vector [D_{i, k}] Is updated and the soft output vector [L_k] (K = 1,2, ..., N2) is calculated. The detailed operation of step ST11 will be described later.

[0021] In step ST12, as shown in the following equation (9), the soft output vector calculated in step ST11 minus the soft input vector is stored in the i-th row of the correction matrix {W}. W_{i, k} L_k-R_k(k = 1,2, ..., N2) (9) [0022] Next, in step ST13, it is determined whether or not the value of the counter i is less than N1, and if it is less than N1, the counter i is set. Increment (step ST14), and repeat the processing after step ST10. On the other hand, if the value of the counter i is N1, the process proceeds to step ST15. At this point, one decoding of each of the C1 code and the C2 code constituting the product code is completed.

[0023] In step ST15, it is determined whether or not to repeat the decoding of the C1 code again. Usually, the decoding process is terminated when the repeated decoding is completed a predetermined number of times. If the decoding of the C1 code is repeated, the process proceeds to step ST3, and the above-mentioned decoding of the C1 code is restarted. On the other hand, if the decoding is not repeated, the process proceeds to step ST16, the determination matrix {D} is output, and the decoding process is completed.

[0024] The component D stored in the K1 row and K2 column of the determination matrix {D} output in step ST16._{i, j}(i = 1,2, ..., K1, j = 1,2, ..., K2) represents the information data estimated by decoding. The component of the determination matrix {D} is "± 1", but "+1" corresponds to the binary number 0 and "-1" corresponds to the binary number 1.

Next, the soft input soft output decoding of the C1 code in step ST5 will be described. FIG. 12 is a flowchart showing the detailed processing contents of step ST5. In step ST21, the soft input vector [R_k] And the decision vector [D_k] Is entered. In step ST22, the soft input vector [R_k], Select the p elements with the smallest absolute value, and set the p positions to k1, k2, ..., kp.

[0026] In step ST23, at the p positions km (m = 1,2, ..., p) selected in step ST22, T_km= 0 or 1, otherwise T_kTest vector with = 0 (k km) [T_k] Is generated. As a test vector, q = 2 in total^pSince there are, add the subscript s [T^s] (S = 1,2, ..., q). Generated test vector [T^s] And the decision vector [D_k] Is added for each component to perform algebraic decoding of the C1 code [U]^s] Is generated. In equation (10) below, [D_k] Component "+1" is converted to binary "0", "-1" is converted to binary "1" and added under method 2.

[U^s] = [D_k] + [T^s] (s = 1,2, ..., q) (10) [0027] In step ST24, q words [U] generated in step ST23.^s] (S = 1,2, ..., q) performs algebraic decoding of the C1 code to generate codeword candidates. [C] r different codewords generated by decoding^t] = (C^t₁, C^t₂, .., C^t_N1) (T = 1,2, ..., r). However, the codeword component is represented by a real number, and the binary number "0" is converted to "+1" and the binary number "1" is converted to "-1".

[0028] In step ST25, the soft input vector [R]_k] And candidate codeword [C^t] (T = 1,2, ..., r) squared Euclidean distance M^tTo calculate. Soft input vector [R_k] And candidate codeword [C^t] Squared Euclidean distance M^tIs given by the following equation (11).

[Number 6]<img file="JP3889286B2_D0006.tif" />[0029] In step ST26, a codeword [C] that gives the minimum value of the Euclidean distance calculated in step ST25.^d], That is, the inequality for the following Euclidean distance, M^t M^dCodewords that satisfy (t = 1,2, ..., r) [C^d] Is detected and substituted into the determination vector [D] as shown in the following equation (12).

[D] [C^d] (12) [0030] In step ST27, the initial value 1 is set in the counter k and the process proceeds to step ST28. In step ST28, the candidate codeword [C^t] (T = 1,2, ..., r) kth component C^t_kWas selected in step ST26 [C^d] Kth component C^d_kCodeword different from (C^t_k=-C^d_kCodeword [C^t]) Is present or not. If it does not exist, proceed to step ST29, and if it does exist, in step ST30, the codeword with the smallest Euclidean distance among such codewords (called concurrent codewords, [C]^c] To proceed to step ST31. In step ST29, the soft output value shown in the following equation (13) is calculated. However, β is an appropriate normalization constant. L_k βC^d_k (13) [0031] In step ST31, the soft output value shown in the following equation (14) is calculated. However, M^cIs a concurrent codeword [C^c] And soft input vector [R_k] To the square Euclidean distance between. L_k ((M^c-M^d) / 4) C^d_k (14) In step ST32, it is determined whether or not the value of the counter k is equal to N1. If they are not equal, the process proceeds to step ST33, the value of the counter k is incremented, and the processes after step ST28 are repeatedly executed. On the other hand, if they are equal, the process proceeds to step ST34 and the soft output vector [L_k] And the decision vector [D_k] Is output to end all processing.

[0033] By the above processing, the soft input soft output decoding of the C1 code in step ST5 is completed. Since the soft input soft output decoding of the C2 code in step ST11 is the same as the soft input soft output decoding of the C1 code described above, the description thereof will be omitted. As can be seen from Eqs. (13) and (14), the conventional soft output value is calculated using at most two of the candidate codewords generated in step ST24.

[0034] [Problem to be Solved by the Invention] Since the conventional decoding method is configured as described above, when calculating the soft output value, Euclidean is used among a large number of codewords found in the codeword generation step. The codeword closest to the soft input vector in terms of distance [C^d] And concurrent codewords [C^s] Is reflected, but the information of other candidate codewords is not reflected at all, and there is a problem that the soft output value cannot be calculated accurately.

Further, in the calculation of the soft output shown in Eq. (14), the soft input vector [R]_k] And candidate codeword [C^d] And concurrent codewords [C^c] Squared Euclidean distance M^d, M^cHowever, the calculation of the square Euclidean distance requires a large amount of calculation, and there is a problem that the circuit scale becomes large when it is realized by hardware. In addition, the above-mentioned decoding method is intended for floating-point processing, and has a problem that it is not suitable for fixed-point processing. In particular, when the demodulated data is represented by the hard judgment value and its reliability information, it is necessary to develop an applicable decoding method and decoding device.

[0036] The present invention has been made to solve the above-mentioned problems, and it is possible to accurately calculate a soft output value by efficiently utilizing the generated codeword candidates, and the amount of calculation. It is an object of the present invention to obtain a product code decoding method, a decoding device and a digital transmission system capable of reducing the circuit scale.

[Means for Solving the Problems] In the decoding method according to the present invention, a code word is generated from the position of the soft input value detected by the detection step and the syndrome calculated by the syndrome calculation step, and a sequence error is obtained. Along with generating the position set<u style="single">Calculate the sum of the soft input values at the error positions included in the error position set of the series as the correlation mismatch amount.</u>A codeword generation step is provided<u style="single">Of that series</u>The correction information is updated based on the error position set and the amount of correlation mismatch.

[0038] In the decoding method according to the present invention, an error position set having a small number of elements is preferentially selected and output to the update step.

[0039] In the decoding method according to the present invention, the amount of correlation mismatch corresponding to the error position set including the position of the binary linear code is sequentially compared, the error position set having the smallest amount of correlation mismatch is selected, and the error is selected. The correction value is added to the position set to calculate the first correlation mismatch amount, and the correlation mismatch amount corresponding to the error position set that does not include the position of the binary linear code is sequentially compared, and the correlation mismatch amount is the largest. Select a small error position set, add a correction value to the error position set to calculate the second correlation mismatch amount, while subtracting the second correlation mismatch amount from the first correlation mismatch amount to determine the likelihood. Is calculated, and the correction information is updated based on the likelihood.

[0040] In the decoding method according to the present invention, when the updated correction information is composed of a hard judgment value indicating a correction flag, the hard judgment value of the correction information and the hard judgment value of the demodulated data are added. It is designed to generate decoded data with a binary linear code.

[0041] The decoding device according to the present invention is<u style="single">One C1 code decoding means</u>Correction information and demodulated data multiplexed by the multiplexing means<u style="single">N1 in parallel</u>The correction information is updated by inputting and performing soft input soft output decoding of the C1 code, and the binary linear code is decoded from the updated correction information and demodulated data.

[0042] The decoding apparatus according to the present invention generates a code word from the position of the soft input value output from the low-reliability position detection circuit and the syndrome calculated by the syndrome calculation circuit to generate an error position set of the sequence. With<u style="single">Calculate the sum of the soft input values at the error positions included in the error position set of the series as the correlation mismatch amount.</u>A codeword generation circuit is provided<u style="single">Of that series</u>The correction information is updated based on the error position set and the amount of correlation mismatch.

[0043] In the decoding apparatus according to the present invention, when the corrected correction information after the update is composed of a hard judgment value indicating a correction flag, the hard judgment value of the correction information and the hard judgment value of the demodulated data are added. It is designed to generate decoded data with a binary linear code.

[0044] The decoding device according to the present invention supplies the updated correction information and demodulated data output from the C1 code decoding means to the separation means to perform cyclic decoding.

[0045] The decoding device according to the present invention is designed to output the updated correction information and the demodulated data output from the C1 code decoding means to the next-stage decoding device having the same configuration in which the demodulation data is connected in multiple stages. ..

[0046] The decoding device according to the present invention is provided with an error number measuring circuit that measures the number of errors by comparing the rigid determination values of the decoding data output from the C1 code decoding means and the demodulated data.

[0047] The decoding device according to the present invention is provided with a rigid determination decoding circuit that performs rigid determination decoding of a C1 code or a C2 code with respect to the decoding data output from the C1 code decoding means.

[0048] The decoding apparatus according to the present invention is an error detection circuit that calculates a syndrome of a C1 code or a C2 code for the decoding data output from the C1 code decoding means and detects an error in the decoded data based on the syndrome. Is provided.

[0049] In the digital transmission system according to the present invention, the decoding device transmits correction information and demodulated data multiplexed by the multiplexing means.<u style="single">N1 in parallel</u>Input and update the correction information by performing soft input soft output decoding of the C1 code, and decode the binary linear code from the updated correction information and demodulated data.<u style="single">1</u>It is provided with a C1 code decoding means.<u style="single">In addition, a code word is generated from the position of the soft input value output from the low-reliability position detection circuit and the syndrome calculated by the syndrome calculation circuit to generate an error position set of the series, and the error position set of the series is used. A codeword generation circuit that calculates the sum of the soft input values at the included error positions as the correlation mismatch amount is provided, and the correction information is updated based on the error position set and the correlation mismatch amount of the series.</u>[0050] In the digital transmission system according to the present invention, the transmission medium is a recording medium.

[0051] The digital transmission system according to the present invention calculates the syndrome of the C1 code or the C2 code for the decoded data output from the C1 code decoding means, and when an error in the decoded data is detected based on the syndrome, it transmits. A retransmission requesting means for outputting a retransmission request for a modulated signal to the machine is provided.

[0052] The digital transmission system according to the present invention is provided with a synthesis means for diversifying the demodulated data output from the demodulator before the retransmission request and the demodulated data output from the demodulator after the retransmission request. is there.

[Embodiments of the Invention] Hereinafter, an embodiment of the present invention will be described. Embodiment 1. FIG. 1 is a configuration diagram showing a product code decoding device according to the first embodiment of the present invention. In the figure, 11, 12, and 13 are product code repetitive element decoders, and repetitive element decoding. Input terminals A of the devices 11, 12, and 13 are terminals for inputting demographic data, input terminal B is a terminal for inputting correction information used for decoding, and output terminal C decodes democratized data supplied from terminal A. The terminal for later output, the output terminal D is the terminal for outputting the updated correction information, and the output terminal E is the terminal for outputting the decoded data.

[0054] Next, the operation will be described. Here, the product code will be used, and it is assumed that both the C1 code and the C2 code are Hamming codes, the parity check matrix of the C1 code is H1, and the parity check matrix of the C2 code is H2. The parity check matrix H1 is expressed by the following equation (15) using the primitive element α of the appropriate Galois field. Similarly, the parity check matrix H2 is also expressed by the following equation (16) using the primitive element β of the appropriate Galois field. It is also assumed that the product code of N1 rows and N2 columns is transmitted column by column (in parallel with N1 bits) in the coding direction of the C2 code.

[Number 7]<img file="JP3889286B2_D0007.tif" />[0055] The demodulated data of the product code is supplied to the input terminal A of the repeating element decoder 11 one column at a time. The demodulated data for one transmission bit is composed of a hard judgment value (1 bit) and reliability information (m bits) for the hard judgment value, and the input terminal A has one column of demodulated data (N1 bits), that is, N1. (1 + m) bits of data are supplied in parallel.

[0056] The initial value of the correction information for the demodulated data described above is supplied to the input terminal B of the repeating element decoder 11 one column at a time. The correction information for one transmission bit is composed of a hard judgment value (1 bit) and a reliability information (n bits) for the hard judgment value, and the input terminal B has one column of correction information (N1 bit), that is, N1. (1 + n) bits of data are supplied in parallel. However, as the initial value of the correction information, the hardness determination value is set to 0, and the reliability information is set to the lowest reliability value (for example, 0). The bit width m of the reliability information of the demodulated data and the bit width n of the reliability information of the correction information can be arbitrarily set, but in the following, it is assumed that n is larger than m.

[0057] The above-mentioned correction information is information indicating whether or not there is an error in the demodulated data, and if the hardness determination value of the correction information is 1, it indicates that the hardness determination of the demodulated data is incorrect, and conversely 0. If so, it indicates that the hard judgment of the demodulated data is correct. Further, the reliability information of the correction information is the reliability associated with the hard judgment value. For example, if the hard judgment value is 1 and the reliability information is large, it indicates that the hard judgment of the demodulated data is incorrect with a high probability. ing. In the initial stage, it is assumed that the hardness judgment value of the correction information is 0, that is, the hardness judgment of the demodulated data is correct, and the lowest value is set for the reliability information.

[0058] The demodulated data of the product code supplied to the input terminal A is output one column at a time from the output terminal C of the repeating element decoder 11 after the decoding process in the repeating element decoder 11 is completed, and at the same time. The correction information updated by the iterative element decoder 11 is output from the output terminal D in parallel with the demodulated data. Further, the decoding data of the product code estimated by the repeating element decoder 11 is output from the output terminal E one column at a time.

[0059] The demodulated data of the product code output from the output terminal C of the repeating element decoder 11 is supplied to the input terminal A of the repeating element decoder 12, and the output terminal of the repeating element decoder 11 is supplied to the input terminal B. The correction information output from D is supplied. Further, the demodulated data (rigidity determination value and reliability information) of the product code supplied to the input terminal A of the iterative element decoder 12 is collected by the iterative element decoder 12 after the decoding process in the iterative element decoder 12 is completed. The output terminal C outputs one column at a time in the order of input, and at the same time, the correction information updated by the iterative element decoder 12 is output one column at a time from the output terminal D. Further, the decoding data estimated by the repeating element decoder 12 is output from the output terminal E.

[0060] In the same manner below, the demodulated data of the product code (hardness determination value and reliability information) and the correction information updated by the iterative element decoder are supplied to the iterative element decoder in the next stage, and the correction information and the decoding are performed. The data will be updated again. The reliability of the decoded data is improved with each update, and the transmission data is estimated from the decoded data of the iterative element decoder in the final stage.

[0061] Fig. 2 is a configuration diagram showing a repeating element decoder. In the figure, 21 is a soft input soft output of N1 C2 codes by separating the demodulated data and the correction information for one column of the product code. Demultiplexer (separation means) that supplies demographic data and correction information to decoders 22A, 22B, 22C, 22A, 22B, 22C inputs demoxer data and correction information of C2 code separated by demultiplexer 21 and C2 It is a C2 code soft input soft output decoder (C2 code decoding means) that updates the correction information by performing soft input soft output decoding of the code and outputs the updated correction information and the above-mentioned demodulated data.

[0062] 23 is a multiplexer (multiplexer) that multiplexes the C2 code demodulation data and correction information output from the soft input soft output decoders 22A, 22B, 22C of N1 C2 code, and 24 is a multiplexer (multiplexer 23). The corrected information is updated by inputting the multiplexed correction information and the demodulated data and performing soft input soft output decoding of the C1 code, and the binary linear code is decoded from the updated corrected information and the demodulated data. It is a C1 code soft input soft output decoder (C1 code decoding means).

[0063] Next, the operation of the iterative element decoder will be specifically described. The demodulated data N1 (1 + m) bits and the correction information N1 (1 + n) bits for one column of the product code supplied to the input terminal A of the repeating element decoder are the N1 C2 codes in the demultiplexer 21. It is separated into a demodulation data (1 + m) bit and a correction information (1 + n) bit, and is supplied to the soft input soft output decoder with the corresponding C2 code. Therefore, every time the demographic data is supplied to the input terminal A, the demodulation data (1 + m) bits and the correction information (1 + n) bits are totaled (2 + m) to the N1 C2 code soft input soft output decoder. + n) Bits are supplied.

[0064] Next, the configuration and operation of the C2 code soft input soft output decoders 22A, 22B, and 22C will be described. Since the configurations and operations of the N1 C2 code soft input soft output decoders 22A, 22B, and 22C are the same, the configuration and operation of the soft input soft output decoder 22A will be described below. The demodulation data and correction information corresponding to the first line of the product code shown in the equation (2) are supplied to the soft input soft output decoder 22A of the C2 code. Set the hardness judgment value of the kth (k = 1,2, ..., N2) demodulated data to Y._k(Y_kIs 0 or 1), its reliability information is Z_k(Z_kIs a positive integer of m bits), and the hard judgment value of the kth correction information is V_k(V_kIs 0 or 1), its reliability information is W_k(W_kIs an n-bit positive integer). The hard input soft output decoder 22A of the C2 code is supplied with the hard judgment value and reliability information of the demodulated data and the hard judgment value and reliability information of the correction information.

FIG. 3 is a configuration diagram showing a C2 code soft input soft output decoder 22A. In the figure, 31 is an input terminal for inputting a hard determination value (1 bit) of demodulated data, and 32 is a reliability of demodulated data. Input terminal for inputting degree information (m bits), 33 is an input terminal for inputting correction information hardness judgment value (1 bit), 34 is an input terminal for inputting correction information reliability information (n bits), 35 is The memory for delaying the rigid determination value of the demodulated data, and 36 is the memory for delaying the reliability information of the demodulated data.

37 is a soft input value calculation circuit that calculates an error pattern and a soft input value from the reliability information of the demodulated data, the hard judgment value of the correction information, and the reliability information, 38 is a soft input value calculation circuit 37 is a soft input value. Is a low-reliability position detection circuit that detects p soft input values in order from the smallest soft input value and outputs the position of the soft input value, 39 is the error pattern and input calculated by the soft input value calculation circuit 37. An adder that adds the rigid judgment values of the demodulated data supplied from the terminal 31 to generate a series, 40 is a syndrome calculation circuit that calculates the syndrome of the series generated by the adder 39, and 41 is a soft input value calculation circuit 37. 42 is a memory for delaying the soft input value calculated by, and 42 is a memory for delaying the error pattern calculated by the soft input value calculation circuit 37.

[0067] 43 generates a codeword from the position of the soft input value output from the low-reliability position detection circuit 38 and the syndrome calculated by the syndrome calculation circuit 40 to generate an error position set of the above series, and also generates an error position set of the above series.<u style="single">Calculate the sum of the soft input values at the error positions included in the error position set of the series as the correlation mismatch amount.</u>C2 code word candidate generation circuit (code word generation circuit), 44 is the reliability information of the demodulated data stored in the reliability information memory 36, and the soft input value and error pattern memory 42 stored in the soft input memory 41. It is a soft output value calculation circuit that updates the hard judgment value and reliability information of correction information from the error pattern stored in.

[0068] 45 is an output terminal that outputs a rigid determination value (1 bit) of the demodulated data, 46 is an output terminal that outputs reliability information (m bits) of the demodulated data, and 47 is calculated by the soft output value calculation circuit 44. The output terminal that outputs the hard judgment value (1 bit) of the correction information, and 48 is the output terminal that outputs the reliability information (n bits) of the correction information calculated by the soft output value calculation circuit 44. FIG. 5 is a flowchart showing the operation of the soft input value calculation circuit 37, FIG. 6 is a flowchart showing the operation of the soft output value calculation circuit 44, and FIG. 7 is a flowchart showing a method of updating correction information in the soft output value calculation circuit 44. ..

[0069] The hard determination value of the demodulated data supplied to the input terminal 31 is supplied to the adder 39 and stored in the hard determination memory 35. At the same time, the reliability information of the demodulated data is supplied to the soft input value calculation circuit 37 and stored in the reliability information memory 36. Further, the rigid determination value and the reliability information of the correction information supplied to the input terminal 33 and the input terminal 34 are supplied to the soft input value calculation circuit 37.

[0070] First, in step ST41, the soft input value calculation circuit 37 substitutes the initial value 1 for the counter k, and proceeds to step ST42. In step ST42, the reliability information W of the kth bit is shown in the following equation (17)._kIs multiplied by a constant to proceed to step ST43. However, the constant γ in Eq. (17) is a constant that is appropriately set according to the number of repeated decodings and the characteristics of the communication path. W_k γ W_k (17) Next, in step ST43, the hardness determination value V of the correction information._kIf is 0, proceed to step ST44, otherwise proceed to step ST45. In step ST44, as shown in the following equations (18) and (19), the k-bit error pattern E_kSubstitute 0 for the k-th soft input value F_kDemodulation data reliability information Z_kAnd the reliability information W of the correction information_kSum (Z)_k+ W_k) Is substituted to proceed to step ST48. However, sum (Z_k+ W_kIf) exceeds n bits, set an appropriate numerical value represented by n bits or less. E_k 0 (18) F_k Z_k+ W_k (19) [0072] In step ST45, the reliability information Z of the demodulated data._kAnd the reliability information W of the correction information_kThe reliability information Z of the demodulated data by comparing the magnitude of_kIs the reliability information W of the correction information_kIf it is larger, the error pattern E of the kth bit is shown in the following equations (20) and (21)._kSubstitute 0 for the soft input value F_kDemodulation data reliability information Z_kReliability information of correction information from W_kSubtracted (Z_k-W_k) Is substituted (step ST46). E_k 0 (20) F_k Z_k-W_k (21) [0073] On the other hand, the reliability information Z of the demodulated data._kIs the reliability information W of the correction information_kIf it is not larger, the error pattern E is shown in the following equations (22) and (23)._kSubstitute 1 for the soft input value F_kReliability information of correction information W_kDemodulation data reliability information from Z_kSubtracted (W)_k-Z_k) Is substituted (step ST47), and the process proceeds to step ST48. E_k 1 (22) F_k W_k-Z_k (23) [0074] In step ST48, it is determined whether or not the counter k is N2 (code length of C2 code) or less. If the counter k is N2 or less, the counter k is incremented in step ST49, and the processes after step ST42 are repeatedly executed. On the other hand, if the value of the counter k is equal to N2, it ends.

[0075] An error pattern E calculated in the soft input value calculation circuit 37._k(k = 1,2, ..., N2) is stored in the error pattern memory 42 and supplied to the adder 39. In the adder 39, as shown in the following equation (24), the hardness determination value Y of the demodulated data supplied from the input terminal 31_kAnd error pattern E_kThere adding (discharge is another disjunction), sequence X_kIs generated. Generated series X_kIs supplied to the syndrome calculation circuit 40. X_k Y_k+ E_k (24) [0076] In the syndrome calculation circuit 40, the series X_kSyndrome S is calculated. Syndrome S is calculated by the following equation (25). However, X is a row vector (X₁, X₂, ..., X_N2) Is a transposed column vector. The syndrome S calculated by the syndrome calculation circuit 40 is supplied to the C2 codeword candidate generation circuit 43. S = H2 · X (25) [0077] On the other hand, the soft input value F calculated in the soft input value calculation circuit 37._k(k = 1,2, ..., N2) is stored in the soft input memory 41 and supplied to the low reliability position detection circuit 38. In the low reliability position detection circuit 38, the supplied soft input value F_kDetects p pieces with the smallest value in order from the minimum value of (k = 1,2, ..., N2), and notifies the C2 codeword candidate generation circuit 43 of the position. Here, p = 3 and its positions are assumed to be l1, l2, and l3.

[0078] In the C2 codeword candidate generation circuit 43, the syndrome S calculated in the syndrome calculation circuit 40 and the modified syndrome S [k] (k =) from the positions l1, l2, and l3 detected in the low-reliability position detection circuit 38. 0,1, ..., 7) is calculated as follows. S [0] SS [1] S [0] + β^l1S [2] S [0] + β^l2S [3] S [1] + β^l2S [4] S [0] + β^l3S [5] S [1] + β^l3S [6] S [2] + β^l3S [7] S [3] + β^l3Further, the error position set is set as follows for each calculated correction syndrome S [k] (k = 0,1, ···, 7). However, Φ represents an empty set. E [0] = ΦE [1] = {l1} E [2] = {l2} E [3] = {l1, l2} E [4] = {l3} E [5] = {l1, l3} E [6] = {l2, l3} E [7] = {l1, l2, l3} [0080] From each modified syndrome S [k] (k = 0,1, ..., 7), on the Galois field The error position is calculated by algebraic arithmetic processing or by referring to the table that stores the error position with respect to the syndrome. The error position of the corrected syndrome S [k] is set to 1 [k]. If the erroneous position 1 [k] is included in the erroneous position set E [k], 1 [k] is deleted from E [k], and if it is not included, 1 [k] is added to the erroneous position set E [k]. Add to [k].

[0081] If the error position sets E [k1] and E [k2] are equal for different k1 and k2 due to the addition and deletion of the error positions, one of them is rejected, and only the different error position sets are displayed below. Think about it and define the set again as E [k] (k = 1,2, ..., K). However, K represents the number of different error position sets.

Next, the C2 codeword candidate generation circuit 43 has a correlation mismatch shown in the following equation (26) based on the calculated error position set E [k] (k = 1,2, ···, K). Calculate the quantity CM [k]. Each calculated error position set E [k] and the correlation mismatch amount CM [k] are supplied to the soft output value calculation circuit 44.

[Number 8]<img file="JP3889286B2_D0008.tif" />[0083] In the soft output value calculation circuit 44, the soft input value F supplied from the soft input memory 41._k(k = 1,2, ..., N2) and the error pattern E supplied from the error pattern memory 42._k(k = 1,2, ..., N2), each error position set E [k] supplied from the C2 codeword candidate generation circuit 43, and the correlation mismatch amount CM [k] (k = 0,1,1, ..., K) and update the error pattern and soft input value.

[0084] Hereinafter, the operation of the soft output value calculation circuit 44 will be described in detail. The soft output value calculation circuit 44 first sets the initial value 1 in the counter i in step ST51, and proceeds to step ST52. Here, the counter i indicates the bit positions 1, 2, ..., N2 of the C2 code. In step ST52, the initial value 1 is set in the counter k, the initial value M is set in the registers L0 and L1, and the process proceeds to step ST53. However, M is a sufficiently large constant that registers L0 and L1 can represent.

[0085] In step ST53, it is determined whether or not the value of the counter i is included in the error position set E [k]. If the value of the counter i is included in the error position set E [k], the process proceeds to step ST54, and if it is not included, the process proceeds to step ST55.

[0086] In step ST54, the register L0 is updated according to the following equation (27), and the process proceeds to step ST56. L0 f (L0, CM [k]) (27) However, f is a function defined by the following equation (28). Here, min (X, Y) is a function that selects the smaller of X and Y, and T is a function that returns an appropriate value for the absolute value | XY | of the difference between X and Y. If the function f is negative, perform appropriate processing such as replacing it with 0. f (X, Y) = min (X, Y) -T (| XY |) (28) [0087] On the other hand, in step ST55, register L1 is updated according to the following equation (29), and the process proceeds to step ST56. .. However, the function f in Eq. (29) is the same as that defined in Eq. (28). L1 f (L1, CM [k]) (29) [0088] In step ST56, it is determined whether or not the value of the counter k is smaller than K. If the value of the counter k is smaller than K, the process proceeds to step ST57, the counter k is incremented, and the processes after step ST53 are repeatedly executed. On the other hand, if the value of the counter k is equal to K, the process proceeds to step ST58.

[0089] In step ST58, it is determined whether or not the values of the registers L0 and L1 are smaller than the constant M. If the values of registers L0 and L1 are both smaller than the constant M, the process proceeds to step ST59. In step ST59, the soft input value F is according to the following equation (30)._kUpdate and proceed to step ST60. F_k L0-L1 (30) [0090] In step ST60, the updated soft input value F_kIs determined to be negative. Soft input value F_kIf is negative, proceed to step ST61, otherwise proceed to step ST65. In step ST61, the error pattern E is based on the following equations (31) and (32)._kAnd soft input value F_kIs updated. However, equation (31) is the addition of method 2, and equation (32) is a general addition on integers. C1 in Eq. (32) is an appropriate constant. E_k E_k+1 (31) F_k -F_k+ C1 (32) [0091] On the other hand, in step ST58, if any of the registers L0 and L1 is equal to the constant M, the process proceeds to step ST62. In step ST62, it is determined whether or not the contents of register L0 are smaller than the constant M. If register L0 is less than the constant M, go to step ST63, otherwise go to step ST64.

[0092] In step ST63, the error pattern E is based on the following equations (33) and (34)._kAnd soft input value F_kTo update. However, C2 in Eq. (34) is an appropriate constant. E_k E_k+1 (33) F_k F_k+ C2 (34) [0093] On the other hand, in step ST64, the soft input value F is calculated by the following equation (35)._kTo update. However, C3 is an appropriate constant. In addition, error pattern E_kWill not be updated. F_k F_k+ C3 (35) [0094] In step ST65, it is determined whether or not the counter i is smaller than N2. If the counter i is smaller than N2, the process proceeds to step ST66, the counter is incremented, and the processes after step ST52 are repeatedly executed. On the other hand, if the counter i is equal to N2, all processing is terminated.

[0095] Next updated error pattern E_kAnd soft input value F_kFrom (k = 1,2, ..., N2), the hard judgment value V of the correction information is calculated by the soft output value calculation circuit 44._kAnd reliability information W_kIs updated.

[0096] First, in step ST71, the soft output value calculation circuit 44 sets the initial value 1 in the counter k and proceeds to step ST72. In step ST72, the hard judgment value V of the correction information_kError pattern E_kIs substituted, and in step ST73, the hardness judgment value V_kDetermines if is 0. Hard judgment value V_kIf is 0, the process proceeds to step ST74, otherwise the process proceeds to step ST77.

[0097] In step ST74, the reliability information W of the correction information_kIs updated by the following equation (36) and the process proceeds to step ST75. W_k F_k+ Z_k (36) In step ST75, the reliability information W of the correction information_kIs determined whether is greater than the constant C4. Reliability information W_kIf is greater than C4, proceed to step ST76, otherwise proceed to step ST80. However, C4 is an appropriate constant represented by n bits or less. In step ST76, reliability information W_kSet to C4 and proceed to step ST80.

On the other hand, in step ST77, the reliability information W of the correction information_kIs updated by the following equation (37) and the process proceeds to step ST78. W_k F_k-Z_k (37) In step ST78, the reliability information W of the correction information_kIs determined to be less than 0. Reliability information W_kIf is less than 0, proceed to step ST79, otherwise proceed to step ST80. In step ST79, reliability information W_kSet to 0 and proceed to step ST80.

[0099] In step ST80, it is determined whether or not the content of the counter k is smaller than N2. If the counter k is smaller than N2, the process proceeds to step ST81, the counter k is incremented, and the processes after step ST72 are repeatedly executed. On the other hand, if the counter k is equal to N2, all processing is terminated.

[0100] Hard determination value V of correction information updated in the soft output value calculation circuit 44._k(k = 1,2, ..., N2) is output in order from k = 1 as a hard judgment value of the correction information for decoding the C1 code from the output terminal 47, and the updated reliability information W._k(k = 1,2, ..., N2) is output from the output terminal 48 in parallel with the above-mentioned rigid determination value as reliability information of the correction information for decoding the C1 code. The hard judgment value of the output correction information and the (1 + n) bits of the reliability information are collectively supplied to the multiplexer 23.

Further, in parallel with the output of the correction information (rigidity determination value and reliability information), the rigidity determination value and reliability information of the demodulated data are output from the rigidity determination memory 35 and the reliability information memory 36. The hard judgment value of the demodulated data and the (1 + m) bit of the reliability information are collectively supplied to the multiplexer 23.

[0102] In the multiplexer 23, the demodulated data N1 × (1 + m) and the correction information N1 × (1 + n) output from the soft input soft output decoders 22A, 22B, 22C having N1 C2 codes at each time point. Is multiplexed and supplied to the C1 code soft input soft output decoder 24.

[0103] FIG. 4 is a configuration diagram showing a soft input soft output decoder 24 having a C1 code. In the figure, the same reference numerals as those in FIG. 3 indicate the same or corresponding parts, and thus the description thereof will be omitted. 43a is a C1 code word candidate generation circuit (code word generation circuit) that generates C1 code word candidates in the same manner as the C2 code word candidate generation circuit 43, and 49 is a hard judgment of the demodulated data supplied from the hard judgment memory 35. Adder (decoding circuit) that adds (exclusive logical sum) the value and the rigid judgment value of the correction information supplied from the soft output value calculation circuit 44 to generate decoding data, 50 is the decoding generated by the adder 49 This is an output terminal for outputting data.

The operation of the C1 code soft input soft output decoder 24 is almost the same as that of the C2 code soft input soft output decoder 22A, 22B, 22C, but the C1 code soft input soft output decoder 24 has a code. The difference is that (code length N1) is processed collectively. That is, the hard determination value N1 bits of the demodulated data are supplied in parallel to the input terminal 31, and the reliability information m · N1 bits of the demodulated data are supplied in parallel to the input terminal 32. Further, the hard judgment value N1 bits of the correction information are supplied in parallel to the input terminal 33, and the reliability information n · N1 bits of the correction information are supplied in parallel to the input terminal 34.

[0105] In the soft input value calculation circuit 37, the processes shown in FIG. 5 are executed in parallel with respect to the counter k, and the error pattern E of each bit is executed._kAnd soft input value F_k(k = 1,2, ..., N1) are calculated at the same time. The calculated soft input value is supplied to the low reliability position detection circuit 38 and stored in the soft input memory 41. Further, the error pattern is supplied to the adder 39 and stored in the error pattern memory 42.

In the adder 39, the hard determination value (N1 bit) of the demodulated data supplied from the input terminal 31 and the error pattern (N1 bit) supplied from the soft input value calculation circuit 37 are the same as in the equation (24). And N1 bit sequence X that is added bit by bit₁, X₂, ..., X_N1Is generated. The generated series is supplied to the syndrome calculation circuit 40.

[0107] In the syndrome calculation circuit 40, the sequence X_kThe syndrome S of (k = 1,2, ..., N1) is calculated. Syndrome S is calculated by the following equation (38). However, H1 is a C1 code parity check matrix defined in Eq. (15), and X is a row vector (X).₁, X₂, ..., X_N1) Is a transposed column vector. The syndrome S calculated by the syndrome calculation circuit 40 is supplied to the C1 codeword candidate generation circuit 43a. S = H1 · X (38) [0108] In the low reliability position detection circuit 38, the supplied soft input value F_kIt detects p pieces with the smallest value in order from the minimum value of (k = 1,2, ..., N1) and notifies the position to the C1 codeword candidate generation circuit 43a. In the following, it is assumed that p = 3 as in the case of the C2 code soft input soft output decoder described above.

[0109] In the C1 codeword candidate generation circuit 43a, the syndrome S calculated in the syndrome calculation circuit 40 and the p positions detected in the low reliability position detection circuit 38 are used in the same manner as in the C2 codeword candidate generation circuit 43. Then, the correction syndrome S [k] and the error position set E [k] (k = 0,1, ···, 7) are calculated. From each correction syndrome S [k] (k = 0,1, ..., 7), the error position is calculated by arithmetic processing on the Galois field or table reference in the same way as decoding the C2 code, and an error occurs. The position set E [k] is redefined. The different set of error positions after redefinition shall be represented by E [k] (k = 1,2, ···, K). Where K is the total number of different error position sets.

Next, the C1 codeword candidate generation circuit 43a uses Eq. (26) to correspond to the error position set E [k] (k = 1,2, ···, K) with the correlation mismatch amount CM [k]. ] Is calculated. Each calculated error position set E [k] and the correlation mismatch amount CM [k] (k = 0,1, ..., K) are supplied to the soft output value calculation circuit 44.

[0111] In the soft output value calculation circuit 44, the soft input value F supplied from the soft input memory 41._k(k = 1,2, ..., N1) and the error pattern E supplied from the error pattern memory 42._k(k = 1,2, ..., N1) and the error position set E [k] supplied from the C1 codeword candidate generation circuit 43a and the amount of correlation mismatch CM [k] (k = 1,2, ... From K), update the error pattern and soft input value in the same way as the flow in Fig. 6. However, in decoding the C1 code, the flow shown in FIG. 6 is expanded in parallel with respect to the counter i, and the error pattern E of each bit is expanded._kAnd soft input value F_kIs updated at the same time.

[0112] Next updated error pattern E_kAnd soft input value F_kCorrection information (hard judgment value V) in the same way as the flow in Fig. 7._kAnd reliability information W_k) Is updated. However, in decoding the C1 code, the flow shown in FIG. 7 is expanded in parallel with respect to the counter k, and the correction information of each bit (hard judgment value V) is expanded._kAnd reliability information W_k) Is updated at the same time.

[0113] The hard judgment value (N1 bit) of the correction information updated in the soft output value calculation circuit 44 is supplied in parallel to the adder 49, and is also used as the hard judgment value of the correction information of the repeat element decoder in the next stage. The reliability information (n / N1 bits) is output in parallel from the output terminal 47, and the reliability information (n / N1 bits) is output in parallel from the output terminal 48 as the reliability information corresponding to the rigid determination value. The total (1 + n) N1 bits of the correction information hardness judgment value and the reliability information are collectively output from the output terminal D of the iterative element decoder.

Further, in parallel with the output of the correction information, the hardness determination value and the reliability information of the demodulated data are output from the rigidity determination memory 35 and the reliability information memory 36. The hard judgment value (N1 bit) of the demodulated data is supplied in parallel to the adder 49 and output in parallel from the output terminal 45, and the reliability information (m · N1 bit) is output in parallel from the output terminal 46. To. The total (1 + m) N1 bits of the hard judgment value of the demodulated data and the reliability information are collectively output from the output terminal C of the iterative element decoder.

In the adder 49, the rigid determination value (N1 bit) of the demodulated data supplied from the rigid determination memory 35 and the rigid determination value (N1 bit) of the correction information supplied from the soft output value calculation circuit 44 are bit by bit. Is added (exclusive logical sum) to, and the decrypted data (N1 bits) of the product code is generated one column at a time. The generated decoded data is output in parallel from the output terminal 50. The output terminal 50 corresponds to the output terminal E of the repeating element decoder.

[0116] The demodulated data (1 + m) N1 bit output from the output terminal C of the repeating element decoder is supplied to the input terminal A of the repeating element decoder in the next stage, and the correction information output from the output terminal D. The (1 + n) N1 bit is supplied to the input terminal B of the repeat element decoder in the next stage. The output terminal C and the output terminal D of the repeating element decoder in the final stage are in an open state, and only the decoded data is output one row at a time from the output terminal E.

As is clear from the above, according to the first embodiment, a code word is generated from the position of the soft input value output from the low-reliability position detection circuit 38 and the syndrome calculated by the syndrome calculation circuit 40. To generate the error position set of the series, and<u style="single">Calculate the sum of the soft input values at the error positions included in the error position set of the series as the correlation mismatch amount.</u>A codeword candidate generation circuit is provided<u style="single">Of that series</u>Since the correction information is updated based on the error position set and the correlation mismatch amount, the soft output value can be calculated accurately by efficiently utilizing the generated codeword candidates, and the calculation amount is calculated. It has the effect of reducing the circuit scale.

That is, the product code decoding apparatus of the first embodiment is convenient when the demodulated data is represented by the rigid determination value and the reliability information, and is not the squared Euclidean distance in the calculation of the likelihood. Since the amount of correlation mismatch is calculated, there is an effect that the amount of calculation is reduced. In particular, when compared in terms of circuit scale, the bit width W1 of the squared Euclidean distance is evaluated by the following equation (39) (where N is N1 or N2), whereas the correlation in the first embodiment 1 The bit width W2 of the discrepancy amount is as shown in the following equation (40), and the bit width can be reduced when p is smaller than N.

[Number 9]<img file="JP3889286B2_D0009.tif" />[0119] In the first embodiment, the Hamming code is used as the C1 code and the C2 code, but another code (for example, a BCH code or a Reed-Muller code) may be used as the element code. Needless to say.

[0120] Further, in the first embodiment, the decoding device in the case where a large number of repeating element decoders are sequentially connected has been described, but the demodulated data output from the output terminal C of the repeating element decoder is used in the same repeating element decoder. It is also possible to supply the correction information output from the output terminal D to the input terminal A and supply it to the input terminal B of the same repeating element decoder for cyclical decoding, which can significantly reduce the circuit scale. it can.

[0121] Further, when the number of low-reliability positions detected in the low-reliability position detection circuit 38 is large, the total number of correction syndromes and error position sets set in the codeword candidate generation circuit becomes enormous. However, in this case, the error position set with a small number of elements may be preferentially selected.

[0122] Further, although not particularly mentioned in the first embodiment, if an error number measuring circuit for comparing the hard determination value of the demodulated data and the decoded data and measuring the number of errors is provided, the state of the communication path. Can be monitored.

[0123] In the first embodiment, it is assumed that the demodulated data is composed of the hard judgment value and the reliability information thereof, but even if the demodulated data is only the hard judgment value, if the reliability information is appropriately set. , The decoding method and the decoding device of the present application can be applied as they are. The product code decoding device according to the first embodiment has a configuration suitable for establishing such good digital transmission, and if the product code coding device and the decoding device are connected by a transmission medium, the value is high. A high-performance digital transmission system can be configured. The transmission medium is not limited to wireless or optical fiber, and may be a recording medium such as an optical disk.

[0124] Embodiment 2. The binary linear code constituting the product code, that is, the C1 code and the C2 code is both an error correction code and an error detection code. In particular, error detection has the advantage that it can be easily performed by calculating the syndrome. By utilizing this feature, error detection of the product code can be easily realized by arranging a syndrome calculation circuit of the element code (C1 code or C2 code) after the product code decoding device described in the first embodiment. can do.

[0125] In this case, if the syndromes of the element codes are all 0, it is determined that there is no error, that is, the decoded data output from the decoding device is correct. On the other hand, if there is even one element code whose syndrome is not 0, it is determined that the decoded data is incorrect. In the case of error detection, it is better to reject the decoded data and stop at error detection.

[0126] Further, the product code decoding device described in the first embodiment is a soft input soft output decoding using a soft determination, and each element component of the decoded data is of the equation (15) or the equation (16). There is no guarantee that the parity check matrix will be satisfied. Therefore, if an error is detected by calculating the syndrome of the C1 code or the C2 code, the reliability of the decoded data can be improved. Further, if the hard judgment decoder of C1 code or C2 code is arranged instead of the syndrome calculation circuit (error detection circuit) and the decoded data is further hard judgment decoding, the reliability is further improved and the error detection can be performed at the same time. It plays the effect.

Embodiment 3. FIG. 8 is a configuration diagram showing a digital transmission system according to Embodiment 3 of the present invention, in which 61 is a coding that encodes input information data to generate a product code. Unit 62 is a modulator that converts the product code generated by the encoder 61 into a signal suitable for the communication path 63, 63 is the communication path, and 64 is the decoder that demodulates the received signal supplied from the communication path 63. A demodulator that supplies demodulated data to 65, 65 is a decoder that decodes demodulated data supplied from demodulator 64 and estimates information data (decoding device, synthesis means), 71 is a retransmission control, 72 is a retransmission buffer. , 73 is a retransmission control (retransmission requesting means), 74 is a receive buffer, and 75 is an error detector. A transmitter is composed of a encoder 61, a retransmission buffer 72, a modulator 62, and a retransmission controller 71, and a receiver from a demodulator 64, a reception buffer 74, a decoder 65, an error detector 75, and a retransmission controller 73. Is configured.

[0128] Hereinafter, the digital code of FIG. 8 is used by using a product code (a product code composed of a binary linear code C1 having a code length N1 and an information length K1 and a binary linear code C2 having a code length N2 and an information length K2). The operation of the transmission system will be described. First, the information data of the K1 and K2 bits is supplied to the encoder 61, and the product code C shown in the equation (2) is generated. The product code C generated in the encoder 61 is stored in the retransmission buffer 72, supplied to the modulator 62, converted into a signal suitable for the communication path 63, and sent to the communication path 63.

The signal received via the communication path 63 is supplied to the demodulator 64 of the receiver. In the demodulator 64, the received signal is shaped and the demodulated data Y of the equation (3) is generated. The generated demodulation data Y is stored in the receive buffer 74 and supplied to the decoder 65. The decoder 65 estimates the information data by the iterative decoding described in the first embodiment, and supplies the decoding result to the error detector 75. The error detector 75 calculates the syndrome of the element code (C1 code or C2 code) to detect an error. That is, if the syndromes of the element codes are all 0, it is determined that there is no error, and if not, it is determined that the error remains.

[0130] When the error detector 75 determines that there is no error, the decoding result is supplied to the host side (not shown). On the other hand, when an error is detected in the error detector 75, the error detector 75 notifies the retransmission controller 73 that the error remains in the decoding result. Upon receiving the error detection notification, the retransmission controller 73 outputs a retransmission request to the transmitter.

[0131] When the transmitter receives the retransmission request, it supplies the product code C stored in the retransmission buffer 72 to the modulator 62 again and sends it to the communication path 63. At the receiver, the demodulator 64 demodulates the retransmission signal to generate demodulated data Y'. Here, the demodulated data Y'is also represented by a matrix of N1 rows and N2 columns as in Eq. (3). The generated demodulation data Y'is supplied to the decoder 65. Further, the demodulated data Y before being stored in the receive buffer 74 is also supplied to the decoder 65.

[0132] In the decoder 65, the demodulated data Y'supplied from the demodulator 64 and the demodulated data Y before being supplied from the receive buffer 74 are combined by a diversity synthesis means (not shown) and decoded again, and the decoding result is obtained. Is supplied to the error detector 75 again. When the error detector 75 detects an error in the decoding result, the retransmission controller 73 again outputs a retransmission request to the transmitter within the time allotted for decoding the current received data. On the other hand, when the timeout occurs, the retransmission controller 73 gives up decoding and starts processing the next received data.

[0133] Since the digital transmission system of the third embodiment is configured as described above, a highly reliable digital transmission system using the product code can be configured. In the above description, when an error is detected, the entire codeword of the product code is retransmitted. However, if only the element code in which the error is detected is retransmitted, the throughput can be significantly improved. it can. Further, by providing the reception buffer 74, it is possible to synthesize the retransmission data and the previous reception data, and a diversity effect can be expected, so that the decoding performance can be significantly improved.

[Effect of the Invention] As described above, according to the present invention, a code word is generated from the position of the soft input value detected by the detection step and the syndrome calculated by the syndrome calculation step, and the error position of the sequence is generated. Along with generating the set<u style="single">Calculate the sum of the soft input values at the error positions included in the error position set of the series as the correlation mismatch amount.</u>A codeword generation step is provided<u style="single">Of that series</u>Since the correction information is updated based on the error position set and the correlation mismatch amount, the soft output value can be calculated accurately by efficiently utilizing the generated codeword candidates, and the calculation amount is calculated. There is an effect that the circuit scale can be reduced.

[0135] According to the present invention, since the error position set having a small number of elements is preferentially selected and output to the update step, there is an effect that the amount of calculation for decoding can be reduced.

[0136] According to the present invention, the amount of correlation mismatch corresponding to the error position set including the position of the binary linear code is sequentially compared, the error position set having the smallest amount of correlation mismatch is selected, and the error position set is selected. The first correlation mismatch amount is calculated by adding the correction value to, and the correlation mismatch amount corresponding to the error position set that does not include the position of the binary linear code is sequentially compared, and the error with the smallest correlation mismatch amount. Select a position set, add a correction value to the error position set to calculate the second correlation mismatch amount, and subtract the second correlation mismatch amount from the first correlation mismatch amount to calculate the likelihood. However, since the correction information is configured to be updated based on the likelihood, there is an effect that the decoding performance can be improved.

[0137] According to the present invention, when the corrected correction information after the update is composed of a hard judgment value indicating a correction flag, the hard judgment value of the correction information and the hard judgment value of the demodulated data are added to form two elements. Since it is configured to generate the decoded data of the linear code, there is an effect that the decoded data of the product code can be easily calculated.

[0138] According to the present invention.<u style="single">One C1 code decoding means</u>Correction information and demodulated data multiplexed by the multiplexing means<u style="single">N1 in parallel</u>The correction information is updated by inputting and performing soft input soft output decoding of the C1 code, and the binary linear code is decoded from the updated correction information and the demodulated data. There is an effect that the soft output value can be calculated accurately by efficiently utilizing the word candidates, and the circuit scale can be reduced by reducing the amount of calculation.

[0139] According to the present invention, a code word is generated from the position of the soft input value output from the low-reliability position detection circuit and the syndrome calculated by the syndrome calculation circuit to generate an error position set of the sequence, and at the same time.<u style="single">Calculate the sum of the soft input values at the error positions included in the error position set of the series as the correlation mismatch amount.</u>A codeword generation circuit is provided<u style="single">Of that series</u>Since the correction information is updated based on the error position set and the correlation mismatch amount, the soft output value can be calculated accurately by efficiently utilizing the generated codeword candidates, and the calculation amount is calculated. There is an effect that the circuit scale can be reduced.

[0140] According to the present invention, when the corrected correction information after the update is composed of a hard judgment value indicating a correction flag, the hard judgment value of the correction information and the hard judgment value of the demodulated data are added to form two elements. Since it is configured to generate the decoded data of the linear code, there is an effect that the decoded data of the product code can be easily calculated.

[0141] According to the present invention, since the updated correction information and the demodulated data output from the C1 code decoding means are supplied to the separation means and configured to be cyclically decoded, the circuit scale can be reduced. There is an effect that can be done.

[0142] According to the present invention, the updated correction information and the demodulated data output from the C1 code decoding means are configured to be output to the next-stage decoding device having the same configuration, which is continuously connected in multiple stages, and thus has high performance. Moreover, there is an effect that a high-throughput product code decoding device can be obtained.

[0143] According to the present invention, since it is configured to provide an error number measuring circuit for measuring the number of errors by comparing the rigid determination values of the decoded data output from the C1 code decoding means and the demodulated data, the communication path. It has the effect of being able to monitor the status of.

[0144] According to the present invention, the reliability of the decoded data is determined because a rigid determination decoding circuit for performing the rigid determination decoding of the C1 code or the C2 code is provided for the decoding data output from the C1 code decoding means. There is an effect that error detection can be performed at the same time.

[0145] According to the present invention, an error detection circuit is provided that calculates the syndrome of the C1 code or the C2 code for the decoded data output from the C1 code decoding means and detects an error in the decoded data based on the syndrome. Since it is configured as such, there is an effect that the reliability of the decoded data can be improved.

[0146] According to the present invention, the decoding apparatus obtains correction information and demodulated data multiplexed by the multiplexing means.<u style="single">N1 in parallel</u>Input and update the correction information by performing soft input soft output decoding of the C1 code, and decode the binary linear code from the updated correction information and demodulated data.<u style="single">1</u>Since it is configured to include a C1 code decoding means, there is an effect that a highly reliable digital transmission system can be constructed.<u style="single">In addition, a code word is generated from the position of the soft input value output from the low-reliability position detection circuit and the syndrome calculated by the syndrome calculation circuit to generate an error position set of the series, and the error position set of the series is used. A codeword generation circuit that calculates the sum of the soft input values at the included error positions as the correlation mismatch amount is provided, and the correction information is updated based on the error position set and the correlation mismatch amount of the series. It has the effect of being able to build a high-quality digital transmission system.</u>[0147] According to the present invention, since the transmission medium is configured to be a recording medium, there is an effect that a highly reliable digital transmission system can be constructed even if the transmission medium is a recording medium.

[0148] According to the present invention, when a C1 code or C2 code syndrome is calculated for the decoded data output from the C1 code decoding means and an error in the decoded data is detected based on the syndrome, the transmitter is notified. Since it is configured to provide the retransmission request means for outputting the retransmission request of the modulated signal, there is an effect that a highly reliable digital transmission system can be constructed.

[0149] According to the present invention, it is configured to provide a synthesis means for diversifying the demodulated data output from the demodulator before the retransmission request and the demodulated data after the retransmission request output from the demodulator. It has the effect of significantly improving the decoding performance.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram showing a product code decoding device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a repeating element decoder.

FIG. 3 is a configuration diagram showing a C2 code soft input soft output decoder.

FIG. 4 is a configuration diagram showing a C1 code soft input soft output decoder.

FIG. 5 is a flowchart showing the operation of a soft input value calculation circuit.

FIG. 6 is a flowchart showing the operation of a soft output value calculation circuit.

FIG. 7 is a flowchart showing a method of updating correction information in a soft output value calculation circuit.

FIG. 8 is a configuration diagram showing a digital transmission system according to a third embodiment of the present invention.

FIG. 9 is an explanatory diagram showing a structure of a product code.

FIG. 10 is a configuration diagram showing a conventional digital transmission system.

FIG. 11 is a flowchart for explaining the operation of the decoder.

FIG. 12 is a flowchart showing a detailed processing content of step ST5.

[Code description] 11,12,13 Repeat element decoder, 21 demultiplexer (separation means), 22A, 22B, 22C C2 code soft input soft output decoder (C2 code decoding means), 23 multiplexer (multiplexer means) ), 24 C1 code soft input soft output decoder (C1 code decoding means), 31 input terminal, 32 input terminal, 33 input terminal, 34 input terminal, 35 memory, 36 memory, 37 soft input value calculation circuit, 38 low Reliability position detection circuit, 39 adder, 40 syndrome calculation circuit, 41 memory, 42 memory, 43 C2 codeword candidate generation circuit (codeword generation circuit), 43a C1 codeword candidate generation circuit (codeword generation circuit), 44 Soft output value calculation circuit, 45 output terminal, 46 output terminal, 47 output terminal, 48 output terminal, 49 adder (decoding circuit), 50 output terminal, 61 encoder, 62 modulator, 63 communication path, 64 demodulator , 65 Decoder (decoding device, synthesis means), 71 Retransmission control, 72 Retransmission buffer, 73 Retransmission control (Retransmission requesting means), 74 Receive buffer, 75 Error detector.