Low-power processor

Technical Field The present invention relates to semiconductor integrated circuit devices such as processors, and in particular, a microprocessor that realizes high-speed operation and low power consumption by controlling the substrate bias of a processor circuit composed of MOS transistors according to the operation mode of the processor. Regarding. Background Technology Currently, CMOS integrated circuits are widely used to realize microprocessors. The power consumption of CMOS circuits includes dynamic power consumption due to charging and discharging during switching and static power consumption due to leakage current. Of these, the dynamic power consumption is proportional to the square of the power supply voltage Vdd and occupies a large power consumption. Therefore, it is effective to lower the power supply voltage in order to reduce the power consumption. Is declining. Some of the current low power consumption microprocessors are provided with a power management mechanism, the processor is provided with a plurality of operation modes, and the clock supply to the execution unit is stopped according to the operation modes. By stopping the clock supply, the dynamic power consumption due to switching in the unnecessary execution unit can be reduced as much as possible. However, the static power consumption due to the leak current cannot be reduced and remains. Since the operating speed of the CMOS circuit slows down as the power supply voltage drops, it is necessary to lower the threshold voltage of the MOS transistor in conjunction with the drop in the power supply voltage in order to prevent deterioration of the operating speed. However, when the threshold voltage is lowered, the leakage current increases extremely. Therefore, as the power supply voltage decreases, the increase in static power consumption due to the leakage current, which has not been so large in the past, has become remarkable. For this reason, it has become a problem to realize a microprocessor that has both high speed and low power consumption. As a method for solving problems related to the operating speed and leakage current of the MOS transistor circuit, a method of controlling the threshold voltage of the MOS transistor by variably setting the substrate bias is described in JP-A-6-53496. It is shown. The device structure for variably setting the substrate bias will be described with reference to FIG. FIG. 2 shows a cross-sectional view of a circuit having a CMOS structure. An n-well 205 is formed on a part of the surface layer of the p-well (p-type substrate) 201, and an n + type is formed on the surface of the p-well 201. An nMOS transistor consisting of a source / drain region 202, a gate oxide film 203, and a gate electrode 204 is formed, and a p + type source / drain region 206, a gate oxide film 207, and a date electrode 208 are formed on the surface of the n well 205. A pMOS transistor is formed. Normally, the sources of the pMOS transistor and the nMOS transistor are connected to the power supply voltage (hereinafter referred to as Vdd) and the ground potential (hereinafter referred to as Vss), respectively, and the drains of the nMOS transistor and the pMOS transistor are connected to the output signal. Vbp209 is provided in the n-well 205 of the pMOS transistor and Vbn210 is provided in the p-well 201 of the nMOS transistor as terminals for applying the substrate bias. Using a device like the one in Figure 2, Vbp209 is normally connected to Vdd and Vbn210 is connected to Vss, but when the circuit is not operating, these board biases are switched so that Vbp209 has a higher potential and Vbn210 has a lower potential. By connecting, the threshold voltage of the MOS transistor can be increased and the leakage current can be reduced. Disclosure of the Invention In order to realize a microprocessor having both high speed and low power consumption, the above-mentioned variable control of the substrate bias is performed on the processor circuit, and the threshold voltage of the MOS transistor is performed during the operation of the processor. It is necessary to reduce the leakage current by lowering the threshold voltage to maintain high speed and raising the threshold voltage during standby. However, in order to variably control the board bias of the processor, it is necessary to accurately control the transition of the operating mode of the processor at the time of switching the board bias, especially the timing of restarting the processor at the time of transition from the standby state to the operating state. Malfunction must be prevented. The object of the present invention is to solve such problems. It is an object of the present invention to provide a high-speed low power consumption processor by realizing the above-mentioned substrate bias control on a processor chip and applying it to various operation modes of the processor. In order to solve the above problems, the features of the processor of the present invention are a processor main circuit that executes a program instruction sequence on a processor chip, a board bias switching device that switches a board bias voltage applied to the board, and a processor. The board bias switching device is controlled so as to switch the bias to the voltage for the standby mode in response to the execution of the instruction to shift to the standby mode in the main circuit, and when the interrupt for releasing the standby is received from the outside, the bias is set to the normal mode. It is provided with an operation mode control unit that controls the board bias switching device so as to switch to a voltage, releases the standby of the processor main circuit after the switched bias voltage stabilizes, and restarts the operation. Another feature of the processor of the present invention is that the semiconductor device of the processor chip has a triple-well structure, and the processor main circuit is formed on a well region different from the substrate bias switching device and the operation mode control unit. Is Rukoto. Another feature of the present invention is that the operation mode control unit is required for bias stabilization as a means of waiting until the switched bias voltage stabilizes before restarting the operation of the processor main circuit at the time of bias switching. It is provided with an on-chip timer for measuring the passage of time or a sensor for detecting that the bias has stabilized at a predetermined voltage. Another feature of the processor of the present invention is that the semiconductor device of the processor chip has a triple-well structure, which is divided into a plurality of functional modules, each of which is formed on a different well region. The circuit, the board bias switching device that switches the board bias applied to the board of each functional module, and the board bias of the functional module in response to the execution of an instruction to put one or more of the functional modules on standby in the processor main circuit. For standby mode The board bias switching device is controlled to switch to the voltage of, and the board bias switching device is controlled to switch the bias to the voltage for normal mode when the standby release signal of the functional module is received from the outside or the processor main circuit. After the switched bias voltage becomes stable, the processor main circuit is provided with an operation mode control unit that notifies that the standby of the functional module has been released. Further, the processor of the present invention uses a means for dynamically switching the operating speed of the processor main circuit and a board bias switching device for the board bias switching device in response to the execution of an instruction for changing the operating frequency in the processor main circuit. Is to be provided with an operation mode control unit which controls to switch to a voltage suitable for the operating frequency and notifies the processor main circuit that the switching of the operating speed is completed after the switched bias voltage becomes stable. Further, a feature of the processor of the present invention is that the substrate bias switching device is composed of a substrate bias generating circuit that internally generates a substrate bias voltage. The present invention also proposes a control method that contributes to lower power consumption of the apparatus. That is, a transistor having a low threshold value has a high speed, but the leakage current between the source and drain is large and the power consumption increases, so it is important to prevent this. The configuration for this is a control method for controlling the power consumption of a semiconductor integrated circuit device having a transistor configured on a semiconductor substrate and having a plurality of element circuit blocks operating based on a clock signal, and is an element circuit block. The first mode in which all of the clocks operate based on the clock, the second mode in which the supply of the clock signal to at least one of the element circuit blocks is stopped, and the supply of the clock signal to all of the element circuit blocks are stopped. At the same time, it is characterized in that it is used by switching to a third mode in which the substrate bias of at least a part of the transistors configured on the semiconductor substrate is controlled to raise the threshold value of the transistors. The main circuit is, for example, a processor including a CPU and the like. 1st Mode is a mode in which the main circuit performs normal operations (calculation, storage, etc.). The second mode is a state in which the clock to a part of the processor is stopped, and is called, for example, a sleep mode, a deep sleep mode, or the like. By selecting the range in which the clock is stopped, low power consumption can be achieved while maintaining only the necessary functions. The third mode is a mode in which the board bias is controlled with respect to the circuit of the processor to raise the threshold value of the transistors constituting the board and reduce the power consumption due to the subthreshold leakage current. For example, the standby mode or the hardware mode. It is called standby mode. The standby mode can be restored to the normal state by interrupt control, but in the hardware standby mode, it cannot be restored without resetting. In the third mode, the function of the main circuit is stopped. In the configuration of the entire circuit, the element circuit block is included in the first circuit block, the clock signal is formed by the oscillation circuit included in the second circuit block, and the clock is clocked from the second circuit block to the first circuit block. The signal and the information signal to be processed by the first circuit block are input. The second circuit block also includes an input / output circuit and a control circuit for controlling the board bias. Normally, the second circuit block is not required to operate as fast as the first circuit block including the main circuit. Therefore, it is desirable that the transistor constituting the second circuit block has a larger threshold value and a higher operating voltage than the transistor constituting the first circuit block. Further, the transistor forming the main circuit of the first circuit block is formed on a well separate from the other circuits, so that the influence of the other circuits can be reduced. When the operating voltages of the first and second circuit blocks are different, a level conversion circuit is required between them. For example, a level-down circuit is provided in the first circuit block, and a level-up circuit is provided in the second circuit block to convert the signal level. In the present invention, the substrate bias voltage is dynamically switched by switching the mode. In addition, the operation sequence is important for ensuring reliability. When switching from the first or second mode to the third mode, the clock signal input from the second circuit block to the first circuit block and the first circuit block to be processed by the first circuit block. The information signal input to the circuit block of the above is stopped first, and then the substrate bias of at least a part of the transistors configured on the semiconductor substrate is controlled to raise the threshold value of the transistor. As a result, it is possible to prevent the input to the first circuit block when the operation of the first circuit block is unstable, and it is possible to prevent the first circuit block from malfunctioning. For this operation, it is possible to adopt a configuration such as stopping the signal input to the first circuit block, waiting for a predetermined time (for example, about 60 microseconds) by a timer or the like, and then controlling the board bias. The timer for standby is arranged outside the first circuit block, for example, inside the second circuit block or outside the device. Further, when switching from the third mode (standby mode) to the first mode, the substrate bias of at least a part of the transistors configured on the semiconductor substrate is controlled to lower the transistor threshold value, and then the transistor threshold value is lowered. , The input of the clock signal input from the second circuit block to the first circuit block and the information signal to be processed by the first circuit block is started. That is, in order to prevent the malfunction of the first circuit block, the signal input is started after the board voltage of the first circuit block is stabilized. Therefore, when switching from the third mode to the first mode, the substrate bias of the first circuit block is controlled to lower the threshold value of the transistor, and the timer waits for a predetermined time to stabilize the operation. After that, the input of the clock signal and other signals input to the first circuit block is started. As another method, after confirming the state of the threshold value of the transistor with a voltage monitor or the like, the signal input to the first circuit block is started. Alternatively, the board bias generating circuit is based on the state of the board bias generating circuit that controls the board voltage. In accordance with the standby release signal output from, the input of the clock signal and other signals input to the first circuit block is started. As a method of stopping the information signal and the clock signal for the first block, it is conceivable to fix the signal level by the output fixing circuit (level hold circuit) provided in the second circuit block. In the first mode, the signal is input to the level down circuit via the output fixed circuit, but in the third mode, the input to the level down circuit is fixed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a processor chip according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a general device structure used for substrate bias control. FIG. 3 is a cross-sectional view showing the device structure according to the first embodiment of the present invention. FIG. 4 is a flowchart used for explaining the operation in the first embodiment of the present invention. FIG. 5 is a block diagram of a processor chip according to a second embodiment of the present invention. FIG. 6 is a block diagram of a processor chip according to a third embodiment of the present invention. FIG. 7 is a block diagram of a processor chip according to a fourth embodiment of the present invention. FIG. 8 is a block diagram of a processor chip according to a fifth embodiment of the present invention. FIG. 9 is a diagram illustrating the relationship between the operation mode of the present invention and the substrate bias control. FIG. 10 is a diagram illustrating a configuration of a processor main circuit of the present invention. FIG. 11 is a diagram illustrating a low power consumption mode of the present invention. FIG. 12 is a diagram illustrating sleep and deep sleep of the present invention. FIG. 13 is a transition diagram of the operation mode of the present invention. FIG. 14 is a configuration diagram of the processor chip of the present invention and a first configuration diagram of a power supply control circuit. FIG. 15 is a diagram illustrating a power supply replacement sequence of the present invention. FIG. 16 is a configuration of the processor chip of the present invention and a second configuration diagram of the power supply control circuit. FIG. 17 is a diagram illustrating a sequence of RTC power backup of the present invention. FIG. 18 is a diagram illustrating a sequence from the low power consumption mode of the present invention to returning by an interrupt. FIG. 19 is a diagram illustrating a sequence from the low power consumption mode of the present invention to returning by reset. Best Mode for Implementing the Invention Hereinafter, examples of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a processor chip for realizing the first embodiment of the present invention. In FIG. 1, the processor chip 101 is an LSI chip having a circuit having a CMOS structure, and includes a processor main circuit 102, an operation mode control unit 103, and a board bias switching device 104. The board bias switching device 104 is equipped with voltages Vdd and Vss and standby in the normal mode of board bias. The voltages Vddb and Vssb in the mode are input from signal 110. The board bias switching device 104 selects either Vdd or Vddb as the board bias of the pMOS transistor constituting the processor main circuit 102 according to the signal 107 output from the operation mode control unit, outputs it to the signal Vbp111, and outputs the board of the nMOS transistor. Either Vss or Vssb is selected as the bias and output to the signal Vbn112. The voltage values for board bias selection are, for example, Vdd = 1.5V, Vddb = 3.0V, Vss = 0.0V, Vssb = -1. It is 5V. As will be described later, the well 302 in which the processor main circuit 102 is formed is formed separately from the well in which the substrate bias switching device 104 and the operation mode control unit are formed. FIG. 3 is a cross-sectional view showing the device structure of the processor chip 101. FIG. 3 differs from FIG. 2 in that the p-well 302 is formed on the n-type substrate 301 and the n-well 205 is formed on a part of the surface phase of the n-type substrate 301, that is, the device has a triple-well structure. is there. An nMOS transistor is formed on the surface of the p-well 302, and a pMOS transistor is formed on the surface of the n-well 205 to form a CMOS circuit. Further, it is the same as FIG. 2 in that Vbp209 is provided in the n-well 205 of the pMOS transistor and Vbn210 is provided in the p-well 302 of the nMOS transistor as terminals for applying the substrate bias. In this embodiment, the processor main circuit 102 is formed in a p-well 302 different from the operation mode control unit 103 and the board bias switching device 104. As a result, the influence of the board bias control extends only to the processor main circuit 102, and the operation mode control unit 103 and the board bias switching device 104 can avoid the influence. The operation of the processor chip 101 in this embodiment will be described with reference to FIG. The operation mode of the processor main circuit 102 includes a normal mode in which normal instruction is executed and a standby mode in which instruction is not executed. FIG. 4 is a flowchart showing processing on the processor chip 101 when the operation mode of the processor main circuit 102 transitions from the normal mode to the standby mode and then from the standby mode to the normal mode. First, the processor main circuit 102 is operating in normal mode. At this time, the substrate bias switching device 104 selects Vdd and Vss for the substrate bias Vbp111 and Vbn112, respectively. The voltage value of the board bias in the normal mode in this example is Vbp = 1. 5V, Vbn = 0V (step 401). When the processor main circuit 102 executes the sleep instruction, it outputs a "standby request" to the signal 105 and transmits it to the operation mode control unit 103, and then stops the instruction execution operation and shifts to the standby mode (step 402). When the operation mode control unit 103 receives this signal 105 from the processor main circuit, it outputs a signal 107 to switch the board bias of the processor main circuit 102 to the voltage for the standby mode. In response to this signal 107, the board bias switching device 104 selects and outputs Vddb and Vssb from the input voltages 110 to the board biases Vbp111 and Vbn112, respectively (steps 403 and 404). In this example, the voltage values of the board bias in standby mode are Vbp = 3.0V and Vbn = -1.5V. When the operation mode control unit 103 detects that a "standby release interrupt" has been asserted to the signal 108 from the outside while the processor main circuit 102 is in the standby state (step 405), the operation mode control unit 103 sets the board bias of the processor main circuit 102. A signal 107 is output to switch to the voltage for normal mode, and the board bias switching device 104 receives this signal 107 and sets the board bias Vbp111 and Vbn112 to Vdd (1.5V) and Vss (0.), respectively. Switch to 0V) (step 406). Since it takes some time for the bias voltage to stabilize after switching the board bias, if the operation of the processor main circuit 102 is restarted immediately, a malfunction may occur. To avoid this, the operation mode control unit 103 starts by setting a sufficient time required for stabilizing the board bias voltage switched to the on-chip timer 109 before switching the operation mode of the processor main circuit 102 (step 407). , Wait until it times out (step 408). Then, after the time-out occurs, the operation mode control unit 103 outputs "standby release" to the signal 106 and transmits it to the processor main circuit 102. Upon receiving this signal 106, the processor main circuit 102 shifts to the normal mode and resumes the instruction execution operation (step 409). As described above, the board biases Vbp111 and Vbn112 of the processor main circuit 102 are controlled to lower the threshold voltage of the MOS transistors constituting the processor main circuit during operation to support high-speed operation, and the threshold during standby. The leakage current can be reduced by increasing the value voltage. FIG. 5 is a block diagram showing a configuration of a processor chip according to a second embodiment of the present invention. In this embodiment, the operation mode control unit 103 includes a sensor 501 that detects a bias voltage applied to the substrate of the processor main circuit 102. When the operation mode of the processor main circuit 102 transitions from the normal mode to the standby mode, it is the same as the processing procedure in the first embodiment. When the operation mode of the processor main circuit 102 transitions from the standby mode to the normal mode, the operation mode control unit 103 controls the board bias switching device 104 to set the board bias to the voltage of the normal mode as in the first embodiment. After switching, the voltage of the substrate bias switched by the sensor 501 is a predetermined value, that is, in this embodiment, Vbp = 1.5V, Vbn = 0. Wait until the signal 502 is output when it is stable at 0V. When the sensor 501 outputs the stability of the board bias to the signal 502, the operation mode control unit 103 outputs "standby release" to the signal 106 to restart the operation of the processor main circuit 102. FIG. 6 is a block diagram showing a configuration of a processor chip according to a third embodiment of the present invention. As the basic device structure of the processor chip 601, consider the triple well structure shown in FIG. In the processor chip 601 of FIG. 6, the processor main circuit is composed of a plurality of functional modules such as CPU604, module A606, and module B608. Each functional module exists separately on a different well region and is not affected by the substrate bias control of other functional modules. Functional modules include smaller units such as CPUs, FPUs, caches, or arithmetic units. The board bias switching devices 605, 607, and 609 are provided corresponding to the respective functional modules 604, 606, and 608, and the board bias of the corresponding functional modules can be switched in the same manner as in the case of the above embodiment. The execution of the instruction is mainly performed by the CPU 604, which is one of the functional modules, and when the instruction to put the functional module unnecessary for execution into standby is executed, the standby of the functional module is transmitted to the operation mode control unit 602. The operation of the processor chip 601 in this embodiment will be described below. First, it is assumed that all function modules are operating in normal mode. When CPU604 executes an instruction to put module A on standby, it outputs this standby request to signal 610, and the module cannot be used until the standby of module A606 is released thereafter. Upon receiving this signal 610, the operation mode control unit 602 outputs a signal 612 to the board bias switching device 607, and switches the board bias of the module A606 to the voltage for the standby mode. When module A606 is in the standby state, the operation mode control unit 602 outputs signal 6 of CPU604. When 10 or the signal 613 external to the processor chip 601 is used to release the standby of module A606, the signal 612 is output to the board bias switching device 607, and the board bias of module A is switched to the voltage for normal mode. Then, the operation mode control unit 602 waits for the board bias switched by using the on-chip timer 603 to stabilize as in the first embodiment of the present invention, and after the stabilization, the standby of the module A is released by passing the signal 611 to the CPU 604. Notify. When the CPU 604 receives this signal 611, the instruction can be executed using the module A. The same applies to the standby control of module B608 and other functional modules. The CPU 604 itself is also subject to standby control. In this case, when the CPU 604 shifts to the standby mode, all instruction execution is stopped, and when the standby release signal of the CPU 604 is asserted to the external signal 613, the operation mode control unit 602 signals after the switching of the board bias of the CPU 604 is completed. It is controlled in the same manner as in the case of the module A606 except that the standby release of the CPU 604 is asserted to the 611 and the instruction execution of the CPU 604 is restarted. By the standby control for each functional module in this embodiment, it is possible to reduce the leakage current of the functional module that is unnecessary during the operation of the processor. FIG. 7 is a block diagram showing a configuration of a processor chip according to a fourth embodiment of the present invention. The difference from the first embodiment is that the types of voltage 701 supplied to the board bias switching device 104 from the outside are increasing, and the board bias switching device 104 selects an appropriate one as the board bias from them and processes the processor. It can be applied to the main circuit 102. In this embodiment, it is assumed that the operating speed of the processor main circuit 102, that is, the operating frequency is dynamically changed by an instruction, and the operating modes of the processor main circuit 102 include a high-speed mode and a low-speed mode. In this embodiment, the substrate bias corresponding to the high-speed mode is used. Vdd (for pMOS) and Vss (for nMOS), Vddb2 (for pMOS) and Vssb2 (for nMOS) as board bias corresponding to low speed mode, Vddb1 (for pMOS) and Vssb1 (for nMOS) as board bias corresponding to standby mode For) is selected. Next, the operation of the processor chip 101 in this embodiment will be described. Here, consider a case where the operation mode of the processor main circuit 102 is switched from the high-speed mode to the low-speed mode. While the processor main circuit 102 is operating in the high-speed mode, the board bias switching device 104 selects Vdd for Vbp111 and Vss for Vbn112 as the board bias of the processor main circuit. When the processor main circuit 102 executes an instruction to shift to the low speed mode, the processor main circuit 102 outputs the request to the signal 105 and interrupts the instruction execution operation. The clock supplied to the processor main circuit 102 is switched to a low frequency by executing an instruction to shift to this low-speed mode. The operation mode control unit 103 receives the signal 105 and outputs it to the signal 107 in order to switch the board bias of the processor main circuit 102 to the voltage for the low speed mode. The board bias switching device 104 receives this signal 107 and switches the board biases Vbp111 and Vbn112 to Vddb2 and Vssb2, respectively. The operation mode control unit 103 uses the on-chip timer 109 as in the above embodiment, waits for the switched board bias to stabilize, and notifies the processor main circuit 102 that the transition to the low speed mode is completed through the signal 106. Upon receiving this signal 106, the processor main circuit 102 resumes the interrupted instruction execution operation in the low speed mode. The operation at the time of switching from low speed mode to high speed mode, switching from high speed mode or low speed mode to standby mode, or switching from standby mode to high speed mode or low speed mode in this embodiment is the same as above, so details are omitted. To do. In this embodiment, the operating speed can be further subdivided and the substrate bias control corresponding to the operating speed can be performed. Furthermore, as in the third embodiment, It is also possible to separate the losser main circuit 102 for each functional module using the triple well structure of the device, and control the board bias in conjunction with the switching of the operating frequency for each functional module. By performing substrate bias control suitable for the operating frequency of the processor as in this embodiment, it is possible to reduce the leakage current in the low-speed operation mode. Furthermore, in this low-speed mode, the range of the input voltage at which both the pMOS and nMOS transistors of the CMOS circuit conduct at the same time becomes narrower than in the high-speed operation mode, so that the effect of reducing the through current during switching can also be obtained. .. FIG. 8 is a block diagram showing a configuration of a processor chip according to a fifth embodiment of the present invention. This embodiment is different from the first embodiment in that the substrate bias switching device is configured by the substrate bias generating circuit 801. The board bias generation circuit 801 is controlled by the output signal 802 of the operation mode control unit 103, internally generates a board bias voltage, and outputs it to Vbp111 and Vbn112. The voltage values of the board biases Vbp111 and Vbn112 generated corresponding to the operation mode of the processor main circuit 102 under the control of the operation mode control unit 103 are the same values as those in the first embodiment. Since the operations of the processor main circuit 102 and the operation mode control unit 103 are the same as those in the first embodiment, the details will be omitted. Further, by configuring the board bias switching device in the second, third, and fourth embodiments with the board bias generation circuit 801 as in the present embodiment, the board bias is generated inside the processor chip, and the operation mode is performed. It can be switched according to. As described above, according to these examples, since the timing of restarting the processor at the time of transition from the standby state to the operating state is accurately controlled by using a timer or a sensor, it is optimal according to the operating mode of the processor. Substrate bias control becomes possible. As a result, the leakage current can be reduced in the standby mode while the operating mode of the processor maintains high speed in the normal mode. Ma Further, by performing board bias control according to the operation mode for each functional module, it is possible to reduce the leakage current of the functional module that is unnecessary for execution even when the processor is operating. Further, by performing the substrate bias control suitable for the operating frequency of the processor, in addition to reducing the leakage current in the low speed mode, the effect of reducing the through current at the time of switching can be obtained. As a result, it is possible to effectively reduce power consumption and provide a microprocessor having both high speed and low power consumption. Hereinafter, as an example of the microcomputer, an operation mode for controlling the substrate bias will be specifically described. The microcomputer has two power supplies of 1.8V and 3.3V, and board bias control is performed only for 1.8V. It is desirable that the circuit that supplies 1.8V be composed of MOS transistors with a relatively low threshold value (for example, about Vth <0.4V). Figure 9 shows an example of the operation mode of the microcomputer. As the operation mode, there are a normal operation mode 982 and a reset mode 981 which are operating normally. Modes that operate with low power consumption include sleep 983, deep sleep 984, standby 985, hardware standby 986, and RTC (real-time clock) battery backup mode. The test mode includes IDDQ measurement. During normal operation 982, high-speed operation is required, so board bias is not controlled. At reset 981, all functions need to be reset, so board bias is not controlled. In the low power consumption mode, the sleep 983 and deep sleep 984, which have a short recovery time from the low power consumption mode, do not control the board bias, but the standby 985 focuses on making the power consumption smaller than the recovery time. , In the case of hardware standby 986, board bias control is performed. RTC battery backup mode is 3. This mode supplies only the power of the RTC circuit that operates at 3V. Since the transition from the low power consumption mode to this mode is performed, the substrate bias is controlled. In addition, IDDQ measurement is a mode in which the standby current is measured to measure the through current due to a short circuit or defect in the transistor. In this case, the substrate bias is always controlled to reduce the leakage power of the chip. , It is necessary to make it easier to find defects. In FIG. 10, before explaining the operation mode of low power consumption, the configuration will be described in the internal block of the processor main circuit 902. This figure is an example of the main constituent blocks of the processor main circuit. There are CPU (Central Processing Unit) 971 and FPU (Floating Point Unit) 972 as arithmetic circuits. In addition, the cache 973, which is the memory built into the chip, the BSC (bus control unit) 974 that interfaces with the external memory, the DMAC (DMA control unit) 975 that performs DMA (direct memory access), and the SCI (SCI) that controls the serial port. There are serial control unit) 976, INTC (interrupt control unit) 977 that controls interrupt input, CPG (clock control unit) 978 that controls clock, and so on. FIG. 11 describes sleep 983, deep sleep 984, and standby 985, which are low power consumption modes. In sleep 983, only the clocks of arithmetic devices such as CPU971, FPU972, and cache 973 are stopped, and the board bias is not controlled, so power consumption cannot be significantly reduced, but DMA transfer by DMAC975 and BSC974 are used. Normal refresh (1024 times / 16 milliseconds refresh) of DRAM (dynamic RAM) or SDRAM (synchronous dynamic RAM) is possible. Since the CPG978 is operating and does not control the board bias, the return time from sleep 983 to normal operation mode 982 is fast. The standby 985 mode stops all operating clocks and also controls the board bias, so power consumption is extremely low. The clock is DMA transfer is not possible because it is stopped. Regarding DRAM and SDRAM refresh, before entering standby 985, set the control signal (RAS signal, CAS signal) of each memory using BSC974 so that the memory will be in self-refresh mode where it refreshes itself. Need to be done. However, since the clock is stopped, the recovery time from the standby 985 to the normal operation 982 becomes longer due to the waiting time for the clock oscillation to stabilize and the recovery time from the board bias state. Deep sleep 984 mode is a low power consumption mode between sleep 983 and standby 985. Figure 12 shows the difference between the operation modules of Sleep 983 and Deep Sleep 984. During sleep 983, the operating BSC973, DMAC974, and SCI975 are stopped in deep sleep 984, so power consumption can be reduced accordingly. However, in deep sleep 984 mode, DMA transfer is not possible and memory refresh is also self-refresh. The return time from deep sleep 984 to normal operation mode 982 is as fast as in sleep mode. By providing the three types of low power consumption modes in this way, it is possible to perform fine-tuned low power consumption control according to the application. FIG. 13 shows and describes a state transition diagram of the operation mode. All power off state 980 to RESET # 952 (or power on reset) pin input causes the processor chip to transition to reset state 981. When RESET # 952 is negated, it transitions to normal operation 982. The transition from this state to the low consumption operation mode. There are two transition methods. One is the transition by instruction. This transitions when CPU971 executes a sleep instruction. The mode register can be set when the sleep instruction is executed, and sleep 983, deep sleep 984, and standby 985 can be selected, and each mode can be transitioned. The return from each mode to the normal operation mode 982 is an interrupt 958. one more The transition method is a transition using HARDSTB # 951 pin. When this pin is asserted, it transitions to the hardware standby state 986. In this state, as in the standby 985, all clocks are stopped and the board bias control is also performed. In this mode, if the input / output buffer is set to high impedance, there will be no transistor through which a through current flows in the 3.3V circuit, and IDDQ can be measured. Also, if the input buffer of the RTC circuit placed in the 3.3V system is fixed, the input signal of the RTC circuit will not float (intermediate level) even when the power supply other than the RTC circuit is turned off, so the RTC circuit will malfunction. Can be prevented and only the RTC circuit can be operated. Next, an application example of hardware standby will be described. FIG. 14 shows the configuration of the processor chip 901 and the configuration of the power supply control circuit in which the power supply 904 (battery) of the processor chip 901 can be replaced by applying the hardware standby. The processor chip 901 is composed of a 1.8V region circuit 930 operating at 1.8V and a 3.3V region circuit 931 operating at 3.3V. The 1.8V region circuit 930 consists of a processor main circuit 902 and level down circuits 905 and 906 that convert the level from 3.3V to 1.8V. The 3.3V region circuit 931 is a board bias generation circuit 903, a clock oscillation circuit 908, an IO circuit 909, an operation mode control unit 913, an RTC circuit 914, and a level-up circuit 904, 910, 3.3V that converts the level from 1.8V to 3.3V. It consists of output fixed circuits 907 and 911 that fix the signal from to 1.8V. As the control circuit of the power supply system, the power supply 904, the power supply monitoring circuit 921, the display 922, 1. There is a voltage generation circuit 920 that generates a voltage of 8V system. The operation will be described below. When the processor chip 901 is in the normal operation mode 982, the board bias generating circuit 903 holds a normal board level (for example, VDD potential for MOSFET, VSS potential for NMOS) without drawing board bias. The clock oscillator circuit 908 is composed of a PLL (Phase Locked Loop) or the like, generates a clock for internal operation, and sends it to the processor main circuit 902 via the output fixed circuit 907 and the level down circuit 905. The IO circuit 909 takes in a signal from the outside and sends it to the processor main circuit 902 via the output fixed circuit 907 and the level down circuit 905. Further, the signal from the processor main circuit 902 is output to the outside via the level-up circuit 904. The RTC circuit 914 operates at 3.3V, receives a control signal from the processor main circuit 902 via the level-up circuit 910, and sends a control signal to the processor main circuit 902 via the level-down circuit 906 and the output fixed circuit 911. Send. The operation mode control unit 913 specifically controls the board bias generation circuit 903. The power supply monitoring circuit 921 monitors the voltage level of the power supply 904. When the voltage level drops below the specified level (detects that the battery is dead), HARD STB # 951 is set to the low level. At the same time, a low battery alarm is displayed on the display 922 to notify the user. The voltage holding circuit 923 can hold the voltage level for a predetermined period (a few minutes to a few hours) even when the voltage level is lowered. During this period, the user can replace the power supply 904. The power supply replacement sequence will be described below with reference to FIG. (1) When HARDS TB # 951 becomes low level, the operation mode enters the hardware standby state 986. Here, the operation mode control unit 913 outputs a fixed 1.8V signal 953, fixes the signal from 3.3V to 1.8V, and stops the 1.8V system clock. As a result, even when the substrate bias is pulled, 1. Since the 8V system signal does not operate, 1.8 in the state where the board bias is pulled (the state where the threshold voltage of the MOS transistor is high and the operating speed is slow and the board potential is unstable). Prevent malfunction of V system circuit. In this state, the board bias control start signal 955 is output to the board bias generation circuit 903. (2) After that, the board bias control start signal 955 is output to the board bias generation circuit 903 based on the timing of the 1.8V signal fixed 953. Between the signal fixing 953 and the board bias control start 955, a time difference is set until the signal is actually fixed and the signal supply to the 1.8V region is stopped. This time difference can be measured by a timer based on the RTC clock of the RTC circuit 914. (3) In response to the board bias control start signal 955, the board bias generation circuit 903 starts to draw the board bias of the 1.8V system board. During the period when the board bias is pulled, the 956 signal during the board bias control is returned to the operation mode control unit 913. (4) The processor main circuit 902 does not operate when the board bias is pulled. Further, since the leakage current is small, the current consumption is small. As a result, the holding time of the voltage holding circuit 923 is also extended. (5) Replace the power supply 904 in this state. (6) After replacing the power supply, the power supply voltage returns to the normal level, so HARDSTB # 951 returns to the high level. (7) After that, the power-on reset circuit operates and RESET # 952 is input. By this reset input, the board bias control start signal 955 output from the operation mode control unit 913 is released. (8) In response to the cancellation of the board bias control start signal 955, the board bias generation circuit 903 is 1. Start returning the substrate bias of the 8V diameter substrate to the operating potential (for example, VDD potential for MOSFET, VSS potential for NMOS). It takes a predetermined time to recover the board bias, and when the board bias is returned, the operation mode control unit 913 is notified by releasing the board bias control signal 956. (9) In response to the release of the board bias control signal 956, the 1.8V signal fixed 953 output from the operation mode control unit 913 is released, and the signal is input to the 1.8V system circuit such as the processor main circuit 902. To. (10) After the reset state 981 is completed, the normal state 982 is entered, and the processor main circuit 902 starts normal operation. As described above, the power supply 904 can be replaced by using the low power consumption mode by the hardware standby. Next, a second application example of the hardware standby will be described. Figure 16 shows a configuration example that realizes the RTC power backup mode. The RTC circuit 914 is called a real-time counter and realizes the functions of a clock and a calendar. Therefore, the function of the clock cannot be realized unless it is always in operation. The RTC circuit 914 must be operating even if the power supply 904 is cut off. In the embodiment shown here, the 3.3V region is divided into a normal 3.3V region 991 and an RTC 3.3V operating region 992 in order to realize the RTC power backup mode. Further, in the 3.3V region 992 of the RTC, an input fixed circuit 912 and an input fixed level-up circuit 960 are added to the input circuit, and other power supplies (1.8V, normal 3.3V power supply) are cut off. In the state, even if the input signal becomes floating, the intermediate level signal is not transmitted to the region 992 which operates at 3.3V of RTC, and the malfunction is prevented. As the control circuit of the power supply system, the power supply 904, the power supply monitoring circuit 921, the display 922, 1. In addition to the voltage generation circuit 920 that generates 8V voltage, there are backup batteries 962, diodes 963, and 964. The operation will be described below. In the normal operation mode 982, the board bias generating circuit 903 holds the normal board level without pulling the board bias. The clock oscillator circuit 908 is composed of a PLL (Phase Locked Loop) or the like, generates a clock for internal operation, and sends it to the processor main circuit 902 via the output fixed circuit 907 and the level down circuit 905. The IO circuit 909 takes in a signal from the outside and sends it to the processor main circuit 902 via the output fixed circuit 907 and the level down circuit 905. Further, the signal from the processor main circuit 902 is output to the outside via the level-up circuit 904. The RTC circuit 914 operates at 3.3V, receives a control signal from the processor main circuit 902 via the input fixed level up circuit 960, and receives a control signal to the processor main circuit 902 via the level down circuit 906 and the output fixed circuit 911. To send. The operation mode control unit 913 receives a control signal via the input fixed circuit 912, and particularly controls the board bias generation circuit 903. The power supply monitoring circuit 921 monitors the voltage level of the power supply 904. When the voltage level drops below the specified level (detects that the battery is dead), HARD STB # 951 is set to a low level, the input of RTC 3.3V area 992 is fixed, and malfunction of RTC circuit 914 is prevented. At the same time, the display 922 displays a low battery alarm. After this, the voltage level continues to drop, and 3.3V and 1.8V voltages are no longer supplied to the processor chip 901. At this time, the backup battery 962 to the RTC via the diode 963 3. The voltage (VDD-RTC, VSS-RTC) is supplied only to the 3V region, and even if there is no power supply 904, only the RTC circuit 914 (calendar counter circuit) operates normally. The diode 964 prevents current from flowing outside the RTC circuit 914. The RTC power backup sequence will be described in detail with reference to FIG. (1) When HARDS TB # 951 becomes low level, the operation mode enters the hardware standby state 986. Here, the operation mode control unit 913 outputs a fixed 1.8V signal 953, fixes the signal from 3.3V to 1.8V, and stops the 1.8V system clock. As a result, even when the board bias is pulled, the 1.8V system signal does not operate, so that the malfunction of the 1.8V system circuit in the state where the board bias is pulled is prevented. At the same time, the input fixed signal 954 to the RTC circuit 914 is output to fix the input signal. This prevents an unstable intermediate level signal from entering the RTC circuit 914 when other power supplies are cut off. (2) After that, the board bias control start signal 955 is output to the board bias generation circuit 903 based on the timing of the 1.8V signal fixed 953. Between the signal fixing 953 and the board bias control start 955, a time difference is set until the signal is actually fixed and the signal supply to the 1.8V region is stopped. This time difference can be measured by a timer based on the RTC clock of the RTC circuit 914. (3) In response to the board bias control start signal 955, the board bias generation circuit 903 is 1. Start pulling the board bias of the 8V board. During the period when the board bias is pulled, the 956 signal during the board bias control is returned to the operation mode control unit 913. (4) The processor main circuit 902 does not operate when the board bias is pulled. Further, since the leakage current is small, the current consumption is small. (5) The cutoff period of the power supply 904 may be long. Also, the power supply 904 can be replaced. (6) After returning from the power supply 904 cutoff (or after replacing the power supply 904), the power supply voltage returns to the normal level, so HARD STB # 951 returns to the high level. (7) After that, the power-on reset circuit operates and RESET # 952 is input. By this reset input, the board bias control start signal 955 is released. (8) In response to the cancellation of the board bias control start signal 955, the board bias generation circuit 903 returns the board bias of the 1.8V diameter board to the operating potential (for example, VDD potential for MOSFET, VSS potential for NMOS). start. It takes a predetermined time to recover the board bias, and when the board bias is returned, the operation mode control unit 913 is notified by releasing the board bias control signal 956. (9) In response to the release of the board bias control signal 956, the 1.8V signal fixed 953 output from the operation mode control unit 913 is released, and the processor main circuit 902, etc. 1. A signal is input to the 8V circuit. (10) After the reset state 981 is completed, the normal state 982 is entered, and the processor main circuit 902 starts normal operation. In the above sequence, it is also possible to provide a power switch on the power supply 904 and operate only the RTC circuit 914 during the power off period. As described above, using the hardware standby, only the RTC circuit 914 can be backed up by a battery and operated. FIG. 18 illustrates a sequence in which the normal sleep instruction 959 is used to enter the standby state 985 and return to the normal state 982 with the interrupt signal 958. (1) The operation mode enters the standby state 985 by the sleep command 959. Here, the operation mode control unit 913 outputs a fixed 1.8V signal 953, fixes the signal from 3.3V to 1.8V, and stops the 1.8V system clock. This prevents malfunction of the 1.8V circuit when the board bias is pulled. (2) After that, the board bias control start signal 955 is output to the board bias generation circuit 903 based on the timing of the 1.8V signal fixed 953. Between the signal fixing 953 and the board bias control start 955, a time difference is set until the signal is actually fixed and the signal supply to the 1.8V region is stopped. This time difference can be measured by a timer based on the RTC clock of the RTC circuit 914. (3) In response to the board bias control start signal 955, the board bias generation circuit 903 is 1. Start pulling the board bias of the 8V board. During the period when the board bias is pulled, the 956 signal during the board bias control is returned to the operation mode control unit 913. (4) The processor main circuit 902 does not operate when the board bias is pulled. Further, since the leakage current is small, the current consumption is small. (5) In this state, when the interrupt signal 958 is received from the control signal 957 (external pin) via the IO circuit 909, the operation mode control unit 913 releases the board bias control start signal 955. (6) In response to the cancellation of the board bias control start signal 955, the board bias generation circuit 903 returns the board bias of the 1.8V diameter board to the operating potential (for example, VDD potential for MOSFET, VSS potential for NMOS). start. It takes a predetermined time to recover the board bias, and when the board bias is returned, the operation mode control unit 913 is notified by releasing the board bias control signal 956. (7) Upon receiving the release of the board bias control signal 956, the operation mode control unit 913 releases the 1.8V signal fixed 953. By releasing the 1.8V signal fixed 953 after the signal during board bias control is released, the 1.8V system circuit is prevented from malfunctioning. (8) A signal is input to a 1.8V system circuit such as the processor main circuit 902, the normal state 982 is entered, and the processor main circuit 902 starts normal operation. As described above, the processor chip 901 enters the low power consumption mode and can be restored by an interrupt. FIG. 19 illustrates a sequence in which the normal sleep instruction 959 is used to enter the standby state 985 and the RESET # 952 returns to the normal state 982. (1) The operation mode enters the standby state 985 by the sleep command 959. Here, the operation mode control unit 913 outputs a fixed 1.8V signal 953, fixes the signal from 3.3V to 1.8V, and stops the 1.8V system clock. This prevents malfunction of the 1.8V circuit when the board bias is pulled. After that, 1. It measures that the signal fixing is completed by the 8V signal fixing 953, and outputs the board bias control start signal 955 to the board bias generation circuit 903. (2) In response to the board bias control start signal 955, the board bias generation circuit 903 starts to draw the board bias of the 1.8V system board. During the period when the board bias is pulled, the 956 signal during the board bias control is returned to the operation mode control unit 913. (3) The processor main circuit 902 does not operate when the board bias is pulled. Further, since the leakage current is small, the current consumption is small. (4) In this state, the operation mode control unit 913 accepts RESET # 952 and releases the board bias control start signal 955. (5) Upon canceling the board bias control start signal 955, the board bias generation circuit 903 starts returning the board bias of the 1.8V-based board to the operating potential. When the board bias is returned, the operation mode control unit 913 is notified by using the board bias control signal 956. (6) In response to this release signal, the 1.8V signal fixed 953 is released. (7) After the reset state 981 is completed, a signal is input to a 1.8V system circuit such as the processor main circuit 902, the normal state 982 is entered, and the processor main circuit 902 starts normal operation. As described above, the processor chip 901 enters the low power consumption mode and can be restored by resetting. As described above, the processor chip 901 has a part in which 1.8V is supplied as a power supply voltage and a part in which 3.3V is supplied as a power supply voltage. As a part to which 1.8V is supplied, for example, there is a processor main circuit 902 and the like. This part has a large circuit scale and needs to be operated at a higher speed. Since the circuit scale is large and high-speed operation is required, the power consumption of this part increases. In this embodiment, the power supply voltage is lowered in order to reduce this power consumption. Also, if the power supply voltage is low (for example, 1.8V), the operating speed will be slow, so the threshold voltage of the MOS transistor will be low (for example, Vth <0. (About 4V). Further, in this embodiment, the substrate voltage is controlled in order to reduce the subthreshold leakage current due to this low threshold value. On the other hand, the part where 3.3V is supplied as the power supply voltage is, for example, the RTC circuit 914. Since these circuits are small and operate at low speed, they consume less power. Therefore, such a circuit block does not need to lower the power supply voltage. For example, Vth> 0.5V can be set. Since it is not necessary to lower the threshold value of the MOS transistor, there is an advantage that it is not necessary to take measures against current by controlling the substrate in order to reduce the subthreshold leakage current. The processor chip 901 of this embodiment uses both power supply voltages properly. That is, in the part where large-scale high-speed operation is required, the low-voltage low-threshold MOS is used under board control, and the high-voltage high-threshold MOS is used without board control. The method of making MOS transistors with different thresholds is not particularly limited, but it can be realized by changing the amount of channel impedance. It can also be realized by changing the thickness of the gate oxide film. In the latter case, the threshold value may be increased by increasing the oxide film thickness in the configuration of the MOS transistor. This is because a high threshold MOS is operated at a high voltage, so it is necessary to increase the oxide film thickness. The process can be simplified if the threshold can be increased by thickening the oxide film. Furthermore, since the input / output circuit 909 needs to transmit and receive an external signal amplitude of 3.3 V, it is desirable to use the same MOS transistor as the high voltage threshold MOS because the process can be shared. It can be set to about 5V. Since it is not necessary to lower the threshold value of the MOS transistor, there is an advantage that it is not necessary to take measures against current by controlling the substrate in order to reduce the subthreshold leakage current. The processor chip 901 of this embodiment uses both power supply voltages properly. That is, in the part where large-scale high-speed operation is required, the low-voltage low-threshold MOS is used under board control, and the high-voltage high-threshold MOS is used without board control. The method of making MOS transistors with different thresholds is not particularly limited, but it can be realized by changing the amount of channel impedance. It can also be realized by changing the thickness of the gate oxide film. In the latter case, the threshold value may be increased by increasing the oxide film thickness in the configuration of the MOS transistor. This is because a high threshold MOS is operated at a high voltage, so it is necessary to increase the oxide film thickness. The process can be simplified if the threshold can be increased by thickening the oxide film. Furthermore, since the input / output circuit 909 needs to transmit and receive an external signal amplitude of 3.3 V, it is desirable to use the same MOS transistor as the high voltage threshold MOS because the process can be shared. It can be set to about 5V. Since it is not necessary to lower the threshold value of the MOS transistor, there is an advantage that it is not necessary to take measures against current by controlling the substrate in order to reduce the subthreshold leakage current. The processor chip 901 of this embodiment uses both power supply voltages properly. That is, in the part where large-scale high-speed operation is required, the low-voltage low-threshold MOS is used under board control, and the high-voltage high-threshold MOS is used without board control. The method of making MOS transistors with different thresholds is not particularly limited, but it can be realized by changing the amount of channel impedance. It can also be realized by changing the thickness of the gate oxide film. In the latter case, the threshold value may be increased by increasing the oxide film thickness in the configuration of the MOS transistor. This is because a high threshold MOS is operated at a high voltage, so it is necessary to increase the oxide film thickness. The process can be simplified if the threshold can be increased by thickening the oxide film. Furthermore, since the input / output circuit 909 needs to transmit and receive an external signal amplitude of 3.3 V, it is desirable to use the same MOS transistor as the high voltage threshold MOS because the process can be shared.