Fec frame forming method and fec multiplexing device

[0001] The present invention has a FEC frame configuration for correcting bit errors due to deterioration of optical SNR by FEC (Forward Error Correction) in an optical transmission system to realize long-distance, large-capacity transmission. It relates to a method and an FEC multiplexing device.

[0002] FIG. 8 is a configuration diagram showing, for example, a conventional FEC multiplexing device shown in ITU-T Recommendation G.975. In the figure, 1 is 2.5 Gbit / s STM-16 data. The first multiplex separation circuit that multiplexes parallel 156Mbit / s data, and 2 is the second multiplex separation circuit that multiplexes 16 parallel 156Mbit / s data into 128 parallel 19Mbit / s data. 3 is the first speed conversion circuit that adds a redundant information area to 128 parallel 19 Mbit / s data and raises the transmission speed to 21 Mbit / s by the amount of the added redundant information area, and 4 is the maintenance of the optical transmission system. This is an overhead insertion circuit that inserts overhead information such as frame synchronization information necessary for operation into the redundant information area. 5 is an RS (255,239) coding circuit represented by a Reed-Solomon (RS) code that generates an error correction code for the overhead information and STM-16 data and stores the redundant information in the redundant information area, and 6 is the overhead information. The first multiplexing circuit that multiplexes STM-16 data with an error correction code added to 16 parallel 167 Mbit / s data, and 7 is the second that multiplexes 16 parallel 167 Mbit / s data into 2.66 Gbit / s FEC frames. It is a multiplexing circuit of.

[0003] Further, 8 is a third multiplexing circuit, 9 which is multiplexed by the second multiplexing circuit 7 and multiplexes 2.66 Gbit / s FEC frames transmitted through the optical transmission line into 16 parallel 167 Mbit / s data. Is a fourth multiplexing circuit that multiplexes 16 parallel 167 Mbit / s data into 128 parallel 21 Mbit / s data. 10 is a frame synchronization circuit that detects the start position of 128 parallel 21Mbit / s data according to the overhead information of the redundant information area added to 128 parallel 21Mbit / s data, and 11 is decoding processing of 128 parallel 21Mbit / s data. , Error correction of the added redundant information area This is an RS (255,239) decoding circuit that detects an error in the data in the FEC frame according to the decoding of the code and corrects it to the original correct data. 12 is an overhead separation circuit that separates the overhead information from the redundant information area of 128 parallel 21 Mbit / s data, and 13 is the transmission speed by deleting the redundant information area from 128 parallel 21 Mbit / s data and removing the redundant information area. Second speed conversion circuit that reduces to 19Mbit / s, 14 is a third multiplexing circuit that multiplexes 128 parallel 19Mbit / s data to 16 parallel 156Mbit / s data, 15 is 16 parallel 156Mbit / s data 2.5Gbit / sSTM-16 This is the fourth multiplexing circuit that multiplexes data.

[0004] Next, the operation will be described. In FIG. 8, the first multiplex separation circuit 1 multiplexes 2.5 Gbit / s STM-16 data into 16 parallel 156 Mbit / s data, and the second multiplex separation circuit 2 multiplexes 16 parallel 156 Mbit / s data. 128 Parallel multiplex separation into 19Mbit / s data. The first speed conversion circuit 3 adds a redundant information area to 128 parallel 19 Mbit / s data, increases the transmission speed by the amount of the added redundant information area, converts it to 128 parallel 21 Mbit / s data, and overheads. The insertion circuit 4 inserts overhead information such as frame synchronization information necessary for maintenance and operation of the optical transmission system into the redundant information area. The RS (255,239) coding circuit 5 generates an error correction code for the overhead information and the STM-16 data, and stores the redundant information in the redundant information area. The first multiplexing circuit 6 multiplexes the STM-16 data to which the overhead information and the redundant information are added into 16 parallel 167 Mbit / s data, and the second multiplexing circuit 7 multiplexes the 16 parallel 167 Mbit / s data. Is multiplexed into 2.66 Gbit / sFEC frames and transmitted to the optical transmission line.

[0005] Further, the third multiplexing circuit 8 multiplexes the 2.66 Gbit / s FEC frame, which is multiplexed by the second multiplexing circuit 7 and transmitted through the optical transmission line, into 16 parallel 167 Mbit / s data. Further, the fourth multiplex separation circuit 9 multiplexes 16 parallel 167 Mbit / s data into 128 parallel 21 Mbit / s data. The frame synchronization circuit 10 detects the start position of the 128 parallel 21Mbit / s data according to the overhead information of the redundant information area added to the 128 parallel 21Mbit / s data, and the RS (255,239) decoding circuit 11 detects the 128 parallel 21Mbit / s data. / s Data is decoded, and the error of the data in the FEC frame is detected according to the decoding of the redundant information of the error correction code of the added redundant information area, and the original correct data is corrected. The overhead separation circuit 12 separates the overhead information from the redundant information area of 128 parallel 21 Mbit / s data, and the second speed conversion circuit 13 removes the redundant information area from the 128 parallel 21 Mbit / s data to remove the redundant information area. The transmission speed is reduced to 19 Mbit / s by the amount of the deletion, and the third multiplexing circuit 14 multiplexes 128 parallel 19 Mbit / s data to 16 parallel 156 Mbit / s data, and further, the fourth multiplexing circuit 15 Multiplexes 16 parallel 156 Mbit / s data to 2.5 Gbit / s STM-16 data.

[0006] FIG. 9 is a configuration diagram showing an FEC frame output from the overhead insertion circuit, and FIG. 10 is a FEC frame output from the RS (255,239) coding circuit and FEC output from the second multiplexing circuit. It is a block diagram which shows the frame. As shown in FIG. 9, the FEC frame output from the overhead insertion circuit 4 is subframes 1 to 128 consisting of 1-bit overhead information, 238-bit STM-16 data, and 16-bit RS (255,239) error correction code. As shown in FIG. 10, error correction coding is performed every 8 subframes by the RS (255,239) coding circuit 5. For example, in subframes 1 to 8, operations of error correction codes ER0-0 to ER0-15 are performed on the overhead information and STM-16 data, and are stored in the 16-bit RS (255,239) redundant information area. The FEC frame output from the second multiplexing circuit 7 is generated by sequentially multiplexing subframes 1 to 128. Here, f is an arbitrary natural number and indicates the number of multiplexings of the error correction codes ER0-0 to ER0-15. In FIGS. 9 and 10, an example of f = 16 is shown. In this FEC frame, the FEC frame output from the second multiplex separation circuit 2 is 238-bit STM-16 data, whereas the first speed conversion circuit 3 provides 1-bit overhead information and 16 bits. A redundant information area consisting of RS (255,239) redundant information is added, and the transmission speed is increased by the amount of the added redundant information area. Therefore, the transmission speed is 255 / of the transmission speed of the original STM-16 data. 238 times higher, FEC frame transmission speed from 2.5 Gbit / s 2. It will be 66 Gbit / s. By configuring the FEC frame in this way, bit errors can be corrected, so that high-quality services can be provided in an optical transmission system in which the optical SNR deteriorates, and a long distance or a large capacity can be provided. It becomes possible to construct an optical transmission system. Further, in the FEC frame configuration shown in FIGS. 9 and 10, the STM-16 data in the subframe is shortened from 238 bits to 110 bits, and RS (255,239) error correction coding is changed to RS (127,111) error correction coding. Then, since the ratio of the error correction code to the target information increases, the error correction performance can be improved.

[0007] [Problems to be Solved by the Invention] Since the conventional FEC frame configuration method and the FEC multiplexing device are configured as described above, the transmission distance of the optical transmission line can be set to a longer distance or the wavelength. When the number of wavelengths is increased in a multiplex system, the optical SNR deteriorates significantly. To compensate for this, for example, by increasing the ratio of the error correction code to the target information, it can be corrected to some extent. By increasing the ratio of error correction code to the target information, the ratio of increase in transmission speed by the first speed conversion circuit 3 must be further increased. For example, in RS (127,111) error correction coding, STM-16 The data transmission speed is 2.5 Gbit / s, and the FEC frame transmission speed is 2.89 Gbit / s, which is 127/110 times higher, and the amount of deterioration of the optical transmission characteristics becomes large. Therefore, even if the ratio of the error correction code to the target information is increased, there is a problem that a long-distance, large-capacity optical transmission system of predetermined quality cannot be constructed.

[0008] The present invention has been made to solve the above problems, and even if the ratio of error correction codes to information increases, the transmission speed increases, and the amount of deterioration of optical transmission characteristics increases. The purpose is to obtain an FEC frame configuration method and FEC multiplexing device that can significantly improve error correction performance.

[Means for Solving the Problems] The FEC frame configuration method according to the present invention encodes information in n subframes for each m subframes and generates a first error correction code. The first error correction code generation step to be added and the n subframes to which the first error correction code is added are divided into m subframes, and the information of the subframes in n / m units is obtained. An interleaving process that interleaves l times, and a second error correction code generation process that encodes information in n subframes for each m subframes and generates and adds a second error correction code. , It is provided with an FEC frame generation step of generating an FEC frame by n-multiplexing n subframes to which a second error correction code is added.

[0010] In the FEC frame configuration method according to the present invention, n subframes are divided into m subframes, and n subframes are interleaved l times with respect to the information of the subframes in n / m units. An interleaving step for generating subframes, and a first error-correcting code generation step for encoding information in n subframes for each m subframes and generating and adding a first error-correcting code. The deinterleaved process that deinterleaves n subframes to which the first error correction code is added l times and returns the information interleaved by the interleaving process to the original information, and the information in n subframes. On the other hand, the second error correction code generation step of encoding every m subframes to generate and add a second error correction code, and n subframes to which the second error correction code is added are n. It is provided with an FEC frame generation step of multiplexing to generate an FEC frame.

[0011] In the FEC frame construction method according to the present invention, l is n / m.

[0012] In the FEC frame construction method according to the present invention, l is k times n / m, and k FEC frames are regarded as one cycle, and n / m times of interleaving for different information of each FEC frame. Is to do.

[0013] In the FEC frame configuration method according to the present invention, the first error correction code and the second error correction code are represented by RS (q, r) and RS (p, q), respectively, as a Reed-Solomon code (p). , q and r are natural numbers, p> q> r, p is the code length of the second error correction code, q is the information length of the second error correction code and the code length of the first error correction code, r Is the information length of the first error correction code).

[0014] The FEC multiplexing device according to the present invention generates a first error correction code for parallel information whose order has been rearranged by the first interleaving means, and stores the first error correction code in the redundant information area. A coding means, a second error-correcting coding means that generates a second error-correcting code for the parallel information reassembled by the first deinterleaving means and stores it in the redundant information area, and an optical transmission path. By a second error correction decoding means and a second interleaving means that decode the second error correction code stored in the redundant information area of the parallel information of the FEC frame transmitted through and correct the error of the parallel information. A first error correction decoding means that decodes the first error correction code stored in the redundant information area of the rearranged parallel information and corrects the residual error of the parallel information, and a second interleaving means of the parallel information. It is provided with a second deinterleaving means for recombining the rearranged order in the original order.

[0015] The FEC multiplexing device according to the present invention has a multi-stage longitudinal sequence of error correction means including a second error correction / decoding means, a second interleaving means, a first error correction / decoding means, and a second deinterleaving means. It is connected.

[0016] The FEC multiplexing device according to the present invention configures an FEC frame according to a FEC frame configuration method and processes the configured FEC frame.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described. Embodiment 1. FIG. 1 is a configuration diagram showing an optical transmission system to which the FEC frame configuration method and the FEC multiplexing device according to the first embodiment of the present invention are applied. In the figure, 21 receives an STM-16 optical signal. Then, the first optical receiver that converts the optical signal into an electric signal, 22 multiplexes the electric signal from the first optical receiver 21, inserts overhead information, performs error correction coding, and the like. The FEC multiplexing circuit (FEC multiplexing device) that performs multiplexing again at, and constitutes the FEC frame, 23 is the first optical transmitter that converts the FEC frame into an optical signal. 24 is an optical transmission line that transmits the FEC frame of the optical signal, 25 is the second optical receiver that converts the FEC frame transmitted by the optical transmission line 24 from the optical signal to the electric signal, and 26 is the second optical receiver. FEC multiplexing circuit (FEC multiplexing device) that multiplexes electrical signals from 25, performs processing such as frame synchronization of FEC frames, decoding of error correction codes, and separation of overhead information, and then multiplexes again. , 27 are the second optical transmitters that convert the electric signal from the FEC multiplexing circuit 26 into an optical signal and output the STM-16 optical signal.

FIG. 2 is a configuration diagram showing the FEC multiplexing device according to the first embodiment of the present invention. In the figure, the upper row shows the FEC multiplexing circuit 22 in FIG. 1, and the lower row shows the FEC multiplexing circuit 26 in FIG. It shows. In the figure, 1 is the first multiplex separation circuit (first multiplex separation means) that multiplexes 2.5Gbit / s STM-16 data into 16 parallel 156Mbit / s data, and 2 is 16 parallel 156Mbit / s data 128 parallel 19Mbit. It is a second multiplex separation circuit (first multiplex separation means) that multiplexes / s data. 31 is a first speed conversion circuit (first speed conversion means) that adds a redundant information area to 128 parallel 19 Mbit / s data and raises the transmission speed to 22 Mbit / s by the amount of the added redundant information area. Reference numeral 4 denotes an overhead insertion circuit (overhead insertion means) for inserting overhead information such as frame synchronization information necessary for maintenance and operation of an optical transmission system into a redundant information area. 32 is the first interleaving circuit (first interleaving means) that rearranges the order of 128 parallel 22Mbit / s data, 33 is RS (239,223) error correction coding, and the redundant information of the error correction code is stored in the redundant information area. It is an RS (239,223) coding circuit (first error correction coding means) to be stored. 34 is the first deinterleaved circuit (first deinterleaved means) that rearranges the order of 128 parallel 22 Mbit / s data rearranged in the first interleaved circuit 32 into the original order, and 5 is RS (255,239) error correction. It is an RS (255,239) coding circuit (second error correction coding means) that performs coding and stores the redundant information of the error correction code in the redundant information area. 6 is the first multiplexing circuit (first multiplexing means) that multiplexes 128 parallel 22Mbit / s data to 16 parallel 179Mbit / s data, and 7 is to multiplex 16 parallel 179Mbit / s data to 2.86Gbit / sFEC frames. It is the second multiplexing circuit (first multiplexing means) to be converted.

[0019] 8 is a third multiplex separation circuit (second multiplex separation means) that multiplexes 2.86 Gbit / s FEC frames into 16 parallel 179 Mbit / s data, and 9 is 16 parallel 179 Mbit / s data 128 parallel 22 Mbit / s. A fourth multiplex separation circuit (second multiplex separation means) that multiplexes data, and 10 is a frame synchronization circuit that detects the start position of 128 parallel 22Mbit / s data according to the overhead information stored in the redundant information area (2nd multiplex separation circuit). Frame synchronization means). Reference numeral 40 denotes an error correction circuit (error correction means). In this error correction circuit 40, 11 decodes 128 parallel 22 Mbit / s data and corrects bit errors according to the decoding of the RS (255,239) error correction code. RS (255,239) decoding circuit (second error correction decoding means), 35 is a second interleaving circuit (second interleaving means) that rearranges the order of 128 parallel 22Mbit / s data in the same way as the first interleaving circuit 32. , 36 decodes 128 parallel 22Mbit / s data excluding RS (255,239) redundant information and corrects bit errors according to the decoding of RS (239,223) error correction code RS (239,223) decoding circuit (first error) Correction / decoding means), 37 is a second deinterleaved circuit (second deinterleaved means) that rearranges the order of 128 parallel 22 Mbit / s data rearranged in the second interleaved circuit 35 into the original order. 12 is an overhead separation circuit (overhead separation means) that separates the overhead information from the redundant information area, and 38 is 128 parallel 22Mbit / s data. It is a second speed conversion circuit (second speed conversion means) that reduces the speed to 19 Mbit / s. 14 is a third multiplexing circuit (second multiplexing means) that multiplexes 128 parallel 19Mbit / s data into 16 parallel 156Mbit / s data, and 15 is 16 parallel 156Mbit / s data.

Next, the operation will be described. In FIG. 1, the first optical receiver 21 receives the STM-16 optical signal and converts the optical signal into an electrical signal. The FEC multiplexing circuit 22 multiplexes and separates the converted electric signal, stores the overhead information and the error correction code in the redundant information area, and performs multiplexing again to form the FEC frame. The first optical transmitter 23 converts the FEC frame into an optical signal and sends it to an optical transmission line 24 made of an optical fiber. The second optical receiver 25 converts the FEC frame transmitted through the optical transmission line 24 from an optical signal to an electric signal. The FEC multiplex separation circuit 26 multiplexes the converted electric signal, synchronizes the FEC frame with the frame according to the overhead information stored in the redundant information area, decodes the error correction code, and corrects the bit error. Then, the redundant information area is deleted and multiplexing is performed again. The second optical transmitter 27 converts the electric signal from the FEC multiplexing circuit 26 into an optical signal and outputs the STM-16 optical signal. Here, since the optical SNR deteriorates in the optical transmission line 24 due to the long-distance large-capacity transmission of the optical signal, a large number of bit errors occur in the FEC frame output from the second optical receiver 25. This bit error is corrected by the FEC multiplex separation circuit 26, and the bit error rate of the STM-16 optical signal output by the second optical transmitter 27 is greatly improved, and a communication service of a predetermined quality can be provided. ..

[0021] In the upper part of FIG. 2, that is, in the FEC multiplexing circuit 22, the first multiplex separation circuit 1 multiplexes 2.5 Gbit / s STM-16 data into 16 parallel 156 Mbit / s data, and the second multiplex separation. Circuit 2 multiplexes 16 parallel 156 Mbit / s data into 128 parallel 19 Mbit / s data. The first speed conversion circuit 31 adds a redundant information area to 128 parallel 19 Mbit / s data, and the transmission speed is increased to 22 Mbit / s by the amount of the added redundant information area, and the overhead insertion circuit 4 is optical. Overhead information such as frame synchronization information required for maintenance and operation of the transmission system is inserted into the redundant information area. The first interleaving circuit 32 rearranges the order of 128 parallel 22Mbit / s data, and the RS (239,223) coding circuit 33 performs RS (239,223) error correction coding, and the redundant information of the error correction code is redundant information. Store in the area. The first redundant circuit 34 rearranges the order of the 128 parallel 22 Mbit / s data rearranged in the first interleaved circuit 32 into the original order, and the RS (255,239) coding circuit 5 has an RS (255,239) error. Correction coding is performed, and the redundant information of the error correction code is stored in the redundant information area. The first multiplexing circuit 6 multiplexes 128 parallel 22Mbit / s data into 16 parallel 179Mbit / s data, and the second multiplexing circuit 7 further multiplexes 16 parallel 179Mbit / s data to 2.86Gbit / sFEC. Output the frame.

On the other hand, in the lower part of FIG. 2, that is, in the FEC multiplex separation circuit 26, the third multiplex separation circuit 8 multiplexes the 2.86 Gbit / s FEC frame into 16 parallel 179 Mbit / s data, and the fourth multiplex separation. Circuit 9 further multiplexes 16 parallel 179 Mbit / s data into 128 parallel 22 Mbit / s data. The frame synchronization circuit 10 verifies the overhead information stored in the redundant information area and detects the start position of 128 parallel 22 Mbit / s data. The RS (255,239) decoding circuit 11 in the error correction circuit 40 decodes 128 parallel 22 Mbit / s data and corrects bit errors according to the decoding of the RS (255,239) error correction code. The second interleaving circuit 35 rearranges the order of 128 parallel 22Mbit / s data in the same manner as the first interleaving circuit 32, and the RS (239,223) decoding circuit 36 is 128 parallel 22Mbit / s excluding RS (255,239) redundant information. The data is decoded, and the bit error is corrected according to the decoding of the RS (239,223) error correction code. The second deinterleaved circuit 37 rearranges the order of the 128 parallel 22 Mbit / s data rearranged in the second interleaved circuit 35 into the original order. The overhead separation circuit 12 separates the overhead information from the redundant information area, and the second speed conversion circuit 38 deletes the redundant information area from the 128 parallel 22 Mbit / s data, and the transmission speed is equal to the deleted redundant information area. To 19 Mbit / s. The third multiplexing circuit 14 multiplexes 128 parallel 19Mbit / s data into 16 parallel 156Mbit / s data, and the fourth multiplexing circuit 15 further multiplexes 16 parallel 156Mbit / s data to 2.5Gbit / s STM. -16 Output data.

FIG. 3 is a configuration diagram showing an FEC frame output from an overhead insertion circuit, FIG. 4 is a configuration diagram showing an FEC frame output from an RS (239,223) coding circuit, and FIG. 5 is a configuration diagram showing an FEC frame output from an RS (239,223) coding circuit. 255,239) It is a block diagram which shows the FEC frame output from a coding circuit and the FEC frame output from a second multiplexing circuit. As shown in FIG. 3, the 128 parallel 22 Mbit / s data output from the overhead insertion circuit 4 includes 1-bit overhead information, 222-bit STM-16 data, 16-bit RS (239,223) redundancy information, and 16-bit. It is composed of n (n = 128) subframes consisting of RS (255,239) redundant information. Here, it is assumed that the STM-16 data is used as transmission information, and the overhead information, RS (239,223) redundant information, and RS (255,239) redundant information are stored in the redundant information area. In the overhead insertion circuit 4, the overhead information is stored in each of the overhead information areas of the subframes 1 to 128. In Fig. 3, subframes 1 to 128 are divided into m (m = 8) subframes, and the overhead information OH1 to OH16 is divided into the overhead information area of the subframe in n / m (128/8 = 16) units. Is shown as being stored. In the first interleaving circuit 32, the 128 parallel 22 Mbit / s data shown in FIG. 3 is divided into m (m = 8) subframes as in the 128 parallel 22 Mbit / s data shown in FIG. , N / m (128/8 = 16) units Subframe data order is rearranged. Here, as an example of data rearrangement, the first column is not replaced, the second column shifts up by one every 8 subframes, the third column shifts up by two, ..., the 16th column is The upper 15 shifts and the 17th column show the upper 16 shifts (same as no replacement), that is, the case of interleaving l (l = 16) times (interleave process). RS (239, 223) The coding circuit 33 generates RS (239,223) error correction code for each of eight subframes for the overhead information and STM-16 data, as in the 128 parallel 22Mbit / s data shown in FIG. Then, the redundant information of the error correction code is stored in the RS (239,223) error correction code area of the redundant information area, respectively (first error correction code generation step). In the first deinterleaved circuit 34, the STM-16 data area is in the original order as in the 128 parallel 22 Mbit / s data shown in FIG. 5 with respect to the 128 parallel 22 Mbit / s data shown in FIG. Reorder the data for each subframe (interleave process, deinterleave process). The RS (255,239) coding circuit 5 has eight subframes for overhead information, STM-16 data, and RS (239,223) redundant information, such as 128 parallel 22Mbit / s data shown in the upper part of FIG. An RS (255,239) error correction code is generated for each, and the redundant information of the error correction code is stored in the redundant area of the RS (255,239) error correction code in the redundant information area (second error correction code generation step). The 128 parallel 22Mbit / s data shown in the upper part of FIG. 5 is multiplexed in the first multiplexing circuit 6 and the second multiplexing circuit 7, and the 2.86Gbit / sFEC frame shown in the lower part of FIG. 5 is configured. .. Where f is (n / m = 128/8 = 16). In the FEC frame of the first embodiment, a 33-bit redundant information area is added to the 222-bit STM-16 data with respect to the transmission speed of 2.86 Gbit / s of the original STM-16 data, and the transmission speed is 255. Since it will increase by / 222 times, the transmission speed of FEC frames will be 2.86 Gbit / s. 223) Store each in the error correction code area (first error correction code generation step). In the first deinterleaved circuit 34, the STM-16 data area is in the original order as in the 128 parallel 22 Mbit / s data shown in FIG. 5 with respect to the 128 parallel 22 Mbit / s data shown in FIG. Reorder the data for each subframe (interleave process, deinterleave process). The RS (255,239) coding circuit 5 has eight subframes for overhead information, STM-16 data, and RS (239,223) redundant information, such as 128 parallel 22Mbit / s data shown in the upper part of FIG. An RS (255,239) error correction code is generated for each, and the redundant information of the error correction code is stored in the redundant area of the RS (255,239) error correction code in the redundant information area (second error correction code generation step). The 128 parallel 22Mbit / s data shown in the upper part of FIG. 5 is multiplexed in the first multiplexing circuit 6 and the second multiplexing circuit 7, and the 2.86Gbit / sFEC frame shown in the lower part of FIG. 5 is configured. .. Where f is (n / m = 128/8 = 16). In the FEC frame of the first embodiment, a 33-bit redundant information area is added to the 222-bit STM-16 data with respect to the transmission speed of 2.86 Gbit / s of the original STM-16 data, and the transmission speed is 255. Since it will increase by / 222 times, the transmission speed of FEC frames will be 2.86 Gbit / s. 223) Store each in the error correction code area (first error correction code generation step). In the first deinterleaved circuit 34, the STM-16 data area is in the original order as in the 128 parallel 22 Mbit / s data shown in FIG. 5 with respect to the 128 parallel 22 Mbit / s data shown in FIG. Reorder the data for each subframe (interleave process, deinterleave process). The RS (255,239) coding circuit 5 has eight subframes for overhead information, STM-16 data, and RS (239,223) redundant information, such as 128 parallel 22Mbit / s data shown in the upper part of FIG. An RS (255,239) error correction code is generated for each, and the redundant information of the error correction code is stored in the redundant area of the RS (255,239) error correction code in the redundant information area (second error correction code generation step). The 128 parallel 22Mbit / s data shown in the upper part of FIG. 5 is multiplexed in the first multiplexing circuit 6 and the second multiplexing circuit 7, and the 2.86Gbit / sFEC frame shown in the lower part of FIG. 5 is configured. .. Where f is (n / m = 128/8 = 16). In the FEC frame of the first embodiment, a 33-bit redundant information area is added to the 222-bit STM-16 data with respect to the transmission speed of 2.86 Gbit / s of the original STM-16 data, and the transmission speed is 255. Since it will increase by / 222 times, the transmission speed of FEC frames will be 2.86 Gbit / s. 223) For redundant information, RS (255,239) error correction code is generated for each of eight subframes, and the redundant information of the error correction code is stored in the redundant area of RS (255,239) error correction code in the redundant information area. Store (second error correction code generation step). The 128 parallel 22Mbit / s data shown in the upper part of FIG. 5 is multiplexed in the first multiplexing circuit 6 and the second multiplexing circuit 7, and the 2.86Gbit / sFEC frame shown in the lower part of FIG. 5 is configured. .. Where f is (n / m = 128/8 = 16). In the FEC frame of the first embodiment, a 33-bit redundant information area is added to the 222-bit STM-16 data with respect to the transmission speed of 2.86 Gbit / s of the original STM-16 data, and the transmission speed is 255. Since it will increase by / 222 times, the transmission speed of FEC frames will be 2.86 Gbit / s. 223) For redundant information, RS (255,239) error correction code is generated for each of eight subframes, and the redundant information of the error correction code is stored in the redundant area of RS (255,239) error correction code in the redundant information area. Store (second error correction code generation step). The 128 parallel 22Mbit / s data shown in the upper part of FIG. 5 is multiplexed in the first multiplexing circuit 6 and the second multiplexing circuit 7, and the 2.86Gbit / sFEC frame shown in the lower part of FIG. 5 is configured. .. Where f is (n / m = 128/8 = 16). In the FEC frame of the first embodiment, a 33-bit redundant information area is added to the 222-bit STM-16 data with respect to the transmission speed of 2.86 Gbit / s of the original STM-16 data, and the transmission speed is 255. Since it will increase by / 222 times, the transmission speed of FEC frames will be 2.86 Gbit / s.

On the other hand, in the FEC multiplex separation circuit 26, the RS (255,239) decoding circuit 11 has 128 parallel 22 Mbit / s data overhead information, STM-16 data, and RS (239,223) redundant information shown in the upper part of FIG. , And RS (255,239) redundancy information by performing RS (255,239) error correction decoding every 8 subframes, depending on the decoding of the RS (255,239) error correction code, overhead information, STM-16. Correct bit errors in data, RS (239, 223) redundancy and RS (255,239) redundancy. Here, when a large number of bit errors exceeding the correction performance occur, the bit errors remain in the output data of the RS (255,239) decoding circuit 11. The second interleaving circuit 35 rearranges the order of the 128 parallel 22Mbit / s data in the same manner as the first interleaving circuit 32, and the RS (239,223) decoding circuit 36 overheads the 128 parallel 22Mbit / s data shown in FIG. By performing RS (239,223) error correction decoding every eight subframes for information, STM-16 data, and RS (239,223) redundant information, depending on the decoding of the RS (239,223) error correction code, Correct the bit error remaining in each code. In this way, the information to be the target of error correction coding is rearranged between the RS (255,239) error correction code and the RS (239,223) error correction code, so that the bit error is distributed among the codes. It is possible to significantly improve the error correction performance. The second deinterleaved circuit 37 rearranges the order of the 128 parallel 22 Mbit / s data rearranged in the second interleaved circuit 35 into the original order.

[0025] As described above, according to the first embodiment, two types of error correction coding are performed in the FEC frame configuration method and the FEC multiplexing device, and the first interleave circuit 32 and the first deinterleave are performed. Since the circuit 34, the second interleaved circuit 35, and the second deinterleaved circuit 37 are arranged and the information is rearranged between the two types of error correction codes, the configuration is significantly higher than that shown in the conventional technique. Even if the error correction performance is improved and the transmission speed increases to 2.89 Gbit / s, it is possible to build a large-capacity optical transmission system over a long distance. Further, the first interleaving circuit 32 is arranged in front of the RS (239,223) coding circuit 33 in the first stage, and the first deinterleaving circuit 34 is arranged in front of the RS (255,239) coding circuit 5 in the next stage. Therefore, the STM-16 data in the FEC frame can be transmitted without changing the order. Furthermore, since the number of interleaved and deinterleaved times (l = 16) and the number of units of interleaved and deinterleaved subframes (n / m = 128/8 = 16) are the same, they are subject to error correction coding. Since the information is evenly rearranged and the information errors are evenly distributed, the error correction performance can be further improved, and the configuration of this FEC multiplexing device can be facilitated and miniaturized.

Embodiment 2. FIG. 6 is a configuration diagram showing an FEC multiplexing device according to a second embodiment of the present invention, RS (255,239) decoding circuit 11, second interleaving circuit 35, RS (239,223) decoding. An error correction circuit (error correction means) 40 composed of a circuit 36 and a second deinterleaved circuit 37 is connected in multiple stages.

[0027] Next, the operation will be described. FIG. 6 shows an error correction circuit 40 connected in multiple stages in the FEC multiplex separation circuit 26. According to the second embodiment, the correction of the bit error is sequentially repeated for two types of error correction codes. The error correction performance can be further improved, there is no need to change the configuration of the FEC frame, and no hardware changes other than connecting the error correction circuit 40 in multiple stages are required. It is possible to construct a capacitive optical transmission system.

Embodiment 3. FIG. 7 is an explanatory diagram showing a FEC frame configuration method according to Embodiment 3 of the present invention, and interleaves each FEC frame with k (k = 4) FEC frames as one cycle. The information to be performed is shifted by 16 bits, interleaved n / m (= 128/8 = 16) times, and interleaved all l times (l is k times n / m: 16 × 4 = 64). It is something to do.

[0029] Next, the operation will be described. In the first embodiment, the case where the interleave number l between the two types of codes is l = 16, but the interleave number l is 16, for example, l = 32,48,64, ... By multiplying by a natural number, it is possible to improve the error correction performance while keeping the rate of increase in the transmission speed constant. Figure 7 shows the case where four FEC frames are set as one cycle. The information to be interleaved for each FEC frame is shifted by 16 bits, interleaved 16 times, and interleaved 16 × 4 = 64 times in total. You can do it.

[0030] As described above, according to the third embodiment, the basic configuration of the FEC frame is not changed, and the hardware is the first interleaving circuit 32, the first deinterleaving circuit 34, and the first. It is possible to improve the error correction performance while keeping the rate of increase in the transmission speed constant by simply changing the interleave circuit 35 of 2 and the deinterleave circuit 37 of the second, and the amount of deterioration of the optical SNR is large. It is possible to construct a long-distance, large-capacity optical transmission system.

Embodiment 4. In the above embodiment, an example of transmitting the optical transmission line 24 with the speed of the FEC frame set to 2.86 Gbit / s has been shown, but a plurality of FEC frames are further multiplexed and optical transmission is performed. The transmission speed of the optical signal transmitted on the road 24 may be a × 2.86 Gbit / s (a is an arbitrary natural number), and as transmission information, it was explained as 2.5 Gbit / s STM-16 data, but FEC multiplexing. The circuit 22 and the FEC multiplex separation circuit 26 are arranged in b to process the FEC frame of the b system (b is an arbitrary natural number), and the information is b × 2.5 Gbit / s data (for example, when b = 4). 10Gbit / s STM-64 data), and further, it is possible to apply the same FEC frame configuration as the above-mentioned conventional technology to the data of the transmission speed according to other standards, in this case. , The speed of the FEC frame corresponding to the data of the transmission speed according to other standards.

Embodiment 5. In the above embodiment, an example of RS (255,239) and RS (239,223) displayed as a Reed-Solomon (RS) code as an error correction code is shown. For example, RS (255,239) And RS (239,207). Here, if the code length of the former RS code is p, the information length is q, and the information length of the latter RS code is r, then RS (p, q) and RS (q, r) may be used, the bit length of each subframe in the FEC frame may be a value corresponding to the values of p, q, and r, and an example in which the overhead information is set to 1 bit in each subframe. As shown, each subframe may be provided with two or more bits of overhead information.

[Effect of the Invention] As described above, according to the present invention, information in n subframes is encoded for each m subframes, and a first error correction code is generated and added. The first error correction code generation step and the n subframes to which the first error correction code is added are divided into m subframes, and l is applied to the information of the subframes in n / m units. An interleaving process that interleaves once, a second error correction code generation process that encodes information in n subframes for each m subframes and generates and adds a second error correction code, and a second. Since it is configured to include an FEC frame generation step of generating an FEC frame by n-multiplexing n subframes to which the error correction code of the above is added, if the FEC frame is configured by this FEC frame configuration method, an error will occur. Since two types of first and second error correction codes in which the information to be corrected coded are rearranged from each other are added, the receiving side decodes those two types of first and second error correction codes. By doing so, it is possible to correct residual errors that cannot be corrected by decoding one type of error correction code. Therefore, even if the ratio of the error correction code to the information increases, the transmission speed increases, and the amount of deterioration of the optical transmission characteristics increases, the effect that the error correction performance can be significantly improved can be obtained.

[0034] According to the present invention, an interleaving step of dividing n subframes into m subframes and interleaving the information of the subframes in n / m units l times, and n subframes. The first error correction code generation step in which the information in the frame is encoded for each m subframes and the first error correction code is generated and added, and the n pieces to which the first error correction code is added. The deinterleaved process that deinterleaves the subframes l times and returns the information interleaved by the interleaving process to the original information, and the information in n subframes is encoded for each m subframes and the second A second error correction code generation step of generating and adding an error correction code of, and an FEC frame generation step of n-multiplexing n subframes to which the second error correction code is added to generate an FEC frame. Therefore, if the FEC frame is configured by this FEC frame configuration method, two types of first and second error correction codes in which the information to be error correction coding is rearranged are added. Therefore, on the receiving side, by decoding these two types of first and second error correction codes, it is possible to correct residual errors that cannot be corrected by decoding one type of error correction code. Therefore, even if the ratio of the error correction code to the information increases, the transmission speed increases, and the amount of deterioration of the optical transmission characteristics increases, the effect that the error correction performance can be significantly improved can be obtained. Further, by deinterleaving the information interleaved by the interleaving process by the deinterleaving process, the FEC frame is constructed by returning to the original information, so that the FEC frame of the original information whose order is not rearranged is transmitted. The effect that can be obtained is obtained.

[0035] According to the present invention, since l is configured to be n / m, the number of interleaves and the number of deinterleaves and the number of units of the interleaved and deinterleaved subframes are the same, and the error correction coding is performed. Since the target information is evenly rearranged and the information errors are evenly distributed, the error correction performance can be further improved, and the device configuration for generating the FEC frame is facilitated by this FEC frame configuration method. The effect of miniaturization can be obtained.

[0036] According to the present invention, l is k times n / m, and k FEC frames are regarded as one cycle, and different information of each FEC frame is interleaved n / m times. Since it is configured, the effect of further improving the error correction performance can be obtained while keeping the rate of increase in the transmission speed constant.

[0037] According to the present invention, a Reed-Solomon code (p, q and r) in which the first error correction code and the second error correction code are represented by RS (q, r) and RS (p, q), respectively. Is a natural number, p> q> r, p is the code length of the second error correction code, q is the information length of the second error correction code and the code length of the first error correction code, and r is the first error correction code. Since it is configured to have the information length of the error correction code), it is possible to easily configure an FEC frame that can improve the error correction performance while keeping the rate of increase in the transmission speed constant according to the above conditions. You can get the effect you can.

[0038] According to the present invention, there is a first error correction coding means that generates a first error correction code for parallel information whose order has been rearranged by the first interleaving means and stores it in a redundant information area. , A second error correction code was generated for the parallel information reassembled by the first deinterleaved means and stored in the redundant information area, and was transmitted through the optical transmission line. The second error correction decoding means that decodes the second error correction code stored in the redundant information area of the parallel information of the FEC frame and corrects the error of the parallel information, and the parallel rearranged by the second interleaving means. The first error correction code stored in the redundant information area of information is decoded, and the first error correction decoding means for correcting the residual error of the parallel information and the second interleaving means for the parallel information are recombined. Since the FEC frame transmitted to the optical transmission line was configured to have a second deinterleaving means for rearranging the order back to the original order, the information to be error-corrected coded was rearranged with each other2. Since the first and second error correction codes of the type are added, the receiving side corrects by decoding the first and second error correction codes of the two types in the decoding of the error correction code of one type. It is possible to correct residual errors that cannot be done. Therefore, even if the ratio of the error correction code to the information increases, the transmission speed increases, and the amount of deterioration of the optical transmission characteristics increases, the effect that the error correction performance can be significantly improved can be obtained. Further, by deinterleaving the information interleaved by the first interleaving means by the first deinterleaving means, the FEC frame of the original information whose order has not been rearranged can be transmitted to the optical transmission line. Is obtained.

[0039] According to the present invention, the error correction means including the second error correction / decoding means, the second interleaving means, the first error correction / decoding means, and the second deinterleaving means are connected in multiple stages. Since it is configured, the error correction performance can be further improved by repeating a large number of error corrections for two types of error correction codes without changing the configuration of the FEC frame by simply additionally configuring the error correction means. The effect that can be obtained is obtained.

[0040] According to the present invention, since the FEC frame is configured according to the FEC frame configuration method and the configured FEC frame is processed, the FEC multiplexing device including the effect of the FEC frame configuration method is included. Has the effect of obtaining.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram showing an optical transmission system to which the FEC frame configuration method and the FEC multiplexing device according to the first embodiment of the present invention are applied.

FIG. 2 is a configuration diagram showing an FEC multiplexing device according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram showing a FEC frame output from an overhead insertion circuit.

FIG. 4 is a configuration diagram showing an FEC frame output from an RS (239,223) coding circuit.

FIG. 5 is a configuration diagram showing a FEC frame output from the RS (255,239) coding circuit and a FEC frame output from the second multiplexing circuit.

FIG. 6 is a configuration diagram showing an FEC multiplexing device according to a second embodiment of the present invention.

FIG. 7 is an explanatory diagram showing a FEC frame configuration method according to the third embodiment of the present invention.

FIG. 8 is a configuration diagram showing a conventional FEC multiplexing device.

FIG. 9 is a configuration diagram showing a FEC frame output from an overhead insertion circuit.

FIG. 10 is a configuration diagram showing a FEC frame output from the RS (255,239) coding circuit and a FEC frame output from the second multiplexing circuit.

[Explanation of Codes] 1 First Multiplexing Circuit (1st Multiplexing Means), 2 2nd Multiplexing Circuit (1st Multiplexing Means), 4 Overhead Insertion Circuit (Overhead Inserting Means), 5 RS ( 255,239) Coding circuit (second error correction coding means), 6 first multiplexing circuit (first multiplexing means), 7 second multiplexing circuit (first multiplexing means), 8th 3 FEC Multiplexing Circuit (2nd Multiplexing Means), 9 4th FEC Multiplexing Circuit (2nd Multiplexing Means), 10 Frame Synchronizing Circuit (Frame Synchronizing Means), 11 RS (255,239) Decoding Circuit ( 2nd error correction decoding means), 12 Overhead separation circuit (Overhead separation means), 14 3rd multiplexing circuit (2nd multiplexing means), 15 4th multiplexing circuit (2nd multiplexing means) , 21 1st optical receiver, 22 FEC multiplexing circuit (FEC multiplexing device), 23 1st optical transmitter, 24 optical transmission line, 25 2nd optical receiver, 26 FEC multiplexing circuit (FEC multiplexing) Device), 27 2nd optical transmitter, 31 1st speed conversion circuit (1st speed conversion means), 32 1st interleaving circuit (1st interleaving means), 33 RS (239,223) coding circuit (1st error correction coding means), 34 1st deinterleaved circuit (1st deinterleaving means), 35th 2 interleaving circuit (second interleaving means), 36 RS (239,223) decoding circuit (first error correction decoding means), 37 second deinterleaving circuit (second deinterleaving means), 38 second speed Conversion circuit (second speed conversion means), 40 error correction circuit (error correction means).