Method for fabricating thin film transistor including a crystalline silicone active layer

[0001] The present invention relates to a thin film transistor (TFT) used in a display device such as a liquid crystal display (LCD) and an organic light emitting diode (OLED). In particular, the present invention relates to a thin film transistor in which the active layer forming the source, drain and channel of the thin film transistor is formed of crystalline silicon, and a method for manufacturing the thin film transistor.

[0002] Conventional Techniques Generally, a thin film transistor used in a display device such as an LCD or OLED deposits silicon on a transparent substrate such as glass or quartz to form a gate and a gate electrode, and a dopant is applied to a source and a drain. It is composed by forming an insulating layer after injecting and activating it by performing an annealing treatment.

[0003] The active layer constituting the source, drain and channel of the thin film transistor is usually formed by depositing a Si layer on a transparent substrate such as glass by using a chemical vapor deposition (CVD) method. However, the Si layer directly deposited on the substrate by a method such as CVD has low electron mobility as an amorphous Si film.

[0004] A display device using a thin film transistor is required to have a high operating speed. However, as the size of the drive IC increases, the aperture ratio of the pixel region tends to decrease. Therefore, the electron mobility of the Si film is increased to form a drive circuit at the same time as the pixel TFT, and the drive circuits are individually formed. It is necessary to increase the pixel aperture ratio of. Therefore, a technique has been proposed in which the amorphous Si layer is heat-treated and crystallized as a crystalline Si layer having a polycrystalline structure having high electron mobility.

[0005] Various methods have been proposed for crystallizing an amorphous Si layer of a thin film transistor as a crystalline Si layer. Solid Phase Crystallization (SPC) is a method of annealing an amorphous Si layer at a temperature of 600 ° C or less, which is the transition temperature of glass, which is a substrate-forming substance, for several hours to several tens of hours. is there.

[0006] However, since the SPC method requires a long time for heat treatment, if the productivity is low and the area of the substrate is large, the substrate may be deformed during the long heat treatment process even at a temperature of 600 ° C. or lower. There was a problem.

[0007] The excimer laser crystallization method (ELC) is a method in which an excimer laser is irradiated to a Si layer to locally generate a high temperature in a very short time to instantaneously crystallize the Si layer. Is. The ELC method is technically difficult to precisely control the irradiation of laser light and can only process one substrate at a time, so it is more productive than processing many substrates at the same time in a blast furnace. There was a problem that it became low.

[0008] In order to overcome the problems of the conventional Si layer crystallization method, a metal such as nickel, gold, or aluminum is brought into contact with amorphous silicon, or these metals are injected into silicon. Has been proposed. In this case, the phenomenon that the phase change from amorphous silicon to crystalline silicon is induced even at a low temperature of about 200 ° C. is utilized. Such a phenomenon is called Metal Induced Crystallization (MIC). However, when a thin film transistor is manufactured using the MIC phenomenon, there arises a problem that metal remains in the crystalline silicon constituting the active layer of the thin film transistor, and a current leak occurs particularly in the channel portion of the thin film transistor.

[0009] Recently, instead of the MIC in which the metal directly induces the phase change of silicon, the metal-induced side surface in which the metal generated by the reaction of the metal and silicon continues to propagate to the side surface and sequentially induces the crystallization of silicon. A method of crystallizing the Si layer using the crystallization (Metal Induced Lateral Crystallization: MILC) phenomenon has been proposed (see SW Lee & S.K. Joo, IEEE Electron Device Letter, 17 (4), p.160, 1996).

[0010] Nickel, palladium, and the like are particularly known as metals that cause such a MILC phenomenon. When the Si layer is crystallized using the MILC phenomenon, the methacrylate interface containing the metal moves to the side surface as the phase change of the Si layer is propagated. In the Si layer crystallized by using the MILC phenomenon in this way, almost no metal component used for inducing crystallization remains. Therefore, there is an advantage that the current leakage of the transistor activation layer and other operating characteristics are not affected. Moreover, when the MILC phenomenon is used, crystallization of silicon can be induced at a relatively low temperature of 300 ° C to 500 ° C. Therefore, there is an advantage that a plurality of substrates can be crystallized at the same time without damaging the substrates by using the blast furnace.

[0011] FIGS. 1 to 4 are cross-sectional views showing a process of a prior art in which a Si layer constituting a TFT is crystallized by using the MIC and MILC phenomena. As shown in FIG. 1, the amorphous Si layer 11 is formed on the insulating substrate 10 on which the buffer layer (not shown) is formed, and the amorphous silicon is patterned by photolithography to form the active layer 11. Will be done.

[0012] The gate insulating layer 12 and the gate electrode 13 are formed on the active layer 11 by a conventional method. As shown in FIG. 2, the entire substrate is doped with impurities using the gate electrode 13 as a mask to form a source region 11S, a channel region 11C, and a drain region 11D in the active layer.

As shown in FIG. 3, the photoresist 14 is formed so as to cover the gate electrode 13, the source region 11S and the drain region 11D around the gate electrode 13, and the entire surface of the substrate 10 and the photoresist 14 is made of metal. Layer 15 is formed by vapor deposition.

As shown in FIG. 4, the photoresist 14 was removed, the entire substrate was annealed at a temperature of 300 ° C to 500 ° C, and the source and drain regions 11S, 11D directly below the remaining metal layer 15 were formed. Part 16 is crystallized by the MIC phenomenon. Also, the rest of the source and drain regions 11S, 11D where the metal layer 15 is not covered (metal-offset) and the portion 17 including the channel region 11C below the gate electrode 13 are derived from the remaining metal layer 15. Crystallization is induced by the MILC phenomenon.

[0015] In the techniques shown in FIGS. 1 to 4, it is the interface between the channel region 11C and the source and gate regions 11S, 11D that covers the photoresist 14 up to the source and drain regions 11S, 11D on both sides of the gate electrode 13. When the metal layer is formed up to, the metal component that has flowed in due to the MIC phenomenon remains in these interface and the channel region 11C, avoiding the problem of current leakage and deterioration of operating characteristics in the channel region 11C. Because.

[0016] The source and drain regions 11S and 11D excluding the channel region 11C are not significantly hindered by the residual metal component. Therefore, a part 16 of the source and drain regions separated from the channel region 11C by about 0.01 to 5 μm or more is crystallized by the MIC phenomenon, and crystallization by the MILC phenomenon is induced only in the channel region 11C and the peripheral region of the channel region 11C. To shorten the crystallization time. However, when the techniques shown in FIGS. 1 to 4 are used, there is a problem that it is necessary to add a step of forming the photoresist 14 in a general TFT manufacturing process and patterning and removing the photoresist 14. It was.

[0017] FIGS. 5 to 9 are cross-sectional views showing a process of manufacturing a crystalline silicon thin film transistor using solid phase crystallization, and include a step of forming an LDD (Lightly Doped Drain) region. By forming the LDD region in the drain region, the off-current of the transistor can be reduced and the electrical characteristics of the transistor can be stabilized.

As shown in FIG. 5, after patterning the active layer region 21, heat treatment is performed at a high temperature for a long time for solid phase heat treatment. In this case, the substrate 20 uses quartz that can withstand high temperatures. A gate insulating film 22, a lower gate electrode 23, and an upper gate electrode 24 are formed on the activation region 21 to form an LDD region as shown in FIG. Next, ion doping is performed in two steps. Initially, high concentration doping is performed to form the source region 21S and the drain region 21D (Fig. 7). After that, the upper gate electrode 24 is removed and ions are doped to a low concentration to form an LDD region (21LDD) (Fig. 8).

[0019] If the lid film and the metal wiring are formed by a conventional method, a thin film transistor having an LDD region can be formed. As shown in FIG. 9, when the LDD region is provided, the off-current can be reduced as described above, and the electrical characteristics of the transistor can be stabilized. Therefore, it is preferable to form the LDD region even when the TFT is constructed by using the MIC and MILC phenomena.

The present invention has been made in view of the above problems, and is a step of forming and removing another photoresist layer by using the MIC and MILC phenomena. It is an object of the present invention to provide a method for producing a TFT having an LDD region without doing so.

[0021] Another object of the present invention is to provide a TFT manufacturing method capable of forming an offset junction without performing a step of forming and removing a separate photoresist layer.

[Means for Solving the Problems] In order to achieve the above object, the invention of the method for manufacturing a thin film transistor according to claim 1 includes a crystalline silicon active layer, and the silicon active layer contains an LDD region or an offset. In the method of manufacturing a thin film transistor in which a joint is formed, an amorphous silicon layer is used as a substrate.<u style="single">Up</u>By forming the active layer of the thin film transistor, an insulating film and<u style="single">Becomes a gate electrode</u>A layer is formed on the active layer<u style="single">And</u>Photoresist layer<u style="single">It becomes the gate electrode</u>The photoresist layer is formed on the layer and the photoresist layer is patterned so as to have a shape corresponding to the desired shape of the gate electrode.<u style="single">Said</u>Patterned<u style="single">Said</u>Using the photoresist as a mask,<u style="single">The insulating film and</u>The gate electrode<u style="single">Etching and</u>Over-etched<u style="single">To form a gate insulating film and a gate electrode.</u>、<u style="single">After the overetching, the</u>Patterned<u style="single">Said</u>The active layer using a photoresist as a mask<u style="single">To</u>High-concentration impurity doping<u style="single">After the high concentration of impurity doping,</u>Patterned<u style="single">Said</u>Using a photoresist as a mask, a crystallization-inducing metal was formed on the active layer.<u style="single">Said</u>Patterned<u style="single">Said</u>The photoresist is removed and the active layer<u style="single">To</u>Dope with low concentration impurities<u style="single">After the low concentration of impurity doping,</u>Annealing the active layer<u style="single">And crystallize the active layer</u>Be prepared to<u style="single">Said</u>LDD area or<u style="single">Said</u>The offset junction was adjacent to the gate electrode<u style="single">Said</u>Formed within the area of the active layer,<u style="single">Said</u>Crystallization induction metal<u style="single">Said</u>The gist is that it is offset from the gate electrode.

[0023] In the invention according to claim 2, Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, as the crystallization inducing metal in the method according to claim 1. Gold at least one of Tr, Ru, Rh, Cd, Pt<u style="single">Genus</u>The gist is to use it.

[0024] In the invention according to claim 3, in the method according to claim 1 or 2, the crystallization inducing metal is the active layer using sputtering, thermal vapor deposition, solution coating or a CVD method.<u style="single">Up</u>The gist is that it is formed with a thickness of 10 Å to 200 Å.

[0025] In the invention according to claim 4, the method according to claim 3 is described above.<u style="single">Crystallization</u>By heat treatment using a blast furnace, RTA, line scan RTA or ELC method by the crystallization induction metal.<u style="single">Do</u>The gist is that.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred first embodiments of the present invention will be described in detail with reference to the accompanying drawings.

10 to 15 are cross-sectional views showing a process of manufacturing a TFT using the MILC phenomenon according to the first embodiment of the present invention. As shown in FIG. 10, the amorphous Si layer 31 constituting the active layer of the thin film transistor is formed on the insulating substrate 30, and the amorphous Si layer 31 is patterned. Subsequently, the gate insulating film 32, the lower gate electrode 33, and the upper gate electrode 34 are sequentially formed on the amorphous Si layer 31.

As shown in FIG. 11, the source and drain regions 31S and 31D are formed by doping the amorphous Si layer 31 with impurities at a high concentration using the upper gate electrode 34 as a mask.

[0037] In the doping step of FIG. 11, when the N-MOS TFT is manufactured, PH is used by using an ion shower doping method, an ion implantation method, or another ion implantation method.₃, P, As and other dopants at an energy of 10 to 200 KeV (preferably 30 to 100 KeV), 1E14 to 1E22 / cm³(Preferably 1E15 ~ 1E21 / cm³) Doping with the dose. When manufacturing P-MOS TFT, B₂H₆, B, BH₃Dopants such as 1E13-1E22 / cm with energy of 20 ~ 70KeV³(Preferably 1E14 ~ 1E21 / cm³) Doping with the dose.

[0038] After that, as shown in FIG. 12, the upper gate electrode 34 is used as a mask to form a metal layer 35 such as nickel that induces crystallization of the amorphous Si layer 31. Nickel (Ni) or palladium (Pd) is preferably used as the metal that induces the crystallization of the amorphous Si layer 35. In addition to these metals, metals such as Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, and Pt or substances containing them can be used. The crystallization-induced metal layer 35 such as nickel or palladium can be formed by sputtering, heat evaporation, PECVD, solution coating or ion implantation, but sputtering is generally used.

[0039] The thickness of the metal layer 35 can be arbitrarily selected within the limits necessary for inducing the crystallization of the amorphous Si layer 31, and is about 1 to 10,000 Å, preferably 10 to 200 Å. Formed by thickness. At this time, if the width of the upper gate electrode 34 is made larger than the width of the lower gate electrode 33, the crystallization-inducing metal layer is not formed in the portion 31LDD where the LDD region is formed later, so that the distance from the channel region 31C is constant. The effect is that the crystallization-inducing metal is offset.

[0040] When the channel region and the crystallization-inducing metal layer are in direct contact with each other without being offset, the crystallization-inducing metal component is generated in the channel region after the crystallization of the amorphous Si layer is induced by the metal. There arises a problem that it is left behind and deteriorates the operating characteristics of the transistor. In the present invention, since the crystallization inducing metal layer 31 is offset, it is possible to prevent the crystallization inducing metal component from being left in the channel region 31C and deteriorating the operating characteristics of the transistor. It is desirable that the offset distance of the crystallization-induced metal layer 31, that is, the width of the region where the LDD region 31LDD is formed later is set to about 1,000 to 20,000 Å, preferably about 5,000 to 20,000 Å. In the present invention, the step of doping impurities at a high concentration and the step of forming the crystallization-inducing metal layer can be performed in a different order.

Next, after forming the crystallization-induced metal layer 35, the upper gate electrode 34 is removed as shown in FIG. Then, as shown in FIG. 14, the lower gate electrode 33 is used as a mask to dope impurities at a low concentration to form the LDD region 31LDD.

[0042] In the low concentration doping step, when manufacturing an N-MOS TFT, PH is performed by using an ion shower doping method, an ion implantation method or another ion implantation method.₃, P, As and other dopants 1E11 ~ 1E20 / cm³Dope with the dose of. When manufacturing P-MOS TFT, B₂H₆, B, BH₃Dopants such as 1E11 ~ 1E20 / cm³Dope with the dose of.

[0043] After the LDD region 31C is formed by the low-concentration doping step, as shown in FIG. 15, the active layer 31 is crystallized by heat treatment to form an insulating film, a contact electrode (not shown), and the like. To make a transistor. In the heat treatment step shown in FIG. 15, any method that causes a metal-induced crystallization phenomenon of amorphous silicon can be used. For example, this step is very fast using a fast annealing (RTA) method, which uses a tungsten-halogen or xenon arc heating lamp to heat at a temperature of about 500 to 1,200 ° C for a short time within a few seconds to a few minutes, or an excimer laser. An ELC method or the like that heats for a short time can be used. Further, in the present invention, a method of crystallizing silicon by heating in a blast furnace at a temperature of 400 to 600 ° C. for 0.1 to 50 hours, preferably 0.5 to 20 hours can be used.

[0044] The method of crystallizing the amorphous Si layer 31 using a blast furnace uses a temperature lower than the deformation temperature of the glass substrate, so that the deformation or damage of the substrate can be prevented. Therefore, since many substrates can be heat-treated at the same time in a blast furnace, there is an advantage that mass production is possible and productivity can be improved. In the active layer region where the crystallization-induced metal layer 35 was formed by the heat treatment step, crystallization by the MIC phenomenon proceeded, and in the remaining portion where the metal was not formed, the MILC phenomenon propagated from the portion where the metal was formed. Crystallization proceeds. Further, in the present invention, the heat treatment conditions for crystallizing the amorphous Si layer 31 with the crystallization-induced metal layer 35 are the same as the annealing conditions for activating the dopant injected into the active layer, so that the crystals of the active layer are crystallized. The crystallization and the activation of the dopant can be performed in one step.

[0045] In the method of the first embodiment, the metal offset region can be formed without a separate photoresist step for offsetting the crystallization induced metal layer 35 from the channel region 31C, and the metal offset region is low. Transistors with an LDD region of 31LDD can be made by doping with a concentration. In the transistor manufactured by the method of the present invention, the metal component that has flowed in due to the MIC phenomenon does not remain in the interface between the source and drain regions 31S and 31D and the channel region 31C and in the channel region 31C, so that leakage current does not occur. It is small and has stable electrical characteristics. Although the configuration of the present invention has been described above with reference to the first embodiment, the present invention can be embodied in the form of the second embodiment described below. The conditions of the specific steps of the second embodiment of the present invention can be performed under the same conditions as those of the first embodiment.

[0046] FIGS. 16 to 21 are cross-sectional views showing a process of manufacturing a TFT using the MILC phenomenon according to the second embodiment of the present invention. As shown in FIG. 16, the amorphous Si layer 41 constituting the active layer of the thin film transistor is formed on the insulating substrate 40, and the amorphous Si layer 41 is patterned. Subsequently, a gate insulating film 42 and a gate electrode 43 are formed on the amorphous Si layer 41.

As shown in FIG. 16, the photoresist 44 used to form the gate electrode 43 is placed on the gate electrode 43 as it is, and excessive etching is performed during etching for forming the gate electrode 43. (Over etching) is performed so that an undercut shaped gate electrode 43 is generated, as shown in FIG. It is then heavily doped for source / drain formation (Figure 17).

[0048] After that, as shown in FIG. 18, the photoresist 44 is used as a mask to form the crystallization-induced metal layer 45. Here, as in the first embodiment, the order of the high-concentration doping step and the crystallization-inducing metal forming step may be changed. At this time, since the crystallization-induced metal layer is not formed in the offset portion where the LDD region 41LLD is formed later, the metal offset effect can be obtained. Then the photoresist 44 is removed (Fig. 19).

After removing the photoresist 44, the gate electrode 43 is used as a mask to dope impurities at a low concentration to form the LDD region 41LDD (FIG. 20). Then, as shown in FIG. 21, heat treatment is performed to proceed with crystallization of the active layer, and a transistor is manufactured according to the prior art.

[0050] FIGS. 22 to 26 are cross-sectional views showing a process of manufacturing a TFT using the MILC phenomenon according to the third embodiment of the present invention. As shown in FIG. 22, the amorphous Si layer 51 constituting the active layer of the thin film transistor is formed on the insulating substrate 50, and the amorphous Si layer 51 is patterned. After that, the gate insulating film 52 and the gate electrode 53 are formed on the amorphous Si layer 51. Next, the amorphous Si layer 51 was doped with impurities at a low concentration using the gate electrode 53 as a mask (Fig. 23).

[0051] After that, the gate electrode 53 is anodized to form an oxide film (anodic oxide) 54 on the gate surface as shown in FIG. 24. Subsequently, the crystallization-inducing metal layer 55 is formed on the oxide film 54 so that the oxide film 54 creates a metal offset region (FIG. 24).

[0052] Next, the amorphous Si layer 51 is heavily doped with impurities to form the source / drain region (Fig. 25). In this case, the order of the crystallization-induced metal formation and the high-concentration doping step may be changed as in the first embodiment. After that, heat treatment is performed to proceed with crystallization of the active layer (amorphous Si layer 51) (Fig. 26), and a transistor is manufactured according to the prior art. According to the method of the third embodiment, the metal offset region formed by forming the oxide film 54 on the gate electrode 53 is not heavily doped, so that the LDD region 51LDD is formed around the gate electrode 53. Is generated.

[0053] FIGS. 27 to 31 are cross-sectional views showing a process of manufacturing a TFT using the MILC phenomenon according to the fourth embodiment of the present invention. As shown in FIG. 27, the amorphous Si layer 61 constituting the active layer of the thin film transistor is formed on the insulating substrate 60, the amorphous Si layer 61 is patterned, and the gate is formed on the amorphous Si layer 61. The insulating film 62 and the gate electrode 63 are formed in order. FIG. 27 shows a state in which the photoresist 64 for etching at the time of forming the gate electrode 63 still remains.

Subsequently, the substrate is heated at a temperature higher than the hard baking temperature of the photoresist 64 to reflow the photoresist 64 and perform high concentration doping for source / drain formation. (Fig. 28). After that, as shown in FIG. 29, the reflowed photoresist 64 is used as a mask to form the crystallization-induced metal layer 65. At this time, a metal offset effect is obtained because the crystallization-inducing metal layer is not formed in the portion covered by the photoresist 64, that is, a part of the amorphous Si layer 61 in which the LDD region 61LDD is formed later. Be done. Here, the formation of the crystallization-induced metal layer 65 and the high-concentration doping may proceed in a different order.

Next, the photoresist 64 is removed and impurities are doped at a low concentration to form the LDD region 61LDD (FIG. 30). Further, heat treatment is performed to proceed with crystallization of the active layer (Fig. 31), and a transistor is manufactured according to the prior art.

[0056] FIGS. 32 to 38 are cross-sectional views showing a process of manufacturing a TFT using the MILC phenomenon according to the fifth embodiment of the present invention. As shown in FIG. 32, the amorphous Si layer 71 constituting the active layer of the thin film transistor is formed on the insulating substrate 70, and the amorphous Si layer 71 is patterned. Subsequently, the gate insulating film 72 and the gate electrode 73 are sequentially formed on the amorphous Si layer 71.

[0057] FIG. 33 is a cross-sectional view showing a state in which the insulating film 74 is formed on the entire substrate. Anisotropic etching in this state leaves a so-called "side wall" portion 75 on the side surfaces of the gate insulating film 72 and the gate electrode 73, as shown in FIG. Even if the side wall portion 75 is used, the same effect as that of each of the above-described embodiments can be obtained. That is, when impurities are doped at low energy and high concentration in this state (Fig. 35) and impurities are doped at high energy and low concentration (Fig. 36), the active layer (amorphous Si layer) below the side wall portion 75 is used. An LDD region can be formed in a part of 71.

[0058] After that, as shown in FIG. 37, the crystallization-induced metal layer 76 is formed, and heat treatment is performed to proceed with the crystallization of the active layer 71 (FIG. 38), and a transistor is manufactured by using the prior art. Also in the fourth embodiment, the crystallization-induced metal layer 76 can be formed before doping with impurities.

[0059] FIGS. 39 to 43 are cross-sectional views showing a process of manufacturing a TFT using the MILC phenomenon according to the sixth embodiment of the present invention. As shown in FIG. 39, the amorphous Si layer 81 constituting the active layer of the thin film transistor is formed on the insulating substrate 80, and the amorphous Si layer 81 is patterned. Subsequently, the gate insulating film 82 and the gate electrode 83 are sequentially formed on the amorphous Si layer 81. In this example, when the gate electrode 83 and the gate insulating film 82 are etched, only the gate electrode 83 is over-etched to form the gate electrode 83 so as to have an undercut shape. By this etching, as shown in FIG. 39, the width of the gate insulating film 82 can be formed wider than the width of the gate electrode 83. Even if such a gate insulating film 82 and a gate electrode 83 are used, the same effect as that of each of the above-described embodiments can be obtained. That is, in this state, when impurities are doped with low energy and high concentration as shown in FIG. 40 and impurities are doped with high energy and low concentration as shown in FIG. 41, the active layer region covered with the gate insulating film 82 In, only low concentrations of doping are performed to form the LDD region.

[0060] After that, as shown in FIG. 42, a crystallization-inducing metal layer 84 such as nickel is formed, and as shown in FIG. 43, heat treatment is performed to proceed with crystallization of the active layer 81, according to the prior art. Make a transistor. In this case as well, the formation of the crystallization-induced metal layer 84 may be performed before doping with impurities.

[0061] In all of the above embodiments, the low concentration doping step can be omitted, although such a method cannot be used to form an LDD region on a thin film transistor, but an offset junction. ) Can be used to form only.

[Effects of the Invention] As described above, according to the present invention, a metal offset region is formed without a separate photoresist step, and impurities are doped into the metal offset region at a low concentration to form an LDD region. be able to. Therefore, the transistor manufactured by the method of the present invention has a small leakage current in the off state and the electrical characteristics are stabilized in the on state.

BRIEF DESCRIPTION OF THE DRAWINGS [FIG. 1] FIG. 1 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor using a conventional MILC phenomenon.

FIG. 2 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 4 is a cross-sectional view showing a manufacturing process of an amorphous silicon thin film transistor following FIG.

FIG. 5 is a cross-sectional view showing a manufacturing process of a conventional crystalline silicon thin film transistor having an LDD region.

FIG. 6 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 7 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 8 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 9 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 10 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 12 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 13 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 14 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 15 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 16 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor according to a second embodiment of the present invention.

FIG. 17 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 18 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 19 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 20 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 21 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 22 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor according to a third embodiment of the present invention.

FIG. 23 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 22.

FIG. 24 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 23.

FIG. 25 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 24.

FIG. 26 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 25.

FIG. 27 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor according to a fourth embodiment of the present invention.

FIG. 28 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 27.

FIG. 29 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 28.

FIG. 30 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 29.

FIG. 31 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG.

FIG. 32 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor according to a fifth embodiment of the present invention.

FIG. 33 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 32.

FIG. 34 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 33.

FIG. 35 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 34.

FIG. 36 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 35.

FIG. 37 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 36.

FIG. 38 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 37.

FIG. 39 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor according to a sixth embodiment of the present invention.

FIG. 40 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 39.

FIG. 41 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 40.

FIG. 42 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 41.

FIG. 43 is a cross-sectional view showing a manufacturing process of a crystalline silicon thin film transistor following FIG. 42.

[Description of Code] 30 ... Insulation substrate 31 ... Amorphous Si layer 32 ... Gate insulating film 33 ... Lower gate electrode 34 ... Upper gate electrode 35 ... Metal layer